[PATCH 4/20] aarch64: Use RTL builtins for [su]paddl[q] intrinsics

[Jonathan Wright via Gcc-patches]

Hi,

As subject, this patch rewrites the [su]paddl[q] Neon intrinsics to use
RTL builtins rather than inline assembly code, allowing for better
scheduling and optimization.

Regression tested and bootstrapped on aarch64-none-linux-gnu - no
issues.

Ok for master?

Thanks,
Jonathan

---

gcc/ChangeLog:

2021-02-08  Jonathan Wright  <jonathan.wri...@arm.com>

        * config/aarch64/aarch64-simd-builtins.def: Add [su]addlp
        builtin generator macros.
        * config/aarch64/aarch64-simd.md (aarch64_<su>addlp<mode>):
        Define.
        * config/aarch64/arm_neon.h (vpaddl_s8): Use RTL builtin
        instead of inline asm.
        (vpaddl_s16): Likewise.
        (vpaddl_s32): Likewise.
        (vpaddl_u8): Likewise.
        (vpaddl_u16): Likewise.
        (vpaddl_u32): Likewise.
        (vpaddlq_s8): Likewise.
        (vpaddlq_s16): Likewise.
        (vpaddlq_s32): Likewise.
        (vpaddlq_u8): Likewise.
        (vpaddlq_u16): Likewise.
        (vpaddlq_u32): Liwewise.
        * config/aarch64/iterators.md: Define [SU]ADDLP unspecs with
        appropriate attributes.

rb14137.patch
Description: rb14137.patch