c-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com; Chen, Ken
; Liu, Hongtao
Subject: Re: [PATCH v1] RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
On 7/7/25 9:48 PM, Li, Pan2 wrote:
>> Is that correct? Don't you need to be testing th
On 7/7/25 9:48 PM, Li, Pan2 wrote:
Is that correct? Don't you need to be testing that the platform has
vector in addition to being rv64?
It is riscv.exp test, so I think vector extension is not required here.
Oh, I see. We're not actually turning on RVV anywhere. OK for the trunk.
It lo
gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com; Chen, Ken
; Liu, Hongtao
Subject: Re: [PATCH v1] RISC-V: Disable uint128_t testcase of SAT_MUL when rv32
On 7/7/25 9:24 PM, pan2...@inte
On 7/7/25 9:24 PM, pan2...@intel.com wrote:
/**/
/* Saturation Add (unsigned and signed)
*/
diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c
From: Pan Li
The rv32 doesn't support __uint128, and then we will have
error like below during test.
error: '__int128' is not supported on this target.
Thus, we disable the uint128_t related test when rv32.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat/sat_arith.h: Add xlen check fo
