LGTM. Thanks for fixing my issue.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2025-07-14 21:55
To: gcc-patches
CC: kito.ch...@gmail.com; juzhe.zh...@rivai.ai; jeffreya...@gmail.com;
pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH] RISC-V: Fix vsetvl merge rule.
Hi,
In PR120297 we fus
Hi. Vineet. The series of patches LGTM from myside.
But I wonder whether you would like to optimize VXRM which is using
mode-switching too.
I saw in spec 2017 spec 624 x264.
csrwi vxrm is calling multiples times.
juzhe.zh...@rivai.ai
From: Vineet Gupta
Date: 2025-06-06 08:04
To: gcc-patches
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2025-06-05 13:01
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; ken.chen; hongtao.liu; Pan
Li
Subject: [PATCH v1] RISC-V: Fix ICE for gcc.dg/graphite/pr33576.c with rv32gcv
From: Pan Li
The div of rvv has not such insn v2
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2025-05-27 16:31
To: gcc-patches
CC: kito.ch...@gmail.com; juzhe.zh...@rivai.ai; jeffreya...@gmail.com;
pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH] RISC-V: Avoid division by zero in check_builtin_call
[PR120436].
Hi,
in check_bu
Hi, vineet.
>> I have a feeling this has to do with following:
>> https://godbolt.org/z/Px9es7j1r
I saw in there are 2 fsrm instruction inside the main loop in Clang generated
ASM which I think GCC is better.
Correct me if I am wrong. Thanks.
juzhe.zh...@rivai.ai
From: Vineet Gupta
Date: 2
LGTM
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2025-04-29 11:35
To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zhong; pan2.li;
vineetg
CC: Kito Cheng
Subject: [PATCH] RISC-V: Allow different dynamic floating point mode to be
merged [PR119832]
Although we already try to set
These patches LGTM from myside. But please wait for other folks to comment.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2025-04-23 09:28
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; ken.chen; hongtao.liu; Pan
Li
Subject: [PATCH v1 0/4] Refactor long function expand_const_
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2025-04-07 03:17
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH] RISC-V: Do not lift up vsetvl if its VL is used [PR119547].
Hi,
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2025-04-02 15:02
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH] RISC-V: Fix vec_duplicate[bimode] expander [PR119572].
Hi,
sin
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2025-02-24 19:14
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH] RISC-V: Include pattern stmts for dynamic LMUL computation
[PR1
in scheduler.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2025-02-13 11:33
To: 钟居哲; ewlu; gcc-patches
CC: gnu-toolchain; vineetg
Subject: Re: [PATCH] RISC-V: Prevent speculative vsetvl insn scheduling
On 2/12/25 6:44 PM, 钟居哲 wrote:
> VSETVL PASS is supposed to insert "vsetvli&
VSETVL PASS is supposed to insert "vsetvli" into optimal place so "vsetvli"
inserted by VSETVL PASS shouldn't involved into instruction scheduling.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2025-02-13 08:47
To: Edwin Lu; gcc-patches
CC: gnu-toolchain; vineetg; juzhe.zhong
Subject: Re: [PATCH]
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2025-02-12 22:03
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH] RISC-V: Avoid more unsplit insns in const expander [PR118832].
H
Could you add PR117974 testcase ?
juzhe.zh...@rivai.ai
From: Edwin Lu
Date: 2025-02-13 07:27
To: gcc-patches
CC: gnu-toolchain; vineetg; juzhe.zhong; Edwin Lu
Subject: [PATCH] RISC-V: Prevent speculative vsetvl insn scheduling
The instruction scheduler appears to be speculatively hoisting vset
>> But I don't think offering the -mvec-elide-x0 option is beneficial.
>> I'd just enable this change unconditionally. Or, in the unlikely
>> event there's a uarch that benefits from the old code generation, this
>> would be better handled as a consequence of -mtune than as a new
>> top-level opti
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2025-02-07 00:36
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH] RISC-V: Fix ratio in vsetvl fuse rule [PR115703].
Hi,
in PR115
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2025-01-26 09:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; vineetg;
richard.sandiford; Pan Li
Subject: [PATCH v2] RISC-V: Make FRM as global register [PR118103] [PR118646]
From: Pan Li
After we enabled the labe-combin
Could you show me the a piece of codegen difference in X264 that make
performance improved ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2025-01-22 15:29
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; pan2...@intel.com; rdapp@g
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2025-01-14 16:19
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH v2] RISC-V: Fix vsetvl compatibility predicate [PR118154].
Hi,
Strided load store should demand RATIO instead of SEW and LMUL.
Is it VSETVL PASS bug ? I don't understand why configure it depand SEW + LMUL
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2025-01-10 16:42
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffr
Thanks for optimizing it.
Did you do the RVV intrinsic CI test ?
riscv-non-isa/rvv-intrinsic-doc
LGTM if you finished the full coverage testing of rvv intrinsic.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2025-01-08 17:36
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; pan2.li; xuli
Subject:
LGTM.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2025-01-02 16:02
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; pan2.li; xuli
Subject: [PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form2~4
From: xuli
Form2:
void __attribute__((noinline)) \
vec_sat_u_sub_imm##IMM#
lgtm
juzhe.zh...@rivai.ai
From: Vineet Gupta
Date: 2024-12-21 06:18
To: gcc-patches
CC: gnu-toolchain; Robin Dapp; Pan Li; Juzhe Zhong; Jeff Law; Vineet Gupta
Subject: [PATCH v2] RISC-V: vector absolute difference expander [PR117722]
Changes since v1:
- Fix snafu in test.
This improves codeg
ok
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-12-20 14:49
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Fix the the operand alignment for strided
load/store pattern [NFC]
From: Pan Li
Just notice the unalignment operand for strid
ok
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-12-18 18:37
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH] RISC-V: Expand shift count in Xmode in interleave pattern.
Hi,
c
OK.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-12-13 23:20
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH v2] RISC-V: Increase cost for vec_construct [PR118019].
Hi,
for
LGTM.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-12-12 18:43
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH] RISC-V: Emit vector shift pattern for const_vector [PR117353].
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-11-25 22:39
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH] RISC-V: avlprop: Do not propagate VL from slidedown.
Hi,
in th
This series patches LGTM.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-11-23 02:20
To: gcc-patches
CC: palmer; kito.cheng; juzhe.zhong; jeffreyalaw; pan2.li; rdapp.gcc
Subject: [PATCH v2 0/4] Improve and add VLS slide strategies.
From: Robin Dapp
Changes from v1:
- Improve function nami
LGTM
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-11-20 15:37
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
Subject: [PATCH] PR target/117669 - RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF'
type condition error
This patch fix the wrong condition for RVVMF2BF. It should
Are you trying to fix this PR ?
117669 �C RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF' type condition error
I think you should add PR target/117669 in the changelog
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-11-20 14:50
To: gcc-patches
CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
+ int vlen = vec_len.to_constant ();
+ if (vlen != (int)indices.length ().to_constant ())
+return false;
Is it possiable to use unsigned vlen ? So that "(int)" conversion can be elided.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-11-17 20:53
To: gcc-patches
CC: palmer; kito.cheng;
shuffle_extract_and_slide1up_patterns (struct expand_vec_perm_d *d)
I think this name is obsolete, since you have changed the codegen which is
possible to use 2 "slides".
Could you rename this function ?
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-11-17 20:53
To: gcc-patches
CC: palmer;
+shuffle_evenodd_patterns (struct expand_vec_perm_d *d)
I prefer it rename into shuffle_even_odd_patterns
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-11-17 20:53
To: gcc-patches
CC: palmer; kito.cheng; juzhe.zhong; jeffreyalaw; pan2.li; rdapp.gcc
Subject: [PATCH 3/4] RISC-V: Add even/odd
LGTM.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-11-14 00:57
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH] RISC-V: Add VLS modes to strided loads.
Hi,
this patch adds V
LGTM
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-11-13 10:36
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; pan2.li; xuli
Subject: [PATCH v2] RISC-V: Bugfix for
max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483]
From: xuli
This patch fixs https://gcc.gnu.org/bugzilla/show_
Do we need to check next.get_ma ?
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-11-13 08:57
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; pan2.li; xuli
Subject: [PATCH] RISC-V: Bugfix for
max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483]
From: xuli
This patch fixs https://
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-11-11 16:45
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Fix one nit indent issue of ustrunc pattern [NFC]
From: Pan Li
Just notice the indent is not that right for ustrunc pattern
LGTM
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-11-08 14:57
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISC-V: Add testcases for unsigned imm vec SAT_SUB form1
From: xuli
form1:
void __attribute__((noinline)) \
vec_sat_u_sub_imm##IMM##_##T##_fmt_
lgtm
juzhe.zh...@rivai.ai
From: Vineet Gupta
Date: 2024-10-30 08:11
To: gcc-patches; Jeff Law; Robin Dapp; juzhe . zhong @ rivai . ai
CC: gnu-toolchain; Vineet Gupta
Subject: [PATCH] RISC-V: fix const interleaved stepped vector with a scalar
pattern
When bisecting for ICE in PR/117353, commi
LGTM. Thanks for fixing it.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-10-28 14:28
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; pan2.li; xuli
Subject: [PATCH] RISC-V:Bugfix for vlmul_ext and vlmul_trunc with NULL return
value[pr117286]
From: xuli
This patch fixes following ICE:
Could you add run test case (verified by QEMU or SPIKE ) ?
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-10-18 15:24
To: gcc-patches
CC: kito.cheng; juzhe.zhong; Feng Wang
Subject: [PATCH v2] RISC-V:Auto vect for vector-bfloat16
This patch add auto-vect patterns for vector-bfloat16 extension
+;; -
+;; - vfwmaccbf16
+;; -
+;; Combine extend + fma to widen_fma (vfwmacc)
+(define_insn_and_split "*widen_bf16_fma"
+ [(set (match_operand:VWEXTF_ZVFB
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-10-15 20:55
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH] RISC-V: Use biggest_mode as mode for constants.
Hi,
in compute
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-10-11 14:22
To: gcc-patches
CC: richard.guenther; Tamar.Christina; juzhe.zhong; kito.cheng; jeffreyalaw;
rdapp.gcc; Pan Li
Subject: [PATCH v1 3/4] RISC-V: Implement vector SAT_SUB for signed integer
From: Pan Li
This patch would like to im
LGTM from my side. But I'd rather let kito chime in to see more comments.
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-10-10 14:24
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; pan2.li; xuli
Subject: [PATCH] RISC-V:Bugfix for C++ code compilation failure with
rv32imafc_zve32f[pr
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-10-10 16:33
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 1/4] RISC-V: Add testcases for form 5 of scalar signed
SAT_TRUNC
From: Pan Li
Form 5:
#define DEF_SAT_S_TRUNC_FMT_5(NT, WT, NT_MIN
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-10-10 16:33
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 2/4] RISC-V: Add testcases for form 6 of scalar signed
SAT_TRUNC
From: Pan Li
Form 6:
#define DEF_SAT_S_TRUNC_FMT_6(NT, WT, NT_MIN
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-10-10 16:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 4/4] RISC-V: Add testcases for form 8 of scalar signed
SAT_TRUNC
From: Pan Li
Form 8:
#define DEF_SAT_S_TRUNC_FMT_8(NT, WT, NT_MIN
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-10-10 16:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 3/4] RISC-V: Add testcases for form 7 of scalar signed
SAT_TRUNC
From: Pan Li
Form 7:
#define DEF_SAT_S_TRUNC_FMT_7(NT, WT, NT_MIN
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-10-10 14:53
To: gcc-patches
CC: richard.guenther; Tamar.Christina; juzhe.zhong; kito.cheng; jeffreyalaw;
rdapp.gcc; Pan Li
Subject: [PATCH v1 2/2] RISC-V: Add testcases for form 4 of scalar signed
SAT_TRUNC
From: Pan Li
Form 4:
#define
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-10-08 09:21
To: gcc-patches
CC: richard.guenther; Tamar.Christina; juzhe.zhong; kito.cheng; jeffreyalaw;
rdapp.gcc; Pan Li
Subject: [PATCH v1 2/3] RISC-V: Add testcases for form 3 of scalar signed
SAT_SUB
From: Pan Li
Form 3:
#define DE
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-10-08 09:21
To: gcc-patches
CC: richard.guenther; Tamar.Christina; juzhe.zhong; kito.cheng; jeffreyalaw;
rdapp.gcc; Pan Li
Subject: [PATCH v1 3/3] RISC-V: Add testcases for form 4 of scalar signed
SAT_SUB
From: Pan Li
Form 4:
#define DE
OK
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-09-25 16:10
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Cleanup debug code for SAT_* testcases [NFC]
From: Pan Li
Some print code for debugging is committed by mistake, remove them
f
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-09-25 14:45
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 3/3] RISC-V: Refine the testcase of vector SAT_TRUNC
From: Pan Li
Take scan-assembler-times for vsadd insn check instead of function
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-09-23 13:43
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: RISC-V: Add testcases for form 4 of signed vector
SAT_ADD
From: Pan Li
Form 4:
#define DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN
LGTM. Thanks for supporting it :).
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-09-12 11:19
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Implement SAT_ADD for signed integer vector
From: Pan Li
This patch would like to implement th
LGTM
juzhe.zh...@rivai.ai
From: Bohan Lei
Date: 2024-09-12 12:38
To: gcc-patches
CC: juzhe.zhong
Subject: [PATCH v2] RISC-V: Eliminate latter vsetvl when fused
Resent to cc Juzhe.
--
Hi all,
A simple assembly check has been added in this version. Previous version:
https://gcc.gnu.org
Could you CC to me ? I can't reply that patch directly.
juzhe.zh...@rivai.ai
From: Bohan Lei
Date: 2024-09-12 10:38
To: Bohan Lei
CC: gcc-patches; juzhe.zhong
Subject: RE: [PATCH 2/2] RISC-V: Eliminate latter vsetvl when fused
An updated version has been submitted:
https://gcc.gnu.org/pipermai
I see the codegen is incorrect before this patch:
foo:
vsetvli a5,a0,e16,m1,ta,ma
vmv.x.s a4,v8
vsetvli a5,a0,e8,mf2,ta,ma ---> wrong VTYPE
vadd.vx v9,v8,a4
vsetvli zero,a5,e16,m1,ta,ma
vadd.vv v8,v9,v8
ret
Could you show me what the codegen
Hi, garthlei.
Thanks for fixing it.
I see, you are trying to fix this bug:
lui a5,%hi(.LANCHOR0)
addia5,a5,%lo(.LANCHOR0)
vsetivlizero,2,e8,mf8,ta,ma ---> It should be a4, 2 instead of
zero, 2
vle64.v v1,0(a5)
--- missing vsetvli a4, a4 here
LGTM
juzhe.zh...@rivai.ai
From: Jin Ma
Date: 2024-09-07 01:40
To: gcc-patches
CC: jeffreyalaw; juzhe.zhong; pan2.li; kito.cheng; jinma.contrib; Jin Ma; nihui
Subject: [PATCH v4] RISC-V: Fix illegal operands "th.vsetvli zero,0,e32,m8" for
XTheadVector
Since the THeadVector vsetvli does not sup
Sorry, I still don't see assembly check.
juzhe.zh...@rivai.ai
From: Jin Ma
Date: 2024-09-06 16:32
To: gcc-patches
CC: jeffreyalaw; juzhe.zhong; pan2.li; kito.cheng; christoph.muellner;
shuizhuyuanluo; pinskia; xry111; jinma.contrib; Jin Ma
Subject: [PATCH v3] RISC-V: Fix illegal operands "th.
Thanks. lgtm.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-09-06 17:56
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.com; pan2...@intel.com; rdapp@gmail.com
Subject: [PATCH] RISC-V: Add more vector-vector extract cases.
Hi,
thi
I think it's better to add a "vsetvli" assembly check in testcase.
juzhe.zh...@rivai.ai
From: Jin Ma
Date: 2024-09-06 15:52
To: gcc-patches
CC: jeffreyalaw; juzhe.zhong; pan2.li; kito.cheng; christoph.muellner;
shuizhuyuanluo; pinskia; xry111; jinma.contrib; Jin Ma
Subject: [PATCH v2] RISC-V:
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-08-28 03:48
To: juzhe.zh...@rivai.ai; gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; jeffreya...@gmail.com;
pan2...@intel.com; Robin Dapp
Subject: Re: [PATCH] RISC-V: Fix subreg of VLS modes larger than a vector
[PR116086].
> +
>> I'm not sure if it's profitable to replace a lmul8 load with 127
>> vslide1down.vx
>> ops but we're being honest with the middle end when returning the # of insns
>> we'll be emitting when costing...
I think it's issue of dynamic LMUL cost model which only care about program
SSA-based registe
Nice Clean up! It's very reasonable to have a dedicated riscv-v.h
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2024-08-23 03:46
To: gcc-patches
CC: rdapp.gcc; juzhe.zhong; kito.cheng; jeffreyalaw; gnu-toolchain; Patrick
O'Neill
Subject: [PATCH 6/9] RISC-V: Emit costs for bool and stepped
Hi, Zeng.
Thanks for fixing it.
LGTM from myside but since I am no expert on dwarf stuff.
I'd like to let kito or Robin review it again.
Thanks.
juzhe.zh...@rivai.ai
Sorry for long time no update of subreg stuff.
I am working on it but recently get stuck in other project and I will be back
after I finish my recent project :)
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2024-08-15 05:55
To: Jeff Law; Xianmiao Qu; gcc-patches; roger; juzhe.zhong; richard.sandi
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index d7a3cfd4602..923122510ac 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1607,3 +1607,19 @@
Such pattern which is natural auto-vectorization pattern should be in
autovec.md
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-08-05 16:01
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Update .SAT_TRUNC dump check due to middle-end
change
From: Pan Li
Due to recent middle-end change, update the .SAT_TRUNC e
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-03 22:17
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix vfmv insn honor zvfhmin for FP16 SEW
[PR115763]
From: Pan Li
According to the ISA, the zvfhmin sub extension shoul
LGTM.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-06-20 11:28
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc
Subject: [PATCH v2] RISC-V: Remove integer vector eqne pattern
We can unify eqne and other comparison operations.
Tested on RV32 and RV64.
gcc/Chan
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-15 10:44
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Refine the SAT_ARITH test help header files [NFC]
From: Pan Li
Separate the vector part code to one standalone header file,
I think it should be backport to GCC-14 since it is a bug.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-05-17 23:24
To: gcc-patches
CC: palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw; rdapp.gcc
Subject: [PATCH] RISC-V: Split vwadd.wx and vwsub.wx and add helpers.
Hi,
vwadd.wx and
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-05-17 23:26
To: gcc-patches
CC: rdapp.gcc; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw
Subject: [PATCH] RISC-V: Add vector popcount, clz, ctz.
Hi,
this patch adds the zvbb vcpop, vclz and vctz to the autovec machinery
as well as
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-05-17 23:26
To: gcc-patches
CC: rdapp.gcc; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw
Subject: [PATCH] RISC-V: Add vandn combine helper.
Hi,
this patch adds a combine pattern for vandn as well as tests for it.
Regtested on rv
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-05-17 23:25
To: gcc-patches
CC: rdapp.gcc; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw
Subject: [PATCH] RISC-V: Use widening shift for scatter/gather if applicable.
Hi,
with the zvbb extension we can emit a widening shift for sc
LGTM.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-05-17 23:25
To: gcc-patches
CC: rdapp.gcc; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw
Subject: [PATCH] RISC-V: Add vwsll combine helpers.
Hi,
this patch enables the usage of vwsll in autovec context by adding the
necessary com
LGTM.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-05-17 23:24
To: gcc-patches
CC: palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw; rdapp.gcc
Subject: [PATCH] RISC-V: Split vwadd.wx and vwsub.wx and add helpers.
Hi,
vwadd.wx and vwsub.wx have the same problem vfwadd.wf had. This p
v0,v8,a5,v0.t > vd and vm are both v0 which is
wrong.
li a0,0
ret
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-05-16 03:31
To: 钟居哲; gcc-patches
CC: rdapp.gcc; palmer; kito.cheng; Jeff Law
Subject: Re: [PATCH] RISC-V: Do not allow v0 as dest when merging [PR115068].
>
LGTM
juzhe.zh...@rivai.ai
>> Seems a bit odd on first sight. If all we want to do is to
>> select between two masks why do we need a large Pmode mode?
Since we are lowering final mask = vcond_mask_len (mask, 1s, 0s, len, bias),
into:
vid.v v1
vcmp v2
vmsltu.vx v2, v1, len, TUMU
Then len is Pmode, so we only allow to low
Hi, Robin.
I saw vwadd/vwsub.wx have same issue. Could you change them and add test too ?
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-05-14 04:15
To: gcc-patches
CC: rdapp.gcc; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw
Subject: [PATCH] RISC-V: Do not allow v0 as dest
Thanks Dim.
We noticed there is regression in aarch64 CI.
We will fix it with following your comments and regression in aarch64 CI.
juzhe.zh...@rivai.ai
From: Dimitar Dimitrov
Date: 2024-05-08 23:57
To: 陈硕
CC: 丁乐华; gcc-patches; 钟居哲; 夏晋; vmakarov; richard.sandiford
Subject: Re: [PATCH 2/4] df
Thanks Vlad.
I noticed there is devel/subreg-coalesce branch.
We are working on supporting subreg coalesce in IRA/LRA base on the latest
version of subreg DF patch.
And we will send the followup patches.
Thanks.
juzhe.zh...@rivai.ai
From: Vladimir Makarov
Date: 2024-05-09 00:29
To: Lehua D
Apologize that we didn't post our (me, kito and Li Pan) disscussions.
This is the story:
We found that my previous patches which support highpart register overlap with
register filter for instructions like (vwadd.wv)
cause ICE reported by:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114714
and t
I think the revert patch exposes latent bug, Li Pan will look into it.
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2024-04-23 03:55
To: pan2.li; gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc
Subject: Re: [PATCH v1] RISC-V: Adjust overlap attr after revert d3544cea63d
and e65aaf8efe1
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-22 21:47
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Adjust overlap attr after revert d3544cea63d and
e65aaf8efe1
From: Pan Li
After we reverted below 2 commits, the reference to attr need
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-21 13:01
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for highpart register overlap
of vx/vf widen
From: Pan Li
We reverted below patch for register group overlap, add th
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-20 23:21
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for incorrect overlap on v0
From: Pan Li
We reverted below patch for register group overlap, add the related
insn tes
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-03-06 21:44
To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai
CC: rdapp.gcc; jeffreyalaw
Subject: [PATCH] RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloads
[PR114200].
Hi,
three-operand instructions like vmacc are mod
+ /* Segment load/store permute cost. */
+ const int segment_permute_2;
+ const int segment_permute_4;
+ const int segment_permute_8;
Why do we only have 2/4/8, I think we should have 2/3/4/5/6/7/8
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-02-28 05:27
To: juzhe.zh...@rivai.ai; gcc-
Hi, han. My comment for this patch is same as
[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
-- Original --
From: "demin.han"
Hi, han. I understand you are trying to support optimize vector-splat_vector
into vector-scalar in "expand" stage, that is,
vv -> vx or vv -> vf.
It's a known issue that we know for a long time.
This patch is trying to transform vv->vf when the splat vector is duplicate
from a constant (by
Hi, han. My review comment of this patch is same as I said in:
[PATCH 1/5] RISC-V: Remove float vector eqne pattern
-- Original --
From: "demin.han"
LGTM. But please commit it with adding [NFC] into the title of this patch:
RISC-V: Refactor expand_vec_cmp [NFC]
-- Original --
From: "demin.han"
Hello, han. Thanks for trying to optimize the codes.
But I believe those vector-scalar patterns (eq/ne) you remove in this patch are
necessary.
This is the story:
1. For commutative RTL code in GCC like plus, eq, ne, ... etc,
we known in semantic Both (eq: (reg) (vec_duplicate ... ) and
I think it makes more sense to remove --param=riscv-autovec-preference and add
-mrvv-vector-bits
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-02-28 20:56
To: pan2.li
CC: gcc-patches; juzhe.zhong; yanzhang.wang; rdapp.gcc; jeffreyalaw
Subject: Re: [PATCH v3] RISC-V: Introduce gcc optio
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