ok
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-12-20 14:49
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Fix the the operand alignment for strided
load/store pattern [NFC]
From: Pan Li <pan2...@intel.com>
Just notice the unalignment operand for strided load/store pattern when
bugfix the strided load/store memory alias, would like to make it align.
gcc/ChangeLog:
* config/riscv/autovec.md: Align the operand for strided
load/store pattern.
Signed-off-by: Pan Li <pan2...@intel.com>
---
gcc/config/riscv/autovec.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 2529dc77f22..88c0f00e0ea 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2903,7 +2903,7 @@ (define_expand "v<bitmanip_optab><mode>3"
;; == Strided Load/Store
;; =========================================================================
(define_expand "mask_len_strided_load_<mode>"
- [(match_operand:V_VLS 0 "register_operand")
+ [(match_operand:V_VLS 0 "register_operand")
(match_operand 1 "pmode_reg_or_0_operand")
(match_operand 2 "pmode_reg_or_0_operand")
(match_operand:<VM> 3 "vector_mask_operand")
@@ -2919,7 +2919,7 @@ (define_expand "mask_len_strided_load_<mode>"
(define_expand "mask_len_strided_store_<mode>"
[(match_operand 0 "pmode_reg_or_0_operand")
(match_operand 1 "pmode_reg_or_0_operand")
- (match_operand:V_VLS 2 "register_operand")
+ (match_operand:V_VLS 2 "register_operand")
(match_operand:<VM> 3 "vector_mask_operand")
(match_operand 4 "autovec_length_operand")
(match_operand 5 "const_0_operand")]
--
2.43.0
