>> vsetvl pass inserts based on needs of vector instructions. Yes. vector instructions should make use of scheduler which could minimize "vsetvli" insertion in VSETVL PASS. What I said is we should not involve "vsetvli" instruction (not vector instructions like vadd.vv) in scheduler.
juzhe.zh...@rivai.ai From: Jeff Law Date: 2025-02-13 11:33 To: 钟居哲; ewlu; gcc-patches CC: gnu-toolchain; vineetg Subject: Re: [PATCH] RISC-V: Prevent speculative vsetvl insn scheduling On 2/12/25 6:44 PM, 钟居哲 wrote: > VSETVL PASS is supposed to insert "vsetvli" into optimal place so > "vsetvli" inserted by VSETVL PASS shouldn't involved into instruction > scheduling. vsetvl pass inserts based on needs of vector instructions. The scheduler will move code to try and minimize the critical path length. That includes potentially hoisting any insn into different control blocks if doing so has the same semantics, which is what's happening here. The hoisting, AFAICT doesn't change semantics. jeff
