Re: [PATCH] RISC-V:Bugfix for vlmul_ext and vlmul_trunc with NULL return value[pr117286]

[钟居哲]

LGTM. Thanks for fixing it.



juzhe.zh...@rivai.ai
 
From: Li Xu
Date: 2024-10-28 14:28
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; pan2.li; xuli
Subject: [PATCH] RISC-V:Bugfix for vlmul_ext and vlmul_trunc with NULL return 
value[pr117286]
From: xuli <xu...@eswincomputing.com>
 
This patch fixes following ICE:
 
test.c: In function 'func':
test.c:37:24: internal compiler error: Segmentation fault
   37 |     vfloat16mf2_t vc = __riscv_vlmul_trunc_v_f16m1_f16mf2(vb);
      |                        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
The root cause is that vlmul_trunc has a null return value.
gimple_call <__riscv_vlmul_trunc_v_f16m1_f16mf2, NULL, vb_13>
                                                 ^^^
 
Passed the rv64gcv_zvfh regression test.
 
Singed-off-by: Li Xu <xu...@eswincomputing.com>
---
gcc/config/riscv/riscv-vector-builtins-bases.cc  |  4 ++++
.../gcc.target/riscv/rvv/base/pr117286.c         | 16 ++++++++++++++++
2 files changed, 20 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c
 
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index fcc1bf93453..b8c337f4e77 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1753,6 +1753,8 @@ public:
   rtx expand (function_expander &e) const override
   {
+    if (!e.target)
+      return NULL_RTX;
     tree arg = CALL_EXPR_ARG (e.exp, 0);
     rtx src = expand_normal (arg);
     emit_move_insn (gen_lowpart (e.vector_mode (), e.target), src);
@@ -1767,6 +1769,8 @@ public:
   rtx expand (function_expander &e) const override
   {
+    if (!e.target)
+      return NULL_RTX;
     rtx src = expand_normal (CALL_EXPR_ARG (e.exp, 0));
     emit_move_insn (e.target, gen_lowpart (GET_MODE (e.target), src));
     return e.target;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c
new file mode 100644
index 00000000000..dabb8ae0751
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr117286.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O1" } */
+
+#include <riscv_vector.h>
+_Float16 a[10];
+void func(){
+  int placeholder0 = 10;
+  _Float16* ptr_a = a;
+  for (size_t vl; placeholder0 > 0; placeholder0 -= vl){
+    vl = __riscv_vsetvl_e16m1(placeholder0);
+    vfloat16mf2_t va = __riscv_vle16_v_f16mf2(ptr_a, vl);
+    vfloat16m1_t vb = __riscv_vlmul_ext_v_f16mf2_f16m1(va);
+    vfloat16mf2_t vc = __riscv_vlmul_trunc_v_f16m1_f16mf2(vb);
+    ptr_a += vl;
+  }
+}
-- 
2.17.1