On Fri, 16 May 2025 09:18:45 -0600, Jeff Law wrote:
>
>
> On 5/16/25 1:32 AM, Jin Ma wrote:
> > Reported-by: huangcunjian
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv.cc (riscv_gpr_save_operation_p): Remove
> > break and fixbug for elt index.
> Ideally we'd have a testcase for w
On Fri, May 16, 2025 at 5:13 PM Matthew Sotoudeh
wrote:
>
> This is a small patch to address
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92386
>
> When a variable is used before being shadowed in the same scope, GCC
> outputs incorrect/misleading debug information. The Bugzilla report has
> a m
This is a small patch to address
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92386
When a variable is used before being shadowed in the same scope, GCC
outputs incorrect/misleading debug information. The Bugzilla report has
a minimal example and explains why a direct fix was not desirable (debug
On 5/10/25 11:41 AM, Simon Martin wrote:
The following test case highlights two issues - see
https://godbolt.org/z/7E1KGYreh:
1. We error out at both L4 and L5, while (at least) clang, EDG and MSVC
only reject L5
2. Our error message for L5 incorrectly mentions using a null pointer
===
On 5/16/25 11:32 AM, Richard Sandiford wrote:
output_add_clobbers emits code to add:
(clobber (scratch:M))
and/or:
(clobber (reg:M R))
expressions to the end of a PARALLEL. At the moment, it does this
using the general gen_exp function. That makes sense with the code
in its current
On 5/16/25 11:32 AM, Richard Sandiford wrote:
gen_exp currently supports the 's' (string) operand type. It would
certainly be possible to make the upcoming bytecode patch support
that too. However, the rtx codes that have string operands should
be very rarely used in hard-coded define_insn/e
On 5/16/25 11:22 AM, Richard Sandiford wrote:
gen_exp has code to detect when the same operand is used multiple
times. It ensures that second and subsequent uses call copy_rtx,
to enforce correct unsharing.
However, for historical reasons that aren't clear to me, this was
skipped for a defin
../../gcc/common/config/riscv/riscv-common.cc: In member function 'bool riscv_ex
t_info_t::apply_implied_ext(riscv_subset_list*) const':
../../gcc/common/config/riscv/riscv-common.cc:248:31: error: possibly dangling r
eference to a temporary [-Werror=dangling-reference]
248 | const riscv_ex
On 5/16/25 11:21 AM, Richard Sandiford wrote:
One slightly awkward part about emitting the generator function
bodies is that:
* define_insn and define_expand routines have a separate argument for
each operand, named "operand0" upwards.
* define_split and define_peephole2 routines take a p
> Pengxuan Zheng writes:
> > diff --git a/gcc/testsuite/gcc.target/aarch64/fmov-3-le.c
> > b/gcc/testsuite/gcc.target/aarch64/fmov-3-le.c
> > new file mode 100644
> > index 000..adbf87243f6
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/fmov-3-le.c
> > @@ -0,0 +1,130 @@
> > +
> Pengxuan Zheng writes:
> > diff --git a/gcc/config/aarch64/aarch64.cc
> > b/gcc/config/aarch64/aarch64.cc index 15f08cebeb1..98ce85dfdae 100644
> > --- a/gcc/config/aarch64/aarch64.cc
> > +++ b/gcc/config/aarch64/aarch64.cc
> > @@ -23621,6 +23621,36 @@ aarch64_simd_valid_and_imm (rtx op)
> >
On 5/16/25 11:22 AM, Richard Sandiford wrote:
gen_exp had code to handle the 'L' operand format. But this format
is specifically for location_ts, which are only used in RTX_INSNs.
Those should never occur in this context, where the input is always
an md file rather than an __RTL function. An
On 5/16/25 11:22 AM, Richard Sandiford wrote:
gen_exp now has quite a few arguments that need to be passed
to each recursive call. This patch turns it and related routines
into member functions of a new generator class, so that the shared
information can be stored in member variables.
This a
> Pengxuan Zheng writes:
> **...
> **and v0.8b, (?:v0.8b, v[0-9]+.8b|v[0-9]+.8b, v0.8b)
> **ret
>
> Same for other tests that can't use a move immediate.
>
> Please leave 24 hours for others to comment on the target-independent
part,
> but otherwise the patch is ok with the chang
cpplib-15.1-b20250316.es.po.gz
Description: Binary data
The Translation Project robot, in the
name of your translation coordinator.
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'cpplib' has been submitted
by the Spanish team of translators. The file is available at:
https://translationproject.org/latest/cpplib/es.po
(This file, 'cpplib-15.1-b202503
On 5/16/25 11:21 AM, Richard Sandiford wrote:
Mostly to reduce cut-&-paste.
gcc/
* genemit.cc (start_gen_insn): New function, split out from...
(gen_insn, gen_expand): ...here.
OK
jeff
On 5/16/25 11:21 AM, Richard Sandiford wrote:
An earlier version of this series wanted to collect information
about all the gen_* functions that are going to be generated.
The current version no longer does that, but the queue seemed
worth keeping anyway, since it gives a more consistent struc
On 5/16/25 11:21 AM, Richard Sandiford wrote:
This patch makes genemit.cc pass the md_rtx_info around by constant
reference rather than pointer. It's somewhat of a cosmetic change
on its own, but it makes later changes less noisy.
gcc/
* genemit.cc (gen_exp): Make the info argument a
On 5/16/25 11:21 AM, Richard Sandiford wrote:
This pattern used operands[2] to hold the shift amount, even though
the pattern doesn't have an operand 2 (not even as a match_dup).
This caused a build failure with -Werror:
array subscript 2 is above array bounds of ‘rtx_def* [2]’
gcc/
On 5/16/25 11:21 AM, Richard Sandiford wrote:
The negsi2 C++ code writes to operands[2] even though the pattern
has no operand 2.
gcc/
* config/stormy16/stormy16.md (negsi2): Remove unused assignment.
Also obviously OK.
jeff
genemit has traditionally used open-coded gen_rtx_FOO sequences
to build up the instruction pattern. This is now the source of
quite a bit of bloat in the binary, and also a source of slow
compile times.
Two obvious ways of trying to deal with this are:
(1) Try to identify rtxes that have a simi
output_add_clobbers emits code to add:
(clobber (scratch:M))
and/or:
(clobber (reg:M R))
expressions to the end of a PARALLEL. At the moment, it does this
using the general gen_exp function. That makes sense with the code
in its current form, but with later patches it's more convenient to
gen_exp currently supports the 's' (string) operand type. It would
certainly be possible to make the upcoming bytecode patch support
that too. However, the rtx codes that have string operands should
be very rarely used in hard-coded define_insn/expand/split/peephole2
rtx templates (as opposed to
libstdc++-v3/ChangeLog:
* include/std/ranges (_ZipTransform::operator()): Remove name of
unused parameter.
(chunk_view::_Iterator, stride_view::_Iterator): Likewise.
(join_with_view): Declare _Iterator and _Sentinel as class
instead of struct.
(repea
[Thanks Jeff and Richard for the reviews of the end_sequence series.
This is the series that that one was written for.]
genemit has traditionally used open-coded gen_rtx_FOO sequences
to build up the instruction pattern. This is now the source of
quite a bit of bloat in the binary, and also a sou
Formatting of chrono::local_days with an empty chrono-specs should be
equivalent to inserting it into an ostream, which should use the
overload for inserting chrono::sys_days into an ostream. The
implementation of empty chrono-specs in _M_format_to_ostream takes some
short cuts, and that wasn't bei
gen_exp has code to detect when the same operand is used multiple
times. It ensures that second and subsequent uses call copy_rtx,
to enforce correct unsharing.
However, for historical reasons that aren't clear to me, this was
skipped for a define_insn unless the define_insn was a parallel.
It wa
gen_exp now has quite a few arguments that need to be passed
to each recursive call. This patch turns it and related routines
into member functions of a new generator class, so that the shared
information can be stored in member variables.
This also helps to make later patches less noisy.
gcc/
This patch makes genemit.cc pass the md_rtx_info around by constant
reference rather than pointer. It's somewhat of a cosmetic change
on its own, but it makes later changes less noisy.
gcc/
* genemit.cc (gen_exp): Make the info argument a constant reference.
(gen_emit_seq, gen_ins
Mostly to reduce cut-&-paste.
gcc/
* genemit.cc (start_gen_insn): New function, split out from...
(gen_insn, gen_expand): ...here.
---
gcc/genemit.cc | 45 ++---
1 file changed, 22 insertions(+), 23 deletions(-)
diff --git a/gcc/genemit.cc
One slightly awkward part about emitting the generator function
bodies is that:
* define_insn and define_expand routines have a separate argument for
each operand, named "operand0" upwards.
* define_split and define_peephole2 routines take a pointer to an array,
named "operands".
* the C++ p
gen_exp had code to handle the 'L' operand format. But this format
is specifically for location_ts, which are only used in RTX_INSNs.
Those should never occur in this context, where the input is always
an md file rather than an __RTL function. Any hard-coded raw
location value would be meaningles
An earlier version of this series wanted to collect information
about all the gen_* functions that are going to be generated.
The current version no longer does that, but the queue seemed
worth keeping anyway, since it gives a more consistent structure.
gcc/
* genemit.cc (queue): New stati
The negsi2 C++ code writes to operands[2] even though the pattern
has no operand 2.
gcc/
* config/stormy16/stormy16.md (negsi2): Remove unused assignment.
---
gcc/config/stormy16/stormy16.md | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/config/stormy16/stormy16
This series tweaks various aspects of genemit.cc so that they are
easier to change later. There should be no functional change.
Bootstrapped & regression-tested on aarch64-linux-gnu. Also tested
using config-list.mk to get cross-target coverage.
The series contains a couple of obvious target ch
This pattern used operands[2] to hold the shift amount, even though
the pattern doesn't have an operand 2 (not even as a match_dup).
This caused a build failure with -Werror:
array subscript 2 is above array bounds of ‘rtx_def* [2]’
gcc/
* config/nds32/nds32-intrinsic.md (unspec_get_pen
On Fri, May 16, 2025 at 9:49 AM Andrew Pinski wrote:
>
> On Fri, May 16, 2025 at 9:32 AM Icen Zeyada wrote:
> >
> > Merge simple_comparison patterns under a single vec_cond_expr for bit_and
> > and bit_ior in the simplify pass.
> >
> > Ensure that when both operands of a bit-and or bit-or are sim
Dimitar Dimitrov writes:
> After r16-160-ge6f89d78c1a752, late_combine2 started transforming the
> following RTL for pru-unknown-elf:
>
> (insn 3949 3948 3951 255 (set (reg:QI 56 r14.b0 [orig:1856 _619 ] [1856])
> (and:QI (reg:QI 1 r0.b1 [orig:1855 _201 ] [1855])
> (const
Hi Joseph,
On Fri, May 16, 2025 at 05:01:36PM +, Joseph Myers wrote:
> On Fri, 16 May 2025, Alejandro Colomar wrote:
>
> > Hmmm, I've been trying to find a compromise between readability and
> > simplicity, and I think I have something. I've seen some tests that
> > define assert() themselve
On Fri, 16 May 2025, Alejandro Colomar wrote:
> Hmmm, I've been trying to find a compromise between readability and
> simplicity, and I think I have something. I've seen some tests that
> define assert() themselves. I like assert(3) because it's more
> readable compared to a conditional plus abo
Dimitar Dimitrov writes:
> When a paradoxical subreg is detected, validate_subreg exits early, thus
> skipping the important checks later in the function.
>
> Fix by continuing with the checks instead of declaring early that the
> paradoxical subreg is valid.
>
> One of the newly allowed subsequen
Hi Joseph,
On Fri, May 16, 2025 at 12:25:39PM +, Joseph Myers wrote:
> On Fri, 16 May 2025, Alejandro Colomar wrote:
>
> > - Add (and NDEBUG) to some test files that were missing it,
> >and also the forward declaration of strcmp(3).
>
> Depending on libc headers like this in tests is d
Jennifer Schmitz writes:
> [PATCH] [PR120276] regcprop: Return from copy_value for unordered modes
>
> The ICE in PR120276 resulted from a comparison of VNx4QI and V8QI using
> partial_subreg_p in the function copy_value during the RTL pass
> regcprop, failing the assertion in
>
> inline bool
> pa
On Fri, May 16, 2025 at 9:32 AM Icen Zeyada wrote:
>
> Merge simple_comparison patterns under a single vec_cond_expr for bit_and
> and bit_ior in the simplify pass.
>
> Ensure that when both operands of a bit-and or bit-or are simple_comparison
> results, they reside within the same vec_cond_expr
Generalize existing scalar gimple_fold rules to apply the same
bitwise comparison simplifications to vector types. Previously, an
expression like
(x < y) && (x > y)
would fold to `false` if x and y are scalars, but equivalent vector
comparisons were left untouched. T
Merge simple_comparison patterns under a single vec_cond_expr for bit_and
and bit_ior in the simplify pass.
Ensure that when both operands of a bit-and or bit-or are simple_comparison
results, they reside within the same vec_cond_expr rather than separate ones.
This prepares the AST so that subseq
This patch generalizes existing scalar bitwise comparison simplifications to
vector types by matching patterns of the form
```
(cmp x y) bit_and (cmp x y)
(cmp x y) bit_ior (cmp x y)
```
for vector operands, it also enables contradictory comparisons like `(x < y) &&
(x > y)` to fold to `false`
On Thu, 15 May 2025, Jeff Law wrote:
> > > Address this issue by recursing into COMPONENT_REF tree nodes until the
> > > outermost one has been reached, which is supposed to be a MEM_REF one,
> > > accumulating the offset as we go, fixing a commit e0dae4da4c45 ("Alpha:
> > > Also use tree informat
0001-cobol-Eliminate-exception-blob-streamline-some-code-.patch
Description: Binary data
ChangeLog:
* MAINTAINERS: Add myself to write after approval.
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a3e3f25d9d1..8993d176c22 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -329,6 +329,7 @@ from other maintainers or reviewers.
N
On Wed, May 14, 2025 at 04:30:35PM +0200, Juergen Christ wrote:
> Since floating point and vector registers overlap on s390, more
> efficient code can be generated to extract FPRs from VRs.
> Additionally, for double vectors, more efficient code can be generated
> to load specific lanes.
>
> gcc/C
On 5/16/25 1:32 AM, Jin Ma wrote:
Reported-by: huangcunjian
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_gpr_save_operation_p): Remove
break and fixbug for elt index.
Ideally we'd have a testcase for whatever issue motivated this change,
but it's pretty clear that the elem
On 5/16/25 2:38 AM, pan2...@intel.com wrote:
From: Pan Li
Some of the previous scalar unsigned SAT_ADD test data are
duplicated in different test files. This patch would like to
move them into a shared header file, to avoid the test data
duplication.
The below test suites are passed for th
On Fri, May 16, 2025 at 4:10 AM Kito Cheng wrote:
>
> I am surprised that such generic names are defined within the system
> header files, I inclined just rename that to major_version,
> minor_version, could you send a patch for that?
major and minor come from extracting the major/minor parts of
On Fri, May 16, 2025 at 3:13 AM Richard Biener
wrote:
>
> On Fri, May 9, 2025 at 5:00 AM Andrew Pinski wrote:
> >
> > This removes the ability to follow statements that can throw internally.
> > This was suggested in bug report as a way to solve the issue here.
> > The overhead is not that high s
On 5/16/25 02:35, Richard Biener wrote:
On Thu, May 15, 2025 at 7:02 PM Andrew MacLeod wrote:
Recent changes to get_range_from_bitmask can sometimes turn a small
range into an undefined one if the bitmask indicates the bits make all
values impossible.
range_cast () was not expecting this and c
Hi Jason,
>>+ = build1_loc (loc, TRUTH_NOT_EXPR, boolean_type_node, iarc_x);
>>+ do_fr_cleanup = build2_loc (loc, TRUTH_AND_EXPR, boolean_type_node,
>>+ do_fr_cleanup, coro_before_return);
>This also needs reversing (and similarly below).
Fixed.
>>+ t
Hi Jason,
>>+ returned reference or prvalue result object ...
>>+ When we use a local to hold this, it is decltype(auto). */
>>+ tree gro_type
>>+= finish_decltype_type (get_ro, /*id_expression_or_member_access_p*/true,
>This should be false, not true; a call is not an id-expr or me
>>+ /* We must manage the cleanups ourselves, because the responsibility for
>>+ them changes after the initial suspend. However, any use of
>>+ cxx_maybe_build_cleanup () can set the throwing_cleanup flag. */
>>+ cp_function_chain->throwing_cleanup = false;
>Hmm...what if the gro clea
This patch implements C++26 function_ref as specified in P0792R14,
with correction for constraints for constructor accepting nontype_t
parameter from LWG 4256.
As function_ref may store a pointer to the const object, __Ptrs::_M_obj is
changed to const void*, so again we do not cast away const from
> On 16 May 2025, at 13:11, Kyrylo Tkachov wrote:
>
>
>
>> On 16 May 2025, at 12:35, Richard Sandiford
>> wrote:
>>
>> Jennifer Schmitz writes:
>>> The ICE in PR120276 resulted from a comparison of VNx4QI and V8QI using
>>> partial_subreg_p in the function copy_value during the RTL pass
>
Hi, Richard,
> On May 14, 2025, at 09:47, Richard Biener wrote:
>
> On Wed, May 14, 2025 at 3:24 PM Qing Zhao wrote:
>>
>> Hi,
>>
>> This patch set has been waiting for the Middle-end review for a very long
>> time since last year.
>>
>> Could you Please take a look and let me know whether
Add debugging for move history.
PR tree-optimization/109071
PR tree-optimization/85788
PR tree-optimization/88771
PR tree-optimization/106762
PR tree-optimization/108770
PR tree-optimization/115274
PR tree-optimization/117179
gcc/ChangeLog:
During array out-of-bound checking or -Wstringop-* warning checking, the
"move_history" that was attached to the gimple statement is used to form
a sequence of diagnostic events that are added to the corresponding rich
location to be used to report the warning message.
PR tree-optimization
Hi,
This is the 6th version of the patches for fixing PR109071.
Adding -fdiagnotics-details into GCC to provide more hints to the
end users on how the warnings come from, in order to help the user
to locate the exact location in source code on the specific warnings
due to compiler optimizations.
Control this with a new option -fdiagnostics-details.
$ cat t.c
extern void warn(void);
static inline void assign(int val, int *regs, int *index)
{
if (*index >= 4)
warn();
*regs = val;
}
struct nums {int vals[4];};
void sparx5_set (int *ptr, struct nums *sg, int index)
{
int *val = &sg
On Thu, 15 May 2025, Tomasz Kamiński wrote:
> This patch implements C++26 function_ref as specified in P0792R14,
> with correction for constraints for constructor accepting nontype_t
> parameter from LWG 4256.
>
> As function_ref may store a pointer to the const object, __Ptrs::_M_obj is
> change
On 5/16/25 9:14 AM, Nathaniel Shead wrote:
Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk?
OK.
-- >8 --
This patch removes some no longer needed special casing in linkage
determination, and makes the distinction between "always_emit" and
"internal" for better future-proofing
Bootstrapped and regtested on x86_64-pc-linux-gnu, OK for trunk?
-- >8 --
This patch removes some no longer needed special casing in linkage
determination, and makes the distinction between "always_emit" and
"internal" for better future-proofing.
gcc/cp/ChangeLog:
* module.cc (importer_
The rules for conditional branches were spread throughout `aarch64.md`.
Group them together so it is easier to understand how `cbranch4`
is lowered to RTL.
gcc/ChangeLog:
* config/aarch64/aarch64.md (condjump): Move.
(*compare_condjump): Likewise.
(aarch64_cb1): Likewise.
The CB family of instructions does not support using the CS or CC
condition codes; instead the synonyms HS and LO must be used. GCC has
traditionally used the CS and CC names. To work around this while
avoiding test churn, add new `j` and `J` format specifiers and use them
when generating CB instru
Make the formatting of the RTL templates in the rules for branch
instructions more consistent with each other.
gcc/ChangeLog:
* config/aarch64/aarch64.md (cbranch4): Reformat.
(cbranchcc4): Likewise.
(condjump): Likewise.
(*compare_condjump): Likewise.
(aar
On Fri, 16 May 2025, Alejandro Colomar wrote:
> - Add (and NDEBUG) to some test files that were missing it,
>and also the forward declaration of strcmp(3).
Depending on libc headers like this in tests is discouraged. The usual
idiom is to use abort () on failure of a runtime check (rather
Add rules for lowering `cbranch4` to CBB/CBH/CB when
CMPBR extension is enabled.
gcc/ChangeLog:
* config/aarch64/aarch64.md (BRANCH_LEN_P_1Kib): New constant.
(BRANCH_LEN_N_1Kib): Likewise.
(cbranch4): Emit CMPBR instructions if possible.
(cbranch4): New expand rul
Move the rules for CBZ/TBZ to be above the rules for
CBB/CBH/CB. We want them to have higher priority
because they can express larger displacements.
gcc/ChangeLog:
* config/aarch64/aarch64.md (aarch64_cbz1): Move
above rules for CBB/CBH/CB.
(*aarch64_tbz1): Likewise.
gcc/
Tested x86_64-pc-linux-gnu, applying to trunk.
-- 8< --
After my r16-670, running the testsuite with explicit --stds didn't run this
one in C++17 mode, but the default did. Let's remove the { target c++17 }
so it doesn't by default, either.
gcc/testsuite/ChangeLog:
* g++.dg/coroutines/
Give the `define_insn` rules used in lowering `cbranch4` to RTL
more descriptive and consistent names: from now on, each rule is named
after the AArch64 instruction that it generates. Also add comments to
document each rule.
gcc/ChangeLog:
* config/aarch64/aarch64.md (condjump): Rename to
This patch series adds support for the CMPBR extension. It includes the
new `+cmpbr` option and rules to generate the new instructions when
lowering conditional branches.
Testing done:
`make bootstrap; make check`
Karl Meakin (10):
AArch64: place branch instruction rules together
AArch64: ref
Commit the test file `cmpbr.c` before rules for generating the new
instructions are added, so that the changes in codegen are more obvious
in the next commit.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Add `cmpbr` to the list of extensions.
* gcc.target/aarch64/cmpbr.c: N
The `far_branch` attribute only ever takes the values 0 or 1, so make it
a `no/yes` valued string attribute instead.
gcc/ChangeLog:
* config/aarch64/aarch64.md (far_branch): Replace 0/1 with
no/yes.
(aarch64_bcond): Handle rename.
(aarch64_cbz1): Likewise.
Add the `+cmpbr` option to enable the FEAT_CMPBR architectural
extension.
gcc/ChangeLog:
* config/aarch64/aarch64-option-extensions.def (cmpbr): New
option.
* config/aarch64/aarch64.h (TARGET_CMPBR): New macro.
* doc/invoke.texi (cmpbr): New option.
---
gcc/config
Extract the hardcoded values for the minimum PC-relative displacements
into named constants and document them.
gcc/ChangeLog:
* config/aarch64/aarch64.md (BRANCH_LEN_P_128MiB): New constant.
(BRANCH_LEN_N_128MiB): Likewise.
(BRANCH_LEN_P_1MiB): Likewise.
(BRANCH_LE
On 5/15/25 4:58 PM, Ville Voutilainen wrote:
On Thu, 15 May 2025 at 18:32, Ville Voutilainen
wrote:
On Thu, 15 May 2025 at 18:19, Jason Merrill wrote:
@@ -3347,8 +3347,6 @@ cp_fold (tree x, fold_flags_t flags)
|| id_equal (DECL_NAME (callee), "as_const")))
{
On Wed, May 14, 2025 at 5:01 PM Andrew Pinski wrote:
>
> As sugguested in
> https://gcc.gnu.org/pipermail/gcc-patches/2025-April/681507.html,
> this adds the aliasing walk limit.
OK for both.
Thanks,
Richard.
> gcc/ChangeLog:
>
> * tree-ssa-forwprop.cc (optimize_memcpy_to_memset): Add
On Fri, 16 May 2025, Richard Sandiford wrote:
> Richard Biener writes:
> > Targets recently got the ability to request the vector mode to be
> > used for a vector epilogue (or the epilogue of a vector epilogue). The
> > following adds the ability for it to indicate the epilogue should use
> > lo
Richard Biener writes:
> On Wed, May 14, 2025 at 6:29 PM James K. Lowden
> wrote:
>>
>> On Wed, 14 May 2025 11:04:50 +0200
>> Rainer Orth wrote:
>>
>> > Work around what appears to be a GNU make bug handling MAKEFLAGS
>>
>> Before I say Yes, could someone please tell me why this rumored bug is
I was thinking of adding a vectorization_mode class that would
encapsulate the mode and whether to allow masking or alternatively
to make the vector_modes array (and the m_suggested_epilogue_mode)
a std::pair of mode and mask flag?
Without having a very strong opinion (or the full background) on
> On 16 May 2025, at 12:35, Richard Sandiford wrote:
>
> Jennifer Schmitz writes:
>> The ICE in PR120276 resulted from a comparison of VNx4QI and V8QI using
>> partial_subreg_p in the function copy_value during the RTL pass
>> regcprop, failing the assertion in
>>
>> inline bool
>> partial_su
I am surprised that such generic names are defined within the system
header files, I inclined just rename that to major_version,
minor_version, could you send a patch for that?
On Fri, May 16, 2025 at 3:50 PM Songhe Zhu wrote:
>
> Hi kito
> When syncing GCC to the master branch and building
For powerpc64 and sparc architectures that both have __float128 and 128bit long
double,
the __float128 is same type as long double/__iee128 and already formattable.
Remaining specializaiton make __float128 formattable on x86_64 via _Float128,
however __float128 is now not formattable on x86_32 (-
Richard Biener writes:
> Targets recently got the ability to request the vector mode to be
> used for a vector epilogue (or the epilogue of a vector epilogue). The
> following adds the ability for it to indicate the epilogue should use
> loop masking, irrespective of the --param vect-partial-vect
Targets recently got the ability to request the vector mode to be
used for a vector epilogue (or the epilogue of a vector epilogue). The
following adds the ability for it to indicate the epilogue should use
loop masking, irrespective of the --param vect-partial-vector-usage
setting.
The simple pr
Jennifer Schmitz writes:
> The ICE in PR120276 resulted from a comparison of VNx4QI and V8QI using
> partial_subreg_p in the function copy_value during the RTL pass
> regcprop, failing the assertion in
>
> inline bool
> partial_subreg_p (machine_mode outermode, machine_mode innermode)
> {
> /* M
On Mon, May 12, 2025 at 11:24 AM Eric Botcazou wrote:
>
> Hi,
>
> the function accepts all handled_component_p expressions and decodes them by
> means of get_inner_reference as expected, but bails out on bitfields:
>
> /* TODO: We can extract value of the small expression via shifting even
>
On Fri, May 9, 2025 at 5:00 AM Andrew Pinski wrote:
>
> This removes the ability to follow statements that can throw internally.
> This was suggested in bug report as a way to solve the issue here.
> The overhead is not that high since without non-call exceptions turned
> on, there is an early exi
On Tue, Apr 15, 2025 at 8:27 AM Eikansh Gupta wrote:
>
> The patterns can be simplified as shown below:
>
> (a != b) & ((a|b) != 0) -> (a != b)
> (a != b) | ((a|b) != 0) -> ((a|b) != 0)
>
> The similar simplification can be there for (a == b). This patch adds
> simplification for above patterns.
On Thu, May 15, 2025 at 5:55 AM Andrew Pinski wrote:
>
> On Wed, May 14, 2025 at 7:39 PM Andrew Pinski
> wrote:
> >
> > This is the next step in removing forward_propagate_into_comparison
> > and forward_propagate_into_gimple_cond; In the case of `((int)(a cmp b)) !=
> > 0`
> > we want to do th
> On 10 May 2025, at 06:17, Andrew Pinski wrote:
>
> Since the AARCH64_CORE defines in aarch64-cores.def all use -1 for
> the variant, it is just easier to add the cast to unsigned in the usage
> in driver-aarch64.cc.
>
> Build and tested on aarch64-linux-gnu.
Ok.
Thanks,
Kyrill
>
> gcc/Ch
> On 10 May 2025, at 05:59, Andrew Pinski wrote:
>
> There is a narrowing warning in aarch64_detect_vector_stmt_subtype
> about gather_load_x32_cost and gather_load_x64_cost converting from int to
> unsigned.
> These fields are always unsigned and even the constructor for sve_vec_cost
> take
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