Commit the test file `cmpbr.c` before rules for generating the new
instructions are added, so that the changes in codegen are more obvious
in the next commit.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Add `cmpbr` to the list of extensions.
* gcc.target/aarch64/cmpbr.c: New test.
---
gcc/testsuite/gcc.target/aarch64/cmpbr.c | 1659 ++++++++++++++++++++++
gcc/testsuite/lib/target-supports.exp | 14 +-
2 files changed, 1667 insertions(+), 6 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/cmpbr.c
diff --git a/gcc/testsuite/gcc.target/aarch64/cmpbr.c
b/gcc/testsuite/gcc.target/aarch64/cmpbr.c
new file mode 100644
index 00000000000..8534283bc26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cmpbr.c
@@ -0,0 +1,1659 @@
+// Test that the instructions added by FEAT_CMPBR are emitted
+// { dg-do compile }
+// { dg-do-if assemble { target aarch64_asm_cmpbr_ok } }
+// { dg-options "-march=armv9.5-a+cmpbr -O2" }
+// { dg-final { check-function-bodies "**" "" "" } }
+
+#include <stdint.h>
+
+typedef uint8_t u8;
+typedef int8_t i8;
+
+typedef uint16_t u16;
+typedef int16_t i16;
+
+typedef uint32_t u32;
+typedef int32_t i32;
+
+typedef uint64_t u64;
+typedef int64_t i64;
+
+int taken();
+int not_taken();
+
+#define COMPARE(ty, name, op, rhs)
\
+ int ty##_x0_##name##_##rhs(ty x0, ty x1) {
\
+ return (x0 op rhs) ? taken() : not_taken();
\
+ }
+
+#define COMPARE_ALL(unsigned_ty, signed_ty, rhs)
\
+ COMPARE(unsigned_ty, eq, ==, rhs);
\
+ COMPARE(unsigned_ty, ne, !=, rhs);
\
+
\
+ COMPARE(unsigned_ty, ult, <, rhs);
\
+ COMPARE(unsigned_ty, ule, <=, rhs);
\
+ COMPARE(unsigned_ty, ugt, >, rhs);
\
+ COMPARE(unsigned_ty, uge, >=, rhs);
\
+
\
+ COMPARE(signed_ty, slt, <, rhs);
\
+ COMPARE(signed_ty, sle, <=, rhs);
\
+ COMPARE(signed_ty, sgt, >, rhs);
\
+ COMPARE(signed_ty, sge, >=, rhs);
+
+// ==== CBB<cc> (register) ====
+COMPARE_ALL(u8, i8, x1);
+
+// ==== CBH<cc> (register) ====
+COMPARE_ALL(u16, i16, x1);
+
+// ==== CB<cc> (register) ====
+COMPARE_ALL(u32, i32, x1);
+COMPARE_ALL(u64, i64, x1);
+
+// ==== CB<cc> (immediate) ====
+COMPARE_ALL(u32, i32, 42);
+COMPARE_ALL(u64, i64, 42);
+
+// ==== Special cases ====
+// Comparisons against the immediate 0 can be done for all types,
+// because we can use the wzr/xzr register as one of the operands.
+// However, we should prefer to use CBZ/CBNZ or TBZ/TBNZ when possible,
+// because they have larger range.
+COMPARE_ALL(u8, i8, 0);
+COMPARE_ALL(u16, i16, 0);
+COMPARE_ALL(u32, i32, 0);
+COMPARE_ALL(u64, i64, 0);
+
+// CBB and CBH cannot have immediate operands.
+// Instead we have to do a MOV+CB.
+COMPARE_ALL(u8, i8, 42);
+COMPARE_ALL(u16, i16, 42);
+
+// 64 is out of the range for immediate operands (0 to 63).
+// * For 8/16-bit types, use a MOV+CB as above.
+// * For 32/64-bit types, use a CMP+B<cc> instead,
+// because B<cc> has a longer range than CB<cc>.
+COMPARE_ALL(u8, i8, 64);
+COMPARE_ALL(u16, i16, 64);
+COMPARE_ALL(u32, i32, 64);
+COMPARE_ALL(u64, i64, 64);
+
+// 4098 is out of the range for CMP (0 to 4095, optionally shifted by left by
12
+// bits), but it can be materialized in a single MOV.
+COMPARE_ALL(u16, i16, 4098);
+COMPARE_ALL(u32, i32, 4098);
+COMPARE_ALL(u64, i64, 4098);
+
+/*
+** u8_x0_eq_x1:
+** and w1, w1, 255
+** cmp w1, w0, uxtb
+** beq .L4
+** b not_taken
+** b taken
+*/
+
+/*
+** u8_x0_ne_x1:
+** and w1, w1, 255
+** cmp w1, w0, uxtb
+** beq .L6
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ult_x1:
+** and w1, w1, 255
+** cmp w1, w0, uxtb
+** bls .L8
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ule_x1:
+** and w1, w1, 255
+** cmp w1, w0, uxtb
+** bcc .L10
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ugt_x1:
+** and w1, w1, 255
+** cmp w1, w0, uxtb
+** bcs .L12
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_uge_x1:
+** and w1, w1, 255
+** cmp w1, w0, uxtb
+** bhi .L14
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_slt_x1:
+** sxtb w1, w1
+** cmp w1, w0, sxtb
+** ble .L16
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sle_x1:
+** sxtb w1, w1
+** cmp w1, w0, sxtb
+** blt .L18
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sgt_x1:
+** sxtb w1, w1
+** cmp w1, w0, sxtb
+** bge .L20
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sge_x1:
+** sxtb w1, w1
+** cmp w1, w0, sxtb
+** bgt .L22
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_eq_x1:
+** and w1, w1, 65535
+** cmp w1, w0, uxth
+** beq .L25
+** b not_taken
+** b taken
+*/
+
+/*
+** u16_x0_ne_x1:
+** and w1, w1, 65535
+** cmp w1, w0, uxth
+** beq .L27
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ult_x1:
+** and w1, w1, 65535
+** cmp w1, w0, uxth
+** bls .L29
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ule_x1:
+** and w1, w1, 65535
+** cmp w1, w0, uxth
+** bcc .L31
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ugt_x1:
+** and w1, w1, 65535
+** cmp w1, w0, uxth
+** bcs .L33
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_uge_x1:
+** and w1, w1, 65535
+** cmp w1, w0, uxth
+** bhi .L35
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_slt_x1:
+** sxth w1, w1
+** cmp w1, w0, sxth
+** ble .L37
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sle_x1:
+** sxth w1, w1
+** cmp w1, w0, sxth
+** blt .L39
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sgt_x1:
+** sxth w1, w1
+** cmp w1, w0, sxth
+** bge .L41
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sge_x1:
+** sxth w1, w1
+** cmp w1, w0, sxth
+** bgt .L43
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_eq_x1:
+** cmp w0, w1
+** beq .L46
+** b not_taken
+** b taken
+*/
+
+/*
+** u32_x0_ne_x1:
+** cmp w0, w1
+** beq .L48
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ult_x1:
+** cmp w0, w1
+** bcs .L50
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ule_x1:
+** cmp w0, w1
+** bhi .L52
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ugt_x1:
+** cmp w0, w1
+** bls .L54
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_uge_x1:
+** cmp w0, w1
+** bcc .L56
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_slt_x1:
+** cmp w0, w1
+** bge .L58
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sle_x1:
+** cmp w0, w1
+** bgt .L60
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sgt_x1:
+** cmp w0, w1
+** ble .L62
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sge_x1:
+** cmp w0, w1
+** blt .L64
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_eq_x1:
+** cmp x0, x1
+** beq .L67
+** b not_taken
+** b taken
+*/
+
+/*
+** u64_x0_ne_x1:
+** cmp x0, x1
+** beq .L69
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ult_x1:
+** cmp x0, x1
+** bcs .L71
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ule_x1:
+** cmp x0, x1
+** bhi .L73
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ugt_x1:
+** cmp x0, x1
+** bls .L75
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_uge_x1:
+** cmp x0, x1
+** bcc .L77
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_slt_x1:
+** cmp x0, x1
+** bge .L79
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sle_x1:
+** cmp x0, x1
+** bgt .L81
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sgt_x1:
+** cmp x0, x1
+** ble .L83
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sge_x1:
+** cmp x0, x1
+** blt .L85
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_eq_42:
+** cmp w0, 42
+** beq .L88
+** b not_taken
+** b taken
+*/
+
+/*
+** u32_x0_ne_42:
+** cmp w0, 42
+** beq .L90
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ult_42:
+** cmp w0, 41
+** bhi .L92
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ule_42:
+** cmp w0, 42
+** bhi .L94
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ugt_42:
+** cmp w0, 42
+** bls .L96
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_uge_42:
+** cmp w0, 41
+** bls .L98
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_slt_42:
+** cmp w0, 41
+** bgt .L100
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sle_42:
+** cmp w0, 42
+** bgt .L102
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sgt_42:
+** cmp w0, 42
+** ble .L104
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sge_42:
+** cmp w0, 41
+** ble .L106
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_eq_42:
+** cmp x0, 42
+** beq .L109
+** b not_taken
+** b taken
+*/
+
+/*
+** u64_x0_ne_42:
+** cmp x0, 42
+** beq .L111
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ult_42:
+** cmp x0, 41
+** bhi .L113
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ule_42:
+** cmp x0, 42
+** bhi .L115
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ugt_42:
+** cmp x0, 42
+** bls .L117
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_uge_42:
+** cmp x0, 41
+** bls .L119
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_slt_42:
+** cmp x0, 41
+** bgt .L121
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sle_42:
+** cmp x0, 42
+** bgt .L123
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sgt_42:
+** cmp x0, 42
+** ble .L125
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sge_42:
+** cmp x0, 41
+** ble .L127
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_eq_0:
+** tst w0, 255
+** bne .L129
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ne_0:
+** tst w0, 255
+** beq .L131
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ult_0:
+** b not_taken
+*/
+
+/*
+** u8_x0_ule_0:
+** tst w0, 255
+** bne .L134
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ugt_0:
+** tst w0, 255
+** beq .L136
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_uge_0:
+** b taken
+*/
+
+/*
+** i8_x0_slt_0:
+** tbnz w0, 7, .L140
+** b not_taken
+** b taken
+*/
+
+/*
+** i8_x0_sle_0:
+** sxtb w0, w0
+** cmp w0, 0
+** ble .L143
+** b not_taken
+** b taken
+*/
+
+/*
+** i8_x0_sgt_0:
+** sxtb w0, w0
+** cmp w0, 0
+** ble .L145
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sge_0:
+** tbnz w0, 7, .L147
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_eq_0:
+** tst w0, 65535
+** bne .L149
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ne_0:
+** tst w0, 65535
+** beq .L151
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ult_0:
+** b not_taken
+*/
+
+/*
+** u16_x0_ule_0:
+** tst w0, 65535
+** bne .L154
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ugt_0:
+** tst w0, 65535
+** beq .L156
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_uge_0:
+** b taken
+*/
+
+/*
+** i16_x0_slt_0:
+** tbnz w0, 15, .L160
+** b not_taken
+** b taken
+*/
+
+/*
+** i16_x0_sle_0:
+** sxth w0, w0
+** cmp w0, 0
+** ble .L163
+** b not_taken
+** b taken
+*/
+
+/*
+** i16_x0_sgt_0:
+** sxth w0, w0
+** cmp w0, 0
+** ble .L165
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sge_0:
+** tbnz w0, 15, .L167
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_eq_0:
+** cbnz w0, .L169
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ne_0:
+** cbz w0, .L171
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ult_0:
+** b not_taken
+*/
+
+/*
+** u32_x0_ule_0:
+** cbnz w0, .L174
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ugt_0:
+** cbz w0, .L176
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_uge_0:
+** b taken
+*/
+
+/*
+** i32_x0_slt_0:
+** tbnz w0, #31, .L180
+** b not_taken
+** b taken
+*/
+
+/*
+** i32_x0_sle_0:
+** cmp w0, 0
+** ble .L183
+** b not_taken
+** b taken
+*/
+
+/*
+** i32_x0_sgt_0:
+** cmp w0, 0
+** ble .L185
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sge_0:
+** tbnz w0, #31, .L187
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_eq_0:
+** cbnz x0, .L189
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ne_0:
+** cbz x0, .L191
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ult_0:
+** b not_taken
+*/
+
+/*
+** u64_x0_ule_0:
+** cbnz x0, .L194
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ugt_0:
+** cbz x0, .L196
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_uge_0:
+** b taken
+*/
+
+/*
+** i64_x0_slt_0:
+** tbnz x0, #63, .L200
+** b not_taken
+** b taken
+*/
+
+/*
+** i64_x0_sle_0:
+** cmp x0, 0
+** ble .L203
+** b not_taken
+** b taken
+*/
+
+/*
+** i64_x0_sgt_0:
+** cmp x0, 0
+** ble .L205
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sge_0:
+** tbnz x0, #63, .L207
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_eq_42:
+** and w0, w0, 255
+** cmp w0, 42
+** beq .L210
+** b not_taken
+** b taken
+*/
+
+/*
+** u8_x0_ne_42:
+** and w0, w0, 255
+** cmp w0, 42
+** beq .L212
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ult_42:
+** and w0, w0, 255
+** cmp w0, 41
+** bhi .L214
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ule_42:
+** and w0, w0, 255
+** cmp w0, 42
+** bhi .L216
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ugt_42:
+** and w0, w0, 255
+** cmp w0, 42
+** bls .L218
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_uge_42:
+** and w0, w0, 255
+** cmp w0, 41
+** bls .L220
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_slt_42:
+** sxtb w0, w0
+** cmp w0, 41
+** bgt .L222
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sle_42:
+** sxtb w0, w0
+** cmp w0, 42
+** bgt .L224
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sgt_42:
+** sxtb w0, w0
+** cmp w0, 42
+** ble .L226
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sge_42:
+** sxtb w0, w0
+** cmp w0, 41
+** ble .L228
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_eq_42:
+** and w0, w0, 65535
+** cmp w0, 42
+** beq .L231
+** b not_taken
+** b taken
+*/
+
+/*
+** u16_x0_ne_42:
+** and w0, w0, 65535
+** cmp w0, 42
+** beq .L233
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ult_42:
+** and w0, w0, 65535
+** cmp w0, 41
+** bhi .L235
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ule_42:
+** and w0, w0, 65535
+** cmp w0, 42
+** bhi .L237
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ugt_42:
+** and w0, w0, 65535
+** cmp w0, 42
+** bls .L239
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_uge_42:
+** and w0, w0, 65535
+** cmp w0, 41
+** bls .L241
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_slt_42:
+** sxth w0, w0
+** cmp w0, 41
+** bgt .L243
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sle_42:
+** sxth w0, w0
+** cmp w0, 42
+** bgt .L245
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sgt_42:
+** sxth w0, w0
+** cmp w0, 42
+** ble .L247
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sge_42:
+** sxth w0, w0
+** cmp w0, 41
+** ble .L249
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_eq_64:
+** and w0, w0, 255
+** cmp w0, 64
+** beq .L252
+** b not_taken
+** b taken
+*/
+
+/*
+** u8_x0_ne_64:
+** and w0, w0, 255
+** cmp w0, 64
+** beq .L254
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ult_64:
+** and w0, w0, 255
+** cmp w0, 63
+** bhi .L256
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ule_64:
+** and w0, w0, 255
+** cmp w0, 64
+** bhi .L258
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ugt_64:
+** and w0, w0, 255
+** cmp w0, 64
+** bls .L260
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_uge_64:
+** and w0, w0, 255
+** cmp w0, 63
+** bls .L262
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_slt_64:
+** sxtb w0, w0
+** cmp w0, 63
+** bgt .L264
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sle_64:
+** sxtb w0, w0
+** cmp w0, 64
+** bgt .L266
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sgt_64:
+** sxtb w0, w0
+** cmp w0, 64
+** ble .L268
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sge_64:
+** sxtb w0, w0
+** cmp w0, 63
+** ble .L270
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_eq_64:
+** and w0, w0, 65535
+** cmp w0, 64
+** beq .L273
+** b not_taken
+** b taken
+*/
+
+/*
+** u16_x0_ne_64:
+** and w0, w0, 65535
+** cmp w0, 64
+** beq .L275
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ult_64:
+** and w0, w0, 65535
+** cmp w0, 63
+** bhi .L277
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ule_64:
+** and w0, w0, 65535
+** cmp w0, 64
+** bhi .L279
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ugt_64:
+** and w0, w0, 65535
+** cmp w0, 64
+** bls .L281
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_uge_64:
+** and w0, w0, 65535
+** cmp w0, 63
+** bls .L283
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_slt_64:
+** sxth w0, w0
+** cmp w0, 63
+** bgt .L285
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sle_64:
+** sxth w0, w0
+** cmp w0, 64
+** bgt .L287
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sgt_64:
+** sxth w0, w0
+** cmp w0, 64
+** ble .L289
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sge_64:
+** sxth w0, w0
+** cmp w0, 63
+** ble .L291
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_eq_64:
+** cmp w0, 64
+** beq .L294
+** b not_taken
+** b taken
+*/
+
+/*
+** u32_x0_ne_64:
+** cmp w0, 64
+** beq .L296
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ult_64:
+** cmp w0, 63
+** bhi .L298
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ule_64:
+** cmp w0, 64
+** bhi .L300
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ugt_64:
+** cmp w0, 64
+** bls .L302
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_uge_64:
+** cmp w0, 63
+** bls .L304
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_slt_64:
+** cmp w0, 63
+** bgt .L306
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sle_64:
+** cmp w0, 64
+** bgt .L308
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sgt_64:
+** cmp w0, 64
+** ble .L310
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sge_64:
+** cmp w0, 63
+** ble .L312
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_eq_64:
+** cmp x0, 64
+** beq .L315
+** b not_taken
+** b taken
+*/
+
+/*
+** u64_x0_ne_64:
+** cmp x0, 64
+** beq .L317
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ult_64:
+** cmp x0, 63
+** bhi .L319
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ule_64:
+** cmp x0, 64
+** bhi .L321
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ugt_64:
+** cmp x0, 64
+** bls .L323
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_uge_64:
+** cmp x0, 63
+** bls .L325
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_slt_64:
+** cmp x0, 63
+** bgt .L327
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sle_64:
+** cmp x0, 64
+** bgt .L329
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sgt_64:
+** cmp x0, 64
+** ble .L331
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sge_64:
+** cmp x0, 63
+** ble .L333
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_eq_4098:
+** mov w1, 4098
+** cmp w1, w0, uxth
+** beq .L336
+** b not_taken
+** b taken
+*/
+
+/*
+** u16_x0_ne_4098:
+** mov w1, 4098
+** cmp w1, w0, uxth
+** beq .L338
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ult_4098:
+** mov w1, 4097
+** cmp w1, w0, uxth
+** bcc .L340
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ule_4098:
+** mov w1, 4098
+** cmp w1, w0, uxth
+** bcc .L342
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ugt_4098:
+** mov w1, 4098
+** cmp w1, w0, uxth
+** bcs .L344
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_uge_4098:
+** mov w1, 4097
+** cmp w1, w0, uxth
+** bcs .L346
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_slt_4098:
+** mov w1, 4097
+** cmp w1, w0, sxth
+** blt .L348
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sle_4098:
+** mov w1, 4098
+** cmp w1, w0, sxth
+** blt .L350
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sgt_4098:
+** mov w1, 4098
+** cmp w1, w0, sxth
+** bge .L352
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sge_4098:
+** mov w1, 4097
+** cmp w1, w0, sxth
+** bge .L354
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_eq_4098:
+** mov w1, 4098
+** cmp w0, w1
+** beq .L357
+** b not_taken
+** b taken
+*/
+
+/*
+** u32_x0_ne_4098:
+** mov w1, 4098
+** cmp w0, w1
+** beq .L359
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ult_4098:
+** mov w1, 4097
+** cmp w0, w1
+** bhi .L361
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ule_4098:
+** mov w1, 4098
+** cmp w0, w1
+** bhi .L363
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ugt_4098:
+** mov w1, 4098
+** cmp w0, w1
+** bls .L365
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_uge_4098:
+** mov w1, 4097
+** cmp w0, w1
+** bls .L367
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_slt_4098:
+** mov w1, 4097
+** cmp w0, w1
+** bgt .L369
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sle_4098:
+** mov w1, 4098
+** cmp w0, w1
+** bgt .L371
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sgt_4098:
+** mov w1, 4098
+** cmp w0, w1
+** ble .L373
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sge_4098:
+** mov w1, 4097
+** cmp w0, w1
+** ble .L375
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_eq_4098:
+** mov x1, 4098
+** cmp x0, x1
+** beq .L378
+** b not_taken
+** b taken
+*/
+
+/*
+** u64_x0_ne_4098:
+** mov x1, 4098
+** cmp x0, x1
+** beq .L380
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ult_4098:
+** mov x1, 4097
+** cmp x0, x1
+** bhi .L382
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ule_4098:
+** mov x1, 4098
+** cmp x0, x1
+** bhi .L384
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ugt_4098:
+** mov x1, 4098
+** cmp x0, x1
+** bls .L386
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_uge_4098:
+** mov x1, 4097
+** cmp x0, x1
+** bls .L388
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_slt_4098:
+** mov x1, 4097
+** cmp x0, x1
+** bgt .L390
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sle_4098:
+** mov x1, 4098
+** cmp x0, x1
+** bgt .L392
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sgt_4098:
+** mov x1, 4098
+** cmp x0, x1
+** ble .L394
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sge_4098:
+** mov x1, 4097
+** cmp x0, x1
+** ble .L396
+** b taken
+** b not_taken
+*/
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index e0495d8437c..de6f48e38b7 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -12381,21 +12381,23 @@ proc check_effective_target_aarch64_tiny { } {
# Create functions to check that the AArch64 assembler supports the
# various architecture extensions via the .arch_extension pseudo-op.
-foreach { aarch64_ext } { "fp" "simd" "crypto" "crc" "lse" "dotprod" "sve"
- "i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" "ls64"
- "lut" "sme" "sme-i16i64" "sme2" "sve-b16b16"
- "sme-b16b16" "sme-f16f16" "sme2p1" "fp8" "fp8fma"
- "ssve-fp8fma" "fp8dot2" "ssve-fp8dot2" "fp8dot4"
- "ssve-fp8dot4"} {
+set exts {
+ "bf16" "cmpbr" "crc" "crypto" "dotprod" "f32mm" "f64mm" "fp" "fp8"
+ "fp8dot2" "fp8dot4" "fp8fma" "i8mm" "ls64" "lse" "lut" "sb" "simd"
+ "sme-b16b16" "sme-f16f16" "sme-i16i64" "sme" "sme2" "sme2p1" "ssve-fp8dot2"
+ "ssve-fp8dot4" "ssve-fp8fma" "sve-b16b16" "sve" "sve2"
+}
+
+foreach { aarch64_ext } $exts {
eval [string map [list FUNC $aarch64_ext] {
proc check_effective_target_aarch64_asm_FUNC_ok { } {
if { [istarget aarch64*-*-*] } {
return [check_no_compiler_messages aarch64_FUNC_assembler
object {
__asm__ (".arch_extension FUNC");
} "-march=armv8-a+FUNC"]
} else {
return 0
}
}
}]
}
--
2.45.2
