The CB<cond> family of instructions does not support using the CS or CC
condition codes; instead the synonyms HS and LO must be used. GCC has
traditionally used the CS and CC names. To work around this while
avoiding test churn, add new `j` and `J` format specifiers and use them
when generating CB<cond> instructions.
Also reformat the definition of the `aarch64_cond_code` enum while we're
in the same neighbourhood, to make the relationship between each code
and its inverse more obvious.
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_cond_code): Reformat.
(aarch64_print_operand): Add new 'j' and 'J' format specifiers.
* config/aarch64/aarch64.md: Use new specifiers.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/cmpbr.c: Update tests.
---
gcc/config/aarch64/aarch64.cc | 35 ++++++++++++++++++------
gcc/config/aarch64/aarch64.md | 4 +--
gcc/testsuite/gcc.target/aarch64/cmpbr.c | 16 +++++------
3 files changed, 37 insertions(+), 18 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 5000672e4a2..9ab324cb2ec 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -913,11 +913,17 @@ static const scoped_attribute_specs *const
aarch64_attribute_table[] =
&aarch64_arm_attribute_table
};
-typedef enum aarch64_cond_code
-{
- AARCH64_EQ = 0, AARCH64_NE, AARCH64_CS, AARCH64_CC, AARCH64_MI, AARCH64_PL,
- AARCH64_VS, AARCH64_VC, AARCH64_HI, AARCH64_LS, AARCH64_GE, AARCH64_LT,
- AARCH64_GT, AARCH64_LE, AARCH64_AL, AARCH64_NV
+/* The condition codes come in opposing pairs. To get the inverse of a given
+ condition, simply flip the LSB. */
+typedef enum aarch64_cond_code {
+ AARCH64_EQ = 0x00, AARCH64_NE = 0x01,
+ AARCH64_CS = 0x02, AARCH64_CC = 0x03,
+ AARCH64_MI = 0x04, AARCH64_PL = 0x05,
+ AARCH64_VS = 0x06, AARCH64_VC = 0x07,
+ AARCH64_HI = 0x08, AARCH64_LS = 0x09,
+ AARCH64_GE = 0x0A, AARCH64_LT = 0x0B,
+ AARCH64_GT = 0x0C, AARCH64_LE = 0x0D,
+ AARCH64_AL = 0x0E, AARCH64_NV = 0x0F,
}
aarch64_cc;
@@ -12289,64 +12295,67 @@ static char
sizetochar (int size)
{
switch (size)
{
case 64: return 'd';
case 32: return 's';
case 16: return 'h';
case 8: return 'b';
default: gcc_unreachable ();
}
}
/* Print operand X to file F in a target specific manner according to CODE.
The acceptable formatting commands given by CODE are:
'c': An integer or symbol address without a preceding #
sign.
'C': Take the duplicated element in a vector constant
and print it in hex.
'D': Take the duplicated element in a vector constant
and print it as an unsigned integer, in decimal.
'e': Print the sign/zero-extend size as a character 8->b,
16->h, 32->w. Can also be used for masks:
0xff->b, 0xffff->h, 0xffffffff->w.
'I': If the operand is a duplicated vector constant,
replace it with the duplicated scalar. If the
operand is then a floating-point constant, replace
it with the integer bit representation. Print the
transformed constant as a signed decimal number.
'p': Prints N such that 2^N == X (X must be power of 2 and
const int).
'P': Print the number of non-zero bits in X (a const_int).
'H': Print the higher numbered register of a pair (TImode)
of regs.
'm': Print a condition (eq, ne, etc).
'M': Same as 'm', but invert condition.
+ 'j': Same as 'm', but use use `hs` and `lo`
+ instead of `cs` and `cc`.
+ 'J': Same as 'j', but invert condition.
'N': Take the duplicated element in a vector constant
and print the negative of it in decimal.
'b/h/s/d/q': Print a scalar FP/SIMD register name.
'Z': Same for SVE registers. ('z' was already taken.)
Note that it is not necessary to use %Z for operands
that have SVE modes. The convention is to use %Z
only for non-SVE (or potentially non-SVE) modes.
'S/T/U/V': Print a FP/SIMD register name for a register
list.
The register printed is the FP/SIMD register name
of X + 0/1/2/3 for S/T/U/V.
'R': Print a scalar Integer/FP/SIMD register name + 1.
'X': Print bottom 16 bits of integer constant in hex.
'w/x': Print a general register name or the zero register
(32-bit or 64-bit).
'0': Print a normal operand, if it's a general register,
then we assume DImode.
'k': Print NZCV for conditional compare instructions.
'K': Print a predicate register as pn<N> rather than p<N>
'A': Output address constant representing the first
argument of X, specifying a relocation offset
if appropriate.
'L': Output constant address specified by X
with a relocation offset if appropriate.
'G': Prints address of X, specifying a PC relative
relocation mode if appropriate.
'y': Output address of LDP or STP - this is used for
some LDP/STPs which don't use a PARALLEL in their
pattern (so the mode needs to be adjusted).
'z': Output address of a typical LDP or STP. */
@@ -12355,494 +12364,504 @@ static void
aarch64_print_operand (FILE *f, rtx x, int code)
{
rtx elt;
switch (code)
{
case 'c':
if (CONST_INT_P (x))
fprintf (f, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
else
{
poly_int64 offset;
rtx base = strip_offset_and_salt (x, &offset);
if (SYMBOL_REF_P (base))
output_addr_const (f, x);
else
output_operand_lossage ("unsupported operand for code '%c'", code);
}
break;
case 'e':
{
x = unwrap_const_vec_duplicate (x);
if (!CONST_INT_P (x))
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
HOST_WIDE_INT val = INTVAL (x);
if ((val & ~7) == 8 || val == 0xff)
fputc ('b', f);
else if ((val & ~7) == 16 || val == 0xffff)
fputc ('h', f);
else if ((val & ~7) == 32 || val == 0xffffffff)
fputc ('w', f);
else
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
}
break;
case 'p':
{
int n;
if (!CONST_INT_P (x) || (n = exact_log2 (INTVAL (x))) < 0)
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
asm_fprintf (f, "%d", n);
}
break;
case 'P':
if (!CONST_INT_P (x))
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
asm_fprintf (f, "%u", popcount_hwi (INTVAL (x)));
break;
case 'H':
if (x == const0_rtx)
{
asm_fprintf (f, "xzr");
break;
}
if (!REG_P (x) || !GP_REGNUM_P (REGNO (x) + 1))
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
asm_fprintf (f, "%s", reg_names [REGNO (x) + 1]);
break;
case 'I':
{
x = aarch64_bit_representation (unwrap_const_vec_duplicate (x));
if (CONST_INT_P (x))
asm_fprintf (f, "%wd", INTVAL (x));
else
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
break;
}
case 'M':
case 'm':
+ case 'j':
+ case 'J':
{
int cond_code;
/* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
if (x == const_true_rtx)
{
- if (code == 'M')
+ if (code == 'M' || code == 'J')
fputs ("nv", f);
return;
}
if (!COMPARISON_P (x))
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
cond_code = aarch64_get_condition_code (x);
gcc_assert (cond_code >= 0);
- if (code == 'M')
+ if (code == 'M' || code == 'J')
cond_code = AARCH64_INVERSE_CONDITION_CODE (cond_code);
if (GET_MODE (XEXP (x, 0)) == CC_NZCmode)
fputs (aarch64_sve_condition_codes[cond_code], f);
else
- fputs (aarch64_condition_codes[cond_code], f);
+ {
+ auto name = aarch64_condition_codes[cond_code];
+ if (code == 'j' || code == 'J')
+ {
+ if (cond_code == AARCH64_CS) name = "hs";
+ if (cond_code == AARCH64_CC) name = "lo";
+ }
+ fputs (name, f);
+ }
}
break;
case 'N':
if (!const_vec_duplicate_p (x, &elt))
{
output_operand_lossage ("invalid vector constant");
return;
}
if (GET_MODE_CLASS (GET_MODE (x)) == MODE_VECTOR_INT)
asm_fprintf (f, "%wd", (HOST_WIDE_INT) -UINTVAL (elt));
else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_VECTOR_FLOAT
&& aarch64_print_vector_float_operand (f, x, true))
;
else
{
output_operand_lossage ("invalid vector constant");
return;
}
break;
case 'b':
case 'h':
case 's':
case 'd':
case 'q':
case 'Z':
code = TOLOWER (code);
if (!REG_P (x) || !FP_REGNUM_P (REGNO (x)))
{
output_operand_lossage ("incompatible floating point / vector
register operand for '%%%c'", code);
return;
}
asm_fprintf (f, "%c%d", code, REGNO (x) - V0_REGNUM);
break;
case 'S':
case 'T':
case 'U':
case 'V':
if (!REG_P (x) || (!FP_REGNUM_P (REGNO (x)) && !PR_REGNUM_P (REGNO (x))))
{
output_operand_lossage ("incompatible operand for '%%%c'", code);
return;
}
if (PR_REGNUM_P (REGNO (x)))
asm_fprintf (f, "p%d", REGNO (x) - P0_REGNUM + (code - 'S'));
else
asm_fprintf (f, "%c%d",
aarch64_sve_data_mode_p (GET_MODE (x)) ? 'z' : 'v',
REGNO (x) - V0_REGNUM + (code - 'S'));
break;
case 'R':
if (REG_P (x) && FP_REGNUM_P (REGNO (x))
&& (aarch64_advsimd_partial_struct_mode_p (GET_MODE (x))))
asm_fprintf (f, "d%d", REGNO (x) - V0_REGNUM + 1);
else if (REG_P (x) && FP_REGNUM_P (REGNO (x)))
asm_fprintf (f, "q%d", REGNO (x) - V0_REGNUM + 1);
else if (REG_P (x) && GP_REGNUM_P (REGNO (x)))
asm_fprintf (f, "x%d", REGNO (x) - R0_REGNUM + 1);
else
output_operand_lossage ("incompatible register operand for '%%%c'",
code);
break;
case 'X':
if (!CONST_INT_P (x))
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
asm_fprintf (f, "0x%wx", UINTVAL (x) & 0xffff);
break;
case 'C':
{
/* Print a replicated constant in hex. */
if (!const_vec_duplicate_p (x, &elt) || !CONST_INT_P (elt))
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
scalar_mode inner_mode = GET_MODE_INNER (GET_MODE (x));
asm_fprintf (f, "0x%wx", UINTVAL (elt) & GET_MODE_MASK (inner_mode));
}
break;
case 'D':
{
/* Print a replicated constant in decimal, treating it as
unsigned. */
if (!const_vec_duplicate_p (x, &elt) || !CONST_INT_P (elt))
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
scalar_mode inner_mode = GET_MODE_INNER (GET_MODE (x));
asm_fprintf (f, "%wd", UINTVAL (elt) & GET_MODE_MASK (inner_mode));
}
break;
case 'w':
case 'x':
if (aarch64_const_zero_rtx_p (x))
{
asm_fprintf (f, "%czr", code);
break;
}
if (REG_P (x) && GP_REGNUM_P (REGNO (x)))
{
asm_fprintf (f, "%c%d", code, REGNO (x) - R0_REGNUM);
break;
}
if (REG_P (x) && REGNO (x) == SP_REGNUM)
{
asm_fprintf (f, "%ssp", code == 'w' ? "w" : "");
break;
}
/* Fall through */
case 0:
if (x == NULL)
{
output_operand_lossage ("missing operand");
return;
}
switch (GET_CODE (x))
{
case CONST_STRING:
{
asm_fprintf (f, "%s", XSTR (x, 0));
break;
}
case REG:
if (aarch64_sve_data_mode_p (GET_MODE (x)))
{
if (REG_NREGS (x) == 1)
asm_fprintf (f, "z%d", REGNO (x) - V0_REGNUM);
else
{
char suffix
= sizetochar (GET_MODE_UNIT_BITSIZE (GET_MODE (x)));
asm_fprintf (f, "{z%d.%c - z%d.%c}",
REGNO (x) - V0_REGNUM, suffix,
END_REGNO (x) - V0_REGNUM - 1, suffix);
}
}
else
asm_fprintf (f, "%s", reg_names [REGNO (x)]);
break;
case MEM:
output_address (GET_MODE (x), XEXP (x, 0));
break;
case LABEL_REF:
case SYMBOL_REF:
output_addr_const (asm_out_file, x);
break;
case CONST_INT:
asm_fprintf (f, "%wd", INTVAL (x));
break;
case CONST:
if (!VECTOR_MODE_P (GET_MODE (x)))
{
output_addr_const (asm_out_file, x);
break;
}
/* fall through */
case CONST_VECTOR:
if (!const_vec_duplicate_p (x, &elt))
{
output_operand_lossage ("invalid vector constant");
return;
}
if (GET_MODE_CLASS (GET_MODE (x)) == MODE_VECTOR_INT)
asm_fprintf (f, "%wd", INTVAL (elt));
else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_VECTOR_FLOAT
&& aarch64_print_vector_float_operand (f, x, false))
;
else
{
output_operand_lossage ("invalid vector constant");
return;
}
break;
case CONST_DOUBLE:
/* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
be getting CONST_DOUBLEs holding integers. */
gcc_assert (GET_MODE (x) != VOIDmode);
if (aarch64_float_const_zero_rtx_p (x))
{
fputc ('0', f);
break;
}
else if (aarch64_float_const_representable_p (x))
{
#define buf_size 20
char float_buf[buf_size] = {'\0'};
real_to_decimal_for_mode (float_buf,
CONST_DOUBLE_REAL_VALUE (x),
buf_size, buf_size,
1, GET_MODE (x));
asm_fprintf (asm_out_file, "%s", float_buf);
break;
#undef buf_size
}
output_operand_lossage ("invalid constant");
return;
default:
output_operand_lossage ("invalid operand");
return;
}
break;
case 'A':
if (GET_CODE (x) == HIGH)
x = XEXP (x, 0);
switch (aarch64_classify_symbolic_expression (x))
{
case SYMBOL_SMALL_GOT_4G:
asm_fprintf (asm_out_file, ":got:");
break;
case SYMBOL_SMALL_TLSGD:
asm_fprintf (asm_out_file, ":tlsgd:");
break;
case SYMBOL_SMALL_TLSDESC:
asm_fprintf (asm_out_file, ":tlsdesc:");
break;
case SYMBOL_SMALL_TLSIE:
asm_fprintf (asm_out_file, ":gottprel:");
break;
case SYMBOL_TLSLE24:
asm_fprintf (asm_out_file, ":tprel:");
break;
case SYMBOL_TINY_GOT:
gcc_unreachable ();
break;
default:
break;
}
output_addr_const (asm_out_file, x);
break;
case 'L':
switch (aarch64_classify_symbolic_expression (x))
{
case SYMBOL_SMALL_GOT_4G:
asm_fprintf (asm_out_file, ":got_lo12:");
break;
case SYMBOL_SMALL_TLSGD:
asm_fprintf (asm_out_file, ":tlsgd_lo12:");
break;
case SYMBOL_SMALL_TLSDESC:
asm_fprintf (asm_out_file, ":tlsdesc_lo12:");
break;
case SYMBOL_SMALL_TLSIE:
asm_fprintf (asm_out_file, ":gottprel_lo12:");
break;
case SYMBOL_TLSLE12:
asm_fprintf (asm_out_file, ":tprel_lo12:");
break;
case SYMBOL_TLSLE24:
asm_fprintf (asm_out_file, ":tprel_lo12_nc:");
break;
case SYMBOL_TINY_GOT:
asm_fprintf (asm_out_file, ":got:");
break;
case SYMBOL_TINY_TLSIE:
asm_fprintf (asm_out_file, ":gottprel:");
break;
default:
break;
}
output_addr_const (asm_out_file, x);
break;
case 'G':
switch (aarch64_classify_symbolic_expression (x))
{
case SYMBOL_TLSLE24:
asm_fprintf (asm_out_file, ":tprel_hi12:");
break;
default:
break;
}
output_addr_const (asm_out_file, x);
break;
case 'k':
{
HOST_WIDE_INT cond_code;
if (!CONST_INT_P (x))
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
cond_code = INTVAL (x);
gcc_assert (cond_code >= 0 && cond_code <= AARCH64_NV);
asm_fprintf (f, "%d", aarch64_nzcv_codes[cond_code]);
}
break;
case 'K':
if (!REG_P (x) || !PR_REGNUM_P (REGNO (x)))
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
asm_fprintf (f, "pn%d", REGNO (x) - P0_REGNUM);
break;
case 'y':
case 'z':
{
machine_mode mode = GET_MODE (x);
if (!MEM_P (x)
|| (code == 'y'
&& maybe_ne (GET_MODE_SIZE (mode), 8)
&& maybe_ne (GET_MODE_SIZE (mode), 16)
&& maybe_ne (GET_MODE_SIZE (mode), 32)))
{
output_operand_lossage ("invalid operand for '%%%c'", code);
return;
}
if (!aarch64_print_address_internal (f, mode, XEXP (x, 0),
code == 'y'
? ADDR_QUERY_LDP_STP_N
: ADDR_QUERY_LDP_STP))
output_operand_lossage ("invalid operand prefix '%%%c'", code);
}
break;
default:
output_operand_lossage ("invalid operand prefix '%%%c'", code);
return;
}
}
/* Print address 'x' of a memory access with mode 'mode'.
'op' is the context required by aarch64_classify_address. It can either be
MEM for a normal memory access or PARALLEL for LDP/STP. */
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index d3514ff1ef9..3f236141ab1 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -865,56 +865,56 @@ (define_insn "*aarch64_tbz<optab><mode>1"
;; Emit a `CB<cond> (register)` or `CB<cond> (immediate)` instruction.
;; Only immediates in the range 0-63 are supported.
;; Comparisons against immediates outside this range fall back to
;; CMP + B<cond>.
(define_insn "aarch64_cb<GPI:mode>"
[(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
[(match_operand:GPI 1 "register_operand" "r")
(match_operand:GPI 2 "aarch64_cb_operand" "ri")])
(label_ref (match_operand 3))
(pc)))]
"TARGET_CMPBR"
- "cb%m0\\t%<w>1, %<w>2, %l3";
+ "cb%j0\\t%<w>1, %<w>2, %l3";
[(set_attr "type" "branch")
(set (attr "length")
(if_then_else (and (ge (minus (match_dup 3) (pc))
(const_int BRANCH_LEN_N_1Kib))
(lt (minus (match_dup 3) (pc))
(const_int BRANCH_LEN_P_1Kib)))
(const_int 4)
(const_int 8)))
(set (attr "far_branch")
(if_then_else (and (ge (minus (match_dup 3) (pc))
(const_int BRANCH_LEN_N_1Kib))
(lt (minus (match_dup 3) (pc))
(const_int BRANCH_LEN_P_1Kib)))
(const_string "no")
(const_string "yes")))]
)
;; Emit a `CBB<cond> (register)` or `CBH<cond> (register)` instruction.
(define_insn "aarch64_cb<SHORT:mode>"
[(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
[(match_operand:SHORT 1 "register_operand" "r")
(match_operand:SHORT 2 "aarch64_cb_short_operand"
"rZ")])
(label_ref (match_operand 3))
(pc)))]
"TARGET_CMPBR"
- "cb<SHORT:cmpbr_suffix>%m0\\t%<w>1, %<w>2, %l3"
+ "cb<SHORT:cmpbr_suffix>%j0\\t%<w>1, %<w>2, %l3"
[(set_attr "type" "branch")
(set (attr "length")
(if_then_else (and (ge (minus (match_dup 3) (pc))
(const_int BRANCH_LEN_N_1Kib))
(lt (minus (match_dup 3) (pc))
(const_int BRANCH_LEN_P_1Kib)))
(const_int 4)
(const_int 8)))
(set (attr "far_branch")
(if_then_else (and (ge (minus (match_dup 3) (pc))
(const_int BRANCH_LEN_N_1Kib))
(lt (minus (match_dup 3) (pc))
(const_int BRANCH_LEN_P_1Kib)))
(const_string "no")
(const_string "yes")))]
)
;; Emit `B<cond>`, assuming that the condition is already in the CC register.
diff --git a/gcc/testsuite/gcc.target/aarch64/cmpbr.c
b/gcc/testsuite/gcc.target/aarch64/cmpbr.c
index 62448214892..dc3f2b5eb55 100644
--- a/gcc/testsuite/gcc.target/aarch64/cmpbr.c
+++ b/gcc/testsuite/gcc.target/aarch64/cmpbr.c
@@ -85,1397 +85,1397 @@ COMPARE_ALL(u32, i32, 4098);
COMPARE_ALL(u64, i64, 4098);
/*
** u8_x0_eq_x1:
** cbbeq w1, w0, .L4
** b not_taken
** b taken
*/
/*
** u8_x0_ne_x1:
** cbbeq w1, w0, .L6
** b taken
** b not_taken
*/
/*
** u8_x0_ult_x1:
** cbbls w1, w0, .L8
** b taken
** b not_taken
*/
/*
** u8_x0_ule_x1:
-** cbbcc w1, w0, .L10
+** cbblo w1, w0, .L10
** b taken
** b not_taken
*/
/*
** u8_x0_ugt_x1:
-** cbbcs w1, w0, .L12
+** cbbhs w1, w0, .L12
** b taken
** b not_taken
*/
/*
** u8_x0_uge_x1:
** cbbhi w1, w0, .L14
** b taken
** b not_taken
*/
/*
** i8_x0_slt_x1:
** cbble w1, w0, .L16
** b taken
** b not_taken
*/
/*
** i8_x0_sle_x1:
** cbblt w1, w0, .L18
** b taken
** b not_taken
*/
/*
** i8_x0_sgt_x1:
** cbbge w1, w0, .L20
** b taken
** b not_taken
*/
/*
** i8_x0_sge_x1:
** cbbgt w1, w0, .L22
** b taken
** b not_taken
*/
/*
** u16_x0_eq_x1:
** cbheq w1, w0, .L25
** b not_taken
** b taken
*/
/*
** u16_x0_ne_x1:
** cbheq w1, w0, .L27
** b taken
** b not_taken
*/
/*
** u16_x0_ult_x1:
** cbhls w1, w0, .L29
** b taken
** b not_taken
*/
/*
** u16_x0_ule_x1:
-** cbhcc w1, w0, .L31
+** cbhlo w1, w0, .L31
** b taken
** b not_taken
*/
/*
** u16_x0_ugt_x1:
-** cbhcs w1, w0, .L33
+** cbhhs w1, w0, .L33
** b taken
** b not_taken
*/
/*
** u16_x0_uge_x1:
** cbhhi w1, w0, .L35
** b taken
** b not_taken
*/
/*
** i16_x0_slt_x1:
** cbhle w1, w0, .L37
** b taken
** b not_taken
*/
/*
** i16_x0_sle_x1:
** cbhlt w1, w0, .L39
** b taken
** b not_taken
*/
/*
** i16_x0_sgt_x1:
** cbhge w1, w0, .L41
** b taken
** b not_taken
*/
/*
** i16_x0_sge_x1:
** cbhgt w1, w0, .L43
** b taken
** b not_taken
*/
/*
** u32_x0_eq_x1:
** cbeq w0, w1, .L46
** b not_taken
** b taken
*/
/*
** u32_x0_ne_x1:
** cbeq w0, w1, .L48
** b taken
** b not_taken
*/
/*
** u32_x0_ult_x1:
-** cbcs w0, w1, .L50
+** cbhs w0, w1, .L50
** b taken
** b not_taken
*/
/*
** u32_x0_ule_x1:
** cbhi w0, w1, .L52
** b taken
** b not_taken
*/
/*
** u32_x0_ugt_x1:
** cbls w0, w1, .L54
** b taken
** b not_taken
*/
/*
** u32_x0_uge_x1:
-** cbcc w0, w1, .L56
+** cblo w0, w1, .L56
** b taken
** b not_taken
*/
/*
** i32_x0_slt_x1:
** cbge w0, w1, .L58
** b taken
** b not_taken
*/
/*
** i32_x0_sle_x1:
** cbgt w0, w1, .L60
** b taken
** b not_taken
*/
/*
** i32_x0_sgt_x1:
** cble w0, w1, .L62
** b taken
** b not_taken
*/
/*
** i32_x0_sge_x1:
** cblt w0, w1, .L64
** b taken
** b not_taken
*/
/*
** u64_x0_eq_x1:
** cbeq x0, x1, .L67
** b not_taken
** b taken
*/
/*
** u64_x0_ne_x1:
** cbeq x0, x1, .L69
** b taken
** b not_taken
*/
/*
** u64_x0_ult_x1:
-** cbcs x0, x1, .L71
+** cbhs x0, x1, .L71
** b taken
** b not_taken
*/
/*
** u64_x0_ule_x1:
** cbhi x0, x1, .L73
** b taken
** b not_taken
*/
/*
** u64_x0_ugt_x1:
** cbls x0, x1, .L75
** b taken
** b not_taken
*/
/*
** u64_x0_uge_x1:
-** cbcc x0, x1, .L77
+** cblo x0, x1, .L77
** b taken
** b not_taken
*/
/*
** i64_x0_slt_x1:
** cbge x0, x1, .L79
** b taken
** b not_taken
*/
/*
** i64_x0_sle_x1:
** cbgt x0, x1, .L81
** b taken
** b not_taken
*/
/*
** i64_x0_sgt_x1:
** cble x0, x1, .L83
** b taken
** b not_taken
*/
/*
** i64_x0_sge_x1:
** cblt x0, x1, .L85
** b taken
** b not_taken
*/
/*
** u32_x0_eq_42:
** cbeq w0, 42, .L88
** b not_taken
** b taken
*/
/*
** u32_x0_ne_42:
** cbeq w0, 42, .L90
** b taken
** b not_taken
*/
/*
** u32_x0_ult_42:
** cbhi w0, 41, .L92
** b taken
** b not_taken
*/
/*
** u32_x0_ule_42:
** cbhi w0, 42, .L94
** b taken
** b not_taken
*/
/*
** u32_x0_ugt_42:
** cbls w0, 42, .L96
** b taken
** b not_taken
*/
/*
** u32_x0_uge_42:
** cbls w0, 41, .L98
** b taken
** b not_taken
*/
/*
** i32_x0_slt_42:
** cbgt w0, 41, .L100
** b taken
** b not_taken
*/
/*
** i32_x0_sle_42:
** cbgt w0, 42, .L102
** b taken
** b not_taken
*/
/*
** i32_x0_sgt_42:
** cble w0, 42, .L104
** b taken
** b not_taken
*/
/*
** i32_x0_sge_42:
** cble w0, 41, .L106
** b taken
** b not_taken
*/
/*
** u64_x0_eq_42:
** cbeq x0, 42, .L109
** b not_taken
** b taken
*/
/*
** u64_x0_ne_42:
** cbeq x0, 42, .L111
** b taken
** b not_taken
*/
/*
** u64_x0_ult_42:
** cbhi x0, 41, .L113
** b taken
** b not_taken
*/
/*
** u64_x0_ule_42:
** cbhi x0, 42, .L115
** b taken
** b not_taken
*/
/*
** u64_x0_ugt_42:
** cbls x0, 42, .L117
** b taken
** b not_taken
*/
/*
** u64_x0_uge_42:
** cbls x0, 41, .L119
** b taken
** b not_taken
*/
/*
** i64_x0_slt_42:
** cbgt x0, 41, .L121
** b taken
** b not_taken
*/
/*
** i64_x0_sle_42:
** cbgt x0, 42, .L123
** b taken
** b not_taken
*/
/*
** i64_x0_sgt_42:
** cble x0, 42, .L125
** b taken
** b not_taken
*/
/*
** i64_x0_sge_42:
** cble x0, 41, .L127
** b taken
** b not_taken
*/
/*
** u8_x0_eq_0:
** cbbne w0, wzr, .L129
** b taken
** b not_taken
*/
/*
** u8_x0_ne_0:
** cbbeq w0, wzr, .L131
** b taken
** b not_taken
*/
/*
** u8_x0_ult_0:
** b not_taken
*/
/*
** u8_x0_ule_0:
** cbbne w0, wzr, .L134
** b taken
** b not_taken
*/
/*
** u8_x0_ugt_0:
** cbbeq w0, wzr, .L136
** b taken
** b not_taken
*/
/*
** u8_x0_uge_0:
** b taken
*/
/*
** i8_x0_slt_0:
** tbnz w0, #7, .L140
** b not_taken
** b taken
*/
/*
** i8_x0_sle_0:
** cbble w0, wzr, .L143
** b not_taken
** b taken
*/
/*
** i8_x0_sgt_0:
** cbble w0, wzr, .L145
** b taken
** b not_taken
*/
/*
** i8_x0_sge_0:
** tbnz w0, #7, .L147
** b taken
** b not_taken
*/
/*
** u16_x0_eq_0:
** cbhne w0, wzr, .L149
** b taken
** b not_taken
*/
/*
** u16_x0_ne_0:
** cbheq w0, wzr, .L151
** b taken
** b not_taken
*/
/*
** u16_x0_ult_0:
** b not_taken
*/
/*
** u16_x0_ule_0:
** cbhne w0, wzr, .L154
** b taken
** b not_taken
*/
/*
** u16_x0_ugt_0:
** cbheq w0, wzr, .L156
** b taken
** b not_taken
*/
/*
** u16_x0_uge_0:
** b taken
*/
/*
** i16_x0_slt_0:
** tbnz w0, #15, .L160
** b not_taken
** b taken
*/
/*
** i16_x0_sle_0:
** cbhle w0, wzr, .L163
** b not_taken
** b taken
*/
/*
** i16_x0_sgt_0:
** cbhle w0, wzr, .L165
** b taken
** b not_taken
*/
/*
** i16_x0_sge_0:
** tbnz w0, #15, .L167
** b taken
** b not_taken
*/
/*
** u32_x0_eq_0:
** cbnz w0, .L169
** b taken
** b not_taken
*/
/*
** u32_x0_ne_0:
** cbz w0, .L171
** b taken
** b not_taken
*/
/*
** u32_x0_ult_0:
** b not_taken
*/
/*
** u32_x0_ule_0:
** cbnz w0, .L174
** b taken
** b not_taken
*/
/*
** u32_x0_ugt_0:
** cbz w0, .L176
** b taken
** b not_taken
*/
/*
** u32_x0_uge_0:
** b taken
*/
/*
** i32_x0_slt_0:
** tbnz w0, #31, .L180
** b not_taken
** b taken
*/
/*
** i32_x0_sle_0:
** cble w0, wzr, .L183
** b not_taken
** b taken
*/
/*
** i32_x0_sgt_0:
** cble w0, wzr, .L185
** b taken
** b not_taken
*/
/*
** i32_x0_sge_0:
** tbnz w0, #31, .L187
** b taken
** b not_taken
*/
/*
** u64_x0_eq_0:
** cbnz x0, .L189
** b taken
** b not_taken
*/
/*
** u64_x0_ne_0:
** cbz x0, .L191
** b taken
** b not_taken
*/
/*
** u64_x0_ult_0:
** b not_taken
*/
/*
** u64_x0_ule_0:
** cbnz x0, .L194
** b taken
** b not_taken
*/
/*
** u64_x0_ugt_0:
** cbz x0, .L196
** b taken
** b not_taken
*/
/*
** u64_x0_uge_0:
** b taken
*/
/*
** i64_x0_slt_0:
** tbnz x0, #63, .L200
** b not_taken
** b taken
*/
/*
** i64_x0_sle_0:
** cble x0, xzr, .L203
** b not_taken
** b taken
*/
/*
** i64_x0_sgt_0:
** cble x0, xzr, .L205
** b taken
** b not_taken
*/
/*
** i64_x0_sge_0:
** tbnz x0, #63, .L207
** b taken
** b not_taken
*/
/*
** u8_x0_eq_42:
** mov w1, 42
** cbbeq w0, w1, .L210
** b not_taken
** b taken
*/
/*
** u8_x0_ne_42:
** mov w1, 42
** cbbeq w0, w1, .L212
** b taken
** b not_taken
*/
/*
** u8_x0_ult_42:
** mov w1, 41
** cbbhi w0, w1, .L214
** b taken
** b not_taken
*/
/*
** u8_x0_ule_42:
** mov w1, 42
** cbbhi w0, w1, .L216
** b taken
** b not_taken
*/
/*
** u8_x0_ugt_42:
** mov w1, 42
** cbbls w0, w1, .L218
** b taken
** b not_taken
*/
/*
** u8_x0_uge_42:
** mov w1, 41
** cbbls w0, w1, .L220
** b taken
** b not_taken
*/
/*
** i8_x0_slt_42:
** mov w1, 41
** cbbgt w0, w1, .L222
** b taken
** b not_taken
*/
/*
** i8_x0_sle_42:
** mov w1, 42
** cbbgt w0, w1, .L224
** b taken
** b not_taken
*/
/*
** i8_x0_sgt_42:
** mov w1, 42
** cbble w0, w1, .L226
** b taken
** b not_taken
*/
/*
** i8_x0_sge_42:
** mov w1, 41
** cbble w0, w1, .L228
** b taken
** b not_taken
*/
/*
** u16_x0_eq_42:
** mov w1, 42
** cbheq w0, w1, .L231
** b not_taken
** b taken
*/
/*
** u16_x0_ne_42:
** mov w1, 42
** cbheq w0, w1, .L233
** b taken
** b not_taken
*/
/*
** u16_x0_ult_42:
** mov w1, 41
** cbhhi w0, w1, .L235
** b taken
** b not_taken
*/
/*
** u16_x0_ule_42:
** mov w1, 42
** cbhhi w0, w1, .L237
** b taken
** b not_taken
*/
/*
** u16_x0_ugt_42:
** mov w1, 42
** cbhls w0, w1, .L239
** b taken
** b not_taken
*/
/*
** u16_x0_uge_42:
** mov w1, 41
** cbhls w0, w1, .L241
** b taken
** b not_taken
*/
/*
** i16_x0_slt_42:
** mov w1, 41
** cbhgt w0, w1, .L243
** b taken
** b not_taken
*/
/*
** i16_x0_sle_42:
** mov w1, 42
** cbhgt w0, w1, .L245
** b taken
** b not_taken
*/
/*
** i16_x0_sgt_42:
** mov w1, 42
** cbhle w0, w1, .L247
** b taken
** b not_taken
*/
/*
** i16_x0_sge_42:
** mov w1, 41
** cbhle w0, w1, .L249
** b taken
** b not_taken
*/
/*
** u8_x0_eq_64:
** mov w1, 64
** cbbeq w0, w1, .L252
** b not_taken
** b taken
*/
/*
** u8_x0_ne_64:
** mov w1, 64
** cbbeq w0, w1, .L254
** b taken
** b not_taken
*/
/*
** u8_x0_ult_64:
** mov w1, 63
** cbbhi w0, w1, .L256
** b taken
** b not_taken
*/
/*
** u8_x0_ule_64:
** mov w1, 64
** cbbhi w0, w1, .L258
** b taken
** b not_taken
*/
/*
** u8_x0_ugt_64:
** mov w1, 64
** cbbls w0, w1, .L260
** b taken
** b not_taken
*/
/*
** u8_x0_uge_64:
** mov w1, 63
** cbbls w0, w1, .L262
** b taken
** b not_taken
*/
/*
** i8_x0_slt_64:
** mov w1, 63
** cbbgt w0, w1, .L264
** b taken
** b not_taken
*/
/*
** i8_x0_sle_64:
** mov w1, 64
** cbbgt w0, w1, .L266
** b taken
** b not_taken
*/
/*
** i8_x0_sgt_64:
** mov w1, 64
** cbble w0, w1, .L268
** b taken
** b not_taken
*/
/*
** i8_x0_sge_64:
** mov w1, 63
** cbble w0, w1, .L270
** b taken
** b not_taken
*/
/*
** u16_x0_eq_64:
** mov w1, 64
** cbheq w0, w1, .L273
** b not_taken
** b taken
*/
/*
** u16_x0_ne_64:
** mov w1, 64
** cbheq w0, w1, .L275
** b taken
** b not_taken
*/
/*
** u16_x0_ult_64:
** mov w1, 63
** cbhhi w0, w1, .L277
** b taken
** b not_taken
*/
/*
** u16_x0_ule_64:
** mov w1, 64
** cbhhi w0, w1, .L279
** b taken
** b not_taken
*/
/*
** u16_x0_ugt_64:
** mov w1, 64
** cbhls w0, w1, .L281
** b taken
** b not_taken
*/
/*
** u16_x0_uge_64:
** mov w1, 63
** cbhls w0, w1, .L283
** b taken
** b not_taken
*/
/*
** i16_x0_slt_64:
** mov w1, 63
** cbhgt w0, w1, .L285
** b taken
** b not_taken
*/
/*
** i16_x0_sle_64:
** mov w1, 64
** cbhgt w0, w1, .L287
** b taken
** b not_taken
*/
/*
** i16_x0_sgt_64:
** mov w1, 64
** cbhle w0, w1, .L289
** b taken
** b not_taken
*/
/*
** i16_x0_sge_64:
** mov w1, 63
** cbhle w0, w1, .L291
** b taken
** b not_taken
*/
/*
** u32_x0_eq_64:
** cmp w0, 64
** beq .L294
** b not_taken
** b taken
*/
/*
** u32_x0_ne_64:
** cmp w0, 64
** beq .L296
** b taken
** b not_taken
*/
/*
** u32_x0_ult_64:
** cbhi w0, 63, .L298
** b taken
** b not_taken
*/
/*
** u32_x0_ule_64:
** cmp w0, 64
** bhi .L300
** b taken
** b not_taken
*/
/*
** u32_x0_ugt_64:
** cmp w0, 64
** bls .L302
** b taken
** b not_taken
*/
/*
** u32_x0_uge_64:
** cbls w0, 63, .L304
** b taken
** b not_taken
*/
/*
** i32_x0_slt_64:
** cbgt w0, 63, .L306
** b taken
** b not_taken
*/
/*
** i32_x0_sle_64:
** cmp w0, 64
** bgt .L308
** b taken
** b not_taken
*/
/*
** i32_x0_sgt_64:
** cmp w0, 64
** ble .L310
** b taken
** b not_taken
*/
/*
** i32_x0_sge_64:
** cble w0, 63, .L312
** b taken
** b not_taken
*/
/*
** u64_x0_eq_64:
** cmp x0, 64
** beq .L315
** b not_taken
** b taken
*/
/*
** u64_x0_ne_64:
** cmp x0, 64
** beq .L317
** b taken
** b not_taken
*/
/*
** u64_x0_ult_64:
** cbhi x0, 63, .L319
** b taken
** b not_taken
*/
/*
** u64_x0_ule_64:
** cmp x0, 64
** bhi .L321
** b taken
** b not_taken
*/
/*
** u64_x0_ugt_64:
** cmp x0, 64
** bls .L323
** b taken
** b not_taken
*/
/*
** u64_x0_uge_64:
** cbls x0, 63, .L325
** b taken
** b not_taken
*/
/*
** i64_x0_slt_64:
** cbgt x0, 63, .L327
** b taken
** b not_taken
*/
/*
** i64_x0_sle_64:
** cmp x0, 64
** bgt .L329
** b taken
** b not_taken
*/
/*
** i64_x0_sgt_64:
** cmp x0, 64
** ble .L331
** b taken
** b not_taken
*/
/*
** i64_x0_sge_64:
** cble x0, 63, .L333
** b taken
** b not_taken
*/
/*
** u16_x0_eq_4098:
** mov w1, 4098
** cbheq w0, w1, .L336
** b not_taken
** b taken
*/
/*
** u16_x0_ne_4098:
** mov w1, 4098
** cbheq w0, w1, .L338
** b taken
** b not_taken
*/
/*
** u16_x0_ult_4098:
** mov w1, 4097
** cbhhi w0, w1, .L340
** b taken
** b not_taken
*/
/*
** u16_x0_ule_4098:
** mov w1, 4098
** cbhhi w0, w1, .L342
** b taken
** b not_taken
*/
/*
** u16_x0_ugt_4098:
** mov w1, 4098
** cbhls w0, w1, .L344
** b taken
** b not_taken
*/
/*
** u16_x0_uge_4098:
** mov w1, 4097
** cbhls w0, w1, .L346
** b taken
** b not_taken
*/
/*
** i16_x0_slt_4098:
** mov w1, 4097
** cbhgt w0, w1, .L348
** b taken
** b not_taken
*/
/*
** i16_x0_sle_4098:
** mov w1, 4098
** cbhgt w0, w1, .L350
** b taken
** b not_taken
*/
/*
** i16_x0_sgt_4098:
** mov w1, 4098
** cbhle w0, w1, .L352
** b taken
** b not_taken
*/
/*
** i16_x0_sge_4098:
** mov w1, 4097
** cbhle w0, w1, .L354
** b taken
** b not_taken
*/
/*
** u32_x0_eq_4098:
** mov w1, 4098
** cbeq w0, w1, .L357
** b not_taken
** b taken
*/
/*
** u32_x0_ne_4098:
** mov w1, 4098
** cbeq w0, w1, .L359
** b taken
** b not_taken
*/
/*
** u32_x0_ult_4098:
** mov w1, 4097
** cbhi w0, w1, .L361
** b taken
** b not_taken
*/
/*
** u32_x0_ule_4098:
** mov w1, 4098
** cbhi w0, w1, .L363
** b taken
** b not_taken
*/
/*
** u32_x0_ugt_4098:
** mov w1, 4098
** cbls w0, w1, .L365
** b taken
** b not_taken
*/
/*
** u32_x0_uge_4098:
** mov w1, 4097
** cbls w0, w1, .L367
** b taken
** b not_taken
*/
/*
** i32_x0_slt_4098:
** mov w1, 4097
** cbgt w0, w1, .L369
** b taken
** b not_taken
*/
/*
** i32_x0_sle_4098:
** mov w1, 4098
** cbgt w0, w1, .L371
** b taken
** b not_taken
*/
/*
** i32_x0_sgt_4098:
** mov w1, 4098
** cble w0, w1, .L373
** b taken
** b not_taken
*/
/*
** i32_x0_sge_4098:
** mov w1, 4097
** cble w0, w1, .L375
** b taken
** b not_taken
*/
/*
** u64_x0_eq_4098:
** mov x1, 4098
** cbeq x0, x1, .L378
** b not_taken
** b taken
*/
/*
** u64_x0_ne_4098:
** mov x1, 4098
** cbeq x0, x1, .L380
** b taken
** b not_taken
*/
/*
** u64_x0_ult_4098:
** mov x1, 4097
** cbhi x0, x1, .L382
** b taken
** b not_taken
*/
/*
** u64_x0_ule_4098:
** mov x1, 4098
** cbhi x0, x1, .L384
** b taken
** b not_taken
*/
/*
** u64_x0_ugt_4098:
** mov x1, 4098
** cbls x0, x1, .L386
** b taken
** b not_taken
*/
/*
** u64_x0_uge_4098:
** mov x1, 4097
** cbls x0, x1, .L388
** b taken
** b not_taken
*/
/*
** i64_x0_slt_4098:
** mov x1, 4097
** cbgt x0, x1, .L390
** b taken
** b not_taken
*/
/*
** i64_x0_sle_4098:
** mov x1, 4098
** cbgt x0, x1, .L392
** b taken
** b not_taken
*/
/*
** i64_x0_sgt_4098:
** mov x1, 4098
** cble x0, x1, .L394
** b taken
** b not_taken
*/
/*
** i64_x0_sge_4098:
** mov x1, 4097
** cble x0, x1, .L396
** b taken
** b not_taken
*/
--
2.45.2
