Jason,
This patch prevents creating out-of-bounds BIT_FIELD_REFs in 3 locations.
It fixes a SIGSEGV (triggered by gimple_fold_indirect_ref_1) in
simplify_bitfield_ref. I've added an assert to detect the problematic
BIT_FIELD_REF there.
Bootstrapped and reg-tested on x86_64.
OK for trunk?
T
MicroBlaze currently only supports mcpu version of format vX.YY.Z
This patch extends the mcpu version format to include;
vX.YY.Z
vXX.YY.Z
vXX.YY
vX.YY.Z
Changelog
2013-11-26 Nagaraju Mekala
* gcc/config/microblaze/microblaze.c: Extend mcpu version format.
0010-Patch-microblaze-Extende
Existing MicroBlaze shift instruction pattern names don't match
surrounding format.
ashlri_reg should be ashrsi_reg - arithmetic shift right for SI mode
lshlri_reg should be lshrsi_reg - logical shift right for SI mode
Changelog
2013-11-26 David Holsgrove
* gcc/config/microblaze/microblaze.m
Add optimized lshrsi3 instruction, to be used when optimizing for size
with immediate values over 5
Changelog
2013-11-26 Nagaraju Mekala
* gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn.
0008-Patch-microblaze-Add-optimized-lshrsi3.patch
Description: Binary data
Added the lwr/swr instructions pattern.
lwr and swr instructions will load/store the data with opposite endianness.
Changelog
2013-11-26 Nagaraju Mekala
* gcc/config/microblaze/microblaze.md: Add movsi4_rev insn pattern.
* gcc/config/microblaze/predicates.md: Add reg_or_mem_operand predicate
Hi Michael,
I've attached patch based on latest gcc master. Please apply when ready.
Changelog
2013-11-26 David Holsgrove
* gcc/config/microblaze/predicates.md: Add cmp_op predicate.
* gcc/config/microblaze/microblaze.md: Add branch_compare
instruction which uses cmp_op predicate and emi
Hi Michael,
I've attached patch based on latest gcc master. Please let me know if
you need anything further.
thanks,
David
On 15 July 2013 14:42, David Holsgrove wrote:
>
> Hi Michael,
>
> On 18 March 2013 22:50, David Holsgrove wrote:
> > Changelog
> >
> > 2013-03-18 David Holsgrove
> >
>
Hi Michael,
I've attached patch based on latest gcc master. Please let me know if
you need anything further.
thanks,
David
On 15 July 2013 14:44, David Holsgrove wrote:
> Hi Michael,
>
> On 18 March 2013 22:49, David Holsgrove wrote:
>> MicroBlaze doesn't have restrictions that would force us
Hi Michael,
I've attached the same patch based on latest gcc master.
Can this be applied to gcc-4_8-branch also.
thanks,
David
On 15 July 2013 14:53, David Holsgrove wrote:
> Add SImode to cstoresf4's comparison operator, prevents ICE during combine
> rtl pass with error message;
>
> internal
Hi Michael,
On 24 July 2013 10:29, David Holsgrove wrote:
> On 24 July 2013 10:22, Michael Eager wrote:
>> On 07/23/13 16:23, David Holsgrove wrote:
>>>
>>> On 24 July 2013 07:10, Michael Eager wrote:
>>> Thanks Michael.
>>>
>>> I think the content of your commit doesnt line up with this C
Hi Michael,
Please find attached same patch based against latest from gcc master.
Can this be applied and backported to gcc-4_8-branch when reviewed.
thanks,
David
On 15 July 2013 14:49, David Holsgrove wrote:
> MicroBlaze insn swaph swaps the contents of register rA as two
> halfwords placing
Implement the "trap" pattern for MicroBlaze using matching
ABORT_INSTRUCTION used in glibc.
Resolves recent build failure while building glibc, also encountered
by ARM and AARCH64 and discussed here;
https://sourceware.org/ml/libc-alpha/2013-11/msg00320.html
ChangeLog
2013-11-26 David Holsgrov
Sergey Matveev wrote:
I think LSAN_OPTIONS should be documented at
https://code.google.com/p/address-sanitizer/wiki/LeakSanitizer, rather
than on the ASan flags page.
I concur, but currently not even LSAN_OPTIONS is mentioned on that page
(or any other of LSAN's wiki pages). Until it is, how
On 11/22/13 18:43, Kai Tietz wrote:
- Original Message -
That is actual wished. We shouldn't come to patterns, which have more
type-casts by this patch.
What we see here is the normalization of shift-left/right operations. This
patch takes care that we prefer in general (Type) (X shi
On 11/22/13 18:43, Kai Tietz wrote:
So at least for f1 and f2, these regexps match regardless of whether or
not the code was transformed.
Without your patch (f1)
x1_2 = (unsigned char) x_1(D);
_3 = x1_2 << 5;
return _3;
With your patch (f1):
_4 = x_1(D) << 5;
_2 = (unsigned
Was Re: [buildrobot] [PATCH] mips: Really remove ENTRY_BLOCK_PTR
On Wed, Nov 20, 2013 at 10:08:45AM +0100, Steven Bosscher wrote:
> This patch is obvious and it fixes breakage. Please go ahead and commit it.
Sorry to pick on you here Steven, but this doesn't meet gcc's
definition of an obvious pat
Hi,
This patch intends to fix ICE when high register is used for pic base
register for thumb1 target. Tested with gcc regression test, no new
regressions. Is it OK to trunk?
BR,
Terry
gcc/ChangeLog:
2013-11-26 Terry Guo
* config/arm/arm.c (require_pic_register): Handle high pic base
Hi,
The trunk patch to support new option -mslow-flash-data at revision 205342
is back ported to arm/embedded-4_8-branch. Tested with regression test and
no regressions.
BR,
Terry
gcc/ChangeLog:
2013-11-26 Terry Guo
Backport mainline r205342
2013-11-25 Terry Guo
*
On Mon, 20 May 2013, Aldy Hernandez wrote:
> I am committing the attached patch.
Thanks, Aldy.
I just noticed the casing of SPARC and a bit of an inconsistency
around IA-32, and committed the follow-up below (which also contains
one "back end" fix).
Gerald
Index: changes.html
==
On Nov 25, 2013, at 12:03 PM, David Edelsohn wrote:
> 3) altivec_resolve_overloaded_builtin, both hunks should be converted
> the same way, using tree_fits_uhwi_p
>
> - && TREE_CODE (arg2) == INTEGER_CST
> - && TREE_INT_CST_HIGH (arg2) == 0
> - && (TREE_INT_CST_LOW (arg2) == 0 || TREE_INT_C
On 11/25/2013 03:46 AM, Eric Botcazou wrote:
Richi has asked the we break the wide-int patch so that the individual port
and front end maintainers can review their parts without have to go through
the entire patch.This patch covers the ada front-end.
I don't think that the mechanical change
On Nov 25, 2013, at 12:03 PM, David Edelsohn wrote:
> 4) easy_altivec_constant, the comment about 32 bit should be removed
> because wide-int should remove the dependency on 32 bit vs 64 bit host
> wide int.
Index: gcc/ChangeLog.wide-int
===
On Nov 2, 2013, at 3:13 AM, Richard Sandiford
wrote:
> I decided to lump these together since the problems were the same.
> There were some typos in the real_to_integer invocation, while changing:
>
> /* There must be no padding. */
> if (!host_integerp (TYPE_SIZE (type), 1)
>
On Nov 23, 2013, at 1:36 PM, Andrew Pinski wrote:
> On Sat, Nov 23, 2013 at 11:19 AM, Mike Stump wrote:
>> Richi has asked the we break the wide-int patch so that the individual port
>> and front end maintainers can review their parts without have to go through
>> the entire patch.This patc
On 26 November 2013 01:25, Mike Stump wrote:
> Oh, and I did mean to ask, Ok? for the original patch as well.
Yes.
On Nov 25, 2013, at 4:31 PM, Joern Rennecke wrote:
> On 25 November 2013 23:27, Mike Stump wrote:
>> Certainly it is reasonable to include this, and by doing this, one doesn't
>> have to worry if another header changes to not include it.
>>
>> Ok for the patch directly below?
>
> OK.
Oh, and
On Nov 25, 2013, at 2:43 AM, Richard Biener wrote:
> On Sat, Nov 23, 2013 at 8:20 PM, Mike Stump wrote:
>> Richi has asked the we break the wide-int patch so that the individual port
>> and front end maintainers can review their parts without have to go through
>> the entire patch.This patc
On 25 November 2013 23:27, Mike Stump wrote:
> Certainly it is reasonable to include this, and by doing this, one doesn't
> have to worry if another header changes to not include it.
>
> Ok for the patch directly below?
OK.
On 24/11/13 02:14, Ian Lance Taylor wrote:
> Kugan writes:
>
>> This RFC patch series implements a simple align divisor shift dividend
>> method.
>>
>> Regression tested on arm-none-linux-gnueabi with no issues.
>>
>> OK?
>>
>> Thanks,
>> Kugan
>>
>> +2013-11-22 Kugan Vivekanandarajah
>> +
>>
On Nov 23, 2013, at 5:19 PM, Joern Rennecke wrote:
> wide-int.h says widest_int is always signed, yet the iterations count
> in the doloop interface is now unsigned. So, which is right, the code
> or the documentation?
The interface for TARGET_CAN_USE_DOLOOP_P's iteration parameter is documented
On 11/06/2013 05:15 PM, Kirill Yukhin wrote:
> Hello,
> This small patch introduces `sd' subst.
> `sd' (Source-Destination) subst is almost the same, as
> the usual mask-subst, but it's only used for zero-masking. The reason is that
> some patterns already have an operand with constraint "0" and we
On 11/01/2013 10:19 PM, Kirill Yukhin wrote:
> Hello Richard,
>
> On 21 Oct 16:01, Richard Henderson wrote:
>> Error on V16SF. Probably better to fill this out.
> Thanks, fixed.
>
>> Better to just use here, as it's a compile-time constant.
> Fixed.
>
>>> +(define_insn "avx512f_store_mask"
>>
On 25 November 2013 21:02, François Dumont wrote:
>
> Hi
>
> Following N3644 discussion thread here is a patch proposal to remove
> default zero-initialization of unordered containers iterator. I also took the
> time to remove default zero-init of nodes _M_nxt pointer.
>
> 2013-11-25 Franço
On 25 November 2013 21:02, François Dumont wrote:
> Hi
>
> Following N3644 discussion thread here is a patch proposal to remove
> default zero-initialization of unordered containers iterator. I also took
> the time to remove default zero-init of nodes _M_nxt pointer.
>
> 2013-11-25 François Du
On Mon, Nov 25, 2013 at 11:19 PM, Joseph S. Myers
wrote:
> soft-fp patches go to libc-alpha, with glibc code then being imported
> unmodified into GCC.
Oh, I totally forgot that.
I'll post there in a moment.
Thanks,
Uros.
soft-fp patches go to libc-alpha, with glibc code then being imported
unmodified into GCC.
--
Joseph S. Myers
jos...@codesourcery.com
On 11/25/13 13:52, Uros Bizjak wrote:
Hello!
Attached patch removes "left shift count >= width of type" warnings in
soft-fp code. The patch implements the same approach - checking of
rsize against _FP_W_TYPE_SIZE - as is implemented in corresponding
FP_FRAC_DISASSEMBLE_{2,4} macros a couple of l
Doing the cleanup at the end of BB could ensure all the groups
inserted for macrofusion will be cleaned. For groups not at the end of
a block, no matter whether they are cleaned up or not, nothing will
happen because other passes will not mess up those groups -- you said
cc0-setter/cc0-user was
On 11/25/13 02:11, Bin.Cheng wrote:
Slightly tune to make iv cand choosing algorithm more accurate:
http://gcc.gnu.org/ml/gcc-patches/2013-11/msg01574.html
It would help if you had some sample codes where this patch was useful.
I can kind-of see what's going on, but I'm way too unfamiliar with
Jakub Jelinek writes:
> On Mon, Nov 25, 2013 at 09:16:24PM +, Richard Sandiford wrote:
>> > Well, the range_info_def struct right now contains 3 double_ints, which is
>> > unnecessary overhead for the most of the cases where the SSA_NAME's type
>> > has just at most HOST_BITS_PER_WIDE_INT bits
Sergey,
Thanks for the modifications and the patch. I tried your patch using
gcc/testsuite/gcc.dg/vect/costmodel/x86_64/costmodel-vect-31.c with the
following change:
--- a/gcc/testsuite/gcc.dg/vect/costmodel/x86_64/costmodel-vect-31.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/x86_64/costmode
On 11/25/2013 05:02 AM, Paolo Carlini wrote:
because then we don't warn *at all*. The reason being that with the
*first* cp_convert we end up calling c_common_truthvalue_conversion with
c_inhibit_evaluation_warnings bumped. The bumping happens in
cp_truthvalue_conversion. A mess, yes.
Perhaps c
On Mon, Nov 25, 2013 at 09:16:24PM +, Richard Sandiford wrote:
> > Well, the range_info_def struct right now contains 3 double_ints, which is
> > unnecessary overhead for the most of the cases where the SSA_NAME's type
> > has just at most HOST_BITS_PER_WIDE_INT bits and thus we could fit all 3
On 11/25/2013 05:30 AM, Paolo Carlini wrote:
On 11/23/2013 10:08 PM, Jason Merrill wrote:
I believe that our current practice is to have one error and then use
inform for follow-on messages. OK with that change.
Thanks. The multiple permerror and error aren't in the new code, my
patch just shu
On Nov 25, 2013, at 1:01 AM, Eric Botcazou wrote:
>> Richi has asked the we break the wide-int patch so that the individual port
>> and front end maintainers can review their parts without have to go through
>> the entire patch.This patch covers the sparc port.
>
> OK if you change the type o
Jakub Jelinek writes:
> On Mon, Nov 25, 2013 at 12:24:30PM +0100, Richard Biener wrote:
>> On Sat, Nov 23, 2013 at 8:21 PM, Mike Stump wrote:
>> > Richi has asked the we break the wide-int patch so that the
>> > individual port and front end maintainers can review their parts
>> > without have to
Hi,
I have attached a patch to fix this bug :
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58944
A similar problem was also reported here:
http://gcc.gnu.org/ml/gcc-patches/2013-11/msg01050.html
Recently, ix86_valid_target_attribute_tree in config/i386/i386.c was
refactored to not depend
On 11/25/2013 03:05 PM, Richard Sandiford wrote:
wi::eq_p (t1, t2) asserts that t1 and t2 are the same precision and
ignores signedness; it just tests whether they are the same bitstring.
wi::to_widest (t1) == wi::to_widest (t2) compares them as logical numbers,
taking sign into account and allow
Hi
Following N3644 discussion thread here is a patch proposal to
remove default zero-initialization of unordered containers iterator. I
also took the time to remove default zero-init of nodes _M_nxt pointer.
2013-11-25 François Dumont
* include/bits/hashtable_policy.h (_Hash_node_
Hello!
Attached patch removes "left shift count >= width of type" warnings in
soft-fp code. The patch implements the same approach - checking of
rsize against _FP_W_TYPE_SIZE - as is implemented in corresponding
FP_FRAC_DISASSEMBLE_{2,4} macros a couple of lines below.
This patch removes all rema
Steven Bosscher writes:
> On Sat, 2013-04-27 at 08:56 +0100, Richard Sandiford wrote:
>> Yeah, I think so. If "=>" mean "accepts more than", then there used
>> to be a nice total order:
>>
>> next_insn
>> => next_nonnote_insn
>> => next_real_insn
>> => next_active_insn
>
>
> Hi Richard
I replied to the wrong email when i sent the first version of this
emal. sorry.This was the comment that was addressed by this fix.
fixed on the wide-int branch 205363.
On 11/24/2013 08:43 AM, Jason Merrill wrote:
On 11/23/2013 09:55 PM, Kenneth Zadeck wrote:
On 11/23/2013 08:47 PM, J
Jason Merrill writes:
> On 11/23/2013 02:20 PM, Mike Stump wrote:
>> @@ -2605,8 +2606,7 @@ cp_tree_equal (tree t1, tree t2)
>> switch (code1)
>> {
>> case INTEGER_CST:
>> - return TREE_INT_CST_LOW (t1) == TREE_INT_CST_LOW (t2)
>> -&& TREE_INT_CST_HIGH (t1) == TREE_INT_CST_
Thanks for doing this conversion work. A few questions and comments:
1) Because rs6000 is one of the few ports that was completely
converted to wide-int instead of simply accommodating wide-int, what
is the compile-time performance impact of this conversion?
2) non_logical_cint_operand changed c
fixed on the wide-int branch 205363.
On 11/23/2013 09:00 PM, Jason Merrill wrote:
On 11/23/2013 02:20 PM, Mike Stump wrote:
@@ -2605,8 +2606,7 @@ cp_tree_equal (tree t1, tree t2)
switch (code1)
{
case INTEGER_CST:
- return TREE_INT_CST_LOW (t1) == TREE_INT_CST_LOW (t2)
-
On Mon, Nov 25, 2013 at 11:25 AM, Jeff Law wrote:
> On 11/25/13 12:16, Wei Mi wrote:
>>>
>>>
>>> I'll note you're doing an extra pass over all the RTL here. Is there
>>> any
>>> clean way you can clean SCHED_GROUP_P without that extra pass over the
>>> RTL?
>>> Perhaps when the group actually ge
On 11/25/13 08:35, David Malcolm wrote:
I'm not a fan of these "_layout" names, but I'm not sure what better to
call them. Perhaps:
GSS_OMP_PARALLEL_LAYOUT -> GSS_OMP_WITH_CLAUSES_CHILD_FN_DATA_ARG
GSS_OMP_SINGLE_LAYOUT -> GSS_OMP_WITH_CLAUSES
GSS_OMP_ATOMIC_STORE_LAYOUT ->
On 11/25/13 12:16, Wei Mi wrote:
I'll note you're doing an extra pass over all the RTL here. Is there any
clean way you can clean SCHED_GROUP_P without that extra pass over the RTL?
Perhaps when the group actually gets scheduled?
jeff
With your help to understand that sched group will not
On Mon, Nov 25, 2013 at 07:20:33PM +0100, Marek Polacek wrote:
> When running bootstrap-ubsan I got an error in stage2, the issue was
> that some Lubsan_types were wrongfully discarded -> link error.
> Thus fixed.
>
> Ubsan testsuite passes with -m32/-m64, ok for trunk?
>
> 2013-11-25 Marek Pola
On Mon, Nov 25, 2013 at 2:11 AM, Richard Biener
wrote:
> On Fri, Nov 22, 2013 at 10:49 PM, Rong Xu wrote:
>> On Fri, Nov 22, 2013 at 4:03 AM, Richard Biener
>> wrote:
>>> On Fri, Nov 22, 2013 at 4:51 AM, Rong Xu wrote:
Hi,
This patch injects a condition into the instrumented code
On Mon, Nov 25, 2013 at 10:36 AM, Jeff Law wrote:
> On 11/24/13 00:30, Wei Mi wrote:
>>
>> Sorry about the problem.
>>
>> For the failed testcase, it was compiled using -fmodulo-sched.
>> modulo-sched phase set SCHED_GROUP_P of a jump insn to be true, which
>> means the jump insn should be schedul
> On Mon, Nov 25, 2013 at 07:48:34PM +0100, Jan Hubicka wrote:
> > > isn't exactly enabled by default ;)
> >
> > OK :))
> > > Anyway, all the pass needs is bodies of functions with "omp declare simd"
> > > attribute which will be defined in the current partition, for functions
> > > defined in oth
On Mon, Nov 25, 2013 at 07:48:34PM +0100, Jan Hubicka wrote:
> > isn't exactly enabled by default ;)
>
> OK :))
> > Anyway, all the pass needs is bodies of functions with "omp declare simd"
> > attribute which will be defined in the current partition, for functions
> > defined in other partitions
> On Mon, Nov 25, 2013 at 06:15:50PM +0100, Jan Hubicka wrote:
> > > > What's the reason you cannot defer SIMD cloning to LTRANS stage
> > > > as simple IPA pass next to IPA-PTA?
> > >
> > > Ok, deferring till after IPA-PTA was easy, just small ipa-cp.c changes
> > > (look at the attribute rather
On 11/25/13 02:22, bin.cheng wrote:
Hi,
I previously committed two patches lowering complex address expression for
IVOPT at http://gcc.gnu.org/ml/gcc-patches/2013-11/msg00546.html and
http://gcc.gnu.org/ml/gcc-patches/2013-11/msg01103.html
When I bootstrapping GCC I found there were some peculiar
On 11/25/13 04:12, Ilya Enkovich wrote:
I'll prepare a patch to remove committed patches. But the first part
of series added new ISA extension support. It is independent from the
checker. Should it be OK to keep ISA in trunk?
I think this can/should reasonably be Uros's call.
I'm sorry we d
On 11/24/13 00:30, Wei Mi wrote:
Sorry about the problem.
For the failed testcase, it was compiled using -fmodulo-sched.
modulo-sched phase set SCHED_GROUP_P of a jump insn to be true, which
means the jump insn should be scheduled with prev insn as a group.
When modulo scheduling is finished, th
On Mon, Nov 25, 2013 at 1:30 PM, Dehao Chen wrote:
> On Mon, Nov 25, 2013 at 10:26 AM, Diego Novillo wrote:
>> On Mon, Nov 25, 2013 at 1:22 PM, Xinliang David Li
>> wrote:
>>> In this case the backedge will be a critical edge, which will be split by
>>> GCC.
>>
>> Right. So, if I split it, I w
On Mon, Nov 25, 2013 at 10:26 AM, Diego Novillo wrote:
> On Mon, Nov 25, 2013 at 1:22 PM, Xinliang David Li wrote:
>> In this case the backedge will be a critical edge, which will be split by
>> GCC.
>
> Right. So, if I split it, I will reach essentially the same
> conclusion, I think. The new b
On Mon, Nov 25, 2013 at 1:22 PM, Xinliang David Li wrote:
> In this case the backedge will be a critical edge, which will be split by GCC.
Right. So, if I split it, I will reach essentially the same
conclusion, I think. The new block will get the original block's
weight, which (in turn) will tran
On Mon, Nov 25, 2013 at 06:15:50PM +0100, Jan Hubicka wrote:
> > > What's the reason you cannot defer SIMD cloning to LTRANS stage
> > > as simple IPA pass next to IPA-PTA?
> >
> > Ok, deferring till after IPA-PTA was easy, just small ipa-cp.c changes
> > (look at the attribute rather than simd*cl
On Mon, Nov 25, 2013 at 10:23 AM, Dehao Chen wrote:
> On Mon, Nov 25, 2013 at 10:08 AM, Diego Novillo wrote:
>> Thanks, Deaho.
>>
>> One other thing that I've found on the LLVM implementation (that I'm
>> not sure happens in GCC): self-referential edges. If a loop consists
>> of a single-basic b
On 11/22/13 08:56, Richard Biener wrote:
So the issue here is we can create irreducible regions & new nested
loops. Does just setting the header,latch fields for the current loop
handle those cases?
Yes.
Fixed via the attached patch.
Bootstrapped and regression tested on x86_64-unknown-lin
On Mon, Nov 25, 2013 at 10:08 AM, Diego Novillo wrote:
> Thanks, Deaho.
>
> One other thing that I've found on the LLVM implementation (that I'm
> not sure happens in GCC): self-referential edges. If a loop consists
> of a single-basic block, the back edge will point to itself. I
> haven't been
In this case the backedge will be a critical edge, which will be split by GCC.
David
On Mon, Nov 25, 2013 at 10:08 AM, Diego Novillo wrote:
> Thanks, Deaho.
>
> One other thing that I've found on the LLVM implementation (that I'm
> not sure happens in GCC): self-referential edges. If a loop con
When running bootstrap-ubsan I got an error in stage2, the issue was
that some Lubsan_types were wrongfully discarded -> link error.
Thus fixed.
Ubsan testsuite passes with -m32/-m64, ok for trunk?
2013-11-25 Marek Polacek
* ubsan.c (ubsan_type_descriptor): Set DECL_PRESERVE_P on a de
Thanks, Deaho.
One other thing that I've found on the LLVM implementation (that I'm
not sure happens in GCC): self-referential edges. If a loop consists
of a single-basic block, the back edge will point to itself. I
haven't been able to reproduce it with regular control flow constructs
in GCC.
Ok.
David
On Mon, Nov 25, 2013 at 9:56 AM, Dehao Chen wrote:
> afdo_propagate_multi_edge can do everything afdo_propagate_single_edge
> does. So we refactor the code to keep only one afdo_propagate_edge
> function.
>
> Bootstrapped and passed all unittests and performance tests.
>
> OK for googl
afdo_propagate_multi_edge can do everything afdo_propagate_single_edge
does. So we refactor the code to keep only one afdo_propagate_edge
function.
Bootstrapped and passed all unittests and performance tests.
OK for googlge branch?
Thanks,
Dehao
Index: gcc/auto-profile.c
===
On Mon, Nov 25, 2013 at 2:08 AM, Alexander Monakov wrote:
> On Sat, 23 Nov 2013, Wei Mi wrote:
>> For the failed testcase, it was compiled using -fmodulo-sched.
>> modulo-sched phase set SCHED_GROUP_P of a jump insn to be true, which
>> means the jump insn should be scheduled with prev insn as a g
On Mon, Nov 25, 2013 at 12:24:30PM +0100, Richard Biener wrote:
> On Sat, Nov 23, 2013 at 8:21 PM, Mike Stump wrote:
> > Richi has asked the we break the wide-int patch so that the individual port
> > and front end maintainers can review their parts without have to go through
> > the entire patc
> > What's the reason you cannot defer SIMD cloning to LTRANS stage
> > as simple IPA pass next to IPA-PTA?
>
> Ok, deferring till after IPA-PTA was easy, just small ipa-cp.c changes
> (look at the attribute rather than simd*clone* fields), passes.def and
> had to tweak ipa_add_new_function which
On Mon, 2013-11-25 at 09:12 +0900, Kaz Kojima wrote:
> Oleg Endo wrote:
> > Currently GCC doesn't pass the --isa parameter to the assembler for SH
> > targets other than SH2A and SH5. This makes the assembler accept any
> > kind of ISA and happily produce e.g. SH2A code even though the target is
Hi,
I am looking into testcases for individual code paths of ipa-devirt and my life
would be much easier if gimple-fold did not take some of them by old code.
This patch also improves code by doing devirtualization earlier in the game
since get_polymorphic_call_info is now supperset of
gimple_extra
Hi,
On Mon, 25 Nov 2013, David Malcolm wrote:
> I'm not a fan of these "_layout" names, but I'm not sure what better to
> call them. Perhaps:
>GSS_OMP_PARALLEL_LAYOUT -> GSS_OMP_WITH_CLAUSES_CHILD_FN_DATA_ARG
>GSS_OMP_SINGLE_LAYOUT -> GSS_OMP_WITH_CLAUSES
>GSS_OMP_ATOMIC_STO
Hello,
This fixes a warning in sh.md caused by a missing mode in the
doloop_end_split pattern.
Tested with
make -k check RUNTESTFLAGS="--target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"
with no new failures. Committed as obvious as rev 205359.
Cheers,
Oleg
gc
On Mon, Nov 25, 2013 at 05:13:25PM +0100, Thomas Schwinge wrote:
> > --- a/gcc/cgraphunit.c
> > +++ b/gcc/cgraphunit.c
> > @@ -2019,7 +2019,18 @@ ipa_passes (void)
> > passes->all_lto_gen_passes);
> >
> >if (!in_lto_p)
> > -ipa_write_summaries ();
> > +{
> >
Hello,
This patch is the same as posted in PR 59243.
Tested with
make -k check RUNTESTFLAGS="--target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"
Pre-approved by Kaz in PR 59243, committed as rev 205358.
Cheers,
Oleg
gcc/ChangeLog:
PR target/53976
On Sat, 23 Nov 2013, Mike Stump wrote:
> Richi has asked the we break the wide-int patch so that the individual
> port and front end maintainers can review their parts without have to go
> through the entire patch. This patch covers the c front end.
>
> Ok?
OK.
--
Joseph S. Myers
jos...@cod
Hi!
Just some suggestion related to terminology.
On Tue, 19 Nov 2013 13:58:29 +0400, Ilya Tocar wrote:
> On 14 Nov 11:27, Richard Biener wrote:
> > > + /* Set when symbol needs to be dumped for lto/offloading. */
> > > + unsigned need_dump : 1;
> > > +
> >
> > That's very non-descriptive.
Il 25/11/2013 16:45, Rainer Orth ha scritto:
> Uros prompted me to look into why we were still getting warnings
> compiling the soft-fp code in libgcc despite this in config/t-softfp:
>
> $(soft-fp-objects) : INTERNAL_CFLAGS += -Wno-missing-prototypes
> -Wno-type-limit
> s
>
> It turned out that
Hi Jason,
Please see my responses below
> -Original Message-
> From: Jason Merrill [mailto:ja...@redhat.com]
> Sent: Friday, November 22, 2013 10:51 AM
> To: Iyer, Balaji V; gcc-patches@gcc.gnu.org
> Cc: Jeff Law
> Subject: Re: _Cilk_spawn and _Cilk_sync for C++
>
> On 11/21/2013 05:4
On 11/25/2013 06:04 AM, Richard Biener wrote:
On Sat, Nov 23, 2013 at 8:22 PM, Mike Stump wrote:
Richi has asked the we break the wide-int patch so that the individual port and
front end maintainers can review their parts without have to go through the
entire patch.This patch covers the
Uros prompted me to look into why we were still getting warnings
compiling the soft-fp code in libgcc despite this in config/t-softfp:
$(soft-fp-objects) : INTERNAL_CFLAGS += -Wno-missing-prototypes -Wno-type-limit
s
It turned out that soft-fp-objects still included the $srcdir prefix.
It seems m
On Sat, Nov 23, 2013 at 8:22 PM, Mike Stump wrote:
> Richi has asked the we break the wide-int patch so that the individual port
> and front end maintainers can review their parts without have to go through
> the entire patch.This patch covers the real.c code.
Ok.
Thanks,
Richard.
> Ok?
>
On Thu, 2013-11-21 at 18:03 -0500, Andrew MacLeod wrote:
> On 11/21/2013 05:42 PM, Jakub Jelinek wrote:
> > On Thu, Nov 21, 2013 at 03:24:55PM -0700, Jeff Law wrote:
> >> On 11/21/13 15:19, Jakub Jelinek wrote:
> >>> On Mon, Nov 18, 2013 at 03:25:52PM -0500, David Malcolm wrote:
> > So is there
On 25/11/13 11:01, Kyrill Tkachov wrote:
> Hi all,
>
> This patch gets the aarch64 backend to use the Cortex A53 costs when tuning
> for
> that core, instead of using the generic costs. The costs table itself was
> added
> recently in arm/aarch-cost-tables.h and is shared between the two ports
On Mon, Nov 25, 2013 at 06:53:59PM +0400, Alexey Samsonov wrote:
> > In GCC, libbacktrace is built as a libtool convenience library only and
> > then linked into whatever libraries want to use it. So indeed, the plan
> > is to link libbacktrace.la into libasan.so.1.0.0 and libasan.a
> > (and the e
On 25/11/13 11:33, Charles Baylis wrote:
> This bug reveals a long standing problem in the ARM ldm/stm patterns
> which allow the virtual hardware register 'afp' to be used. A similar
> problem may affect vfp_pop_multiple_with_writeback, so that is also
> addressed.
>
> I have not included a test
On Fri, Nov 22, 2013 at 10:34 PM, Jakub Jelinek wrote:
> On Fri, Nov 22, 2013 at 10:19:02PM +0400, Alexey Samsonov wrote:
>> On Tue, Nov 19, 2013 at 8:42 PM, Jakub Jelinek wrote:
>> > Ok, here it is (untested though, because libsanitizer in gcc is older and I
>> > don't have spare cycles to play
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