[gcc r14-9334] LoongArch: testsuite: Rewrite {x, }vfcmp-{d, f}.c to avoid named registers

https://gcc.gnu.org/g:7719b9be2daa55edf336d721839300e62a7abbdc commit r14-9334-g7719b9be2daa55edf336d721839300e62a7abbdc Author: Xi Ruoyao Date: Tue Mar 5 20:46:57 2024 +0800 LoongArch: testsuite: Rewrite {x,}vfcmp-{d,f}.c to avoid named registers Loops on named vector register ar

[gcc r15-355] driver: Move -fdiagnostics-urls= early like -fdiagnostics-color= [PR114980]

https://gcc.gnu.org/g:f75806ec63ec1af2d76a194e5fa73e114b2b8857 commit r15-355-gf75806ec63ec1af2d76a194e5fa73e114b2b8857 Author: Xi Ruoyao Date: Wed May 8 11:25:57 2024 +0800 driver: Move -fdiagnostics-urls= early like -fdiagnostics-color= [PR114980] In GCC 14 we started to emit UR

[gcc r14-10192] driver: Move -fdiagnostics-urls= early like -fdiagnostics-color= [PR114980]

https://gcc.gnu.org/g:21051de4bed3d541804bf965cbdc3e8047698777 commit r14-10192-g21051de4bed3d541804bf965cbdc3e8047698777 Author: Xi Ruoyao Date: Wed May 8 11:25:57 2024 +0800 driver: Move -fdiagnostics-urls= early like -fdiagnostics-color= [PR114980] In GCC 14 we started to emit

[gcc r15-3189] vect: Fix STMT_VINFO_DEF_TYPE check for odd/even widen mult [PR116348]

https://gcc.gnu.org/g:d3e71b99194bff878d3bf3b35f9528a350d10df9 commit r15-3189-gd3e71b99194bff878d3bf3b35f9528a350d10df9 Author: Xi Ruoyao Date: Thu Aug 22 21:18:29 2024 +0800 vect: Fix STMT_VINFO_DEF_TYPE check for odd/even widen mult [PR116348] After fixing PR116142 some code st

[gcc r14-10616] i386: testsuite: Add -no-pie for pr113689-1.c [PR70150]

https://gcc.gnu.org/g:377c3e9a8b73b47a1211d43fee162179ee1f87e7 commit r14-10616-g377c3e9a8b73b47a1211d43fee162179ee1f87e7 Author: Xi Ruoyao Date: Mon May 6 11:33:43 2024 +0800 i386: testsuite: Add -no-pie for pr113689-1.c [PR70150] For a --enable-default-pie build, using -fno-pic

[gcc r14-10617] i386: testsuite: Adapt fentryname3.c for r14-811 change [PR70150]

https://gcc.gnu.org/g:f5b3dae221e6e41ebd806f504d83012173737dab commit r14-10617-gf5b3dae221e6e41ebd806f504d83012173737dab Author: Xi Ruoyao Date: Mon May 6 11:39:14 2024 +0800 i386: testsuite: Adapt fentryname3.c for r14-811 change [PR70150] After r14-811 "call *nop@GOTPCREL(%rip)

[gcc r15-1611] doc: gccint: Fix typos in jump_table_data description

https://gcc.gnu.org/g:d27049a38a4c07fa1e662ffd66df3f15d330503f commit r15-1611-gd27049a38a4c07fa1e662ffd66df3f15d330503f Author: Xi Ruoyao Date: Tue Jun 25 21:42:38 2024 +0800 doc: gccint: Fix typos in jump_table_data description gcc/ChangeLog: * doc/rtl.texi (jum

[gcc r15-1674] LoongArch: Tweak IOR rtx_cost for bstrins

https://gcc.gnu.org/g:94aade062a4ab689abc4c3422c1b901ab0733c19 commit r15-1674-g94aade062a4ab689abc4c3422c1b901ab0733c19 Author: Xi Ruoyao Date: Sat Jun 15 18:29:43 2024 +0800 LoongArch: Tweak IOR rtx_cost for bstrins Consider c &= 0xfff; a &= ~0xfff;

[gcc r15-1675] LoongArch: NFC: Dedup and sort the comment in loongarch_print_operand_reloc

https://gcc.gnu.org/g:2280e88ab05ebab994b7db588d577b29f1b12b87 commit r15-1675-g2280e88ab05ebab994b7db588d577b29f1b12b87 Author: Xi Ruoyao Date: Sun Jun 16 12:22:40 2024 +0800 LoongArch: NFC: Dedup and sort the comment in loongarch_print_operand_reloc gcc/ChangeLog:

[gcc r14-9411] LoongArch: Emit R_LARCH_RELAX for TLS IE with non-extreme code model to allow the IE to LE linker re

https://gcc.gnu.org/g:42cd49aa48c7ca99e8d5e91ce582d41fdb75f3fc commit r14-9411-g42cd49aa48c7ca99e8d5e91ce582d41fdb75f3fc Author: Xi Ruoyao Date: Fri Jan 26 18:28:32 2024 +0800 LoongArch: Emit R_LARCH_RELAX for TLS IE with non-extreme code model to allow the IE to LE linker relaxation

[gcc r14-9474] LoongArch: Remove unused and incorrect "sge_" define_insn

https://gcc.gnu.org/g:f98b85b1ef74b7c5c0852b3d063262bce63df14e commit r14-9474-gf98b85b1ef74b7c5c0852b3d063262bce63df14e Author: Xi Ruoyao Date: Wed Mar 13 20:44:38 2024 +0800 LoongArch: Remove unused and incorrect "sge_" define_insn If this insn is really used, we'll have someth

[gcc r14-9538] LoongArch: Fix C23 (...) functions returning large aggregates [PR114175]

https://gcc.gnu.org/g:c1fd4589c2bf9fd8409d51b94df219cb75107762 commit r14-9538-gc1fd4589c2bf9fd8409d51b94df219cb75107762 Author: Xi Ruoyao Date: Mon Mar 18 17:18:34 2024 +0800 LoongArch: Fix C23 (...) functions returning large aggregates [PR114175] We were assuming TYPE_NO_NAMED_A

[gcc r14-9582] LoongArch: Fix a typo [PR 114407]

https://gcc.gnu.org/g:806621dc14f893476dd6f2a9ae5cf773f3b0951b commit r14-9582-g806621dc14f893476dd6f2a9ae5cf773f3b0951b Author: Xi Ruoyao Date: Thu Mar 21 04:01:17 2024 +0800 LoongArch: Fix a typo [PR 114407] gcc/ChangeLog: PR target/114407 * config/l

[gcc r14-9717] testsuite: Add a test case for negating FP vectors containing zeros

https://gcc.gnu.org/g:26a723625bb63e42b8c78bbce52ba0286eefda1c commit r14-9717-g26a723625bb63e42b8c78bbce52ba0286eefda1c Author: Xi Ruoyao Date: Tue Feb 6 17:49:50 2024 +0800 testsuite: Add a test case for negating FP vectors containing zeros Recently I've fixed two wrong FP vecto

[gcc r14-9728] mips: Fix C23 (...) functions returning large aggregates [PR114175]

https://gcc.gnu.org/g:6fc84f680d098f82c1c43435fdb206099f0df4df commit r14-9728-g6fc84f680d098f82c1c43435fdb206099f0df4df Author: Xi Ruoyao Date: Wed Mar 20 15:09:21 2024 +0800 mips: Fix C23 (...) functions returning large aggregates [PR114175] We were assuming TYPE_NO_NAMED_ARGS_S

[gcc r13-8526] LoongArch: Fix C23 (...) functions returning large aggregates [PR114175]

https://gcc.gnu.org/g:b73a6a20113ca607cf3073c751698b12aa167881 commit r13-8526-gb73a6a20113ca607cf3073c751698b12aa167881 Author: Xi Ruoyao Date: Mon Mar 18 17:18:34 2024 +0800 LoongArch: Fix C23 (...) functions returning large aggregates [PR114175] We were assuming TYPE_NO_NAMED_A

[gcc r13-8527] mips: Fix C23 (...) functions returning large aggregates [PR114175]

https://gcc.gnu.org/g:1ab646f678a9d47b338424ed69e9ae5d774b06ae commit r13-8527-g1ab646f678a9d47b338424ed69e9ae5d774b06ae Author: Xi Ruoyao Date: Wed Mar 20 15:09:21 2024 +0800 mips: Fix C23 (...) functions returning large aggregates [PR114175] We were assuming TYPE_NO_NAMED_ARGS_S

[gcc r15-11] LoongArch: Add constraints for bit string operation define_insn_and_split's [PR114861]

https://gcc.gnu.org/g:140124ad54eef88ca87909f63aedc8aaeacefc65 commit r15-11-g140124ad54eef88ca87909f63aedc8aaeacefc65 Author: Xi Ruoyao Date: Fri Apr 26 15:59:11 2024 +0800 LoongArch: Add constraints for bit string operation define_insn_and_split's [PR114861] Without the constra

[gcc r14-10142] LoongArch: Add constraints for bit string operation define_insn_and_split's [PR114861]

https://gcc.gnu.org/g:3e04b6f6ba568e6183e8aa8223d4156234503843 commit r14-10142-g3e04b6f6ba568e6183e8aa8223d4156234503843 Author: Xi Ruoyao Date: Fri Apr 26 15:59:11 2024 +0800 LoongArch: Add constraints for bit string operation define_insn_and_split's [PR114861] Without the cons

[gcc r15-2426] LoongArch: Expand some SImode operations through "si3_extend" instructions if TARGET_64BIT

https://gcc.gnu.org/g:b929083dd83ab50f26e10bbaa5097d5f6fb3c908 commit r15-2426-gb929083dd83ab50f26e10bbaa5097d5f6fb3c908 Author: Xi Ruoyao Date: Sat Jul 20 20:38:13 2024 +0800 LoongArch: Expand some SImode operations through "si3_extend" instructions if TARGET_64BIT We already ha

[gcc r15-2432] LoongArch: Relax ins_zero_bitmask_operand and remove and3_align

https://gcc.gnu.org/g:70a4e79dc9ed73b056aa0362f61302e04227049f commit r15-2432-g70a4e79dc9ed73b056aa0362f61302e04227049f Author: Xi Ruoyao Date: Sun Jul 28 17:02:49 2024 +0800 LoongArch: Relax ins_zero_bitmask_operand and remove and3_align In r15-1207 I was too stupid to realize w

[gcc r15-2433] LoongArch: Rework bswap{hi,si,di}2 definition

https://gcc.gnu.org/g:996c2e2144c4a534b65424170c596dcbf44ba6db commit r15-2433-g996c2e2144c4a534b65424170c596dcbf44ba6db Author: Xi Ruoyao Date: Sun Jul 28 19:57:02 2024 +0800 LoongArch: Rework bswap{hi,si,di}2 definition Per a gcc-help thread we are generating sub-optimal code fo

[gcc r15-2791] vect: Fix vect_reduction_def check for odd/even widen mult [PR116142]

https://gcc.gnu.org/g:2083389a18d36684a88d9e2653bacc87ad894b50 commit r15-2791-g2083389a18d36684a88d9e2653bacc87ad894b50 Author: Xi Ruoyao Date: Tue Aug 6 17:48:42 2024 +0800 vect: Fix vect_reduction_def check for odd/even widen mult [PR116142] The check was implemented incorrectl

[gcc r15-2869] i386: testsuite: Add -no-pie for pr113689-1.c [PR70150]

https://gcc.gnu.org/g:331f7d8a393af99afccdb2729d4ab45797fd7a86 commit r15-2869-g331f7d8a393af99afccdb2729d4ab45797fd7a86 Author: Xi Ruoyao Date: Mon May 6 11:33:43 2024 +0800 i386: testsuite: Add -no-pie for pr113689-1.c [PR70150] For a --enable-default-pie build, using -fno-pic (

[gcc r15-2870] i386: testsuite: Adapt fentryname3.c for r14-811 change [PR70150]

https://gcc.gnu.org/g:8035619b7313d9503852e1c7c8c06cfddca4d648 commit r15-2870-g8035619b7313d9503852e1c7c8c06cfddca4d648 Author: Xi Ruoyao Date: Mon May 6 11:39:14 2024 +0800 i386: testsuite: Adapt fentryname3.c for r14-811 change [PR70150] After r14-811 "call *nop@GOTPCREL(%rip)"

[gcc r15-2931] LoongArch: Implement scalar isinf, isnormal, and isfinite via fclass

https://gcc.gnu.org/g:ee4a6343225b6e44b3d2b2c90c355c21f7ec6855 commit r15-2931-gee4a6343225b6e44b3d2b2c90c355c21f7ec6855 Author: Xi Ruoyao Date: Thu Jul 4 02:49:28 2024 +0800 LoongArch: Implement scalar isinf, isnormal, and isfinite via fclass Doing so can avoid loading FP constan

[gcc r15-856] LoongArch: Guard REGNO with REG_P in loongarch_expand_conditional_move [PR115169]

https://gcc.gnu.org/g:ded91d857772c0183cc342cdc54d9128f6c57fa2 commit r15-856-gded91d857772c0183cc342cdc54d9128f6c57fa2 Author: Xi Ruoyao Date: Wed May 22 09:29:43 2024 +0800 LoongArch: Guard REGNO with REG_P in loongarch_expand_conditional_move [PR115169] gcc/ChangeLog:

[gcc r14-10249] LoongArch: Guard REGNO with REG_P in loongarch_expand_conditional_move [PR115169]

https://gcc.gnu.org/g:e78980fdd5e82e09e26f524e98ad9cd90a29c1c4 commit r14-10249-ge78980fdd5e82e09e26f524e98ad9cd90a29c1c4 Author: Xi Ruoyao Date: Wed May 22 09:29:43 2024 +0800 LoongArch: Guard REGNO with REG_P in loongarch_expand_conditional_move [PR115169] gcc/ChangeLog:

[gcc r15-1206] LoongArch: Fix mode size comparision in loongarch_expand_conditional_move

https://gcc.gnu.org/g:53c703888eb51314f762c8998dc9215871b12722 commit r15-1206-g53c703888eb51314f762c8998dc9215871b12722 Author: Xi Ruoyao Date: Wed Jun 12 11:01:53 2024 +0800 LoongArch: Fix mode size comparision in loongarch_expand_conditional_move We were comparing a mode size w

[gcc r15-1207] LoongArch: Use bstrins for "value & (-1u << const)"

https://gcc.gnu.org/g:d0da347a1dd6e57cb0e0c55fd654d81dde545cf8 commit r15-1207-gd0da347a1dd6e57cb0e0c55fd654d81dde545cf8 Author: Xi Ruoyao Date: Sun Jun 9 14:43:48 2024 +0800 LoongArch: Use bstrins for "value & (-1u << const)" A move/bstrins pair is as fast as a (addi.w|lu12i.w|lu

[gcc r15-4172] LoongArch: Fix up r15-4130

https://gcc.gnu.org/g:60e99901aef8e7efd4d60adf9f82021fcbd1101f commit r15-4172-g60e99901aef8e7efd4d60adf9f82021fcbd1101f Author: Xi Ruoyao Date: Wed Jul 10 12:15:23 2024 +0800 LoongArch: Fix up r15-4130 An earlier version of the patch (lacking the regeneration of some files) w

[gcc r15-4845] testsuite: Fix up builtin-prefetch-1.c tests

https://gcc.gnu.org/g:e8689ac75faca61a0251d1098dbafa8c637ec489 commit r15-4845-ge8689ac75faca61a0251d1098dbafa8c637ec489 Author: Xi Ruoyao Date: Sat Nov 2 00:05:44 2024 +0800 testsuite: Fix up builtin-prefetch-1.c tests How can you use "read-shared" as an identifier? It's not all

[gcc r15-4842] Always set SECTION_RELRO for or .data.rel.ro{, .local} [PR116887]

https://gcc.gnu.org/g:c8d35f2ecbf124bdd164dbb1c36de9d90695843b commit r15-4842-gc8d35f2ecbf124bdd164dbb1c36de9d90695843b Author: Xi Ruoyao Date: Fri Oct 11 02:44:27 2024 +0800 Always set SECTION_RELRO for or .data.rel.ro{,.local} [PR116887] At least two ports (hppa and loongarch)

[gcc r15-4844] LoongArch: testsuite: Add -O for jump-table-annotate.c

https://gcc.gnu.org/g:caf6b6fdfdaa1d0d78b8d740aa0e0646ca182a2a commit r15-4844-gcaf6b6fdfdaa1d0d78b8d740aa0e0646ca182a2a Author: Xi Ruoyao Date: Sat Nov 2 01:26:47 2024 +0800 LoongArch: testsuite: Add -O for jump-table-annotate.c Without optimization, GCC does not emit a jump tabl

[gcc r15-5641] pa: Remove pa_section_type_flags

https://gcc.gnu.org/g:e1ac811d5a724e6714465ad951703d334248bc83 commit r15-5641-ge1ac811d5a724e6714465ad951703d334248bc83 Author: Xi Ruoyao Date: Sat Nov 2 20:20:32 2024 +0800 pa: Remove pa_section_type_flags It's no longer needed since r15-4842 (when the target-independent code

[gcc r15-7370] vect: Fix wrong code with pr108692.c on targets with only non-widening ABD [PR118727]

https://gcc.gnu.org/g:da88e7027a34a44de84f6d8d5a96d262c29080a7 commit r15-7370-gda88e7027a34a44de84f6d8d5a96d262c29080a7 Author: Xi Ruoyao Date: Sun Feb 2 21:22:36 2025 +0800 vect: Fix wrong code with pr108692.c on targets with only non-widening ABD [PR118727] With things like

[gcc r15-7408] LoongArch: Correct the mode for mask{eq,ne}z

https://gcc.gnu.org/g:bad9a7303a4b4ec8192e2ab5da49ab1a9cc86347 commit r15-7408-gbad9a7303a4b4ec8192e2ab5da49ab1a9cc86347 Author: Xi Ruoyao Date: Sun Jan 19 21:26:59 2025 +0800 LoongArch: Correct the mode for mask{eq,ne}z For mask{eq,ne}z, rk is always compared with 0 in the full w

[gcc r15-7465] testsuite: LoongArch: Remove from btrunc, ceil, and floor effective target allowlist

https://gcc.gnu.org/g:d171f214a43b1b18f1fc9b6aa1fc8a9e8c50953c commit r15-7465-gd171f214a43b1b18f1fc9b6aa1fc8a9e8c50953c Author: Xi Ruoyao Date: Wed Feb 5 09:16:19 2025 +0800 testsuite: LoongArch: Remove from btrunc, ceil, and floor effective target allowlist Now that C default i

[gcc r15-6322] LoongArch: Combine xor and crc instructions

https://gcc.gnu.org/g:80491b0493ac1e2b0cdbdfc3eab8c5c5a390d77c commit r15-6322-g80491b0493ac1e2b0cdbdfc3eab8c5c5a390d77c Author: Xi Ruoyao Date: Thu Dec 5 14:19:02 2024 +0800 LoongArch: Combine xor and crc instructions For a textbook-style CRC implementation: uint32_t

[gcc r15-6320] LoongArch: Add bit reverse operations

https://gcc.gnu.org/g:13ea50fdac104b674eb484936023e20dec0b62cf commit r15-6320-g13ea50fdac104b674eb484936023e20dec0b62cf Author: Xi Ruoyao Date: Mon Dec 2 10:53:27 2024 +0800 LoongArch: Add bit reverse operations LoongArch supports native bit reverse operation for QI, SI, DI, and

[gcc r15-6323] LoongArch: Add crc tests

https://gcc.gnu.org/g:c5424185b0c3652086efc914fa1e0c83365f6072 commit r15-6323-gc5424185b0c3652086efc914fa1e0c83365f6072 Author: Xi Ruoyao Date: Fri Dec 13 15:46:00 2024 +0800 LoongArch: Add crc tests gcc/testsuite/ChangeLog: * g++.target/loongarch/crc.C: New test

[gcc r15-6321] LoongArch: Add CRC expander to generate faster CRC

https://gcc.gnu.org/g:5b5b517e819837e1950cd4d809cdc6efb8e80302 commit r15-6321-g5b5b517e819837e1950cd4d809cdc6efb8e80302 Author: Xi Ruoyao Date: Mon Dec 16 20:43:03 2024 +0800 LoongArch: Add CRC expander to generate faster CRC 64-bit LoongArch has native CRC instructions for two s

[gcc r15-6319] LoongArch: Remove QHSD and use QHWD instead

https://gcc.gnu.org/g:8e47615f24b9fdebf14e270e6131cea6a67f1b04 commit r15-6319-g8e47615f24b9fdebf14e270e6131cea6a67f1b04 Author: Xi Ruoyao Date: Mon Dec 2 14:48:24 2024 +0800 LoongArch: Remove QHSD and use QHWD instead QHSD and QHWD are basically the same thing, but QHSD will be i

[gcc r15-7145] LoongArch: Fix invalid subregs in xorsign [PR118501]

https://gcc.gnu.org/g:9ddf4a6cc650360e620c8fd97f550bf833cc177a commit r15-7145-g9ddf4a6cc650360e620c8fd97f550bf833cc177a Author: Xi Ruoyao Date: Wed Jan 22 17:16:29 2025 +0800 LoongArch: Fix invalid subregs in xorsign [PR118501] The test case added in r15-7073 now triggers an ICE,

[gcc r15-7060] testsuite: Fix name of PR116348 test case

https://gcc.gnu.org/g:67b10ee872197ba53524db4f0ca777899e27b151 commit r15-7060-g67b10ee872197ba53524db4f0ca777899e27b151 Author: Xi Ruoyao Date: Mon Jan 20 20:41:34 2025 +0800 testsuite: Fix name of PR116348 test case gcc/testsuite/ChangeLog: * gcc.c-torture/compi

[gcc r15-7061] LoongArch: Simplify using bstr{ins, pick} instructions for and

https://gcc.gnu.org/g:f3bedc9a3b8b7dd3911272731a1ea595621e13cd commit r15-7061-gf3bedc9a3b8b7dd3911272731a1ea595621e13cd Author: Xi Ruoyao Date: Thu Sep 5 17:53:41 2024 +0800 LoongArch: Simplify using bstr{ins,pick} instructions for and For bstrins, we can merge it into and3 inste

[gcc r15-7062] LoongArch: Improve reassociation for bitwise operation and left shift [PR 115921]

https://gcc.gnu.org/g:10e98638998745ebc3888a20e661a8364e88ea3a commit r15-7062-g10e98638998745ebc3888a20e661a8364e88ea3a Author: Xi Ruoyao Date: Tue Jan 14 17:26:04 2025 +0800 LoongArch: Improve reassociation for bitwise operation and left shift [PR 115921] For things like

[gcc r15-7012] LoongArch: Fix cost model for alsl

https://gcc.gnu.org/g:ce36692f8e10a619563938851f507cdb15567cf8 commit r15-7012-gce36692f8e10a619563938851f507cdb15567cf8 Author: Xi Ruoyao Date: Fri Sep 6 00:34:55 2024 +0800 LoongArch: Fix cost model for alsl Our cost model for alsl was wrong: it matches (a + b * imm) where imm i

[gcc r15-7011] LoongArch: Add alsl.wu

https://gcc.gnu.org/g:cc6176a921cbe3b9db323b1cd557efe4f299171a commit r15-7011-gcc6176a921cbe3b9db323b1cd557efe4f299171a Author: Xi Ruoyao Date: Fri Sep 6 03:27:19 2024 +0800 LoongArch: Add alsl.wu On 64-bit capable LoongArch hardware, alsl.wu is similar to alsl.w but zero-ext

[gcc r15-7121] LoongArch: Fix wrong code with _alsl_reversesi_extended

https://gcc.gnu.org/g:8c93a8aa67f12c8e03eb7fd90f671a03ae46935b commit r15-7121-g8c93a8aa67f12c8e03eb7fd90f671a03ae46935b Author: Xi Ruoyao Date: Tue Jan 21 23:01:38 2025 +0800 LoongArch: Fix wrong code with _alsl_reversesi_extended The second source register of this insn cannot be

[gcc r15-7617] LoongArch: Allow moving TImode vectors

https://gcc.gnu.org/g:ac1b0586297c6d4d39380f77a4915728511d79f0 commit r15-7617-gac1b0586297c6d4d39380f77a4915728511d79f0 Author: Xi Ruoyao Date: Fri Jan 24 08:33:39 2025 +0800 LoongArch: Allow moving TImode vectors We have some vector instructions for operations on 128-bit integer

[gcc r15-7615] LoongArch: Accept ADD, IOR or XOR when combining objects with no bits in common [PR115478]

https://gcc.gnu.org/g:ea3ebe48150d2109845f2c4622ebff182f618d97 commit r15-7615-gea3ebe48150d2109845f2c4622ebff182f618d97 Author: Xi Ruoyao Date: Mon Feb 10 23:39:24 2025 +0800 LoongArch: Accept ADD, IOR or XOR when combining objects with no bits in common [PR115478] Since r15-112

[gcc r15-7616] LoongArch: Try harder using vrepli instructions to materialize const vectors

https://gcc.gnu.org/g:ed9794546db62279199a1cd84b8cdacd14ceab42 commit r15-7616-ged9794546db62279199a1cd84b8cdacd14ceab42 Author: Xi Ruoyao Date: Fri Jan 24 08:32:18 2025 +0800 LoongArch: Try harder using vrepli instructions to materialize const vectors For a = (v4si){0x

[gcc r15-7618] LoongArch: Simplify {lsx_, lasx_x}v{add, sub, mul}l{ev, od} description

https://gcc.gnu.org/g:a36c15aa6612bcb69a5784c014a6cd046d97ebb4 commit r15-7618-ga36c15aa6612bcb69a5784c014a6cd046d97ebb4 Author: Xi Ruoyao Date: Sat Feb 15 00:29:41 2025 +0800 LoongArch: Simplify {lsx_,lasx_x}v{add,sub,mul}l{ev,od} description These pattern definitions are tedious

[gcc r15-7622] LoongArch: Implement vec_widen_mult_{even, odd}_* for LSX and LASX modes

https://gcc.gnu.org/g:7c54e46b209664d3a501a03908339c9903d01f1e commit r15-7622-g7c54e46b209664d3a501a03908339c9903d01f1e Author: Xi Ruoyao Date: Mon Jan 20 20:43:07 2025 +0800 LoongArch: Implement vec_widen_mult_{even,odd}_* for LSX and LASX modes Since PR116142 has been fixed, no

[gcc r15-7620] LoongArch: Simplify {lsx_,lasx_x}vmaddw description

https://gcc.gnu.org/g:f727a4c57ec9f9ea628f6d330be513f01c318a61 commit r15-7620-gf727a4c57ec9f9ea628f6d330be513f01c318a61 Author: Xi Ruoyao Date: Fri Aug 9 10:23:07 2024 +0800 LoongArch: Simplify {lsx_,lasx_x}vmaddw description Like what we've done for {lsx_,lasx_x}v{add,sub,mul}l{

[gcc r15-7621] LoongArch: Simplify lsx_vpick description

https://gcc.gnu.org/g:7dda6715126c0c5aedbd5f2e4056adf43bb4ea2a commit r15-7621-g7dda6715126c0c5aedbd5f2e4056adf43bb4ea2a Author: Xi Ruoyao Date: Wed Feb 12 02:42:58 2025 +0800 LoongArch: Simplify lsx_vpick description Like what we've done for {lsx_,lasx_x}v{add,sub,mul}l{ev,od}, u

[gcc r15-7623] LoongArch: Implement [su]dot_prod* for LSX and LASX modes

https://gcc.gnu.org/g:cef5f23adb6f9f052d03286ad8ccf352eefccf86 commit r15-7623-gcef5f23adb6f9f052d03286ad8ccf352eefccf86 Author: Xi Ruoyao Date: Mon Jan 20 23:13:19 2025 +0800 LoongArch: Implement [su]dot_prod* for LSX and LASX modes Despite it's just a special case of "a widening

[gcc r15-7624] LoongArch: Use normal RTL pattern instead of UNSPEC for {x, }vsr{a, l}ri instructions

https://gcc.gnu.org/g:427386042f056a2910882bf0c632b4db68c52bbb commit r15-7624-g427386042f056a2910882bf0c632b4db68c52bbb Author: Xi Ruoyao Date: Thu Feb 13 22:51:31 2025 +0800 LoongArch: Use normal RTL pattern instead of UNSPEC for {x,}vsr{a,l}ri instructions Allowing (t + (1ul <

[gcc r15-7619] LoongArch: Simplify {lsx_, lasx_x}vh{add, sub}w description

https://gcc.gnu.org/g:2ca759fc529f0b74a593c7df54353281a0e5208c commit r15-7619-g2ca759fc529f0b74a593c7df54353281a0e5208c Author: Xi Ruoyao Date: Thu Aug 8 21:05:32 2024 +0800 LoongArch: Simplify {lsx_,lasx_x}vh{add,sub}w description Like what we've done for {lsx_,lasx_x}v{add,sub,

[gcc r14-11389] LoongArch: Fix incorrect reorder of __lsx_vldx and __lasx_xvldx [PR119084]

https://gcc.gnu.org/g:43d777078387ab2c4aabe526f6ee0ff13055e0b6 commit r14-11389-g43d777078387ab2c4aabe526f6ee0ff13055e0b6 Author: Xi Ruoyao Date: Sun Mar 2 19:02:50 2025 +0800 LoongArch: Fix incorrect reorder of __lsx_vldx and __lasx_xvldx [PR119084] They could be incorrectly reor

[gcc r15-7767] testsuite: Fix up toplevel-asm-1.c for LoongArch

https://gcc.gnu.org/g:20d95bfa29057104b352e5d82699edede8658499 commit r15-7767-g20d95bfa29057104b352e5d82699edede8658499 Author: Xi Ruoyao Date: Mon Feb 3 11:15:22 2025 +0800 testsuite: Fix up toplevel-asm-1.c for LoongArch Like RISC-V, on LoongArch we don't really support %cN for

[gcc r15-7923] LoongArch: Fix ICE when trying to recognize bitwise + alsl.w pair [PR119127]

https://gcc.gnu.org/g:c7d493baf13f1f144f2c4bc375383b6ce5d88a76 commit r15-7923-gc7d493baf13f1f144f2c4bc375383b6ce5d88a76 Author: Xi Ruoyao Date: Fri Mar 7 12:49:54 2025 +0800 LoongArch: Fix ICE when trying to recognize bitwise + alsl.w pair [PR119127] When we call loongarch_reasso

[gcc r15-7821] LoongArch: Fix incorrect reorder of __lsx_vldx and __lasx_xvldx [PR119084]

https://gcc.gnu.org/g:4856292f7a680ec478e7607f1b71781996d7d542 commit r15-7821-g4856292f7a680ec478e7607f1b71781996d7d542 Author: Xi Ruoyao Date: Sun Mar 2 19:02:50 2025 +0800 LoongArch: Fix incorrect reorder of __lsx_vldx and __lasx_xvldx [PR119084] They could be incorrectly reord

[gcc r15-8017] LoongArch: Don't use C++17 feature [PR119238]

https://gcc.gnu.org/g:4e6967aba1aaa9dfc362ce59b3d9358a6a15603c commit r15-8017-g4e6967aba1aaa9dfc362ce59b3d9358a6a15603c Author: Xi Ruoyao Date: Wed Mar 12 21:02:38 2025 +0800 LoongArch: Don't use C++17 feature [PR119238] Structured binding is a C++17 feature but the GCC code base

[gcc r15-8284] LoongArch: Add ABI names for FPR

https://gcc.gnu.org/g:d0110185eb78f14a8e485f410bee237c9c71548d commit r15-8284-gd0110185eb78f14a8e485f410bee237c9c71548d Author: Xi Ruoyao Date: Sun Mar 16 14:19:53 2025 +0800 LoongArch: Add ABI names for FPR We already allow the ABI names for GPR in inline asm clobber list, so

[gcc r14-11475] Reuse scratch registers generated by LRA

https://gcc.gnu.org/g:d54c8ebda8674fbed85e2a3c4f141ffe9fa7f8a4 commit r14-11475-gd54c8ebda8674fbed85e2a3c4f141ffe9fa7f8a4 Author: Denis Chertykov Date: Thu Oct 17 11:12:38 2024 +0400 Reuse scratch registers generated by LRA Test file: udivmoddi.c problem insn: 484 Bef

[gcc r15-9167] LoongArch: Make gen-evolution.awk compatible with FreeBSD awk

https://gcc.gnu.org/g:92ca72b41a74aef53978cadbda33dd38b69d3ed3 commit r15-9167-g92ca72b41a74aef53978cadbda33dd38b69d3ed3 Author: Xi Ruoyao Date: Wed Apr 2 10:41:18 2025 +0800 LoongArch: Make gen-evolution.awk compatible with FreeBSD awk Avoid using gensub that FreeBSD awk lacks, u