[gcc r15-342] RISC-V: Make full-vec-move1.c test robust for optimization

https://gcc.gnu.org/g:b1520d2260c5e0cfcd7a4354fab70f66e2912ff2 commit r15-342-gb1520d2260c5e0cfcd7a4354fab70f66e2912ff2 Author: Pan Li Date: Thu May 9 10:56:46 2024 +0800 RISC-V: Make full-vec-move1.c test robust for optimization During investigate the support of early break autov

[gcc r15-435] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar

https://gcc.gnu.org/g:41b3cf262e61aee9d26380f1c820e0eaae740f50 commit r15-435-g41b3cf262e61aee9d26380f1c820e0eaae740f50 Author: Pan Li Date: Sat May 11 15:25:28 2024 +0800 RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar For the vfw vx format RVV intrinsic, the scalar t

[gcc r15-442] RISC-V: Fix format issue for trailing operator [NFC]

https://gcc.gnu.org/g:b6dc8464e613d1da2b28235bbd2f9c3fd4bc386b commit r15-442-gb6dc8464e613d1da2b28235bbd2f9c3fd4bc386b Author: Pan Li Date: Tue May 14 09:38:55 2024 +0800 RISC-V: Fix format issue for trailing operator [NFC] This patch would like to fix below format issue of trail

[gcc r15-576] Internal-fn: Support new IFN SAT_ADD for unsigned scalar int

https://gcc.gnu.org/g:52b0536710ff3f3ace72ab00ce9ef6c630cd1183 commit r15-576-g52b0536710ff3f3ace72ab00ce9ef6c630cd1183 Author: Pan Li Date: Wed May 15 10:14:05 2024 +0800 Internal-fn: Support new IFN SAT_ADD for unsigned scalar int This patch would like to add the middle-end pres

[gcc r15-577] Vect: Support new IFN SAT_ADD for unsigned vector int

https://gcc.gnu.org/g:d4dee347b3fe1982bab26485ff31cd039c9df010 commit r15-577-gd4dee347b3fe1982bab26485ff31cd039c9df010 Author: Pan Li Date: Wed May 15 10:14:06 2024 +0800 Vect: Support new IFN SAT_ADD for unsigned vector int For vectorize, we leverage the existing vect pattern re

[gcc r15-578] Vect: Support loop len in vectorizable early exit

https://gcc.gnu.org/g:57f8a2f67c1536be23231808ab00613ab69193ed commit r15-578-g57f8a2f67c1536be23231808ab00613ab69193ed Author: Pan Li Date: Thu May 16 09:58:13 2024 +0800 Vect: Support loop len in vectorizable early exit This patch adds early break auto-vectorization support for

[gcc r15-582] RISC-V: Implement vectorizable early exit with vcond_mask_len

https://gcc.gnu.org/g:6c1de786e53a11150feb16ba990d0d6c6fd910db commit r15-582-g6c1de786e53a11150feb16ba990d0d6c6fd910db Author: Pan Li Date: Thu May 16 10:02:40 2024 +0800 RISC-V: Implement vectorizable early exit with vcond_mask_len After we support the loop lens for the vectoriz

[gcc r15-583] RISC-V: Enable vectorizable early exit testsuite

https://gcc.gnu.org/g:556e777298dac8574533935000c57335c5232921 commit r15-583-g556e777298dac8574533935000c57335c5232921 Author: Pan Li Date: Thu May 16 10:04:10 2024 +0800 RISC-V: Enable vectorizable early exit testsuite After we supported vectorizable early exit in RISC-V, we wo

[gcc r15-585] RISC-V: Cleanup some temporally files [NFC]

https://gcc.gnu.org/g:d477d683d5c6db90c80d348c795709ae6444ba7a commit r15-585-gd477d683d5c6db90c80d348c795709ae6444ba7a Author: Pan Li Date: Fri May 17 07:45:19 2024 +0800 RISC-V: Cleanup some temporally files [NFC] Just notice some temporally files under gcc/config/riscv, del

[gcc r15-642] RISC-V: Implement IFN SAT_ADD for both the scalar and vector

https://gcc.gnu.org/g:34ed2b4593fa98b613632d0dde30b6ba3e7ecad9 commit r15-642-g34ed2b4593fa98b613632d0dde30b6ba3e7ecad9 Author: Pan Li Date: Fri May 17 18:49:46 2024 +0800 RISC-V: Implement IFN SAT_ADD for both the scalar and vector The patch implement the SAT_ADD in the riscv bac

[gcc r15-655] DSE: Fix ICE after allow vector type in get_stored_val

https://gcc.gnu.org/g:88b3f83238087cbe2aa2c51c6054796856f2fb94 commit r15-655-g88b3f83238087cbe2aa2c51c6054796856f2fb94 Author: Pan Li Date: Tue Apr 30 09:42:39 2024 +0800 DSE: Fix ICE after allow vector type in get_stored_val We allowed vector type for get_stored_val when read is

[gcc r15-2962] RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305]

https://gcc.gnu.org/g:a11dcaff9fc94971188d54310d3053e9f68a0d3d commit r15-2962-ga11dcaff9fc94971188d54310d3053e9f68a0d3d Author: 曾治金 Date: Wed Aug 14 14:06:23 2024 +0800 RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305] This patch is to fix the bug (BugId:116305) int

[gcc r15-2977] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2

https://gcc.gnu.org/g:6fbdbad97d451cc220a5654c8b97b9911485ef4a commit r15-2977-g6fbdbad97d451cc220a5654c8b97b9911485ef4a Author: Pan Li Date: Sat Aug 17 18:04:00 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2 This patch would like to add test cases for the

[gcc r15-2978] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3

https://gcc.gnu.org/g:8d0efcf5581abf2560701f4143a0c2ccb261d1f7 commit r15-2978-g8d0efcf5581abf2560701f4143a0c2ccb261d1f7 Author: Pan Li Date: Sat Aug 17 19:27:11 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3 This patch would like to add test cases for the

[gcc r15-2979] RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]

https://gcc.gnu.org/g:e8f31f4f58f0fcf1716fc1d9ee003fbcdda600c3 commit r15-2979-ge8f31f4f58f0fcf1716fc1d9ee003fbcdda600c3 Author: Pan Li Date: Fri Aug 9 10:26:32 2024 +0800 RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278] For QI/HImode of .SAT_ADD,

[gcc r15-2980] RISC-V: Implement the quad and oct .SAT_TRUNC for scalar

https://gcc.gnu.org/g:a183b255be8ec8f434c3c39f3f4e01d6bd5566f8 commit r15-2980-ga183b255be8ec8f434c3c39f3f4e01d6bd5566f8 Author: Pan Li Date: Tue Jul 23 11:18:48 2024 +0800 RISC-V: Implement the quad and oct .SAT_TRUNC for scalar This patch would like to implement the quad and oct

[gcc r15-3054] RISC-V: Fix one typo in .SAT_TRUNC test func name [NFC]

https://gcc.gnu.org/g:1b72e07696a062e628c35e4bd25926c11ac18297 commit r15-3054-g1b72e07696a062e628c35e4bd25926c11ac18297 Author: Pan Li Date: Tue Aug 20 21:08:23 2024 +0800 RISC-V: Fix one typo in .SAT_TRUNC test func name [NFC] Fix one typo `sat_truc` to `sat_trunc`, as well as `

[gcc r15-3075] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2

https://gcc.gnu.org/g:1e99e1ba79964f47f8850871d025209dfab73693 commit r15-3075-g1e99e1ba79964f47f8850871d025209dfab73693 Author: Pan Li Date: Wed Aug 21 17:43:12 2024 +0800 RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2 This patch would like to add test cases for the

[gcc r15-3076] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3

https://gcc.gnu.org/g:91f213908c0443b0249490b03b8046509f6e7e9d commit r15-3076-g91f213908c0443b0249490b03b8046509f6e7e9d Author: Pan Li Date: Wed Aug 21 17:57:47 2024 +0800 RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3 This patch would like to add test cases for the

[gcc r15-3122] Match: Support form 4 for unsigned integer .SAT_TRUNC

https://gcc.gnu.org/g:07988874c340e575521473b01dc98c8a1b2886b5 commit r15-3122-g07988874c340e575521473b01dc98c8a1b2886b5 Author: Pan Li Date: Tue Aug 20 15:44:38 2024 +0800 Match: Support form 4 for unsigned integer .SAT_TRUNC This patch would like to support the form 4 of the uns

[gcc r15-3172] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4

https://gcc.gnu.org/g:5ab1e238aa23d1773429f8f28abfb6ed16f655f6 commit r15-3172-g5ab1e238aa23d1773429f8f28abfb6ed16f655f6 Author: Pan Li Date: Sun Aug 25 11:02:10 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4 This patch would like to add test cases for the

[gcc r15-3173] RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4

https://gcc.gnu.org/g:8f2f7aabcef8d801af002a26885a97ccf9889099 commit r15-3173-g8f2f7aabcef8d801af002a26885a97ccf9889099 Author: Pan Li Date: Sun Aug 25 14:15:40 2024 +0800 RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4 This patch would like to add test cases for the

[gcc r15-3174] RISC-V: Support IMM for operand 0 of ussub pattern

https://gcc.gnu.org/g:17be00916e51835dcc47e30ed32fc892ee0c581d commit r15-3174-g17be00916e51835dcc47e30ed32fc892ee0c581d Author: Pan Li Date: Sat Aug 3 07:02:57 2024 + RISC-V: Support IMM for operand 0 of ussub pattern This patch would like to allow IMM for the operand 0 of us

[gcc r15-3188] Match: Add int type fits check for .SAT_ADD imm operand

https://gcc.gnu.org/g:3b78aa3e316a22b4ae477c91866d47f654f129b1 commit r15-3188-g3b78aa3e316a22b4ae477c91866d47f654f129b1 Author: Pan Li Date: Sat Aug 24 10:16:28 2024 +0800 Match: Add int type fits check for .SAT_ADD imm operand This patch would like to add strict check for imm op

[gcc r15-3208] RISC-V: Support IMM for operand 1 of ussub pattern

https://gcc.gnu.org/g:a1062b0c07bb729cf6a1fff34929d22e5d5b633d commit r15-3208-ga1062b0c07bb729cf6a1fff34929d22e5d5b633d Author: Pan Li Date: Mon Aug 26 15:58:52 2024 +0800 RISC-V: Support IMM for operand 1 of ussub pattern This patch would like to allow IMM for the operand 1 of u

[gcc r15-3238] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3

https://gcc.gnu.org/g:cb0b8b62223b485a058a56fc5c6345974ebaa230 commit r15-3238-gcb0b8b62223b485a058a56fc5c6345974ebaa230 Author: Pan Li Date: Tue Aug 27 14:37:01 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3 This patch would like to add test cases for th

[gcc r15-3239] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 4

https://gcc.gnu.org/g:3989e31d867b3505f847ecb6d870eacacfdf47bf commit r15-3239-g3989e31d867b3505f847ecb6d870eacacfdf47bf Author: Pan Li Date: Tue Aug 27 15:14:40 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 4 This patch would like to add test cases for th

[gcc r15-3241] Match: Support form 1 for scalar signed integer .SAT_ADD

https://gcc.gnu.org/g:fe5f652bab420eb372645281f7fe3e5aa1534d01 commit r15-3241-gfe5f652bab420eb372645281f7fe3e5aa1534d01 Author: Pan Li Date: Mon Aug 26 10:11:38 2024 +0800 Match: Support form 1 for scalar signed integer .SAT_ADD This patch would like to support the form 1 of the

[gcc r15-3243] Vect: Reconcile the const_int operand type of unsigned .SAT_ADD

https://gcc.gnu.org/g:6dccd5710380429c7addec9fe92a1a0bcb2f3367 commit r15-3243-g6dccd5710380429c7addec9fe92a1a0bcb2f3367 Author: Pan Li Date: Tue Aug 27 15:01:02 2024 +0800 Vect: Reconcile the const_int operand type of unsigned .SAT_ADD The .SAT_ADD has 2 operand, when one of the

[gcc r15-3244] Test: Move pr116278 run test to dg/torture [NFC]

https://gcc.gnu.org/g:3178786c88761e47b3cbe700a97a0de2b6e133cb commit r15-3244-g3178786c88761e47b3cbe700a97a0de2b6e133cb Author: Pan Li Date: Mon Aug 19 10:02:46 2024 +0800 Test: Move pr116278 run test to dg/torture [NFC] Move the run test of pr116278 to dg/torture and leave the r

[gcc r15-3348] RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM

https://gcc.gnu.org/g:72f3e9021e55f14e90773cf2966805a318f44842 commit r15-3348-g72f3e9021e55f14e90773cf2966805a318f44842 Author: Pan Li Date: Fri Aug 30 08:36:45 2024 +0800 RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM This patch would like to add test cases for

[gcc r15-3349] RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM

https://gcc.gnu.org/g:56ed1dfa79c436b769f3266258d34d160b4330d9 commit r15-3349-g56ed1dfa79c436b769f3266258d34d160b4330d9 Author: Pan Li Date: Fri Aug 30 11:01:37 2024 +0800 RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM This patch would like to add test cases for

[gcc r15-3347] RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64

https://gcc.gnu.org/g:e96d4bf6a6e8b8a5ea1b81a79f4efa07dee77af1 commit r15-3347-ge96d4bf6a6e8b8a5ea1b81a79f4efa07dee77af1 Author: Pan Li Date: Fri Aug 30 14:07:12 2024 +0800 RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64 In previous, we have some speciall

[gcc r15-3351] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3

https://gcc.gnu.org/g:5239902210a16b22d59d2cf8b535d615922a5c00 commit r15-3351-g5239902210a16b22d59d2cf8b535d615922a5c00 Author: Pan Li Date: Sun Aug 18 14:08:21 2024 +0800 RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3 This patch would like to add test c

[gcc r15-3350] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2

https://gcc.gnu.org/g:ea81e21d5398bdacf883533fd738fc45ea8d6dd9 commit r15-3350-gea81e21d5398bdacf883533fd738fc45ea8d6dd9 Author: Pan Li Date: Sun Aug 18 12:49:47 2024 +0800 RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2 This patch would like to add test c

[gcc r15-3390] RISC-V: Support form 1 of integer scalar .SAT_ADD

https://gcc.gnu.org/g:539fcaae67c6cf54bd377eba6c9d5b1792a3 commit r15-3390-g539fcaae67c6cf54bd377eba6c9d5b1792a3 Author: Pan Li Date: Thu Aug 29 11:25:44 2024 +0800 RISC-V: Support form 1 of integer scalar .SAT_ADD This patch would like to support the scalar signed ssadd p

[gcc r15-3438] RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD

https://gcc.gnu.org/g:9ea9d05908432fc5f3632f3e397e3709f95ef636 commit r15-3438-g9ea9d05908432fc5f3632f3e397e3709f95ef636 Author: Pan Li Date: Mon Sep 2 15:54:43 2024 +0800 RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD This patch would like to allow the IMM operand of the

[gcc r15-3502] Match: Add int type fits check for form 1 of .SAT_SUB imm operand

https://gcc.gnu.org/g:019335b404c8d7fb2d234bb179745cc28693dd20 commit r15-3502-g019335b404c8d7fb2d234bb179745cc28693dd20 Author: Pan Li Date: Mon Sep 2 09:48:46 2024 +0800 Match: Add int type fits check for form 1 of .SAT_SUB imm operand This patch would like to add strict check f

[gcc r15-3503] Match: Add int type fits check for form 2 of .SAT_SUB imm operand

https://gcc.gnu.org/g:a2e28b105cea4c44c3903d8d979c7a4afa1193f0 commit r15-3503-ga2e28b105cea4c44c3903d8d979c7a4afa1193f0 Author: Pan Li Date: Mon Sep 2 11:33:08 2024 +0800 Match: Add int type fits check for form 2 of .SAT_SUB imm operand This patch would like to add strict check f

[gcc r15-3569] Match: Support form 2 for scalar signed integer .SAT_ADD

https://gcc.gnu.org/g:a7eaf7d5edb194bae0d7d9bc3d20bb5730be57d8 commit r15-3569-ga7eaf7d5edb194bae0d7d9bc3d20bb5730be57d8 Author: Pan Li Date: Tue Sep 3 15:39:16 2024 +0800 Match: Support form 2 for scalar signed integer .SAT_ADD This patch would like to support the form 2 of the s

[gcc r15-3578] RISC-V: Fix asm check for Vector SAT_* due to middle-end change

https://gcc.gnu.org/g:6bd3ee7f2f2f4beed5b9d9a530736ad69d2cac42 commit r15-3578-g6bd3ee7f2f2f4beed5b9d9a530736ad69d2cac42 Author: Pan Li Date: Wed Sep 11 07:00:13 2024 +0800 RISC-V: Fix asm check for Vector SAT_* due to middle-end change The middle-end change makes the effect on th

[gcc r15-3580] Vect: Support form 1 of vector signed integer .SAT_ADD

https://gcc.gnu.org/g:9b14a5823b685e3a604dc17b02c033f60ad90414 commit r15-3580-g9b14a5823b685e3a604dc17b02c033f60ad90414 Author: Pan Li Date: Wed Sep 11 09:54:38 2024 +0800 Vect: Support form 1 of vector signed integer .SAT_ADD This patch would like to support the vector signed ss

[gcc r15-3593] RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass

https://gcc.gnu.org/g:c08e493ceee47bbeb466eeef100be7c1dd01a4e5 commit r15-3593-gc08e493ceee47bbeb466eeef100be7c1dd01a4e5 Author: garthlei Date: Wed Sep 11 17:09:37 2024 +0800 RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass This patch fixes a bug in the current vsetvl pass

[gcc r15-3595] RISC-V: Eliminate latter vsetvl when fused

https://gcc.gnu.org/g:3f212eabbba3edc1827d6da53cf6d5a64c6524f0 commit r15-3595-g3f212eabbba3edc1827d6da53cf6d5a64c6524f0 Author: Bohan Lei Date: Thu Sep 12 10:28:03 2024 +0800 RISC-V: Eliminate latter vsetvl when fused Hi all, A simple assembly check has been added in thi

[gcc r15-3620] Match: Remove unnecessary types_match for case 1 of signed SAT_ADD

https://gcc.gnu.org/g:45e7cc9caf327bfddd75b3093eb855b8b64acae8 commit r15-3620-g45e7cc9caf327bfddd75b3093eb855b8b64acae8 Author: Pan Li Date: Fri Sep 13 11:36:40 2024 +0800 Match: Remove unnecessary types_match for case 1 of signed SAT_ADD Given all commutative binary operators re

[gcc r15-1671] Vect: Support truncate after .SAT_SUB pattern in zip

https://gcc.gnu.org/g:f2476a2649e9975d454d179145574c21d8218aee commit r15-1671-gf2476a2649e9975d454d179145574c21d8218aee Author: Pan Li Date: Thu Jun 27 09:28:04 2024 +0800 Vect: Support truncate after .SAT_SUB pattern in zip The zip benchmark of coremark-pro have one SAT_SUB like

[gcc r15-1672] Internal-fn: Support new IFN SAT_TRUNC for unsigned scalar int

https://gcc.gnu.org/g:212441e19d8179645efbec6dd98a74eb673734dd commit r15-1672-g212441e19d8179645efbec6dd98a74eb673734dd Author: Pan Li Date: Wed Jun 26 09:28:05 2024 +0800 Internal-fn: Support new IFN SAT_TRUNC for unsigned scalar int This patch would like to add the middle-end p

[gcc r15-1676] RISC-V: Add testcases for vector truncate after .SAT_SUB

https://gcc.gnu.org/g:b55798c0fc5cb02512b58502961d8425fb60588f commit r15-1676-gb55798c0fc5cb02512b58502961d8425fb60588f Author: Pan Li Date: Mon Jun 24 22:25:57 2024 +0800 RISC-V: Add testcases for vector truncate after .SAT_SUB This patch would like to add the test cases of the

[gcc r15-1721] Match: Support imm form for unsigned scalar .SAT_ADD

https://gcc.gnu.org/g:21e3565927eda5ce9907d91100623052fa8182cd commit r15-1721-g21e3565927eda5ce9907d91100623052fa8182cd Author: Pan Li Date: Fri Jun 28 11:33:41 2024 +0800 Match: Support imm form for unsigned scalar .SAT_ADD This patch would like to support the form of unsigned s

[gcc r15-1753] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1

https://gcc.gnu.org/g:ed213b384fdca9375c3ec53c2a0eae134fb98612 commit r15-1753-ged213b384fdca9375c3ec53c2a0eae134fb98612 Author: Pan Li Date: Sun Jun 30 16:03:41 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 1 This patch would like to add test cases for th

[gcc r15-1754] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2

https://gcc.gnu.org/g:bff0d025aff8efaa5d991fcd13dd9876b115dc94 commit r15-1754-gbff0d025aff8efaa5d991fcd13dd9876b115dc94 Author: Pan Li Date: Sun Jun 30 16:14:38 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 2 This patch would like to add test cases for th

[gcc r15-1755] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3

https://gcc.gnu.org/g:6d98e88f61f9b2e6864775ce390e9ce0a1359624 commit r15-1755-g6d98e88f61f9b2e6864775ce390e9ce0a1359624 Author: Pan Li Date: Sun Jun 30 16:41:16 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 3 This patch would like to add test cases for th

[gcc r15-1756] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4

https://gcc.gnu.org/g:7a65ab6b5f38d3018ffd456f278a9fd885487a27 commit r15-1756-g7a65ab6b5f38d3018ffd456f278a9fd885487a27 Author: Pan Li Date: Sun Jun 30 16:48:19 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM form 4 This patch would like to add test cases for th

[gcc r15-1805] RISC-V: Fix asm check failure for truncated after SAT_SUB

https://gcc.gnu.org/g:ab3e3d2f0564c2eb0640de3f4d0a50e1fcc8c318 commit r15-1805-gab3e3d2f0564c2eb0640de3f4d0a50e1fcc8c318 Author: Pan Li Date: Wed Jul 3 13:17:16 2024 +0800 RISC-V: Fix asm check failure for truncated after SAT_SUB It seems that the asm check is incorrect for trunca

[gcc r15-1819] Vect: Support IFN SAT_TRUNC for unsigned vector int

https://gcc.gnu.org/g:8d2c460e79aa013cc4eeb79bb45d18bd3d0aee58 commit r15-1819-g8d2c460e79aa013cc4eeb79bb45d18bd3d0aee58 Author: Pan Li Date: Tue Jul 2 21:23:43 2024 +0800 Vect: Support IFN SAT_TRUNC for unsigned vector int This patch would like to support the .SAT_TRUNC for the u

[gcc r15-1820] Match: Allow more types truncation for .SAT_TRUNC

https://gcc.gnu.org/g:44c767c06b6882d05fe56f4a3e03195101402fb0 commit r15-1820-g44c767c06b6882d05fe56f4a3e03195101402fb0 Author: Pan Li Date: Tue Jul 2 08:57:50 2024 +0800 Match: Allow more types truncation for .SAT_TRUNC The .SAT_TRUNC has the input and output types, aka cvt fro

[gcc r15-1822] RISC-V: Bugfix vfmv insn honor zvfhmin for FP16 SEW [PR115763]

https://gcc.gnu.org/g:de9254e224eb3d89303cb9b3ba50b4c479c55f7c commit r15-1822-gde9254e224eb3d89303cb9b3ba50b4c479c55f7c Author: Pan Li Date: Wed Jul 3 22:06:48 2024 +0800 RISC-V: Bugfix vfmv insn honor zvfhmin for FP16 SEW [PR115763] According to the ISA, the zvfhmin sub extensi

[gcc r15-1894] RISC-V: Implement .SAT_TRUNC for vector unsigned int

https://gcc.gnu.org/g:dafd63d7c5cddce1e00803606e742d75927b1a1e commit r15-1894-gdafd63d7c5cddce1e00803606e742d75927b1a1e Author: Pan Li Date: Fri Jul 5 09:02:47 2024 +0800 RISC-V: Implement .SAT_TRUNC for vector unsigned int This patch would like to implement the .SAT_TRUNC for th

[gcc r15-1903] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1

https://gcc.gnu.org/g:35b1096896a94a90d787f5ef402ba009dd4f0393 commit r15-1903-g35b1096896a94a90d787f5ef402ba009dd4f0393 Author: Pan Li Date: Mon Jul 8 20:31:31 2024 +0800 RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1 After the middle-end supported the vector mode

[gcc r15-1904] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2

https://gcc.gnu.org/g:ecde8d50bea3573194f21277666f83463cbbe9c9 commit r15-1904-gecde8d50bea3573194f21277666f83463cbbe9c9 Author: Pan Li Date: Mon Jul 8 21:58:59 2024 +0800 RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2 After the middle-end supported the vector mode

[gcc r14-10396] RISC-V: Bugfix vfmv insn honor zvfhmin for FP16 SEW [PR115763]

https://gcc.gnu.org/g:505382ceee0b5e72dc5defa05aec77a97658feca commit r14-10396-g505382ceee0b5e72dc5defa05aec77a97658feca Author: Pan Li Date: Wed Jul 3 22:06:48 2024 +0800 RISC-V: Bugfix vfmv insn honor zvfhmin for FP16 SEW [PR115763] According to the ISA, the zvfhmin sub extens

[gcc r15-1936] Match: Support form 2 for the .SAT_TRUNC

https://gcc.gnu.org/g:80e446e829d818dc19daa6e671b9626e93ee4949 commit r15-1936-g80e446e829d818dc19daa6e671b9626e93ee4949 Author: Pan Li Date: Fri Jul 5 20:36:35 2024 +0800 Match: Support form 2 for the .SAT_TRUNC This patch would like to add form 2 support for the .SAT_TRUNC. Aka

[gcc r15-1959] Vect: Optimize truncation for .SAT_SUB operands

https://gcc.gnu.org/g:3918bea620e826b0df68a9c8492b791a67f294b5 commit r15-1959-g3918bea620e826b0df68a9c8492b791a67f294b5 Author: Pan Li Date: Sun Jun 30 10:55:50 2024 +0800 Vect: Optimize truncation for .SAT_SUB operands To get better vectorized code of .SAT_SUB, we would like to

[gcc r15-1967] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark

https://gcc.gnu.org/g:b3c686416e88bf135def0e72d316713af01445a1 commit r15-1967-gb3c686416e88bf135def0e72d316713af01445a1 Author: Pan Li Date: Thu Jul 11 15:54:32 2024 +0800 RISC-V: Add testcases for vector .SAT_SUB in zip benchmark This patch would like to add the test cases for t

[gcc r15-2138] Doc: Add Standard-Names ustrunc and sstrunc for integer modes

https://gcc.gnu.org/g:ebac11afbcb7a52536da5f04fc524b870f5d76e0 commit r15-2138-gebac11afbcb7a52536da5f04fc524b870f5d76e0 Author: Pan Li Date: Thu Jul 18 11:30:38 2024 +0800 Doc: Add Standard-Names ustrunc and sstrunc for integer modes This patch would like to add the doc for the S

[gcc r15-2149] Match: Only allow single use of MIN_EXPR for SAT_TRUNC form 2 [PR115863]

https://gcc.gnu.org/g:02cc8494745c4235890ad58e93b5acce5a89a775 commit r15-2149-g02cc8494745c4235890ad58e93b5acce5a89a775 Author: Pan Li Date: Thu Jul 18 20:16:34 2024 +0800 Match: Only allow single use of MIN_EXPR for SAT_TRUNC form 2 [PR115863] The SAT_TRUNC form 2 has below patt

[gcc r15-2189] RISC-V: Rearrange the test helper files for vector .SAT_*

https://gcc.gnu.org/g:4ab19e461159989b7fb43e858190adcf480762b7 commit r15-2189-g4ab19e461159989b7fb43e858190adcf480762b7 Author: Pan Li Date: Sat Jul 20 10:43:44 2024 +0800 RISC-V: Rearrange the test helper files for vector .SAT_* Rearrange the test help header files, as well as

[gcc r15-2209] RISC-V: Implement the .SAT_TRUNC for scalar

https://gcc.gnu.org/g:5d2115b850df63b0ecdf56efb720ad848e7afe21 commit r15-2209-g5d2115b850df63b0ecdf56efb720ad848e7afe21 Author: Pan Li Date: Mon Jul 1 16:36:35 2024 +0800 RISC-V: Implement the .SAT_TRUNC for scalar This patch would like to implement the simple .SAT_TRUNC pattern

[gcc r15-2241] Internal-fn: Only allow modes describe types for internal fn[PR115961]

https://gcc.gnu.org/g:905973410957891fec8a3e42eeefa4618780e0ce commit r15-2241-g905973410957891fec8a3e42eeefa4618780e0ce Author: Pan Li Date: Thu Jul 18 17:23:36 2024 +0800 Internal-fn: Only allow modes describe types for internal fn[PR115961] The direct_internal_fn_supported_p ha

[gcc r14-9418] VECT: Fix ICE for vectorizable LD/ST when both len and store are enabled

https://gcc.gnu.org/g:993c6de642ffeb2867edbe80ff2a72c0a2eb604e commit r14-9418-g993c6de642ffeb2867edbe80ff2a72c0a2eb604e Author: Pan Li Date: Sun Mar 10 11:02:35 2024 +0800 VECT: Fix ICE for vectorizable LD/ST when both len and store are enabled This patch would like to fix one IC

[gcc r14-9436] RISC-V: Fix some code style issue(s) in riscv-c.cc [NFC]

https://gcc.gnu.org/g:cdf0c6604d03afd7f544dd8bd5d43d9ded059ada commit r14-9436-gcdf0c6604d03afd7f544dd8bd5d43d9ded059ada Author: Pan Li Date: Tue Mar 12 15:01:57 2024 +0800 RISC-V: Fix some code style issue(s) in riscv-c.cc [NFC] Notice some code style issue(s) when add __riscv_v_

[gcc r14-9604] RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))

https://gcc.gnu.org/g:d3c24e9e55a7cf18df313a8b32b6de4b3ba81013 commit r14-9604-gd3c24e9e55a7cf18df313a8b32b6de4b3ba81013 Author: Pan Li Date: Mon Mar 18 11:21:29 2024 +0800 RISC-V: Bugfix ICE for __attribute__((target("arch=+v")) This patch would like to fix one ICE for __attribut

[gcc r14-9605] RISC-V: Bugfix function target attribute pollution

https://gcc.gnu.org/g:9941f0295a14659e25260458efd2e46a68ad0342 commit r14-9605-g9941f0295a14659e25260458efd2e46a68ad0342 Author: Pan Li Date: Tue Mar 19 09:43:24 2024 +0800 RISC-V: Bugfix function target attribute pollution This patch depends on below ICE fix. https://gcc

[gcc r14-9616] RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV

https://gcc.gnu.org/g:47de95d801c6899033c303b1fe642feb0489994f commit r14-9616-g47de95d801c6899033c303b1fe642feb0489994f Author: Pan Li Date: Fri Mar 22 14:43:47 2024 +0800 RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV This patch would like to introduce one new gcc

[gcc r14-9651] RISC-V: Allow RVV intrinsic when function target("arch=+v")

https://gcc.gnu.org/g:5cab64a9cfb93fb0e246a25e3fdc7b664afb774e commit r14-9651-g5cab64a9cfb93fb0e246a25e3fdc7b664afb774e Author: Pan Li Date: Mon Mar 25 14:22:31 2024 +0800 RISC-V: Allow RVV intrinsic when function target("arch=+v") This patch would like to allow the RVV intrinsic

[gcc r14-9730] RISC-V: Fix one unused varable in riscv_subset_list::parse

https://gcc.gnu.org/g:46eb34a75a9d004ce776bba382fe8af0978cace7 commit r14-9730-g46eb34a75a9d004ce776bba382fe8af0978cace7 Author: Pan Li Date: Sat Mar 30 21:32:06 2024 +0800 RISC-V: Fix one unused varable in riscv_subset_list::parse This patch would like to fix one unused variable

[gcc r14-9731] RISC-V: Fix misspelled term builtin in error message

https://gcc.gnu.org/g:b313baba57f7e09f66b603e1e30dd4b48800693f commit r14-9731-gb313baba57f7e09f66b603e1e30dd4b48800693f Author: Pan Li Date: Sat Mar 30 20:03:18 2024 +0800 RISC-V: Fix misspelled term builtin in error message This patch would like to fix below misspelled term in e

[gcc r14-9828] RISC-V: Refine the error msg for RVV intrinisc required ext

https://gcc.gnu.org/g:7d051f7d45789e1442d26c07bfc5e7fb77433b87 commit r14-9828-g7d051f7d45789e1442d26c07bfc5e7fb77433b87 Author: Pan Li Date: Mon Apr 8 12:33:05 2024 +0800 RISC-V: Refine the error msg for RVV intrinisc required ext The RVV intrinisc API has sorts of required exten

[gcc r14-9908] RISC-V: Bugfix ICE for the vector return arg in mode switch

https://gcc.gnu.org/g:e40a3d86511efcea71e9eadde8fb9f96be52f790 commit r14-9908-ge40a3d86511efcea71e9eadde8fb9f96be52f790 Author: Pan Li Date: Thu Apr 11 09:39:44 2024 +0800 RISC-V: Bugfix ICE for the vector return arg in mode switch This patch would like to fix a ICE in mode sw fo

[gcc r14-9909] RISC-V: Remove -Wno-psabi for test build option [NFC]

https://gcc.gnu.org/g:f3fdcf4a37a7be07f2acbf5c8ed5e3399440a0ef commit r14-9909-gf3fdcf4a37a7be07f2acbf5c8ed5e3399440a0ef Author: Pan Li Date: Thu Apr 11 11:42:40 2024 +0800 RISC-V: Remove -Wno-psabi for test build option [NFC] Just notice there are some test case still have -Wno-p

[gcc r14-9930] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P

https://gcc.gnu.org/g:dc51a6428f6d8e5a57b8b1bf559145288e87660b commit r14-9930-gdc51a6428f6d8e5a57b8b1bf559145288e87660b Author: Pan Li Date: Fri Apr 12 11:12:24 2024 +0800 RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P This patch would like to fix one ICE when vec

[gcc r14-9936] RISC-V: Fix Werror=sign-compare in riscv_validate_vector_type

https://gcc.gnu.org/g:6e7e5943619a2c20d93fc7089c885483786558bc commit r14-9936-g6e7e5943619a2c20d93fc7089c885483786558bc Author: Pan Li Date: Fri Apr 12 16:38:18 2024 +0800 RISC-V: Fix Werror=sign-compare in riscv_validate_vector_type This patch would like to fix the Werror=sign-c

[gcc r14-10049] Revert "RISC-V: Support one more overlap for wv instructions"

https://gcc.gnu.org/g:0cbeafe26513954b0aea3293d2f82d4863f10f1d commit r14-10049-g0cbeafe26513954b0aea3293d2f82d4863f10f1d Author: Pan Li Date: Sat Apr 20 08:29:38 2024 +0800 Revert "RISC-V: Support one more overlap for wv instructions" This reverts commit b3b2799b872bc4c1944629af9

[gcc r14-10050] RISC-V: Add xfail test case for wv insn register overlap

https://gcc.gnu.org/g:9f10005dbc9b660465ec4a9640bcbdcc1e5171c3 commit r14-10050-g9f10005dbc9b660465ec4a9640bcbdcc1e5171c3 Author: Pan Li Date: Sat Apr 20 09:02:39 2024 +0800 RISC-V: Add xfail test case for wv insn register overlap We reverted below patch for wv insn overlap, add t

[gcc r14-10051] Revert "RISC-V: Support highest overlap for wv instructions"

https://gcc.gnu.org/g:f5447eae72f11d9bfbb403183fd282918c0445c6 commit r14-10051-gf5447eae72f11d9bfbb403183fd282918c0445c6 Author: Pan Li Date: Sat Apr 20 09:42:57 2024 +0800 Revert "RISC-V: Support highest overlap for wv instructions" This reverts commit 7e854b58084c131fceca9e8fa9

[gcc r14-10052] RISC-V: Add xfail test case for wv insn highest overlap

https://gcc.gnu.org/g:1690e47e101c1e273b1ee052de21d5214257c13a commit r14-10052-g1690e47e101c1e273b1ee052de21d5214257c13a Author: Pan Li Date: Sat Apr 20 13:05:52 2024 +0800 RISC-V: Add xfail test case for wv insn highest overlap We reverted below patch for wv insn overlap, add th

[gcc r14-10054] Revert "RISC-V: Fix overlap group incorrect overlap on v0"

https://gcc.gnu.org/g:3afcb04bd7d444b4c6547ad98668c2a6a7f37a21 commit r14-10054-g3afcb04bd7d444b4c6547ad98668c2a6a7f37a21 Author: Pan Li Date: Sat Apr 20 22:37:56 2024 +0800 Revert "RISC-V: Fix overlap group incorrect overlap on v0" This reverts commit 018ba3ac952bed4ae01344c06036

[gcc r14-10056] RISC-V: Add xfail test case for incorrect overlap on v0

https://gcc.gnu.org/g:d37b34fe82e6e19e80ec9c46400f63fa90ba5255 commit r14-10056-gd37b34fe82e6e19e80ec9c46400f63fa90ba5255 Author: Pan Li Date: Sat Apr 20 22:43:13 2024 +0800 RISC-V: Add xfail test case for incorrect overlap on v0 We reverted below patch for register group overlap,

[gcc r14-10057] Revert "RISC-V: Support highpart register overlap for widen vx/vf instructions"

https://gcc.gnu.org/g:ef2392236ec629351496d7f299d6a0956080e4d9 commit r14-10057-gef2392236ec629351496d7f299d6a0956080e4d9 Author: Pan Li Date: Sun Apr 21 09:37:00 2024 +0800 Revert "RISC-V: Support highpart register overlap for widen vx/vf instructions" This reverts commit a23415

[gcc r14-10061] RISC-V: Add xfail test case for highpart register overlap of vx/vf widen

https://gcc.gnu.org/g:338640fbee2977485efb6ff0f1d3c7c8220074ad commit r14-10061-g338640fbee2977485efb6ff0f1d3c7c8220074ad Author: Pan Li Date: Sun Apr 21 12:34:19 2024 +0800 RISC-V: Add xfail test case for highpart register overlap of vx/vf widen We reverted below patch for regist

[gcc r14-10062] Revert "RISC-V: Support widening register overlap for vf4/vf8"

https://gcc.gnu.org/g:ec78916bb37bec0cd3ede5c6263387345ce16f94 commit r14-10062-gec78916bb37bec0cd3ede5c6263387345ce16f94 Author: Pan Li Date: Mon Apr 22 09:26:04 2024 +0800 Revert "RISC-V: Support widening register overlap for vf4/vf8" This reverts commit 303195e2a6b6f0e8f42e0578

[gcc r14-10063] RISC-V: Add xfail test case for widening register overlap of vf4/vf8

https://gcc.gnu.org/g:c4fdbdac1226787b4d33046f0be189a24dac468e commit r14-10063-gc4fdbdac1226787b4d33046f0be189a24dac468e Author: Pan Li Date: Mon Apr 22 10:11:25 2024 +0800 RISC-V: Add xfail test case for widening register overlap of vf4/vf8 We reverted below patch for register g

[gcc r14-10064] Revert "RISC-V: Support highest-number regno overlap for widen ternary"

https://gcc.gnu.org/g:cc46b6d4f3b4edc832a319ebf5053131dada3c8c commit r14-10064-gcc46b6d4f3b4edc832a319ebf5053131dada3c8c Author: Pan Li Date: Mon Apr 22 14:10:02 2024 +0800 Revert "RISC-V: Support highest-number regno overlap for widen ternary" This reverts commit 27fde325d64447a

[gcc r14-10065] RISC-V: Add xfail test case for highest-number regno ternary overlap

https://gcc.gnu.org/g:c7506847c020ad34eff248ab715eae238b9d1ed3 commit r14-10065-gc7506847c020ad34eff248ab715eae238b9d1ed3 Author: Pan Li Date: Mon Apr 22 14:32:25 2024 +0800 RISC-V: Add xfail test case for highest-number regno ternary overlap We reverted below patch for register g

[gcc r14-10067] Revert "RISC-V: Support highpart overlap for indexed load with SRC EEW < DEST EEW"

https://gcc.gnu.org/g:9257c7a72059aba0df1684a0722c4d1538cbb6d4 commit r14-10067-g9257c7a72059aba0df1684a0722c4d1538cbb6d4 Author: Pan Li Date: Mon Apr 22 15:39:45 2024 +0800 Revert "RISC-V: Support highpart overlap for indexed load with SRC EEW < DEST EEW" This reverts commit 441

[gcc r14-10068] RISC-V: Add xfail test case for indexed load overlap with SRC EEW < DEST EEW

https://gcc.gnu.org/g:a367b99f916cb7d2d673180ace640096fd118950 commit r14-10068-ga367b99f916cb7d2d673180ace640096fd118950 Author: Pan Li Date: Mon Apr 22 15:36:59 2024 +0800 RISC-V: Add xfail test case for indexed load overlap with SRC EEW < DEST EEW Update in v2: * Add change

[gcc r14-10069] Revert "RISC-V: Support highpart overlap for floating-point widen instructions"

https://gcc.gnu.org/g:4df96b4ec788f2d588febf3555685f2700b932b3 commit r14-10069-g4df96b4ec788f2d588febf3555685f2700b932b3 Author: Pan Li Date: Mon Apr 22 16:25:57 2024 +0800 Revert "RISC-V: Support highpart overlap for floating-point widen instructions" This reverts commit 8614cb

[gcc r14-10070] RISC-V: Add xfail test case for highpart overlap floating-point widen insn

https://gcc.gnu.org/g:b991193eb8a79ec7562f3de3df866df9f041015a commit r14-10070-gb991193eb8a79ec7562f3de3df866df9f041015a Author: Pan Li Date: Mon Apr 22 16:07:36 2024 +0800 RISC-V: Add xfail test case for highpart overlap floating-point widen insn We reverted below patch for regi

[gcc r14-10073] Revert "RISC-V: Robostify the W43, W86, W87 constraint enabled attribute"

https://gcc.gnu.org/g:b78c88438cf3672987736edc013ffc0b20e879f7 commit r14-10073-gb78c88438cf3672987736edc013ffc0b20e879f7 Author: Pan Li Date: Mon Apr 22 20:44:38 2024 +0800 Revert "RISC-V: Robostify the W43, W86, W87 constraint enabled attribute" This reverts commit d3544cea63d0a

[gcc r14-10074] Revert "RISC-V: Rename vconstraint into group_overlap"

https://gcc.gnu.org/g:cacc55a4c0be8d0bc7417b6a28924eadbbe428e3 commit r14-10074-gcacc55a4c0be8d0bc7417b6a28924eadbbe428e3 Author: Pan Li Date: Mon Apr 22 20:45:40 2024 +0800 Revert "RISC-V: Rename vconstraint into group_overlap" This reverts commit e65aaf8efe1900f7bbf76235a078000b

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