[gcc r13-8701] RISC-V: Fix vsetvli local eliminate [PR114747]

https://gcc.gnu.org/g:c4c0b0be87b4e08dab0e5e62c6f38a610a7423e7 commit r13-8701-gc4c0b0be87b4e08dab0e5e62c6f38a610a7423e7 Author: Kito Cheng Date: Mon May 6 23:45:22 2024 +0800 RISC-V: Fix vsetvli local eliminate [PR114747] vsetvli local eliminate is only consider the current deman

[gcc r15-356] RISC-V: Fix typos in code or comment [NFC]

https://gcc.gnu.org/g:d83070aebdb810e38f12d008e7a10acf1063f456 commit r15-356-gd83070aebdb810e38f12d008e7a10acf1063f456 Author: Kito Cheng Date: Tue May 7 10:18:58 2024 +0800 RISC-V: Fix typos in code or comment [NFC] Just found some typo when fixing bugs and then use aspell to fi

[gcc r15-3242] RISC-V: Add missing mode_idx for vrol and vror

https://gcc.gnu.org/g:3cde331e9590944819621bcde41ddbffd9bbf0ba commit r15-3242-g3cde331e9590944819621bcde41ddbffd9bbf0ba Author: Kito Cheng Date: Tue Aug 27 21:27:02 2024 +0800 RISC-V: Add missing mode_idx for vrol and vror We add pattern for vector rotate, but seems like we forgo

[gcc r15-1992] RISC-V: Add SiFive extensions, xsfvcp and xsfcease

https://gcc.gnu.org/g:3ea47ea1fcab95fd1b80acc724fdbb27fc436985 commit r15-1992-g3ea47ea1fcab95fd1b80acc724fdbb27fc436985 Author: Kito Cheng Date: Tue Jul 9 15:50:57 2024 +0800 RISC-V: Add SiFive extensions, xsfvcp and xsfcease We have already upstreamed these extensions into binut

[gcc r14-10463] [RISC-V] add implied extension repeatly until stable

https://gcc.gnu.org/g:b218c425328cd54994f717aaaca757b852df6aa9 commit r14-10463-gb218c425328cd54994f717aaaca757b852df6aa9 Author: Fei Gao Date: Fri Jul 5 09:56:30 2024 + [RISC-V] add implied extension repeatly until stable Call handle_implied_ext repeatly until there's no

[gcc r14-10464] RISC-V: Use tu policy for first-element vec_set [PR115725].

https://gcc.gnu.org/g:2d7dda84730e0e364b3b1776d387c9ceb85385ea commit r14-10464-g2d7dda84730e0e364b3b1776d387c9ceb85385ea Author: Robin Dapp Date: Mon Jul 1 13:37:17 2024 +0200 RISC-V: Use tu policy for first-element vec_set [PR115725]. This patch changes the tail policy for vmv.s

[gcc r14-10465] [PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_conditional_move()

https://gcc.gnu.org/g:c32995c4453fa4e04d27fda1597e31e6664f5eb4 commit r14-10465-gc32995c4453fa4e04d27fda1597e31e6664f5eb4 Author: Artemiy Volkov Date: Sun Jun 23 14:54:00 2024 -0600 [PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_conditional_move() Presently, the code

[gcc r14-10469] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar

https://gcc.gnu.org/g:68ef0c321a7df5899e1fbc3e20e75cce4233d6f7 commit r14-10469-g68ef0c321a7df5899e1fbc3e20e75cce4233d6f7 Author: Pan Li Date: Sat May 11 15:25:28 2024 +0800 RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar For the vfw vx format RVV intrinsic, the scalar

[gcc r14-10471] RISC-V: Add -X to link spec

https://gcc.gnu.org/g:3a7e796b48b9d8e37ec142abd9c20b1847535f7e commit r14-10471-g3a7e796b48b9d8e37ec142abd9c20b1847535f7e Author: Fangrui Song Date: Fri Apr 26 18:14:33 2024 -0700 RISC-V: Add -X to link spec --discard-locals (-X) instructs the linker to remove local .L* symbols,

[gcc r14-10466] RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch

https://gcc.gnu.org/g:87346ed74cc069d133918e28761fa8ef3c8ec874 commit r14-10466-g87346ed74cc069d133918e28761fa8ef3c8ec874 Author: Pan Li Date: Thu Jun 13 15:26:59 2024 +0800 RISC-V: Bugfix vec_extract vls mode iterator restriction mismatch We have vec_extract pattern which takes Z

[gcc r14-10468] RISC-V: Fix missing boolean_expression in zmmul extension

https://gcc.gnu.org/g:c38dbfc1ce7e827c4386c4b2595a5327a92b89d2 commit r14-10468-gc38dbfc1ce7e827c4386c4b2595a5327a92b89d2 Author: Liao Shihua Date: Fri May 24 13:03:57 2024 +0800 RISC-V: Fix missing boolean_expression in zmmul extension Update v1->v2 Add testcase for this

[gcc r14-10470] RISC-V: Fix parsing of Zic* extensions

https://gcc.gnu.org/g:92003fad999edfeb98edfd6e3e5bbe1254389127 commit r14-10470-g92003fad999edfeb98edfd6e3e5bbe1254389127 Author: Christoph Müllner Date: Mon Apr 29 00:46:06 2024 +0200 RISC-V: Fix parsing of Zic* extensions The extension parsing table entries for a range of Zic* e

[gcc r14-10472] RISC-V: Do not allow v0 as dest when merging [PR115068].

https://gcc.gnu.org/g:937713a5235bf9a9b8960635315882e8cee2706e commit r14-10472-g937713a5235bf9a9b8960635315882e8cee2706e Author: Robin Dapp Date: Mon May 13 13:49:57 2024 +0200 RISC-V: Do not allow v0 as dest when merging [PR115068]. This patch splits the vfw...wf pattern so we d

[gcc r14-10473] RISC-V: Split vwadd.wx and vwsub.wx and add helpers.

https://gcc.gnu.org/g:0abce4116a5ac58fdf1b8839b7db8ce04dd8a55a commit r14-10473-g0abce4116a5ac58fdf1b8839b7db8ce04dd8a55a Author: Robin Dapp Date: Thu May 16 12:43:43 2024 +0200 RISC-V: Split vwadd.wx and vwsub.wx and add helpers. vwadd.wx and vwsub.wx have the same problem vfwadd

[gcc r14-10467] RISC-V: Bugfix vec_extract v mode iterator restriction mismatch

https://gcc.gnu.org/g:4db38759dcae7426ea5ce4432afe97bdd2d87ac8 commit r14-10467-g4db38759dcae7426ea5ce4432afe97bdd2d87ac8 Author: Pan Li Date: Fri Jun 14 14:54:22 2024 +0800 RISC-V: Bugfix vec_extract v mode iterator restriction mismatch We have vec_extract pattern which takes ZVF

[gcc r14-9700] RISC-V: Add vxsat as a register

https://gcc.gnu.org/g:f6d7ff4796709c0639317bfd8fa58a2957a1e299 commit r14-9700-gf6d7ff4796709c0639317bfd8fa58a2957a1e299 Author: Palmer Dabbelt Date: Wed Mar 27 12:54:04 2024 -0700 RISC-V: Add vxsat as a register We aren't doing anything with vxsat right now, but I'd like to add i

[gcc r14-9835] RISC-V: Implement TLS Descriptors.

https://gcc.gnu.org/g:97069657c4e40b209c7b774e12faaca13812a86c commit r14-9835-g97069657c4e40b209c7b774e12faaca13812a86c Author: Tatsuyuki Ishi Date: Fri Mar 29 14:52:39 2024 +0900 RISC-V: Implement TLS Descriptors. This implements TLS Descriptors (TLSDESC) as specified in [1].

[gcc r13-8598] RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64

https://gcc.gnu.org/g:fb6ec6df54317ed3f6e6f878b6ea29dbef6bfe2d commit r13-8598-gfb6ec6df54317ed3f6e6f878b6ea29dbef6bfe2d Author: Kito Cheng Date: Wed Feb 28 16:01:52 2024 +0800 RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64 atomic_compare_and_swapsi will use lr.w

[gcc r12-10319] RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64

https://gcc.gnu.org/g:d37be5c0413783c5459c5664b6ffb9f47acfca4e commit r12-10319-gd37be5c0413783c5459c5664b6ffb9f47acfca4e Author: Kito Cheng Date: Wed Feb 28 16:01:52 2024 +0800 RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64 atomic_compare_and_swapsi will use lr.w

[gcc r11-11317] RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64

https://gcc.gnu.org/g:cb68221c59e8f98e107bb5842d319bee3a66b8dc commit r11-11317-gcb68221c59e8f98e107bb5842d319bee3a66b8dc Author: Kito Cheng Date: Wed Feb 28 16:01:52 2024 +0800 RISC-V: Fix __atomic_compare_exchange with 32 bit value on RV64 atomic_compare_and_swapsi will use lr.w

[gcc r13-8644] RISC-V: Fix recursive vsetvli checking [PR114172]

https://gcc.gnu.org/g:67e50daa5bd05f16d98c2dc651af2d6fa8335186 commit r13-8644-g67e50daa5bd05f16d98c2dc651af2d6fa8335186 Author: Kito Cheng Date: Wed Apr 24 16:54:44 2024 +0800 RISC-V: Fix recursive vsetvli checking [PR114172] extract_single_source will recursive checking the sour

[gcc r13-8659] RISC-V: Fix vsetvl pass ICE

https://gcc.gnu.org/g:129b64b0c2766d66d97be68a36f7d72685a9d29e commit r13-8659-g129b64b0c2766d66d97be68a36f7d72685a9d29e Author: Lehua Ding Date: Wed Aug 30 17:48:00 2023 +0800 RISC-V: Fix vsetvl pass ICE This patch fix pr111234 (a vsetvl pass ICE) when fuse a mask any vlmax v

[gcc r13-8663] [PATCH v3] RISC-V: Add split pattern to generate SFB instructions. [PR113095]

https://gcc.gnu.org/g:6335baaf31c0f1f0952d1a3f507b0e5655b1136f commit r13-8663-g6335baaf31c0f1f0952d1a3f507b0e5655b1136f Author: Monk Chiang Date: Wed Jan 24 10:19:28 2024 -0700 [PATCH v3] RISC-V: Add split pattern to generate SFB instructions. [PR113095] Since the match.pd trans

[gcc r14-10584] RISC-V: Make full-vec-move1.c test robust for optimization

https://gcc.gnu.org/g:8c98f0601f7f0d8051eda47370939198f4e01fc4 commit r14-10584-g8c98f0601f7f0d8051eda47370939198f4e01fc4 Author: Pan Li Date: Thu May 9 10:56:46 2024 +0800 RISC-V: Make full-vec-move1.c test robust for optimization During investigate the support of early break aut

[gcc r14-10585] [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests

https://gcc.gnu.org/g:d9bd361d893d3b62797f2962bca1b8d56521f3c3 commit r14-10585-gd9bd361d893d3b62797f2962bca1b8d56521f3c3 Author: Craig Blackmore Date: Sat Jun 22 22:07:06 2024 -0600 [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests These tests check the sched2 dump, so skip them f

[gcc r15-845] RISC-V: Fix missing boolean_expression in zmmul extension

https://gcc.gnu.org/g:06bb125521dec5648b725ddee4345b00decfdc77 commit r15-845-g06bb125521dec5648b725ddee4345b00decfdc77 Author: Liao Shihua Date: Fri May 24 13:03:57 2024 +0800 RISC-V: Fix missing boolean_expression in zmmul extension Update v1->v2 Add testcase for this pa

[gcc r15-4319] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

https://gcc.gnu.org/g:ca44eb7f6a33ff3b93e7685606b4fc286ce0fe80 commit r15-4319-gca44eb7f6a33ff3b93e7685606b4fc286ce0fe80 Author: Kito Cheng Date: Mon Oct 14 16:07:16 2024 +0800 RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits This

[gcc r15-4325] RISC-V: Add detailed comments on processing implied extensions. [NFC]

https://gcc.gnu.org/g:1c507a02f29c6ca735f40f4b16b341ce9d5aa1b1 commit r15-4325-g1c507a02f29c6ca735f40f4b16b341ce9d5aa1b1 Author: Yangyu Chen Date: Mon Oct 14 18:31:06 2024 +0800 RISC-V: Add detailed comments on processing implied extensions. [NFC] In some cases, we don't need to h

[gcc r15-5199] RISC-V: Implement TARGET_GENERATE_VERSION_DISPATCHER_BODY and TARGET_GET_FUNCTION_VERSIONS_DISPATCHE

https://gcc.gnu.org/g:917d03e4f366f7738684bed2eae02482b535b7fc commit r15-5199-g917d03e4f366f7738684bed2eae02482b535b7fc Author: Yangyu Chen Date: Tue Nov 5 11:23:07 2024 +0800 RISC-V: Implement TARGET_GENERATE_VERSION_DISPATCHER_BODY and TARGET_GET_FUNCTION_VERSIONS_DISPATCHER T

[gcc r15-5193] Introduce TARGET_CLONES_ATTR_SEPARATOR for RISC-V

https://gcc.gnu.org/g:9bf0dbe67244fffc5cb939e51ead2876557c8c37 commit r15-5193-g9bf0dbe67244fffc5cb939e51ead2876557c8c37 Author: Yangyu Chen Date: Tue Nov 5 11:21:22 2024 +0800 Introduce TARGET_CLONES_ATTR_SEPARATOR for RISC-V Some architectures may use ',' in the attribute string

[gcc r15-5195] RISC-V: Implement riscv_minimal_hwprobe_feature_bits

https://gcc.gnu.org/g:1f99a39da290291121d08701b218f23781a8 commit r15-5195-g1f99a39da290291121d08701b218f23781a8 Author: Yangyu Chen Date: Tue Nov 5 11:22:16 2024 +0800 RISC-V: Implement riscv_minimal_hwprobe_feature_bits This patch implements the riscv_minimal_hwprobe_fea

[gcc r15-5194] RISC-V: Implement Priority syntax parser for Function Multi-Versioning

https://gcc.gnu.org/g:6b572d4eecc99c4a014ce1eab5e79976e30f4d9f commit r15-5194-g6b572d4eecc99c4a014ce1eab5e79976e30f4d9f Author: Yangyu Chen Date: Tue Nov 5 11:22:00 2024 +0800 RISC-V: Implement Priority syntax parser for Function Multi-Versioning This patch adds the priority synt

[gcc r15-5196] RISC-V: Implement TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P

https://gcc.gnu.org/g:bd975bd1ce5fdbe99901df9145ba40d7145fd066 commit r15-5196-gbd975bd1ce5fdbe99901df9145ba40d7145fd066 Author: Yangyu Chen Date: Tue Nov 5 11:22:29 2024 +0800 RISC-V: Implement TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P This patch implements the TARGET_OPTION_VALID_

[gcc r15-5198] RISC-V: Implement TARGET_MANGLE_DECL_ASSEMBLER_NAME

https://gcc.gnu.org/g:0c77c4b082bf110fd2fc9c800268ac58fa579d06 commit r15-5198-g0c77c4b082bf110fd2fc9c800268ac58fa579d06 Author: Yangyu Chen Date: Tue Nov 5 11:22:56 2024 +0800 RISC-V: Implement TARGET_MANGLE_DECL_ASSEMBLER_NAME This patch implements the TARGET_MANGLE_DECL_ASSEMBL

[gcc r15-5200] RISC-V: Add Multi-Versioning Test Cases

https://gcc.gnu.org/g:f42f8dcf495e0a17df95a71c6a91093532cb9f3b commit r15-5200-gf42f8dcf495e0a17df95a71c6a91093532cb9f3b Author: Yangyu Chen Date: Tue Nov 5 11:23:16 2024 +0800 RISC-V: Add Multi-Versioning Test Cases This patch adds test cases for the Function Multi-Versioning (FM

[gcc r15-5197] RISC-V: Implement TARGET_COMPARE_VERSION_PRIORITY and TARGET_OPTION_FUNCTION_VERSIONS

https://gcc.gnu.org/g:78753c75cf154e7432624e24c68aae3b81ed49f0 commit r15-5197-g78753c75cf154e7432624e24c68aae3b81ed49f0 Author: Yangyu Chen Date: Tue Nov 5 11:22:45 2024 +0800 RISC-V: Implement TARGET_COMPARE_VERSION_PRIORITY and TARGET_OPTION_FUNCTION_VERSIONS This patch implem

[gcc r15-4798] RISC-V: Split riscv_process_target_attr with const char *args argument

https://gcc.gnu.org/g:a57c16e50d478cc413e3e530db21de693e4eb2ae commit r15-4798-ga57c16e50d478cc413e3e530db21de693e4eb2ae Author: Yangyu Chen Date: Thu Oct 24 15:10:57 2024 +0800 RISC-V: Split riscv_process_target_attr with const char *args argument This patch splits static bool ri

[gcc r15-4800] RISC-V: Do not inline when callee is versioned but caller is not

https://gcc.gnu.org/g:eb828a1e380e7bb5a708c899081541ee9130ff87 commit r15-4800-geb828a1e380e7bb5a708c899081541ee9130ff87 Author: Yangyu Chen Date: Thu Oct 24 15:12:45 2024 +0800 RISC-V: Do not inline when callee is versioned but caller is not When the callee is versioned but the c

[gcc r15-4795] RISC-V: allow -fno-plt to disable PLT

https://gcc.gnu.org/g:1f7b1c555c66cf55f9032ea14135f29d27d34811 commit r15-4795-g1f7b1c555c66cf55f9032ea14135f29d27d34811 Author: Yangyu Chen Date: Thu Oct 31 16:31:24 2024 +0800 RISC-V: allow -fno-plt to disable PLT Currently, the RISC-V target uses the target specific mplt option

[gcc r15-5171] RISC-V: Add norelax function attribute

https://gcc.gnu.org/g:4bee5252c1dedad044300ff89731ac26e27c9b21 commit r15-5171-g4bee5252c1dedad044300ff89731ac26e27c9b21 Author: yulong Date: Fri Nov 8 00:19:04 2024 +0800 RISC-V: Add norelax function attribute This patch adds norelax function attribute that be discussed in riscv

[gcc r15-5166] libsanitizer: Improve FrameIsInternal

https://gcc.gnu.org/g:4d2cd304714fddc8a995fc0311090fce7e70c122 commit r15-5166-g4d2cd304714fddc8a995fc0311090fce7e70c122 Author: Kito Cheng Date: Wed Nov 6 17:35:46 2024 +0800 libsanitizer: Improve FrameIsInternal `FrameIsInternal` is a function that improves report quality by fil

[gcc r15-5165] libsanitizer: Apply local patches

https://gcc.gnu.org/g:b53f7de3e6205f76a794e159a282193e2afaad16 commit r15-5165-gb53f7de3e6205f76a794e159a282193e2afaad16 Author: Kito Cheng Date: Wed Nov 15 12:46:56 2023 +0100 libsanitizer: Apply local patches This patch just reapplies local patches (will be noted in LOCAL_PATCHE

[gcc r15-5167] libsanitizer: update test

https://gcc.gnu.org/g:1b35b929354c41f3e2682aa7a30013e1bfe31bd4 commit r15-5167-g1b35b929354c41f3e2682aa7a30013e1bfe31bd4 Author: Kito Cheng Date: Wed Nov 6 11:47:03 2024 +0800 libsanitizer: update test gcc/testsuite/ChangeLog: * c-c++-common/ubsan/builtin-1.c: Upd

[gcc r15-5169] libsanitizer: Update LOCAL_PATCHES

https://gcc.gnu.org/g:0256c8b4687080e17e32f525d362814f238c8d32 commit r15-5169-g0256c8b4687080e17e32f525d362814f238c8d32 Author: Kito Cheng Date: Fri Nov 1 21:23:43 2024 +0800 libsanitizer: Update LOCAL_PATCHES Diff: --- libsanitizer/LOCAL_PATCHES | 5 ++--- 1 file changed, 2 insertions(

[gcc r15-3918] RISC-V/libgcc: Save/Restore routines for E goes with ABI.

https://gcc.gnu.org/g:bb01c9d6d280d7ffbaa8f09c36ae57908a4f6883 commit r15-3918-gbb01c9d6d280d7ffbaa8f09c36ae57908a4f6883 Author: Jim Lin Date: Fri Sep 27 14:44:12 2024 +0800 RISC-V/libgcc: Save/Restore routines for E goes with ABI. That Save/Restore routines for E can be used for

[gcc r15-5793] RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions.

https://gcc.gnu.org/g:356bfe8ca123954e524a9d09dd8bba5ae8474a2d commit r15-5793-g356bfe8ca123954e524a9d09dd8bba5ae8474a2d Author: yulong Date: Thu Nov 28 10:36:04 2024 +0800 RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions. This commit adds intrinsics support f

[gcc r15-5794] RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/dod extensions.

https://gcc.gnu.org/g:fe29b03825c9971ef1726bf9c7288de3389511b3 commit r15-5794-gfe29b03825c9971ef1726bf9c7288de3389511b3 Author: yulong Date: Thu Nov 28 10:36:05 2024 +0800 RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/dod extensions. This commit adds testcases for Xsfv

[gcc r15-5483] RISC-V: Add the mini support for SiFive extensions.

https://gcc.gnu.org/g:139bd3198a738a1d49cd27f37bab16c1916f3164 commit r15-5483-g139bd3198a738a1d49cd27f37bab16c1916f3164 Author: yulong Date: Sun Nov 17 17:55:30 2024 +0800 RISC-V: Add the mini support for SiFive extensions. This patch add the mini support for xsfvqmaccqoq, xsfvqm

[gcc r15-5860] RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions.

https://gcc.gnu.org/g:1352d4dd09293faf170072269fcef3aa6694d6ae commit r15-5860-g1352d4dd09293faf170072269fcef3aa6694d6ae Author: yulong Date: Mon Dec 2 09:31:53 2024 +0800 RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions. This commit adds intrinsics support for

[gcc r15-5861] RISC-V: Add intrinsics testcases for SiFive Xsfvfnrclipxfqf extensions.

https://gcc.gnu.org/g:275197057677406d575bfdbffa259ba7225e671f commit r15-5861-g275197057677406d575bfdbffa259ba7225e671f Author: yulong Date: Mon Dec 2 09:31:54 2024 +0800 RISC-V: Add intrinsics testcases for SiFive Xsfvfnrclipxfqf extensions. This commit adds testcases for Xsfvfn

[gcc r15-5644] asan: Support dynamic shadow offset

https://gcc.gnu.org/g:63c68752768fd6d67c695e09c85e0e1ca59cd6d4 commit r15-5644-g63c68752768fd6d67c695e09c85e0e1ca59cd6d4 Author: Kito Cheng Date: Fri Nov 15 12:14:54 2024 +0800 asan: Support dynamic shadow offset AddressSanitizer has supported dynamic shadow offsets since 2016[1],

[gcc r15-5645] RISC-V: Use dynamic shadow offset

https://gcc.gnu.org/g:c84a8a274af3163a4042bcfd77dd1988bd1eb0ce commit r15-5645-gc84a8a274af3163a4042bcfd77dd1988bd1eb0ce Author: Kito Cheng Date: Fri Nov 15 12:14:55 2024 +0800 RISC-V: Use dynamic shadow offset Switch to dynamic offset so that we can support Sv39, Sv48, and Sv57 a

[gcc r15-5643] RISC-V: Minimal support for svvptc extension.

https://gcc.gnu.org/g:e4f4b2dc08b6720acab563db48fd4b0427d2b0c6 commit r15-5643-ge4f4b2dc08b6720acab563db48fd4b0427d2b0c6 Author: Dongyan Chen Date: Fri Nov 22 13:13:46 2024 +0800 RISC-V: Minimal support for svvptc extension. This patch support svvptc extension[1]. To enable GC

[gcc r15-5931] RISC-V: Add const to function_shape::get_name [NFC]

https://gcc.gnu.org/g:9bf4cad4e4e1ec92c320a619c9bad35535596ced commit r15-5931-g9bf4cad4e4e1ec92c320a619c9bad35535596ced Author: Kito Cheng Date: Tue Dec 3 00:44:09 2024 -0800 RISC-V: Add const to function_shape::get_name [NFC] function_shape::get_name is the funciton for building

[gcc r15-5967] RISC-V: Add --with-cmodel configure option

https://gcc.gnu.org/g:feea589d78fd5ebe1c02cf937e184d2c66cd99ed commit r15-5967-gfeea589d78fd5ebe1c02cf937e184d2c66cd99ed Author: Hau Hsu Date: Fri Aug 2 13:11:51 2024 +0800 RISC-V: Add --with-cmodel configure option Sometimes we want to use default cmodel other than medlow. Add a

[gcc r15-6564] RISC-V: Move fortran testcase to gfortran.target

https://gcc.gnu.org/g:a35b89a20ed6ef697867e9149474bcdc584cd969 commit r15-6564-ga35b89a20ed6ef697867e9149474bcdc584cd969 Author: Kito Cheng Date: Mon Dec 23 21:27:46 2024 +0800 RISC-V: Move fortran testcase to gfortran.target gcc/testsuite/ChangeLog: * gcc.target/

[gcc r15-6297] RISC-V: Rename constraint c0* to k0*

https://gcc.gnu.org/g:1a2e0fcb857d82a7cb8909cf27a5dc833fecfa9a commit r15-6297-g1a2e0fcb857d82a7cb8909cf27a5dc833fecfa9a Author: Kito Cheng Date: Mon Dec 9 15:05:37 2024 +0800 RISC-V: Rename constraint c0* to k0* Rename those constraint since we want define other constraint start

[gcc r15-6298] RISC-V: Add cr and cf constraint

https://gcc.gnu.org/g:46888571d242cf5623b7b0b74bb4490572f81cc9 commit r15-6298-g46888571d242cf5623b7b0b74bb4490572f81cc9 Author: Kito Cheng Date: Wed Nov 13 17:54:16 2024 +0800 RISC-V: Add cr and cf constraint gcc/ChangeLog: * config/riscv/constraints.md (cr): New

[gcc r15-6299] RISC-V: Rename internal operand modifier N to n

https://gcc.gnu.org/g:192790e994c9e15949e694e0a52010001b291611 commit r15-6299-g192790e994c9e15949e694e0a52010001b291611 Author: Kito Cheng Date: Thu Nov 14 16:41:52 2024 +0800 RISC-V: Rename internal operand modifier N to n Here is a purposal that using N for printing register en

[gcc r15-6301] RISC-V: Add new constraint R for register even-odd pairs

https://gcc.gnu.org/g:fcbb8456a58ba073d4d5b10fcb9057b6e9a100db commit r15-6301-gfcbb8456a58ba073d4d5b10fcb9057b6e9a100db Author: Kito Cheng Date: Mon Dec 9 14:55:20 2024 +0800 RISC-V: Add new constraint R for register even-odd pairs Although this constraint is not currently used f

[gcc r15-6300] RISC-V: Implment N modifier for printing the register number rather than the register name

https://gcc.gnu.org/g:2a22db391d1819f6068aa43e63632b350a0b4bec commit r15-6300-g2a22db391d1819f6068aa43e63632b350a0b4bec Author: Kito Cheng Date: Thu Nov 14 17:24:45 2024 +0800 RISC-V: Implment N modifier for printing the register number rather than the register name The modifier

[gcc r15-6006] Revert "RISC-V: Add const to function_shape::get_name [NFC]"

https://gcc.gnu.org/g:567b0405e38b0336a4416628424c97c67d0e92b3 commit r15-6006-g567b0405e38b0336a4416628424c97c67d0e92b3 Author: Kito Cheng Date: Sat Dec 7 08:23:58 2024 +0800 Revert "RISC-V: Add const to function_shape::get_name [NFC]" This reverts commit 9bf4cad4e4e1ec92c320a619

[gcc r15-7037] RISC-V: Add sifive_vector.h

https://gcc.gnu.org/g:43a6001ff58d1e0da791b5f7f4c51aa2ed1e4493 commit r15-7037-g43a6001ff58d1e0da791b5f7f4c51aa2ed1e4493 Author: Kito Cheng Date: Wed Jan 15 16:13:05 2025 +0800 RISC-V: Add sifive_vector.h sifive_vector.h is a vendor specfic header, it should include before usi

[gcc r15-6949] RISC-V: Update Xsfvqmacc and Xsfvfnrclip's testcases

https://gcc.gnu.org/g:8682fcbf3ced5a415d3ff9a27d6c1fa0392bb187 commit r15-6949-g8682fcbf3ced5a415d3ff9a27d6c1fa0392bb187 Author: Liao Shihua Date: Fri Dec 13 20:38:29 2024 +0800 RISC-V: Update Xsfvqmacc and Xsfvfnrclip's testcases Update Sifive Xsfvqmacc and Xsfvfnrclip extension'

[gcc r15-6948] RISC-V: Update Xsfvfnrclip implementation.

https://gcc.gnu.org/g:030aaea78c130a31d36d1dd56b0e8b90d973b522 commit r15-6948-g030aaea78c130a31d36d1dd56b0e8b90d973b522 Author: Jiawei Date: Fri Dec 13 20:38:28 2024 +0800 RISC-V: Update Xsfvfnrclip implementation. Update implementation of Xsfvfnrclip, using return type as iterat

[gcc r15-6906] RISC-V: Fix code gen for reduction with length 0 [PR118182]

https://gcc.gnu.org/g:40ad10f708b19d3e88948ac820fbfb9f3c3689ae commit r15-6906-g40ad10f708b19d3e88948ac820fbfb9f3c3689ae Author: Kito Cheng Date: Mon Dec 23 23:23:44 2024 +0800 RISC-V: Fix code gen for reduction with length 0 [PR118182] `.MASK_LEN_FOLD_LEFT_PLUS`(or `mask_len_fold

[gcc r15-7681] RISC-V: Fix .cfi_offset directive when push/pop in zcmp

https://gcc.gnu.org/g:4dcd3c7749734133f7f59509b1a118f3a13de4ee commit r15-7681-g4dcd3c7749734133f7f59509b1a118f3a13de4ee Author: Lino Hsing-Yu Peng Date: Thu Feb 20 17:09:22 2025 +0800 RISC-V: Fix .cfi_offset directive when push/pop in zcmp The incorrect cfi directive info breaks

[gcc r14-11575] RISC-V:Bugfix for vlmul_ext and vlmul_trunc with NULL return value[pr117286]

https://gcc.gnu.org/g:4bd63c709de82bfecde8cf99145974b349918d5d commit r14-11575-g4bd63c709de82bfecde8cf99145974b349918d5d Author: xuli Date: Mon Oct 28 04:41:09 2024 + RISC-V:Bugfix for vlmul_ext and vlmul_trunc with NULL return value[pr117286] This patch fixes following ICE:

[gcc r14-11561] [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx

https://gcc.gnu.org/g:d0663c143071331bd3bff7e396bc0e761dd98939 commit r14-11561-gd0663c143071331bd3bff7e396bc0e761dd98939 Author: Bohan Lei Date: Wed Sep 18 07:20:23 2024 -0600 [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx The RISC-V vector machine description re

[gcc r14-11564] [PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector

https://gcc.gnu.org/g:4f41d8fa5a73e2703d417b0e44bce48aa35bfd91 commit r14-11564-g4f41d8fa5a73e2703d417b0e44bce48aa35bfd91 Author: Jin Ma Date: Sat Sep 7 10:29:02 2024 -0600 [PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli zero,0,e32,m8" for XTheadVector Since t

[gcc r14-11547] [RISC-V][PR target/116308] Fix generation of initial RTL for atomics

https://gcc.gnu.org/g:f3ac41f84249d10a1685c73d67e5d071902fcc4c commit r14-11547-gf3ac41f84249d10a1685c73d67e5d071902fcc4c Author: Jeff Law Date: Sat Jan 18 13:44:33 2025 -0700 [RISC-V][PR target/116308] Fix generation of initial RTL for atomics While this wasn't originally marked

[gcc r14-11568] RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB'

https://gcc.gnu.org/g:28fe2b087baea05759aa7386fb8c3862aecf51ef commit r14-11568-g28fe2b087baea05759aa7386fb8c3862aecf51ef Author: Jin Ma Date: Thu Aug 8 07:49:51 2024 -0600 RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB' gcc/ChangeLog: * config/riscv/riscv.h

[gcc r14-11551] RISC-V: Fix vsetvl compatibility predicate [PR118154].

https://gcc.gnu.org/g:6f549f865d02f897f682dddf56f392a22c01df6c commit r14-11551-g6f549f865d02f897f682dddf56f392a22c01df6c Author: Robin Dapp Date: Thu Jan 9 20:45:10 2025 +0100 RISC-V: Fix vsetvl compatibility predicate [PR118154]. In PR118154 we emit strided stores but the first

[gcc r14-11548] [PR target/118357] RISC-V: Disable fusing vsetvl instructions by VSETVL_VTYPE_CHANGE_ONLY for XThead

https://gcc.gnu.org/g:e4586ae318436d63aa91c2d417f068987c77e442 commit r14-11548-ge4586ae318436d63aa91c2d417f068987c77e442 Author: Jin Ma Date: Sat Jan 18 07:43:17 2025 -0700 [PR target/118357] RISC-V: Disable fusing vsetvl instructions by VSETVL_VTYPE_CHANGE_ONLY for XTheadVector.

[gcc r14-11556] RISC-V: Add assert for insn operand out of range access [PR117878][NFC]

https://gcc.gnu.org/g:acb636a9c3ac18e7234e37c99bd6e9200b80b9bd commit r14-11556-gacb636a9c3ac18e7234e37c99bd6e9200b80b9bd Author: Pan Li Date: Wed Dec 4 13:53:52 2024 +0800 RISC-V: Add assert for insn operand out of range access [PR117878][NFC] According to the the initial analysi

[gcc r14-11580] RISC-V: Fix the behavior for multilib-generator with --cmodel=large on rv32

https://gcc.gnu.org/g:fb0653a0e54203eeb9ff399aee93ed904030b4bd commit r14-11580-gfb0653a0e54203eeb9ff399aee93ed904030b4bd Author: Kito Cheng Date: Thu Apr 10 16:58:49 2025 +0800 RISC-V: Fix the behavior for multilib-generator with --cmodel=large on rv32 Large code model is only su

[gcc r15-9353] RISC-V: Include local riscv_vector.h in testsuite

https://gcc.gnu.org/g:9e48698228dbf1bbebba3a52d7ae2f47fee89624 commit r15-9353-g9e48698228dbf1bbebba3a52d7ae2f47fee89624 Author: Kito Cheng Date: Wed Apr 9 21:58:23 2025 +0800 RISC-V: Include local riscv_vector.h in testsuite That could prevent us including stdint.h from glibc, an

[gcc r15-9354] RISC-V: Fix the behavior for multilib-generator with --cmodel=large on rv32

https://gcc.gnu.org/g:72dff34bcdd6f05b64bbf07739ab815e673b5946 commit r15-9354-g72dff34bcdd6f05b64bbf07739ab815e673b5946 Author: Kito Cheng Date: Thu Apr 10 16:58:49 2025 +0800 RISC-V: Fix the behavior for multilib-generator with --cmodel=large on rv32 Large code model is only sup

[gcc r14-11571] RISC-V: Reject 'd' extension with ILP32E ABI

https://gcc.gnu.org/g:eaf423763c780795ea7ae914d390ac07e149871e commit r14-11571-geaf423763c780795ea7ae914d390ac07e149871e Author: Patrick O'Neill Date: Tue Jul 30 14:28:23 2024 -0700 RISC-V: Reject 'd' extension with ILP32E ABI Also add a testcase for -mabi=lp64d where 'd' is requ

[gcc r14-11562] riscv: Fix duplicate assmbler label in @tlsdesc insn

https://gcc.gnu.org/g:5615fea2fce63d49d67691f102601868147c2bbc commit r14-11562-g5615fea2fce63d49d67691f102601868147c2bbc Author: Andreas Schwab Date: Thu Sep 12 13:55:09 2024 +0200 riscv: Fix duplicate assmbler label in @tlsdesc insn Use %= instead of maintaining a sequence numbe

[gcc r14-11572] RISC-V: Error early with V and no M extension.

https://gcc.gnu.org/g:b7d975945025d1e4e9237c90b46bf4f660289d22 commit r14-11572-gb7d975945025d1e4e9237c90b46bf4f660289d22 Author: Robin Dapp Date: Wed Jul 24 09:08:00 2024 +0200 RISC-V: Error early with V and no M extension. For calculating the value of a poly_int at runtime we us

[gcc r14-11570] RISC-V: Correct mode_idx attribute for viwalu wx variants [PR116149].

https://gcc.gnu.org/g:95ac2d8afb386ccd7277f4906e0aca88d53c835a commit r14-11570-g95ac2d8afb386ccd7277f4906e0aca88d53c835a Author: Robin Dapp Date: Wed Jul 31 16:54:03 2024 +0200 RISC-V: Correct mode_idx attribute for viwalu wx variants [PR116149]. In PR116149 we choose a wrong vec

[gcc r14-11563] RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass

https://gcc.gnu.org/g:94b774c5c1cd67608c31d593167996351e952cea commit r14-11563-g94b774c5c1cd67608c31d593167996351e952cea Author: garthlei Date: Wed Sep 11 17:09:37 2024 +0800 RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass This patch fixes a bug in the current vsetvl pas

[gcc r14-11567] RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305]

https://gcc.gnu.org/g:327c7c38123eec6264324acd98b4386363d05cb4 commit r14-11567-g327c7c38123eec6264324acd98b4386363d05cb4 Author: 曾治金 Date: Wed Aug 14 14:06:23 2024 +0800 RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305] This patch is to fix the bug (BugId:116305) in

[gcc r14-11550] RISC-V: Fix code gen for reduction with length 0 [PR118182]

https://gcc.gnu.org/g:1eb6bf312839d0ff6f0f1a246f9b0b715d1c4b7a commit r14-11550-g1eb6bf312839d0ff6f0f1a246f9b0b715d1c4b7a Author: Kito Cheng Date: Mon Dec 23 23:23:44 2024 +0800 RISC-V: Fix code gen for reduction with length 0 [PR118182] `.MASK_LEN_FOLD_LEFT_PLUS`(or `mask_len_fol

[gcc r14-11574] RISC-V: Bugfix for max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483]

https://gcc.gnu.org/g:6cd78e383a98553482811f10318ff3da9a101d38 commit r14-11574-g6cd78e383a98553482811f10318ff3da9a101d38 Author: xuli Date: Tue Nov 12 02:31:28 2024 + RISC-V: Bugfix for max_sew_overlap_and_next_ratio_valid_for_prev_sew_p[pr117483] This patch fixs https://gcc

[gcc r14-11565] RISC-V: Fix subreg of VLS modes larger than a vector [PR116086].

https://gcc.gnu.org/g:e19a21f8edda3de1e460094e54239928bd289a31 commit r14-11565-ge19a21f8edda3de1e460094e54239928bd289a31 Author: Robin Dapp Date: Tue Aug 27 10:25:34 2024 +0200 RISC-V: Fix subreg of VLS modes larger than a vector [PR116086]. When the source mode is potentially la

[gcc r14-11569] [RISC-V][PR target/116240] Ensure object is a comparison before extracting arguments

https://gcc.gnu.org/g:86b0f63adb0815b40705051484dcb7ac640d commit r14-11569-g86b0f63adb0815b40705051484dcb7ac640d Author: Jeff Law Date: Thu Aug 8 07:42:26 2024 -0600 [RISC-V][PR target/116240] Ensure object is a comparison before extracting arguments This was supposed to

[gcc r14-11549] RISC-V: Move fortran testcase to gfortran.target

https://gcc.gnu.org/g:af3ebb414e2b88973d570e8878bc6262c0a1b3a9 commit r14-11549-gaf3ebb414e2b88973d570e8878bc6262c0a1b3a9 Author: Kito Cheng Date: Mon Dec 23 21:27:46 2024 +0800 RISC-V: Move fortran testcase to gfortran.target gcc/testsuite/ChangeLog: * gcc.target

[gcc r14-11553] [PATCH] riscv: add mising masking in lrsc expander (PR118137)

https://gcc.gnu.org/g:46732eb89db2f5124f9433ef9460ff301ab7d737 commit r14-11553-g46732eb89db2f5124f9433ef9460ff301ab7d737 Author: Andreas Schwab Date: Tue Jan 7 12:23:37 2025 -0700 [PATCH] riscv: add mising masking in lrsc expander (PR118137) gcc: PR target/118137

[gcc r14-11573] [committed] [RISC-V] Fix false-positive uninitialized variable

https://gcc.gnu.org/g:cdb987e977e03ba78a8a0e094967a5121e01f2ce commit r14-11573-gcdb987e977e03ba78a8a0e094967a5121e01f2ce Author: Jeff Law Date: Sun Jun 9 09:17:55 2024 -0600 [committed] [RISC-V] Fix false-positive uninitialized variable Andreas noted we were getting an uninit war

[gcc r14-11576] RISC-V: Fix vid const vector expander for non-npatterns size steps

https://gcc.gnu.org/g:6a66212916e70a9f27adf458b79c309c926dcf42 commit r14-11576-g6a66212916e70a9f27adf458b79c309c926dcf42 Author: Patrick O'Neill Date: Wed Aug 21 23:48:24 2024 -0700 RISC-V: Fix vid const vector expander for non-npatterns size steps Prior to this patch the expande

[gcc r14-11552] RISC-V: Disallow negative step for interleaving [PR117682]

https://gcc.gnu.org/g:08e381e8af3ec9beaa887824c41d4551b54e5063 commit r14-11552-g08e381e8af3ec9beaa887824c41d4551b54e5063 Author: Robin Dapp Date: Mon Jan 13 17:09:35 2025 -0700 RISC-V: Disallow negative step for interleaving [PR117682] Hi, in PR117682 we build an interle

[gcc r14-11554] [RISC-V][PR target/106544] Avoid ICEs due to bogus asms

https://gcc.gnu.org/g:6547906bdbdb3feb0d3bd96e09ceffcbc489349f commit r14-11554-g6547906bdbdb3feb0d3bd96e09ceffcbc489349f Author: Jeff Law Date: Mon Dec 30 13:51:55 2024 -0700 [RISC-V][PR target/106544] Avoid ICEs due to bogus asms This is a fix for a bug Andrew P filed a while ba

[gcc r14-11559] [PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expression.

https://gcc.gnu.org/g:80ab25142565e83477af7c3e57f0a4dcf51b9659 commit r14-11559-g80ab25142565e83477af7c3e57f0a4dcf51b9659 Author: Xianmiao Qu Date: Wed Sep 18 07:35:12 2024 -0600 [PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expression. I think it is a t

[gcc r14-11560] [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32.

https://gcc.gnu.org/g:5b3558944a7a03071744585ee8c55f30d51b5653 commit r14-11560-g5b3558944a7a03071744585ee8c55f30d51b5653 Author: Xianmiao Qu Date: Wed Sep 18 07:28:44 2024 -0600 [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32. The Combine Pass may generate zero_extra

[gcc r14-11557] RISC-V: Ensure vtype for full-register moves [PR117544].

https://gcc.gnu.org/g:164aededa828c5db6195a10f9d0f6a500f2cbef9 commit r14-11557-g164aededa828c5db6195a10f9d0f6a500f2cbef9 Author: Robin Dapp Date: Thu Nov 21 14:49:53 2024 +0100 RISC-V: Ensure vtype for full-register moves [PR117544]. As discussed in PR117544 the VTYPE register is

[gcc r14-11558] [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on

https://gcc.gnu.org/g:37d13153635b78013a8d27d2be9da99d0f2a88a7 commit r14-11558-g37d13153635b78013a8d27d2be9da99d0f2a88a7 Author: Jin Ma Date: Wed Sep 18 08:56:23 2024 -0600 [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32.

[gcc r14-11555] RISC-V: Fix compress shuffle pattern [PR117383].

https://gcc.gnu.org/g:ca6adeda373fc97ff57a79bc1a078f90776330cd commit r14-11555-gca6adeda373fc97ff57a79bc1a078f90776330cd Author: Robin Dapp Date: Wed Dec 11 20:48:30 2024 +0100 RISC-V: Fix compress shuffle pattern [PR117383]. This patch makes vcompress use the tail-undisturbed po

[gcc r14-11566] RISC-V: Add missing mode_idx for vrol and vror

https://gcc.gnu.org/g:d2f5d28415fe28881b4b8cadf6df85cf94ded233 commit r14-11566-gd2f5d28415fe28881b4b8cadf6df85cf94ded233 Author: Kito Cheng Date: Tue Aug 27 21:27:02 2024 +0800 RISC-V: Add missing mode_idx for vrol and vror We add pattern for vector rotate, but seems like we forg

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