[gcc r15-834] [PATCH] libcpp: Correct typo 'r' -> '\r'

https://gcc.gnu.org/g:87463737b9942249ceb0d0d60050adf452f44f7c commit r15-834-g87463737b9942249ceb0d0d60050adf452f44f7c Author: Peter Damianov Date: Sun May 26 08:06:14 2024 -0600 [PATCH] libcpp: Correct typo 'r' -> '\r' libcpp/ChangeLog: * lex.cc (do_peek_prev): Corre

[gcc r15-835] [to-be-committed][RISC-V] Generate nearby constant, then adjust to our final desired constant

https://gcc.gnu.org/g:95660223c434000a42957cf6cabed0236bb4bae8 commit r15-835-g95660223c434000a42957cf6cabed0236bb4bae8 Author: Jeff Law Date: Sun May 26 10:54:18 2024 -0600 [to-be-committed][RISC-V] Generate nearby constant, then adjust to our final desired constant Next step in

[gcc r15-836] doc: Quote singular '=' signs

https://gcc.gnu.org/g:53d919873c56cec0e7354907e8da3d8dba158a69 commit r15-836-g53d919873c56cec0e7354907e8da3d8dba158a69 Author: Gerald Pfeifer Date: Sun May 26 23:48:36 2024 +0200 doc: Quote singular '=' signs gcc: * doc/extend.texi (Attribute Syntax): Use @samp{=} ins

[gcc r15-837] go: Move web references from golang.org to go.dev.

https://gcc.gnu.org/g:a06df6644a4403bb63b0ab68532ea67b938d8baf commit r15-837-ga06df6644a4403bb63b0ab68532ea67b938d8baf Author: Gerald Pfeifer Date: Mon May 27 00:23:38 2024 +0200 go: Move web references from golang.org to go.dev. gcc/go: * gccgo.texi (Top): Move a web

[gcc r15-838] [to-be-committed] [RISC-V] Try inverting for constant synthesis

https://gcc.gnu.org/g:3a915d6ad5fc3e0fadd14e54515b48b1d655c5a4 commit r15-838-g3a915d6ad5fc3e0fadd14e54515b48b1d655c5a4 Author: Jeff Law Date: Sun May 26 17:54:51 2024 -0600 [to-be-committed] [RISC-V] Try inverting for constant synthesis So there's another class of constants we're

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [v2] More logical op simplifications in simplify-rtx.cc

https://gcc.gnu.org/g:fee06b936580108cee30467ad5ae98be5c8d1a4f commit fee06b936580108cee30467ad5ae98be5c8d1a4f Author: Jeff Law Date: Sat May 25 12:39:05 2024 -0600 [committed] [v2] More logical op simplifications in simplify-rtx.cc This is a revamp of what started as a target spe

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Try inverting for constant synthesis

https://gcc.gnu.org/g:19868f0990e87159025646bf99cf461c07e12563 commit 19868f0990e87159025646bf99cf461c07e12563 Author: Jeff Law Date: Sun May 26 17:54:51 2024 -0600 [to-be-committed] [RISC-V] Try inverting for constant synthesis So there's another class of constants we're failing

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V] Generate nearby constant, then adjust to our final desired constant

https://gcc.gnu.org/g:f69c19f64e96e3cb04767d2f41191df114d4b309 commit f69c19f64e96e3cb04767d2f41191df114d4b309 Author: Jeff Law Date: Sun May 26 10:54:18 2024 -0600 [to-be-committed][RISC-V] Generate nearby constant, then adjust to our final desired constant Next step in constant

[gcc/riscv/heads/gcc-14-with-riscv-opts] (141 commits) [to-be-committed] [RISC-V] Try inverting for constant synth

The branch 'riscv/heads/gcc-14-with-riscv-opts' was updated to point to: 7f716ba0f6c... [to-be-committed] [RISC-V] Try inverting for constant synth It previously pointed to: 19868f0990e... [to-be-committed] [RISC-V] Try inverting for constant synth Diff: !!! WARNING: THE FOLLOWING COMMITS AR

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add -X to link spec

https://gcc.gnu.org/g:0761c4e460775424643c45a09558b8b85ad6b0a4 commit 0761c4e460775424643c45a09558b8b85ad6b0a4 Author: Fangrui Song Date: Fri Apr 26 18:14:33 2024 -0700 RISC-V: Add -X to link spec --discard-locals (-X) instructs the linker to remove local .L* symbols, which oc

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix parsing of Zic* extensions

https://gcc.gnu.org/g:fe3b44c779a51ebf0d5c017d4c676b6cc41932ae commit fe3b44c779a51ebf0d5c017d4c676b6cc41932ae Author: Christoph Müllner Date: Mon Apr 29 00:46:06 2024 +0200 RISC-V: Fix parsing of Zic* extensions The extension parsing table entries for a range of Zic* extensions

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] This is almost exclusively Jivan's work. His original post:

https://gcc.gnu.org/g:1f741dd358b094b57ca820cadf046b3fe6fbe736 commit 1f741dd358b094b57ca820cadf046b3fe6fbe736 Author: Jivan Hakobyan Date: Tue Apr 30 09:44:02 2024 -0600 This is almost exclusively Jivan's work. His original post: > https://www.mail-archive.com/gcc-patches@gcc.gn

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refine the condition for add additional vars in RVV cost model

https://gcc.gnu.org/g:0285854739ff710005770f8e956197f34fe9b967 commit 0285854739ff710005770f8e956197f34fe9b967 Author: demin.han Date: Tue Mar 26 16:52:12 2024 +0800 RISC-V: Refine the condition for add additional vars in RVV cost model The adjacent_dr_p is sufficient and unnecess

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Fix detection of store pair fusion cases

https://gcc.gnu.org/g:241fbf90eb65e11a028aa72e0b48529fecb3f3c9 commit 241fbf90eb65e11a028aa72e0b48529fecb3f3c9 Author: Jeff Law Date: Wed May 1 11:28:41 2024 -0600 [committed] [RISC-V] Fix detection of store pair fusion cases We've got the ability to count the number of store pair

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Don't run new rounding tests on newlib risc-v targets

https://gcc.gnu.org/g:d3c8cb96e4e2a04dc3765467fc609a12ca6e6e25 commit d3c8cb96e4e2a04dc3765467fc609a12ca6e6e25 Author: Jeff Law Date: Thu May 2 08:42:32 2024 -0600 [committed] [RISC-V] Don't run new rounding tests on newlib risc-v targets The new round_32.c and round_64.c tests de

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Trivial pattern cleanup

https://gcc.gnu.org/g:1659526b1e18375f3a604245a0769dfa4b5548ab commit 1659526b1e18375f3a604245a0769dfa4b5548ab Author: Jeff Law Date: Wed May 1 12:43:37 2024 -0600 [committed] [RISC-V] Trivial pattern cleanup As I was reviewing and cleaning up some internal work, I noticed a part

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RFA][RISC-V] Improve constant synthesis for constants with 2 bits set

https://gcc.gnu.org/g:43130081438c423616549bf3a6b0649b84baddfc commit 43130081438c423616549bf3a6b0649b84baddfc Author: Jeff Law Date: Thu May 2 14:06:22 2024 -0600 [RFA][RISC-V] Improve constant synthesis for constants with 2 bits set In doing some preparation work for using zbkb'

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: miscll comment fixes [NFC]

https://gcc.gnu.org/g:4751ac4274c4a8b21f35325aae6794c1626f16bc commit 4751ac4274c4a8b21f35325aae6794c1626f16bc Author: Vineet Gupta Date: Tue Mar 1 03:45:19 2022 -0800 RISC-V: miscll comment fixes [NFC] gcc/ChangeLog: * config/riscv/riscv.cc: Comment updates.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][RISC-V] Fix nearbyint failure on rv32 and formatting nits

https://gcc.gnu.org/g:733526b306158f6e68c8ef9ad7bf6adb04f4e894 commit 733526b306158f6e68c8ef9ad7bf6adb04f4e894 Author: Jeff Law Date: Thu May 2 17:13:12 2024 -0600 [committed][RISC-V] Fix nearbyint failure on rv32 and formatting nits The CI system tripped an execution failure for

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] So another constant synthesis improvement.

https://gcc.gnu.org/g:6c0a8dff816db539a523f9feab9d19cb2bf13f94 commit 6c0a8dff816db539a523f9feab9d19cb2bf13f94 Author: Jeff Law Date: Mon May 6 15:27:43 2024 -0600 So another constant synthesis improvement. In this patch we're looking at cases where we'd like to be able to use

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Document -mcmodel=large

https://gcc.gnu.org/g:fdaac11cd9b4680ef895754de9ef09493eb2182f commit fdaac11cd9b4680ef895754de9ef09493eb2182f Author: Palmer Dabbelt Date: Mon May 6 15:34:26 2024 -0600 RISC-V: Document -mcmodel=large This slipped through the cracks. Probably also NEWS-worthy. gcc/Cha

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcase for PR114749.

https://gcc.gnu.org/g:03d11c2142d2b375161fa50d367c2bb9bfe742bd commit 03d11c2142d2b375161fa50d367c2bb9bfe742bd Author: Robin Dapp Date: Mon May 6 15:51:37 2024 -0600 RISC-V: Add testcase for PR114749. this adds a test case for PR114749. Going to commit as obvious unless somebo

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Add support for _Bfloat16

https://gcc.gnu.org/g:1c61e73ff62e1fc84de2bda1c35215b3d058699c commit 1c61e73ff62e1fc84de2bda1c35215b3d058699c Author: Xiao Zeng Date: Mon May 6 15:39:12 2024 -0600 [RISC-V] Add support for _Bfloat16 1 At point , BF16 has already been

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= option

https://gcc.gnu.org/g:a38ee93f25444aea92a24e5cd9ebb948b92dcdc3 commit a38ee93f25444aea92a24e5cd9ebb948b92dcdc3 Author: Xiao Zeng Date: Mon May 6 15:57:37 2024 -0600 [PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= option This patch would like to add new sub extension (aka

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] [PATCH v2] Enable inlining str* by default

https://gcc.gnu.org/g:411f7cc1778500ed2c5cfa26e3217b4b61a5 commit 411f7cc1778500ed2c5cfa26e3217b4b61a5 Author: Jeff Law Date: Tue May 7 11:43:09 2024 -0600 [RISC-V] [PATCH v2] Enable inlining str* by default So with Chrstoph's patches from late 2022 we've had the ability t

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Allow uarchs to set TARGET_OVERLAP_OP_BY_PIECES_P

https://gcc.gnu.org/g:aeadd95aeb5f6e6e0e4f1a98c93a11754f536472 commit aeadd95aeb5f6e6e0e4f1a98c93a11754f536472 Author: Christoph Müllner Date: Tue May 7 15:16:21 2024 -0600 [committed] [RISC-V] Allow uarchs to set TARGET_OVERLAP_OP_BY_PIECES_P This is almost exclusively work from

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][RISC-V] Turn on overlap_op_by_pieces for generic-ooo tuning

https://gcc.gnu.org/g:30096ff9c4e5b8f31a0f65841db44f3b4fd71fda commit 30096ff9c4e5b8f31a0f65841db44f3b4fd71fda Author: Jeff Law Date: Tue May 7 15:34:16 2024 -0600 [committed][RISC-V] Turn on overlap_op_by_pieces for generic-ooo tuning Per quick email exchange with Palmer. Given

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add test for sraiw-31 special case

https://gcc.gnu.org/g:929ef4d2fa08eabbf645c86ffe12ebbfb8219190 commit 929ef4d2fa08eabbf645c86ffe12ebbfb8219190 Author: Christoph Müllner Date: Tue May 7 22:59:44 2024 +0200 RISC-V: Add test for sraiw-31 special case We already optimize a sign-extension of a right-shift by 31 in

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2

https://gcc.gnu.org/g:31ab40016ae2864e4aa7741a1e3b6d867a6779cc commit 31ab40016ae2864e4aa7741a1e3b6d867a6779cc Author: Christoph Müllner Date: Tue May 7 23:26:02 2024 +0200 RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2 The pattern lshrsi3_zero_extend_2 extracts the MSB bi

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add zero_extract support for rv64gc

https://gcc.gnu.org/g:76f36d93c3107544c6dbdffa616599ce3fdb44eb commit 76f36d93c3107544c6dbdffa616599ce3fdb44eb Author: Christoph Müllner Date: Mon May 6 12:33:32 2024 +0200 RISC-V: Add zero_extract support for rv64gc The combiner attempts to optimize a zero-extension of a logical

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cover sign-extensions in lshr3_zero_extend_4

https://gcc.gnu.org/g:d3660f7816fbc403a97492545a687b0651fe3429 commit d3660f7816fbc403a97492545a687b0651fe3429 Author: Christoph Müllner Date: Tue May 7 22:23:26 2024 +0200 RISC-V: Cover sign-extensions in lshr3_zero_extend_4 The lshr3_zero_extend_4 pattern targets bit extraction

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usage in constant synthesis

https://gcc.gnu.org/g:b30496ab6f0706b373ca68cea832fe13dd0c0e59 commit b30496ab6f0706b373ca68cea832fe13dd0c0e59 Author: Jeff Law Date: Wed May 8 13:44:00 2024 -0600 [RISC-V][V2] Fix incorrect if-then-else nesting of Zbs usage in constant synthesis Reposting without the patch that

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16

https://gcc.gnu.org/g:6c5e2178e97baaba8ca156bc705222eae9a52f17 commit 6c5e2178e97baaba8ca156bc705222eae9a52f17 Author: Xiao Zeng Date: Wed May 8 14:00:58 2024 -0600 [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16 1 This patch implements the Nan-box of bf16.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Make full-vec-move1.c test robust for optimization

https://gcc.gnu.org/g:227ec9bfd49a7bf388f5c5ddd4f556e254c7a928 commit 227ec9bfd49a7bf388f5c5ddd4f556e254c7a928 Author: Pan Li Date: Thu May 9 10:56:46 2024 +0800 RISC-V: Make full-vec-move1.c test robust for optimization During investigate the support of early break autovec, we no

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add tests for cpymemsi expansion

https://gcc.gnu.org/g:94912842c2baae5ac6a1fe0c0d91330a7376d21f commit 94912842c2baae5ac6a1fe0c0d91330a7376d21f Author: Christoph Müllner Date: Thu Apr 11 12:07:10 2024 +0200 RISC-V: Add tests for cpymemsi expansion cpymemsi expansion was available for RISC-V since the initial port

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [RISC-V] Provide splitting guidance to combine to faciliate shNadd.uw generation

https://gcc.gnu.org/g:a4b72b2f9d6e5a560ebb42f485121d66576979ee commit a4b72b2f9d6e5a560ebb42f485121d66576979ee Author: Jeff Law Date: Thu May 9 21:07:06 2024 -0600 [committed] [RISC-V] Provide splitting guidance to combine to faciliate shNadd.uw generation This fixes a minor code

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix typos in code or comment [NFC]

https://gcc.gnu.org/g:73fe7fd03bc4adeac1b5ce7619b58b60e9f5dca6 commit 73fe7fd03bc4adeac1b5ce7619b58b60e9f5dca6 Author: Kito Cheng Date: Tue May 7 10:18:58 2024 +0800 RISC-V: Fix typos in code or comment [NFC] Just found some typo when fixing bugs and then use aspell to find few

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Use shNadd for constant synthesis

https://gcc.gnu.org/g:972cb5c8dbb56c378c12d2ca88b1940c1c1c1c45 commit 972cb5c8dbb56c378c12d2ca88b1940c1c1c1c45 Author: Jeff Law Date: Fri May 10 13:49:44 2024 -0600 [RISC-V] Use shNadd for constant synthesis So here's the next idiom to improve constant synthesis. The basi

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] RISC-V Fix minor regression in synthesis WRT bseti usage

https://gcc.gnu.org/g:4853bebb4dd07ffa6d836f3a8f630188e3180662 commit 4853bebb4dd07ffa6d836f3a8f630188e3180662 Author: Jeff Law Date: Sun May 12 07:05:43 2024 -0600 [to-be-committed] RISC-V Fix minor regression in synthesis WRT bseti usage Overnight testing showed a small number o

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve usage of slli.uw in constant synthesis

https://gcc.gnu.org/g:a971125e9455f91915d5be5e701c1cfcafed2b94 commit a971125e9455f91915d5be5e701c1cfcafed2b94 Author: Jeff Law Date: Sun May 12 07:12:04 2024 -0600 [to-be-committed,RISC-V] Improve usage of slli.uw in constant synthesis And an improvement to using slli.uw...

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve single inverted bit extraction - v3

https://gcc.gnu.org/g:ab251bdcabb261d630eef18f022c63ae9b8e3cd3 commit ab251bdcabb261d630eef18f022c63ae9b8e3cd3 Author: Jeff Law Date: Mon May 13 07:14:08 2024 -0600 [to-be-committed,RISC-V] Improve single inverted bit extraction - v3 So this patch fixes a minor code generation ine

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar

https://gcc.gnu.org/g:7bee3e55f02b3ae55128b22db20d0030cbeb745e commit 7bee3e55f02b3ae55128b22db20d0030cbeb745e Author: Pan Li Date: Sat May 11 15:25:28 2024 +0800 RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar For the vfw vx format RVV intrinsic, the scalar type _Floa

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix format issue for trailing operator [NFC]

https://gcc.gnu.org/g:4bcc64ea9e0232535a3fd9a2ee41775e78803244 commit 4bcc64ea9e0232535a3fd9a2ee41775e78803244 Author: Pan Li Date: Tue May 14 09:38:55 2024 +0800 RISC-V: Fix format issue for trailing operator [NFC] This patch would like to fix below format issue of trailing opera

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve AND with some constants

https://gcc.gnu.org/g:2d309988ce6388f5a4531a768ba85a983dc50535 commit 2d309988ce6388f5a4531a768ba85a983dc50535 Author: Jeff Law Date: Mon May 13 17:37:46 2024 -0600 [to-be-committed,RISC-V] Improve AND with some constants If we have an AND with a constant operand and the constant

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [1/3] expr: Export clear_by_pieces()

https://gcc.gnu.org/g:94b1fb81dd8f3db24b6db5476bbaa60db81014bd commit 94b1fb81dd8f3db24b6db5476bbaa60db81014bd Author: Christoph Müllner Date: Tue May 14 09:19:13 2024 -0600 [1/3] expr: Export clear_by_pieces() Make clear_by_pieces() available to other parts of the compiler, s

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 2/3] RISC-V: testsuite: Make cmo tests LTO safe

https://gcc.gnu.org/g:547adc910bdec0abc590444fe2d5d1eead4358a6 commit 547adc910bdec0abc590444fe2d5d1eead4358a6 Author: Christoph Müllner Date: Tue May 14 09:20:18 2024 -0600 [PATCH 2/3] RISC-V: testsuite: Make cmo tests LTO safe Let's add '\t' to the instruction match pattern to a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 3/3] RISC-V: Add memset-zero expansion to cbo.zero

https://gcc.gnu.org/g:80bf573afa3709c9716ead134480872bf88318ca commit 80bf573afa3709c9716ead134480872bf88318ca Author: Christoph Müllner Date: Tue May 14 09:21:17 2024 -0600 [PATCH 3/3] RISC-V: Add memset-zero expansion to cbo.zero The Zicboz extension offers the cbo.zero instruct

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: avoid LUI based const materialization ... [part of PR/106265]

https://gcc.gnu.org/g:b80fa21091b28877984b9cc0cabefb2b5687a07e commit b80fa21091b28877984b9cc0cabefb2b5687a07e Author: Vineet Gupta Date: Mon May 13 11:45:55 2024 -0700 RISC-V: avoid LUI based const materialization ... [part of PR/106265] ... if the constant can be represented as

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Remove redundant AND in shift-add sequence

https://gcc.gnu.org/g:1db555ae358fd9a98e98c47e8f4a3cfbea155da4 commit 1db555ae358fd9a98e98c47e8f4a3cfbea155da4 Author: Jeff Law Date: Tue May 14 18:17:59 2024 -0600 [to-be-committed,RISC-V] Remove redundant AND in shift-add sequence So this patch allows us to eliminate an redundan

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] Fix rv32 issues with recent zicboz work

https://gcc.gnu.org/g:184fca91cc3131368c0bfe2ce84ffa835d8ef08e commit 184fca91cc3131368c0bfe2ce84ffa835d8ef08e Author: Jeff Law Date: Tue May 14 22:50:15 2024 -0600 [committed] Fix rv32 issues with recent zicboz work I should have double-checked the CI system before pushing Christ

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow unaligned accesses in cpymemsi expansion

https://gcc.gnu.org/g:242ebff4075f6dde512f75be4b3e4d0b880dd080 commit 242ebff4075f6dde512f75be4b3e4d0b880dd080 Author: Christoph Müllner Date: Wed May 1 18:50:38 2024 +0200 RISC-V: Allow unaligned accesses in cpymemsi expansion The RISC-V cpymemsi expansion is called, whenever the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add test cases for cpymem expansion

https://gcc.gnu.org/g:3993646dcfd9fe06eaca5d0252589487444c7ef5 commit 3993646dcfd9fe06eaca5d0252589487444c7ef5 Author: Christoph Müllner Date: Wed May 1 16:54:42 2024 +0200 RISC-V: Add test cases for cpymem expansion We have two mechanisms in the RISC-V backend that expand cpy

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: add tests for overlapping mem ops

https://gcc.gnu.org/g:15af00b183cdc5a3884e35d733e9a2aad475a806 commit 15af00b183cdc5a3884e35d733e9a2aad475a806 Author: Christoph Müllner Date: Mon Apr 29 03:06:52 2024 +0200 RISC-V: add tests for overlapping mem ops A recent patch added the field overlap_op_by_pieces to the struct

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow by-pieces to do overlapping accesses in block_move_straight

https://gcc.gnu.org/g:db2ad3d782827fefec35b3cf140a3690033098af commit db2ad3d782827fefec35b3cf140a3690033098af Author: Christoph Müllner Date: Mon Apr 29 02:53:20 2024 +0200 RISC-V: Allow by-pieces to do overlapping accesses in block_move_straight The current implementation of ris

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Test cbo.zero expansion for rv32

https://gcc.gnu.org/g:d8f7ba2edaecdaa515d0dfca65934d2a90c63db6 commit d8f7ba2edaecdaa515d0dfca65934d2a90c63db6 Author: Christoph Müllner Date: Wed May 15 01:34:54 2024 +0200 RISC-V: Test cbo.zero expansion for rv32 We had an issue when expanding via cmo-zero for RV32. This was

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [v2, 1/2] RISC-V: Add cmpmemsi expansion

https://gcc.gnu.org/g:1687d671459b63b7e19fe33d275ebbcddd43381e commit 1687d671459b63b7e19fe33d275ebbcddd43381e Author: Christoph Müllner Date: Wed May 15 12:18:20 2024 -0600 [v2,1/2] RISC-V: Add cmpmemsi expansion GCC has a generic cmpmemsi expansion via the by-pieces framework,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [v2, 2/2] RISC-V: strcmp expansion: Use adjust_address() for address calculation

https://gcc.gnu.org/g:3411fe01e724eb941b7416e596487c55f59cf9e4 commit 3411fe01e724eb941b7416e596487c55f59cf9e4 Author: Christoph Müllner Date: Wed May 15 12:19:40 2024 -0600 [v2,2/2] RISC-V: strcmp expansion: Use adjust_address() for address calculation We have an arch-independen

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Add missing hunk in recent change.

https://gcc.gnu.org/g:d04ee599f2b7bde5bcef0ea5ff09dbacab214046 commit d04ee599f2b7bde5bcef0ea5ff09dbacab214046 Author: Jeff Law Date: Wed May 15 17:05:24 2024 -0600 Add missing hunk in recent change. gcc/ * config/riscv/riscv-string.cc: Add missing hunk from last chang

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add Zvfbfwma extension to the -march= option

https://gcc.gnu.org/g:5b202f0c899617507fb325deb7f53611f9561f1e commit 5b202f0c899617507fb325deb7f53611f9561f1e Author: Xiao Zeng Date: Wed May 15 10:03:40 2024 +0800 RISC-V: Add Zvfbfwma extension to the -march= option This patch would like to add new sub extension (aka Zvfbfwma)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: testsuite: Drop march-string in cmpmemsi/cpymemsi tests

https://gcc.gnu.org/g:423d10a1e064ef86d1c046ee8ed89ed6c5078495 commit 423d10a1e064ef86d1c046ee8ed89ed6c5078495 Author: Christoph Müllner Date: Thu May 16 09:53:47 2024 +0200 RISC-V: testsuite: Drop march-string in cmpmemsi/cpymemsi tests The tests cmpmemsi-1.c and cpymemsi-1.c are

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Internal-fn: Support new IFN SAT_ADD for unsigned scalar int

https://gcc.gnu.org/g:592205a276422c31872bf41764c59589e4a17c85 commit 592205a276422c31872bf41764c59589e4a17c85 Author: Pan Li Date: Wed May 15 10:14:05 2024 +0800 Internal-fn: Support new IFN SAT_ADD for unsigned scalar int This patch would like to add the middle-end presentation

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Vect: Support new IFN SAT_ADD for unsigned vector int

https://gcc.gnu.org/g:210fa5eb9089ee81334d8b315a6d4a0ee26b4a8d commit 210fa5eb9089ee81334d8b315a6d4a0ee26b4a8d Author: Pan Li Date: Wed May 15 10:14:06 2024 +0800 Vect: Support new IFN SAT_ADD for unsigned vector int For vectorize, we leverage the existing vect pattern recog to fi

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Vect: Support loop len in vectorizable early exit

https://gcc.gnu.org/g:f3aa41387600263a3c05b05623bd430fd7beeed2 commit f3aa41387600263a3c05b05623bd430fd7beeed2 Author: Pan Li Date: Thu May 16 09:58:13 2024 +0800 Vect: Support loop len in vectorizable early exit This patch adds early break auto-vectorization support for target wh

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement vectorizable early exit with vcond_mask_len

https://gcc.gnu.org/g:a65f9b17080323a8a936ce5a627b7ff53f25030f commit a65f9b17080323a8a936ce5a627b7ff53f25030f Author: Pan Li Date: Thu May 16 10:02:40 2024 +0800 RISC-V: Implement vectorizable early exit with vcond_mask_len After we support the loop lens for the vectorizable, we

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Enable vectorizable early exit testsuite

https://gcc.gnu.org/g:2d6625b39c814a9dc860a361a2855d6547163a69 commit 2d6625b39c814a9dc860a361a2855d6547163a69 Author: Pan Li Date: Thu May 16 10:04:10 2024 +0800 RISC-V: Enable vectorizable early exit testsuite After we supported vectorizable early exit in RISC-V, we would like

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cleanup some temporally files [NFC]

https://gcc.gnu.org/g:9beeebac68fc0dfb58db7d9cbdcb1b3f3cebf6aa commit 9beeebac68fc0dfb58db7d9cbdcb1b3f3cebf6aa Author: Pan Li Date: Fri May 17 07:45:19 2024 +0800 RISC-V: Cleanup some temporally files [NFC] Just notice some temporally files under gcc/config/riscv, deleted as u

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add initial cost handling for segment loads/stores.

https://gcc.gnu.org/g:7a46f679b3ad302431a0fdd1dc30cca9712c92ec commit 7a46f679b3ad302431a0fdd1dc30cca9712c92ec Author: Robin Dapp Date: Mon Feb 26 13:09:15 2024 +0100 RISC-V: Add initial cost handling for segment loads/stores. This patch makes segment loads and stores more expensi

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] internal-fn: Do not force vcond_mask operands to reg.

https://gcc.gnu.org/g:12ceb8df30661c10cfba80742a2503636359c79e commit 12ceb8df30661c10cfba80742a2503636359c79e Author: Robin Dapp Date: Fri May 10 12:44:44 2024 +0200 internal-fn: Do not force vcond_mask operands to reg. In order to directly use constants this patch removes force_

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement IFN SAT_ADD for both the scalar and vector

https://gcc.gnu.org/g:0b3502c3dfe791e6c13de9c2419905519689d0da commit 0b3502c3dfe791e6c13de9c2419905519689d0da Author: Pan Li Date: Fri May 17 18:49:46 2024 +0800 RISC-V: Implement IFN SAT_ADD for both the scalar and vector The patch implement the SAT_ADD in the riscv backend as t

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Modify _Bfloat16 to __bf16

https://gcc.gnu.org/g:a320bcf71489a14a634dbebeccee3b4e932b4ddb commit a320bcf71489a14a634dbebeccee3b4e932b4ddb Author: Xiao Zeng Date: Fri May 17 13:48:21 2024 +0800 RISC-V: Modify _Bfloat16 to __bf16 According to the description in:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix "Nan-box the result of movbf on soft-bf16"

https://gcc.gnu.org/g:5b632ee99b187761fc6bf02a8c6312278563fbdc commit 5b632ee99b187761fc6bf02a8c6312278563fbdc Author: Xiao Zeng Date: Wed May 15 16:23:16 2024 +0800 RISC-V: Fix "Nan-box the result of movbf on soft-bf16" 1 According to unpriv-isa spec:

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, RISC-V] Improve some shift-add sequences

https://gcc.gnu.org/g:e043aa621946842ccbc319e9683ad042abdf3ed5 commit e043aa621946842ccbc319e9683ad042abdf3ed5 Author: Jeff Law Date: Sat May 18 15:08:07 2024 -0600 [to-be-committed,RISC-V] Improve some shift-add sequences So this is a minor fix/improvement for shift-add sequences

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement -m{, no}fence-tso

https://gcc.gnu.org/g:48ab926d0426e3e4d682d518b8656a9c6d8b9b96 commit 48ab926d0426e3e4d682d518b8656a9c6d8b9b96 Author: Palmer Dabbelt Date: Sat May 18 15:15:09 2024 -0600 RISC-V: Implement -m{,no}fence-tso Some processors from T-Head don't implement the `fence.tso` instruction

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] DSE: Fix ICE after allow vector type in get_stored_val

https://gcc.gnu.org/g:98a48906bfb653d1e18323997d0854bef18986e7 commit 98a48906bfb653d1e18323997d0854bef18986e7 Author: Pan Li Date: Tue Apr 30 09:42:39 2024 +0800 DSE: Fix ICE after allow vector type in get_stored_val We allowed vector type for get_stored_val when read is less tha

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn

https://gcc.gnu.org/g:58349b4561b0cc315e60ff5aa2b777a3e80c7f9f commit 58349b4561b0cc315e60ff5aa2b777a3e80c7f9f Author: Jeff Law Date: Sun May 19 09:56:16 2024 -0600 [to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn The circumstances which trigger

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Regenerate riscv.opt.urls and i386.opt.urls

https://gcc.gnu.org/g:e42956aafe991efc2128ac0b661f2ddefd11b4f3 commit e42956aafe991efc2128ac0b661f2ddefd11b4f3 Author: Mark Wielaard Date: Mon May 20 13:13:02 2024 +0200 Regenerate riscv.opt.urls and i386.opt.urls risc-v added an -mfence-tso option. i386 removed Xeon Phi ISA suppo

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]

https://gcc.gnu.org/g:5f7595e74bba8ac4ab984ce6b47eac48b82edda2 commit 5f7595e74bba8ac4ab984ce6b47eac48b82edda2 Author: Vineet Gupta Date: Mon May 13 11:46:03 2024 -0700 RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] If the constant used for stack offs

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: avoid LUI based const mat in alloca epilogue expansion

https://gcc.gnu.org/g:d85def27f51584040cffb571ea476d43a132c59e commit d85def27f51584040cffb571ea476d43a132c59e Author: Vineet Gupta Date: Wed Mar 6 15:44:27 2024 -0800 RISC-V: avoid LUI based const mat in alloca epilogue expansion This is continuing on the prev patch in function e

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Enable vectorization for vect-early-break_124-pr114403.c

https://gcc.gnu.org/g:cd9b981f3b5124900f44b5e156c773de2f186ced commit cd9b981f3b5124900f44b5e156c773de2f186ced Author: xuli Date: Mon May 20 01:56:47 2024 + RISC-V: Enable vectorization for vect-early-break_124-pr114403.c Because "targetm.slow_unaligned_access" is set to true

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed, v2, RISC-V] Use bclri in constant synthesis

https://gcc.gnu.org/g:b6c92195b428de63a4aabcea1a8e00911f2c596d commit b6c92195b428de63a4aabcea1a8e00911f2c596d Author: Jeff Law Date: Fri May 24 07:27:00 2024 -0600 [to-be-committed,v2,RISC-V] Use bclri in constant synthesis Testing with Zbs enabled by default showed a minor logic

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed] [v2] More logical op simplifications in simplify-rtx.cc

https://gcc.gnu.org/g:91f41ea3f28d8ba5d5d93dcfcd82c7d94e4e668d commit 91f41ea3f28d8ba5d5d93dcfcd82c7d94e4e668d Author: Jeff Law Date: Sat May 25 12:39:05 2024 -0600 [committed] [v2] More logical op simplifications in simplify-rtx.cc This is a revamp of what started as a target spe

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed][RISC-V] Generate nearby constant, then adjust to our final desired constant

https://gcc.gnu.org/g:dbd78bcf532086b55ef133074259ad29d33a400a commit dbd78bcf532086b55ef133074259ad29d33a400a Author: Jeff Law Date: Sun May 26 10:54:18 2024 -0600 [to-be-committed][RISC-V] Generate nearby constant, then adjust to our final desired constant Next step in constant

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [to-be-committed] [RISC-V] Try inverting for constant synthesis

https://gcc.gnu.org/g:7f716ba0f6c0360db3643c815d390aee04d2794f commit 7f716ba0f6c0360db3643c815d390aee04d2794f Author: Jeff Law Date: Sun May 26 17:54:51 2024 -0600 [to-be-committed] [RISC-V] Try inverting for constant synthesis So there's another class of constants we're failing

[gcc r15-840] Gen-Match: Fix gen_kids_1 right hand braces mis-alignment

https://gcc.gnu.org/g:5d99cf74c9f748c93ea218eca9bd2f08edfb2a88 commit r15-840-g5d99cf74c9f748c93ea218eca9bd2f08edfb2a88 Author: Pan Li Date: Sat May 25 23:16:50 2024 +0800 Gen-Match: Fix gen_kids_1 right hand braces mis-alignment Notice some mis-alignment for gen_kids_1 right hand

[gcc r15-841] x86: Fix Logical Shift Issue in expand_vec_perm_psrlw_psllw_por [PR115146]

https://gcc.gnu.org/g:0022064649d0ec40e97df24279c48842e278fedc commit r15-841-g0022064649d0ec40e97df24279c48842e278fedc Author: Levy Hsu Date: Tue May 21 12:47:21 2024 +0930 x86: Fix Logical Shift Issue in expand_vec_perm_psrlw_psllw_por [PR115146] Replaced arithmetic shifts with

[gcc r15-842] [to-be-committed][RISC-V] Reassociate constants in logical ops

https://gcc.gnu.org/g:160929406f0c44df5b0d377a014ebfe5027fe4e7 commit r15-842-g160929406f0c44df5b0d377a014ebfe5027fe4e7 Author: Lyut Nersisyan Date: Sun May 26 21:24:40 2024 -0600 [to-be-committed][RISC-V] Reassociate constants in logical ops This patch from Lyut will reassociate

[gcc r15-843] vax: Fix descriptions of the FP format options [PR79646]

https://gcc.gnu.org/g:a7f6543f21303583356fd2d2d1805bffbecc1bc5 commit r15-843-ga7f6543f21303583356fd2d2d1805bffbecc1bc5 Author: Abe Skolnik Date: Mon May 27 05:07:32 2024 +0100 vax: Fix descriptions of the FP format options [PR79646] Replace "Target" with "Generate" consistently a

[gcc r15-844] VAX/doc: Fix issues with FP format option documentation

https://gcc.gnu.org/g:314448fc65f40c98ee8bc02dfb54ea49d2f2c60d commit r15-844-g314448fc65f40c98ee8bc02dfb54ea49d2f2c60d Author: Maciej W. Rozycki Date: Mon May 27 05:07:32 2024 +0100 VAX/doc: Fix issues with FP format option documentation Use the correct names of the D_floating an

[gcc r15-845] RISC-V: Fix missing boolean_expression in zmmul extension

https://gcc.gnu.org/g:06bb125521dec5648b725ddee4345b00decfdc77 commit r15-845-g06bb125521dec5648b725ddee4345b00decfdc77 Author: Liao Shihua Date: Fri May 24 13:03:57 2024 +0800 RISC-V: Fix missing boolean_expression in zmmul extension Update v1->v2 Add testcase for this pa