https://gcc.gnu.org/g:5b202f0c899617507fb325deb7f53611f9561f1e
commit 5b202f0c899617507fb325deb7f53611f9561f1e
Author: Xiao Zeng <zengx...@eswincomputing.com>
Date: Wed May 15 10:03:40 2024 +0800
RISC-V: Add Zvfbfwma extension to the -march= option
This patch would like to add new sub extension (aka Zvfbfwma) to the
-march= option. It introduces a new data type BF16.
1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin
extension."
1.1 In Embedded Processor: Zvfbfwma -> Zvfbfmin -> Zve32f
1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V
1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin
2 Zvfbfmin's information is in:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09>
3 Zfbfmin's formation is in:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31>
4 Depending on different usage scenarios, the Zvfbfwma extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies in
scenario of Embedded Processor. This is consistent with the processing
strategy in Zvfbfmin. In scenario of Application Processor, it is
necessary to explicitly indicate the dependent 'V' extension.
5 You can locate more information about Zvfbfwma from below spec doc:
<https://github.com/riscv/riscv-bfloat16/releases/download/v59042fc71c31a9bcb2f1957621c960ed36fac401/riscv-bfloat16.pdf>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zvfbfwma item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv.opt:
(MASK_ZVFBFWMA): New macro.
(TARGET_ZVFBFWMA): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-37.c: New test.
* gcc.target/riscv/arch-38.c: New test.
* gcc.target/riscv/predef-36.c: New test.
* gcc.target/riscv/predef-37.c: New test.
(cherry picked from commit 38dd4e26e07c6be7cf4d169141ee4f3a03f3a09d)
Diff:
---
gcc/common/config/riscv/riscv-common.cc | 5 ++++
gcc/config/riscv/riscv.opt | 2 ++
gcc/testsuite/gcc.target/riscv/arch-37.c | 5 ++++
gcc/testsuite/gcc.target/riscv/arch-38.c | 5 ++++
gcc/testsuite/gcc.target/riscv/predef-36.c | 48 ++++++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/predef-37.c | 48 ++++++++++++++++++++++++++++++
6 files changed, 113 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index fb76017ffbc..88204393fde 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -162,6 +162,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zfa", "f"},
{"zvfbfmin", "zve32f"},
+ {"zvfbfwma", "zvfbfmin"},
+ {"zvfbfwma", "zfbfmin"},
{"zvfhmin", "zve32f"},
{"zvfh", "zve32f"},
{"zvfh", "zfhmin"},
@@ -336,6 +338,7 @@ static const struct riscv_ext_version
riscv_ext_version_table[] =
{"zfh", ISA_SPEC_CLASS_NONE, 1, 0},
{"zfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
{"zvfbfmin", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zvfbfwma", ISA_SPEC_CLASS_NONE, 1, 0},
{"zvfhmin", ISA_SPEC_CLASS_NONE, 1, 0},
{"zvfh", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1667,6 +1670,7 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zve64f", &gcc_options::x_riscv_vector_elen_flags,
MASK_VECTOR_ELEN_FP_32},
{"zve64d", &gcc_options::x_riscv_vector_elen_flags,
MASK_VECTOR_ELEN_FP_64},
{"zvfbfmin", &gcc_options::x_riscv_vector_elen_flags,
MASK_VECTOR_ELEN_BF_16},
+ {"zvfbfwma", &gcc_options::x_riscv_vector_elen_flags,
MASK_VECTOR_ELEN_BF_16},
{"zvfhmin", &gcc_options::x_riscv_vector_elen_flags,
MASK_VECTOR_ELEN_FP_16},
{"zvfh", &gcc_options::x_riscv_vector_elen_flags,
MASK_VECTOR_ELEN_FP_16},
@@ -1704,6 +1708,7 @@ static const riscv_ext_flag_table_t
riscv_ext_flag_table[] =
{"zfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
{"zfh", &gcc_options::x_riscv_zf_subext, MASK_ZFH},
{"zvfbfmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN},
+ {"zvfbfwma", &gcc_options::x_riscv_zf_subext, MASK_ZVFBFWMA},
{"zvfhmin", &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
{"zvfh", &gcc_options::x_riscv_zf_subext, MASK_ZVFH},
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 1252834aec5..d209ac896fd 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -401,6 +401,8 @@ Mask(ZFH) Var(riscv_zf_subext)
Mask(ZVFBFMIN) Var(riscv_zf_subext)
+Mask(ZVFBFWMA) Var(riscv_zf_subext)
+
Mask(ZVFHMIN) Var(riscv_zf_subext)
Mask(ZVFH) Var(riscv_zf_subext)
diff --git a/gcc/testsuite/gcc.target/riscv/arch-37.c
b/gcc/testsuite/gcc.target/riscv/arch-37.c
new file mode 100644
index 00000000000..5b19a73c556
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-37.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zvfbfwma -mabi=ilp32f" } */
+int
+foo ()
+{}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-38.c
b/gcc/testsuite/gcc.target/riscv/arch-38.c
new file mode 100644
index 00000000000..cee3efebe75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-38.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64iv_zvfbfwma -mabi=lp64d" } */
+int
+foo ()
+{}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-36.c
b/gcc/testsuite/gcc.target/riscv/predef-36.c
new file mode 100644
index 00000000000..b0205b08513
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-36.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32i_zvfbfwma -mabi=ilp32f -mcmodel=medlow
-misa-spec=20191213" } */
+
+int
+main ()
+{
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 32
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_zfbfmin)
+#error "__riscv_zfbfmin"
+#endif
+
+#if !defined(__riscv_zvfbfwma)
+#error "__riscv_zvfbfwma"
+#endif
+
+#if defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-37.c
b/gcc/testsuite/gcc.target/riscv/predef-37.c
new file mode 100644
index 00000000000..b5aa41102f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-37.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64iv_zvfbfwma -mabi=lp64d -mcmodel=medlow
-misa-spec=20191213" } */
+
+int
+main ()
+{
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i)
+#error "__riscv_i"
+#endif
+
+#if !defined(__riscv_f)
+#error "__riscv_f"
+#endif
+
+#if !defined(__riscv_d)
+#error "__riscv_d"
+#endif
+
+#if !defined(__riscv_v)
+#error "__riscv_v"
+#endif
+
+#if !defined(__riscv_zfbfmin)
+#error "__riscv_zfbfmin"
+#endif
+
+#if !defined(__riscv_zvfbfwma)
+#error "__riscv_zvfbfwma"
+#endif
+
+#if defined(__riscv_c)
+#error "__riscv_c"
+#endif
+
+#if defined(__riscv_a)
+#error "__riscv_a"
+#endif
+
+ return 0;
+}
