[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Enable vectorizable early exit testsuite

[Jeff Law via Gcc-cvs]

https://gcc.gnu.org/g:2d6625b39c814a9dc860a361a2855d6547163a69

commit 2d6625b39c814a9dc860a361a2855d6547163a69
Author: Pan Li <pan2...@intel.com>
Date:   Thu May 16 10:04:10 2024 +0800

    RISC-V: Enable vectorizable early exit testsuite
    
    After we supported vectorizable early exit in RISC-V,  we would like to
    enable the gcc vect test for vectorizable early test.
    
    The vect-early-break_124-pr114403.c failed to vectorize for now.
    Because that the __builtin_memcpy with 8 bytes failed to folded into
    int64 assignment during ccp1.  We will improve that first and mark
    this as xfail for RISC-V.
    
    The below tests are passed for this patch:
    1. The riscv fully regression tests.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.dg/vect/slp-mask-store-1.c: Add pragma novector as it will
            have 2 times LOOP VECTORIZED in RISC-V.
            * gcc.dg/vect/vect-early-break_124-pr114403.c: Xfail for the
            riscv backend.
            * lib/target-supports.exp: Add RISC-V backend.
    
    Signed-off-by: Pan Li <pan2...@intel.com>
    (cherry picked from commit 556e777298dac8574533935000c57335c5232921)

Diff:
---
 gcc/testsuite/gcc.dg/vect/slp-mask-store-1.c              | 2 ++
 gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c | 2 +-
 gcc/testsuite/lib/target-supports.exp                     | 2 ++
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/vect/slp-mask-store-1.c 
b/gcc/testsuite/gcc.dg/vect/slp-mask-store-1.c
index fdd9032da98..2f80bf89e5e 100644
--- a/gcc/testsuite/gcc.dg/vect/slp-mask-store-1.c
+++ b/gcc/testsuite/gcc.dg/vect/slp-mask-store-1.c
@@ -28,6 +28,8 @@ main ()
 
   if (__builtin_memcmp (x, res, sizeof (x)) != 0)
     abort ();
+
+#pragma GCC novector
   for (int i = 0; i < 32; ++i)
     if (flag[i] != 0 && flag[i] != 1)
       abort ();
diff --git a/gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c 
b/gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c
index 51abf245ccb..101ae1e0eaa 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-early-break_124-pr114403.c
@@ -2,7 +2,7 @@
 /* { dg-require-effective-target vect_early_break_hw } */
 /* { dg-require-effective-target vect_long_long } */
 
-/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */
+/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { xfail riscv*-*-* } } 
} */
 
 #include "tree-vect.h"
 
diff --git a/gcc/testsuite/lib/target-supports.exp 
b/gcc/testsuite/lib/target-supports.exp
index 3a55b2a4159..6c828b73ded 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4105,6 +4105,7 @@ proc check_effective_target_vect_early_break { } {
        || [check_effective_target_arm_v8_neon_ok]
        || [check_effective_target_sse4]
        || [istarget amdgcn-*-*]
+       || [check_effective_target_riscv_v]
        }}]
 }
 
@@ -4120,6 +4121,7 @@ proc check_effective_target_vect_early_break_hw { } {
        || [check_effective_target_arm_v8_neon_hw]
        || [check_sse4_hw_available]
        || [istarget amdgcn-*-*]
+       || [check_effective_target_riscv_v_ok]
        }}]
 }