[gcc r14-11233] c++/modules: Propagate FNDECL_USED_AUTO when propagating deduced return types [PR118049]

https://gcc.gnu.org/g:a82352a2a074230d841a3944e30bd497726e0bfa commit r14-11233-ga82352a2a074230d841a3944e30bd497726e0bfa Author: Nathaniel Shead Date: Fri Jan 17 21:29:08 2025 +1100 c++/modules: Propagate FNDECL_USED_AUTO when propagating deduced return types [PR118049] In the l

[gcc r15-7085] c++/modules: Check linkage of structured binding decls

https://gcc.gnu.org/g:2fcb0c079530b019586e5693f057d2eb72855e70 commit r15-7085-g2fcb0c079530b019586e5693f057d2eb72855e70 Author: Nathaniel Shead Date: Sun Jan 19 15:26:03 2025 +1100 c++/modules: Check linkage of structured binding decls When looking at PR c++/118513 I noticed that

[gcc r15-7084] c++/modules: Handle mismatching TYPE_CANONICAL when deduping partial specs [PR118101]

https://gcc.gnu.org/g:5c0e1879ea639dc527d3928af877d3df985e3f13 commit r15-7084-g5c0e1879ea639dc527d3928af877d3df985e3f13 Author: Nathaniel Shead Date: Mon Jan 20 22:09:22 2025 +1100 c++/modules: Handle mismatching TYPE_CANONICAL when deduping partial specs [PR118101] In r15-4862

[gcc r12-10921] d: Fix failing test with 32-bit compiler [PR114434]

https://gcc.gnu.org/g:f4b8c08c86237e7eb29defb2f8ae3bff22581e5f commit r12-10921-gf4b8c08c86237e7eb29defb2f8ae3bff22581e5f Author: Iain Buclaw Date: Mon Jan 20 20:01:03 2025 +0100 d: Fix failing test with 32-bit compiler [PR114434] Since the introduction of gdc.test/runnable/test23

[gcc r15-7083] [PR118560][LRA]: Fix typo in checking secondary memory mode for the reg class

https://gcc.gnu.org/g:07f62ed9a7b09951f83855e19d41641b098190b1 commit r15-7083-g07f62ed9a7b09951f83855e19d41641b098190b1 Author: Vladimir N. Makarov Date: Mon Jan 20 17:08:50 2025 -0500 [PR118560][LRA]: Fix typo in checking secondary memory mode for the reg class The patch for

[gcc r15-7082] [PR target/116256] Adjust expected output in a couple testcases

https://gcc.gnu.org/g:1edd93fbaddce9b2938e2927014272fa621ade9c commit r15-7082-g1edd93fbaddce9b2938e2927014272fa621ade9c Author: Jeff Law Date: Mon Jan 20 15:05:34 2025 -0700 [PR target/116256] Adjust expected output in a couple testcases I've had a long standing TODO to review th

[gcc r15-7081] [PR target/114442] Add reservations for all insn types to xiangshan-nanhu model

https://gcc.gnu.org/g:64a162d5562a333b816f6dc188814c14ba3c9f2c commit r15-7081-g64a162d5562a333b816f6dc188814c14ba3c9f2c Author: Jeff Law Date: Mon Jan 20 14:50:57 2025 -0700 [PR target/114442] Add reservations for all insn types to xiangshan-nanhu model The RISC-V backend has ch

[gcc r15-7080] [PR target/116256] Fix latent regression in pattern to associate arithmetic to simplify constants

https://gcc.gnu.org/g:59e5d086a348f2b9e5adae1ba820ba7aaf7289db commit r15-7080-g59e5d086a348f2b9e5adae1ba820ba7aaf7289db Author: Jeff Law Date: Mon Jan 20 14:35:59 2025 -0700 [PR target/116256] Fix latent regression in pattern to associate arithmetic to simplify constants This is

[gcc r14-11231] Update gcc zh_CN.po

https://gcc.gnu.org/g:696b87db7d56bb491e08822a7b4fb8463c45491e commit r14-11231-g696b87db7d56bb491e08822a7b4fb8463c45491e Author: Joseph Myers Date: Mon Jan 20 21:24:59 2025 + Update gcc zh_CN.po * zh_CN.po: Update. Diff: --- gcc/po/zh_CN.po | 520 +++

[gcc r15-7079] Update gcc zh_CN.po

https://gcc.gnu.org/g:5ad94b64089f05f55dbf9014096106ff395c7892 commit r15-7079-g5ad94b64089f05f55dbf9014096106ff395c7892 Author: Joseph Myers Date: Mon Jan 20 21:23:15 2025 + Update gcc zh_CN.po * zh_CN.po: Update. Diff: --- gcc/po/zh_CN.po | 520

[gcc r15-7071] d: Fix failing test with 32-bit compiler [PR114434]

https://gcc.gnu.org/g:9ab38952a2033d6d4a8e31c3c4d2ab1a25a406c6 commit r15-7071-g9ab38952a2033d6d4a8e31c3c4d2ab1a25a406c6 Author: Iain Buclaw Date: Mon Jan 20 20:01:03 2025 +0100 d: Fix failing test with 32-bit compiler [PR114434] Since the introduction of gdc.test/runnable/test235

[gcc r15-7077] Fortran: improve error message for conflicting OpenMP clauses [PR107122]

https://gcc.gnu.org/g:96f4ba4d19a765902af7b79aa77d52c62fa2f82c commit r15-7077-g96f4ba4d19a765902af7b79aa77d52c62fa2f82c Author: Harald Anlauf Date: Mon Jan 20 21:21:48 2025 +0100 Fortran: improve error message for conflicting OpenMP clauses [PR107122] PR fortran/107122

[gcc r13-9336] d: Fix failing test with 32-bit compiler [PR114434]

https://gcc.gnu.org/g:76d660277e5cd61055c3838bf59c90321d4686fb commit r13-9336-g76d660277e5cd61055c3838bf59c90321d4686fb Author: Iain Buclaw Date: Mon Jan 20 20:01:03 2025 +0100 d: Fix failing test with 32-bit compiler [PR114434] Since the introduction of gdc.test/runnable/test235

[gcc r15-7078] [PR117868][LRA]: Restrict the reuse of spill slots

https://gcc.gnu.org/g:5cd4605141b8b45cab95e4de8005c69273071107 commit r15-7078-g5cd4605141b8b45cab95e4de8005c69273071107 Author: Denis Chertykov Date: Tue Jan 21 00:27:04 2025 +0400 [PR117868][LRA]: Restrict the reuse of spill slots This is an LRA bug derived from reuse spilling s

[gcc r12-10920] i386: Disable SImode/DImode moves from/to mask regs without avx512bw [PR118067]

https://gcc.gnu.org/g:9a1efd1ee2509abb93878bd911d8c07143b10e33 commit r12-10920-g9a1efd1ee2509abb93878bd911d8c07143b10e33 Author: Uros Bizjak Date: Mon Jan 20 16:19:43 2025 +0100 i386: Disable SImode/DImode moves from/to mask regs without avx512bw [PR118067] SImode and DImode mov

[gcc r15-7076] vect: Preserve OMP info for conditional stores [PR118348]

https://gcc.gnu.org/g:749dcd9ba8466fec5b51dd564cd63424c44f808b commit r15-7076-g749dcd9ba8466fec5b51dd564cd63424c44f808b Author: Richard Sandiford Date: Mon Jan 20 20:05:05 2025 + vect: Preserve OMP info for conditional stores [PR118348] OMP reductions are lowered into the for

[gcc r15-7075] Revert "vect: Preserve OMP info for conditional stores [PR118384]"

https://gcc.gnu.org/g:09c8aa319e1da30c5629024bfd3bcfc6cf42770e commit r15-7075-g09c8aa319e1da30c5629024bfd3bcfc6cf42770e Author: Richard Sandiford Date: Mon Jan 20 20:05:04 2025 + Revert "vect: Preserve OMP info for conditional stores [PR118384]" This reverts commit 8edf8b5523

[gcc r14-11230] d: Fix failing test with 32-bit compiler [PR114434]

https://gcc.gnu.org/g:ffa44df6768368dc516c9626ec388a3561c7644f commit r14-11230-gffa44df6768368dc516c9626ec388a3561c7644f Author: Iain Buclaw Date: Mon Jan 20 20:01:03 2025 +0100 d: Fix failing test with 32-bit compiler [PR114434] Since the introduction of gdc.test/runnable/test23

[gcc r15-7073] aarch64: Fix invalid subregs in xorsign [PR118501]

https://gcc.gnu.org/g:6612b8e55471fabd2071a9637a06d3ffce2b05a6 commit r15-7073-g6612b8e55471fabd2071a9637a06d3ffce2b05a6 Author: Richard Sandiford Date: Mon Jan 20 19:52:31 2025 + aarch64: Fix invalid subregs in xorsign [PR118501] In the testcase, we try to use xorsign on:

[gcc r15-7074] vect: Preserve OMP info for conditional stores [PR118384]

https://gcc.gnu.org/g:8edf8b552313951cb4f2f97821ee4b3820c9506b commit r15-7074-g8edf8b552313951cb4f2f97821ee4b3820c9506b Author: Richard Sandiford Date: Mon Jan 20 19:52:31 2025 + vect: Preserve OMP info for conditional stores [PR118384] OMP reductions are lowered into the for

[gcc r15-7072] aarch64: Add missing simd requirements for INS [PR118531]

https://gcc.gnu.org/g:1b8820421488d220a95f651b51175d618063c48c commit r15-7072-g1b8820421488d220a95f651b51175d618063c48c Author: Richard Sandiford Date: Mon Jan 20 19:52:30 2025 + aarch64: Add missing simd requirements for INS [PR118531] In g:b096a6ebe9d9f9fed4c105f6555f724eb3

[gcc r15-7070] Fortran: do not copy back for parameter actual arguments [PR81978]

https://gcc.gnu.org/g:0d1e62b83561baa185bf080515750a89dd3ac410 commit r15-7070-g0d1e62b83561baa185bf080515750a89dd3ac410 Author: Harald Anlauf Date: Sun Jan 19 21:06:56 2025 +0100 Fortran: do not copy back for parameter actual arguments [PR81978] When an array is packed for passin

[gcc r15-7069] c++: Handle RAW_DATA_CST in make_tree_vector_from_ctor [PR118528]

https://gcc.gnu.org/g:0b58219fe112c01ff335edf699c4fc69e718c75b commit r15-7069-g0b58219fe112c01ff335edf699c4fc69e718c75b Author: Jakub Jelinek Date: Mon Jan 20 18:00:43 2025 +0100 c++: Handle RAW_DATA_CST in make_tree_vector_from_ctor [PR118528] This is the first bug discovered to

[gcc r15-7068] RISC-V: Correct the mode that is causing the program to fail for XTheadCondMov

https://gcc.gnu.org/g:9d869296f095a02c37d3721f546ce99663e5417c commit r15-7068-g9d869296f095a02c37d3721f546ce99663e5417c Author: Jin Ma Date: Mon Jan 20 09:29:30 2025 -0700 RISC-V: Correct the mode that is causing the program to fail for XTheadCondMov For XTheadCondMov, the bit w

[gcc r15-7067] inline: Purge the abnormal edges as needed in fold_marked_statements [PR118077]

https://gcc.gnu.org/g:0fe35e9b93a286de78dd5b80d8d58e9ef0591f03 commit r15-7067-g0fe35e9b93a286de78dd5b80d8d58e9ef0591f03 Author: Andrew Pinski Date: Sun Jan 19 16:07:10 2025 -0800 inline: Purge the abnormal edges as needed in fold_marked_statements [PR118077] While fixing PR targ

[gcc r15-7066] libstdc++: perfectly forward std::ranges::clamp arguments

https://gcc.gnu.org/g:b342614139c0a981b369176980663941b9c27f39 commit r15-7066-gb342614139c0a981b369176980663941b9c27f39 Author: Giuseppe D'Angelo Date: Sun Jan 19 16:30:20 2025 +0100 libstdc++: perfectly forward std::ranges::clamp arguments As reported in PR118185, std::ranges::c

[gcc r15-7065] arm, testsuite: fix fast-math-bb-slp-complex-mla-float.c dg-add-options

https://gcc.gnu.org/g:7cc573017274acfd5a276d959a8297ba04e98002 commit r15-7065-g7cc573017274acfd5a276d959a8297ba04e98002 Author: Christophe Lyon Date: Thu Dec 19 10:07:28 2024 + arm, testsuite: fix fast-math-bb-slp-complex-mla-float.c dg-add-options The test uses floats, not f

[gcc r15-7064] arm, testsuite: remove duplicate dg-add-options arm_v8_3a_complex_neon

https://gcc.gnu.org/g:cb35651269cef74301250f5d7c0412f81a33aef4 commit r15-7064-gcb35651269cef74301250f5d7c0412f81a33aef4 Author: Christophe Lyon Date: Wed Dec 18 13:49:20 2024 + arm, testsuite: remove duplicate dg-add-options arm_v8_3a_complex_neon These two testcases have twi

[gcc r13-9335] i386: Disable SImode/DImode moves from/to mask regs without avx512bw [PR118067]

https://gcc.gnu.org/g:1fe03d184723ee942c74b5e6f8cde45d2fcdcd60 commit r13-9335-g1fe03d184723ee942c74b5e6f8cde45d2fcdcd60 Author: Uros Bizjak Date: Mon Jan 20 16:12:26 2025 +0100 i386: Disable SImode/DImode moves from/to mask regs without avx512bw [PR118067] SImode and DImode move

[gcc r15-7063] tree-optimization/117875 - missed SLP vectorization

https://gcc.gnu.org/g:7b64f757a8df8efd989000baa667279f8957442e commit r15-7063-g7b64f757a8df8efd989000baa667279f8957442e Author: Richard Biener Date: Mon Jan 20 14:25:31 2025 +0100 tree-optimization/117875 - missed SLP vectorization There's a discrepancy in SLP vs non-SLP vectoriz

[gcc r15-7062] LoongArch: Improve reassociation for bitwise operation and left shift [PR 115921]

https://gcc.gnu.org/g:10e98638998745ebc3888a20e661a8364e88ea3a commit r15-7062-g10e98638998745ebc3888a20e661a8364e88ea3a Author: Xi Ruoyao Date: Tue Jan 14 17:26:04 2025 +0800 LoongArch: Improve reassociation for bitwise operation and left shift [PR 115921] For things like

[gcc r15-7061] LoongArch: Simplify using bstr{ins, pick} instructions for and

https://gcc.gnu.org/g:f3bedc9a3b8b7dd3911272731a1ea595621e13cd commit r15-7061-gf3bedc9a3b8b7dd3911272731a1ea595621e13cd Author: Xi Ruoyao Date: Thu Sep 5 17:53:41 2024 +0800 LoongArch: Simplify using bstr{ins,pick} instructions for and For bstrins, we can merge it into and3 inste

[gcc r15-7060] testsuite: Fix name of PR116348 test case

https://gcc.gnu.org/g:67b10ee872197ba53524db4f0ca777899e27b151 commit r15-7060-g67b10ee872197ba53524db4f0ca777899e27b151 Author: Xi Ruoyao Date: Mon Jan 20 20:41:34 2025 +0800 testsuite: Fix name of PR116348 test case gcc/testsuite/ChangeLog: * gcc.c-torture/compi

[gcc r15-7059] tree-optimization/118552 - failed LC SSA update after unrolling

https://gcc.gnu.org/g:1265afa91d51606605f85e732344e86e4e4dae9b commit r15-7059-g1265afa91d51606605f85e732344e86e4e4dae9b Author: Richard Biener Date: Mon Jan 20 11:50:53 2025 +0100 tree-optimization/118552 - failed LC SSA update after unrolling When unrolling changes nesting relat

[gcc r15-7058] nvptx: Gracefully handle '-mptx=3.1' if neither sm_30 nor sm_35 multilib variant is built

https://gcc.gnu.org/g:6c5937991bd744a4916e9cf65eb5d9c9b5706120 commit r15-7058-g6c5937991bd744a4916e9cf65eb5d9c9b5706120 Author: Thomas Schwinge Date: Fri Jan 17 21:45:42 2025 +0100 nvptx: Gracefully handle '-mptx=3.1' if neither sm_30 nor sm_35 multilib variant is built For exam

[gcc r12-10919] c++: Friend classes don't shadow enclosing template class paramater [PR118255]

https://gcc.gnu.org/g:7bb462dd2a6a6551d142e7ad983fa2afd1df9253 commit r12-10919-g7bb462dd2a6a6551d142e7ad983fa2afd1df9253 Author: Simon Martin Date: Sun Jan 5 10:36:47 2025 +0100 c++: Friend classes don't shadow enclosing template class paramater [PR118255] We currently reject th

[gcc r15-7057] tree, c++: Consider TARGET_EXPR invariant like SAVE_EXPR [PR118509]

https://gcc.gnu.org/g:d9d0eeea93d39d304c7420e87f4b903d89f2e9fa commit r15-7057-gd9d0eeea93d39d304c7420e87f4b903d89f2e9fa Author: Jakub Jelinek Date: Mon Jan 20 10:26:49 2025 +0100 tree, c++: Consider TARGET_EXPR invariant like SAVE_EXPR [PR118509] My October PR117259 fix to get_me

[gcc r15-7056] tree-ssa-dce: Fix calloc handling [PR118224]

https://gcc.gnu.org/g:d882e48d48bf300941c3610c5af157c64ccf0a84 commit r15-7056-gd882e48d48bf300941c3610c5af157c64ccf0a84 Author: Jakub Jelinek Date: Mon Jan 20 10:24:18 2025 +0100 tree-ssa-dce: Fix calloc handling [PR118224] As reported by Dimitar, this should have been a multipli

[gcc r15-7054] s390: Vector shift: Add 128-bit integer support

https://gcc.gnu.org/g:10c52b3866572df9f84e41d8045cbf8c6ce6ab04 commit r15-7054-g10c52b3866572df9f84e41d8045cbf8c6ce6ab04 Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:10 2025 +0100 s390: Vector shift: Add 128-bit integer support Add 128-bit vector shift support. Depr

[gcc r15-7052] s390: arch15: Vector load positive: Add 128-bit integer support

https://gcc.gnu.org/g:4cf5e261df34878033e20fb2b8a13ea643ab7f4c commit r15-7052-g4cf5e261df34878033e20fb2b8a13ea643ab7f4c Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:10 2025 +0100 s390: arch15: Vector load positive: Add 128-bit integer support For previous architectu

[gcc r15-7055] s390: Update vec_(load,store)_len(,_r)

https://gcc.gnu.org/g:459816efa13d9d553a5c900336f6eef22072f1a1 commit r15-7055-g459816efa13d9d553a5c900336f6eef22072f1a1 Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:10 2025 +0100 s390: Update vec_(load,store)_len(,_r) Reflect latest updates for vec_(load,store)_len(

[gcc r15-7051] s390: arch15: Vector compare: Add 128-bit integer support

https://gcc.gnu.org/g:2e87d6e44198e2b134555d661366a2f941615511 commit r15-7051-g2e87d6e44198e2b134555d661366a2f941615511 Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:10 2025 +0100 s390: arch15: Vector compare: Add 128-bit integer support gcc/ChangeLog:

[gcc r15-7050] s390: arch15: Vector devide/remainder

https://gcc.gnu.org/g:f31dd2d9e683ddd8534663af092984ddb911 commit r15-7050-gf31dd2d9e683ddd8534663af092984ddb911 Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:09 2025 +0100 s390: arch15: Vector devide/remainder gcc/ChangeLog: * config/s390/vec

[gcc r15-7053] s390: arch15: Vector maximum/minimum: Add 128-bit integer support

https://gcc.gnu.org/g:ec226016ca4954a431409699a52850717617bbfa commit r15-7053-gec226016ca4954a431409699a52850717617bbfa Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:10 2025 +0100 s390: arch15: Vector maximum/minimum: Add 128-bit integer support For previous architec

[gcc r15-7049] s390: arch15: Count leading/trailing zeros

https://gcc.gnu.org/g:0f0b91ef70218e2cb4ab795ef04725a68ea04b15 commit r15-7049-g0f0b91ef70218e2cb4ab795ef04725a68ea04b15 Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:09 2025 +0100 s390: arch15: Count leading/trailing zeros Add vector single element 128-bit integer su

[gcc r15-7048] s390: arch15: Vector generate element masks

https://gcc.gnu.org/g:41a69915d06a707bb6c80cc1ebf5d1c1396d commit r15-7048-g41a69915d06a707bb6c80cc1ebf5d1c1396d Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:09 2025 +0100 s390: arch15: Vector generate element masks Add instruction vgem and vector builtins

[gcc r15-7047] s390: arch15: Vector eval

https://gcc.gnu.org/g:7fb7b36293519ed68481ca8477244b5a4f142d4a commit r15-7047-g7fb7b36293519ed68481ca8477244b5a4f142d4a Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:09 2025 +0100 s390: arch15: Vector eval Add instruction veval and builtin vec_evaluate. gcc/

[gcc r15-7046] s390: arch15: Vector blend

https://gcc.gnu.org/g:adeb6ecc5d906ce2389400085f3262b4a248c71c commit r15-7046-gadeb6ecc5d906ce2389400085f3262b4a248c71c Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:09 2025 +0100 s390: arch15: Vector blend Add instruction vblend and builtin vec_blend. gcc/C

[gcc r15-7045] s390: arch15: Bit deposit and extract

https://gcc.gnu.org/g:d71e20b889ac82c3ca14a1c5c420765a11b06df9 commit r15-7045-gd71e20b889ac82c3ca14a1c5c420765a11b06df9 Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:09 2025 +0100 s390: arch15: Bit deposit and extract Add instructions bdepg and bextg and correspondin

[gcc r15-7043] s390: arch15: New instruction variants supporting 128-bit integer

https://gcc.gnu.org/g:447b917e98ee34e2eae455b43784ab6a86b604f2 commit r15-7043-g447b917e98ee34e2eae455b43784ab6a86b604f2 Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:08 2025 +0100 s390: arch15: New instruction variants supporting 128-bit integer Add new instruction v

[gcc r15-7044] s390: arch15: Load indexed address

https://gcc.gnu.org/g:86a1acfd86f881c32e0ae57036df65edd7d1d441 commit r15-7044-g86a1acfd86f881c32e0ae57036df65edd7d1d441 Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:09 2025 +0100 s390: arch15: Load indexed address Add instructions lxa and llxa. gcc/ChangeLo

[gcc r15-7042] s390: arch15: Prepare for future builtins

https://gcc.gnu.org/g:b963174abfb601bc39504d09ac6b86c53660e170 commit r15-7042-gb963174abfb601bc39504d09ac6b86c53660e170 Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:08 2025 +0100 s390: arch15: Prepare for future builtins gcc/ChangeLog: * config/s390

[gcc r15-7041] s390: Bump __VEC__ and add 128-bit integer zvector types

https://gcc.gnu.org/g:13efa59ce66516937fd5e0608d2aa3aab46c5d76 commit r15-7041-g13efa59ce66516937fd5e0608d2aa3aab46c5d76 Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:08 2025 +0100 s390: Bump __VEC__ and add 128-bit integer zvector types Bump __VEC__ version to 10305

[gcc r15-7040] s390: arch15: Prepare for a future architecture

https://gcc.gnu.org/g:a8192b59175e2cfcf665573d8168a8be09bdfa51 commit r15-7040-ga8192b59175e2cfcf665573d8168a8be09bdfa51 Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:08 2025 +0100 s390: arch15: Prepare for a future architecture gcc/ChangeLog: * commo

[gcc r15-7039] s390: Sort definitions in vecintrin.h

https://gcc.gnu.org/g:2638aea49a927ed7419f334f3e3d44c49cf44a3e commit r15-7039-g2638aea49a927ed7419f334f3e3d44c49cf44a3e Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:08 2025 +0100 s390: Sort definitions in vecintrin.h gcc/ChangeLog: * config/s390/vec

[gcc r15-7038] s390: Stay scalar for TOINTVEC/tointvec

https://gcc.gnu.org/g:0c6fdb9befa611135f6f94f15d97664e8f02e41f commit r15-7038-g0c6fdb9befa611135f6f94f15d97664e8f02e41f Author: Stefan Schulze Frielinghaus Date: Mon Jan 20 10:01:08 2025 +0100 s390: Stay scalar for TOINTVEC/tointvec Currently TOINTVEC maps scalar mode TI/TF to ve