https://gcc.gnu.org/g:1edd93fbaddce9b2938e2927014272fa621ade9c
commit r15-7082-g1edd93fbaddce9b2938e2927014272fa621ade9c
Author: Jeff Law <j...@ventanamicro.com>
Date: Mon Jan 20 15:05:34 2025 -0700
[PR target/116256] Adjust expected output in a couple testcases
I've had a long standing TODO to review the RISC-V testsuite regressions
from
enabling the late-combine pass (pr116256). I adjusted a few cases months
ago,
this adjusts a couple more were it looks like the right thing to do.
All that's left after this are the vls/dup-? tests which regress in
meaningful
ways and I'm still investigating reasonable approaches to fix them (they
play
into the whole mvconst_internal pattern situation), late-combine isn't doing
anything wrong.
PR target/116256
gcc/testsuite
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c: Update expected
output.
* gcc.target/riscv/rvv/vsetvl/vsetvl-15.c: Likewise.
Diff:
---
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
index 3e0f290c7c76..945beed5ebb3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-37.c
@@ -38,4 +38,4 @@ void f (int32_t * restrict in, int32_t * restrict out,
int32_t * restrict in2, i
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c
index 610727b258ee..e42f77deaef9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-15.c
@@ -18,5 +18,5 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t
*out, size_t n, int c
}
}
-/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"
no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
/* { dg-final { scan-assembler-times {srli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*4} 1 {
target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
