[Bug target/117877] New: [RISC-V][14/15 Regression] internal compiler error: Floating point exception

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117877 Bug ID: 117877 Summary: [RISC-V][14/15 Regression] internal compiler error: Floating point exception Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: n

[Bug target/117953] New: [15 Regression] GCC miscompile rvv intrinsics at `-O2` and `-O3`, missing `csrwi` to modify `vxrm`

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117953 Bug ID: 117953 Summary: [15 Regression] GCC miscompile rvv intrinsics at `-O2` and `-O3`, missing `csrwi` to modify `vxrm` Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug target/117955] [15 Regression] GCC generate illegal riscv instruction `vsetvli zero,zero,e64,mf4,ta,ma` with -O2 and -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117955 --- Comment #3 from rvismith --- (In reply to Andrew Pinski from comment #1) > What version of qemu are you usirng? Thanks for your reply. I use qemu v9.1.0: ``` $ /home/emulator/qemu-9.1.0/build/qemu-riscv64 --version qemu-riscv64 version 9.1.

[Bug target/117953] [15 Regression] GCC miscompile rvv intrinsics at `-O2` and `-O3`, missing `csrwi` to modify `vxrm`

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117953 --- Comment #1 from rvismith --- Here are results of array b I get (by gcc 15 + qemu 9.1.0): at -O0 (correct) >>> 0 2 5 7 10 12 15 17 20 22 at -O3 (rounding error) >>> 0 3 5 8 10 13 15 18 20 23

[Bug target/117955] New: [15 Regression] GCC generate illegal riscv instruction `vsetvli zero,zero,e64,mf4,ta,ma` with -O2 and -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117955 Bug ID: 117955 Summary: [15 Regression] GCC generate illegal riscv instruction `vsetvli zero,zero,e64,mf4,ta,ma` with -O2 and -O3 Product: gcc Version: 15.0 Status: UNCO

[Bug target/118100] New: [14/15 Regression] Segment Fault by rvv intrinsic compilation at `-O2` and `-O3`.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118100 Bug ID: 118100 Summary: [14/15 Regression] Segment Fault by rvv intrinsic compilation at `-O2` and `-O3`. Product: gcc Version: 15.0 Status: UNCONFIRMED Severi

[Bug target/118103] New: [15 Regression] GCC miscompile rvv intrinsics at `-O3`, missing the `fsrm` instruction to the recover status of frm CSR

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118103 Bug ID: 118103 Summary: [15 Regression] GCC miscompile rvv intrinsics at `-O3`, missing the `fsrm` instruction to the recover status of frm CSR Product: gcc Vers

[Bug target/117947] New: [14/15 Regression] GCC miscompile rvv intrinsics at `-O2` and `-O3`, use `vlenb` after an inappropriate `vsetvli`

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117947 Bug ID: 117947 Summary: [14/15 Regression] GCC miscompile rvv intrinsics at `-O2` and `-O3`, use `vlenb` after an inappropriate `vsetvli` Product: gcc Version: 1