[Bug target/117955] [15 Regression] GCC generate illegal riscv instruction `vsetvli zero,zero,e64,mf4,ta,ma` with -O2 and -O3

[rvismith1115 at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117955

--- Comment #3 from rvismith <rvismith1115 at gmail dot com> ---
(In reply to Andrew Pinski from comment #1)
> What version of qemu are you usirng?

Thanks for your reply. I use qemu v9.1.0:
```
$ /home/emulator/qemu-9.1.0/build/qemu-riscv64 --version
qemu-riscv64 version 9.1.0
Copyright (c) 2003-2024 Fabrice Bellard and the QEMU Project developers
```

I have tried the illegal instruction can be fixed by changing the instruction
to `vsetvli zero,zero,e16,mf4,ta,ma`. 

`e64mf4` is illegal because `vlen` can be 128, and in this case the fraction of
vector register cannot hold 64-bit elements (1/4 * 128 = 32 < 64). In the type
system of rvv intrinsic
(https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/main/doc/rvv-intrinsic-spec.adoc#type-system),
there are also no 64mf4 types.