https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117953
Bug ID: 117953 Summary: [15 Regression] GCC miscompile rvv intrinsics at `-O2` and `-O3`, missing `csrwi` to modify `vxrm` Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: rvismith1115 at gmail dot com Target Milestone: --- Created attachment 59818 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59818&action=edit reduced testcase An test case example: ``` #include <riscv_vector.h> void abort(void); #define dataLen 10 int16_t a[dataLen]; int16_t b[dataLen]; int main(){ for (int i = 0; i < dataLen; ++i) { a[i] = i * 5; } for (int i = 0; i < dataLen; ++i) { b[i] = 0; } int avl = dataLen; int16_t* ptr_a = a; int16_t* ptr_b = b; for (size_t vl; avl > 0; avl -= vl){ vl = __riscv_vsetvl_e64m1(avl); vint16mf4_t va = __riscv_vle16_v_i16mf4(ptr_a, vl); va = __riscv_vasub_vx_i16mf4(va, 0, __RISCV_VXRM_RDN, vl); //round-down (truncate) __riscv_vse16_v_i16mf4(ptr_b, va, vl); ptr_a += vl; ptr_b += vl; } for(int i=0; i<dataLen; ++i) { if( (int)a[i]/2 != b[i] ) abort(); __builtin_printf("%d ", b[i]); } __builtin_printf("\n"); return 0; } ``` Flag and version info: ``` $ riscv64-unknown-elf-gcc --version gcc () 15.0.0 20241117 (experimental) Copyright (C) 2024 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ riscv64-unknown-elf-gcc -O3 -march=rv64gcv_zvfh -mabi=lp64d -Wno-psabi -static bug.c ``` By saving intermediate files using `-save-temps`, I find there are no instructions to modify `vxrm` register like `csrwi vxrm,2`. The assembly file is uploaded (by snapshot 20241117 at -O3).