[Bug target/117955] New: [15 Regression] GCC generate illegal riscv instruction `vsetvli zero,zero,e64,mf4,ta,ma` with -O2 and -O3

[rvismith1115 at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117955

            Bug ID: 117955
           Summary: [15 Regression] GCC generate illegal riscv instruction
                    `vsetvli zero,zero,e64,mf4,ta,ma` with -O2 and -O3
           Product: gcc
           Version: 15.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: rvismith1115 at gmail dot com
  Target Milestone: ---

Created attachment 59819
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59819&action=edit
reduced testcase

The test case is large and I have tried my best to reduce the case.
In the assembly file I report, line 1405 `vsetvli      
zero,zero,e64,mf4,ta,ma` is illegal. No `e64mf4` in current riscv vector
extension.

command:
```
$ riscv64-unknown-elf-gcc --version
gcc () 15.0.0 20241117 (experimental)
Copyright (C) 2024 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ riscv64-unknown-elf-gcc -O3 -march=rv64gcv_zvfh -mabi=lp64d -Wno-psabi
-static -save-temps bug.c
$ qemu-riscv64 a.out
Illegal instruction (core dumped)
```