Hello all,
Can anyone tell me where i can find the definition of tree.
One structure is typedef-ed to tree. But i cant find that structure.
I have been hunting it for sometime.
Can some one help me.
Thanks in advance.
Regards,
Shafi
Hello all,
During regression tests if i want to disable some features like trampolines i
can give -DNO_TRAMPOLINES
as an compiler flag.
Do i have similar flags for profiling and PIC?
thanks in advance
Regards,
Shafi
Hello all,
For targets which doesn't have simd hardware support like fr30 , simd stuff is
emulated?
Is there some flags/macros in gcc to indicate that?
How is it done in other targets which deosnt have the hardware support?
Thanks in advance
Regards,
Shafi.
target hook TARGET_VECTOR_MODE_SUPPORTED_P hep me to indicate that?
Guess this is the right mailing list for my question.
Thanks in advance.
Regards,
Shafi.
- Original Message
From: Ian Lance Taylor <[EMAIL PROTECTED]>
To: Mohamed Shafi <[EMAIL PROTECTED]>
Cc: gcc@gcc.
hello all,
Sorry i am asking this kind of question.This might be weird to most of you but
i am new to GCC.
Can somebody tell me how to analyze the below instruction pattern
(insn 8 6 9 1 (parallel [
(set (reg/f:SI 32)
(symbol_ref:SI ("t") ))
(clobber (reg:
t;
int main()
{
if (!(t.bit++))
exit (0);
else
abort ();
}
is -1 for my target. Can you explain this?
Thanks in advance.
Regards,
Shafi
- Original Message
From: Rask Ingemann Lambertsen <[EMAIL PROTECTED]>
To: Mohamed Shafi <[EMAIL PROTECTED]>
Cc: gcc@g
> It is because matching has not yet been attempted.
ok.. so what is the option to get hold of a rtl dump after all the matching is
done
- Original Message
From: Rask Ingemann Lambertsen <[EMAIL PROTECTED]>
To: Mohamed Shafi <[EMAIL PROTECTED]>
Cc: gcc@gcc.gnu.org
Hello,
For the code (20020611-1.c)
int p;int k;unsigned int n;
void x ()
{
unsigned int h;//line 1
h = n <= 30; //line 2
// printf("%u\n",h);
if (h)
p = 1;
else
p = 0;
if (h)
k = 1;
else
k = 0;
}
unsigned int n = 30;
ma
Hello all,
Can anybody tell me the purpose of the testcase
testsuite\gcc.dg\special\gcsec-1.c in the gcc testsuite ?
Is it something related with garbage clooection?
What exactly doec this testcase test ?
Thanks in advance.
Regards ,
Shafi.
Hello all,
Can anyone tell me what the below expression means ?
(insn 38 37 40 4 (parallel [
(asm_operands/v ("") ("") 0 [ //line 2
(reg:SI 32 [ s5.1 ])
//line 3
]
[
(asm_input:SI ("r")
Hello all,
Looking at a .md file of a backend it there a way to know whether a
target supports long long
Should i look for patterns with machine mode DI?
Is there some other way?
Thanks in advance for the help.
Regards,
Shafi
:
On Mon, Nov 06, 2006 at 10:52:00AM +0530, Mohamed Shafi wrote:
> Hello all,
>
> Looking at a .md file of a backend it there a way to know whether a
> target supports long long
> Should i look for patterns with machine mode DI?
No. For example, 8-bit, 16-bit and 32-bit targets
On 11/7/06, Mike Stump <[EMAIL PROTECTED]> wrote:
On Nov 6, 2006, at 9:30 PM, Mohamed Shafi wrote:
> My target (non gcc/private one) fails for long long testcases
Does it work flawlessly otherwise, if not, fix all those problems
first. After those are all fixed, then you can see if
Thanks for the input and the questions
Did you examine:
long long l, k;
l = -k;
for correctness by itself? Was it valid or invalid?
Yes this is working.
[ read ahead for spoilers, I'd rather you pull this information out
of the dump and present it to us... ]
A quick glance at th
On 11/10/06, Mike Stump <[EMAIL PROTECTED]> wrote:
On Nov 9, 2006, at 6:39 AM, Mohamed Shafi wrote:
> When i diff the rtl dumps for programs passing negative value with and
> without frame pointer i find changes from file.greg .
A quick glance at the rtl shows that insn 95 tries
First thanks very much for your thoughts
If those two instructions appear for the first time in the .greg dump
file, then they have been created by reload.
Yes they appear for the first time in .greg dump file.
> 1. What could be the reason for this behavior?
I'm really shooting in the da
I'm really shooting in the dark here, but my guess is that you have a
define_expand for movdi that is not reload safe. You can do this
operation correctly, you just have to reverse the instructions: load
a5 from (a4 + 4) before you load a4 from (a4). See, e.g.,
mips_split_64bit_move in mips.c an
From: Markus Franke <[EMAIL PROTECTED]>
To: gcc@gcc.gnu.org
Date: Tue, 05 Dec 2006 21:37:30 +0100
Subject: poisened macro definitions
Dear GCC Developers,
I want to port an existing backend (based on version gcc-2.7.2.3) on the
most recent release (gcc-4.1.1). During compilation process I get
sev
Hello all,
I am building a GCC Compiler. I have some ifdef checks in the compiler
source code. In case i define a symbolic literal in command line while
compiling a sample program, I want that set of statements to be
invoked after ifdef checks.
e.g.
GCC Source:
#ifdef SHAFI_DEBUG
printf("\n Shaf
Hello all,
In arithmetic expressions we need to conversion when the operands are
of different data types.
In gcc 4.1.1 where is this process started?
Is this in c-typeck.c, particularly in the function c_common_type ?
Thanks in advance,
Regards,
Shafi.
Hello all,
I added few testcases to the existing testsuite in gcc 4.1.1 for a
private target.
After running the testsuite i found out that all my test cases with
scan-tree-dump testing failed for one particular situation.
The values are scanned from gimple tree dump and its fails for cases like
Hello all,
I would like to know if there is any way to control the gcc driver
program to pass a default option to the assembler if no option/switch
is given.
say
-march=arch1
if no -march option is provided by the user.
The macro TARGET_OPTION_TRANSLATE_TABLE does something like this but
with t
Hello all,
Looking at the internals i couldn't find an answer for my problem.
I have a define_expand with the pattern name mov and a
define_insn mov_store
The predicate in define_expand is general_operand, so that all
operands are matched.
While in define_insn i have a predicate which allows onl
hello everyone,
I have the following 2 patterns which are consecutive. (from shorten
rtl dump file)
(insn 69 34 70 (set (reg:SQ 0 d0)
(reg:SQ 18 f2)) 79 {movsq} (nil)
(nil))
(insn 70 69 35 (set (reg:SQ 16 f0 [orig:38 D.3693 ] [38])
(reg:SQ 0 d0)) 79 {movsq} (nil)
(nil))
Fo
On 4/12/07, Andreas Schwab <[EMAIL PROTECTED]> wrote:
"Mohamed Shafi" <[EMAIL PROTECTED]> writes:
> hello everyone,
>
> I have the following 2 patterns which are consecutive. (from shorten
> rtl dump file)
>
> (insn 69 34 70 (set (reg:SQ 0 d0)
>
hello all,
Depending on the machine mode the compiler will generate automatically
the offset required for the stack operation i.e for a machine with
word size is 32, for char type the offset is 1, for int type the
offset is 2 and so on..
Is there a way to control this ? i mean say for long long
On 4/16/07, J.C. Pizarro <[EMAIL PROTECTED]> wrote:
2007/4/16, Mohamed Shafi <[EMAIL PROTECTED]>:
> hello all,
>
> Depending on the machine mode the compiler will generate automatically
> the offset required for the stack operation i.e for a machine with
> word si
On 4/16/07, J.C. Pizarro <[EMAIL PROTECTED]> wrote:
2007/4/16, Mohamed Shafi <[EMAIL PROTECTED]> wrote:
> > > Depending on the machine mode the compiler will generate automatically
> > > the offset required for the stack operation i.e for a machine with
> >
Hi all,
I am trying to port a private target in GCC 4.5.1. Following are the
properties of the target
#define BITS_PER_UNIT 32
#define BITS_PER_WORD32
#define UNITS_PER_WORD 1
#define CHAR_TYPE_SIZE32
#define SHORT_TYPE_SIZE 32
#define INT_TYPE_SIZE
On 10 February 2011 15:57, Richard Guenther wrote:
> On Thu, Feb 10, 2011 at 6:23 AM, Mohamed Shafi wrote:
>> Hi all,
>>
>> I am trying to port a private target in GCC 4.5.1. Following are the
>> properties of the target
>>
>> #define BITS_PER_UNIT
On 10 February 2011 17:16, Richard Guenther wrote:
> On Thu, Feb 10, 2011 at 12:42 PM, Mohamed Shafi wrote:
>> On 10 February 2011 15:57, Richard Guenther
>> wrote:
>>> On Thu, Feb 10, 2011 at 6:23 AM, Mohamed Shafi wrote:
>>>> Hi all,
>>>>
Hello all,
I am porting GCC 4.5.1 for a private target. For one particular test
reloading pass is being asked to reload the following instruction:
(insn 45 175 46 11 pr20601-1.c:90 (set (reg/f:PQI 3 g3 [70])
(mem/f:PQI (pre_inc:PQI (reg/f:PQI 1 g1 [orig:55 prephitmp.16
] [55])) [2 S1 A32]
On 11 February 2011 15:28, Paulo J. Matos wrote:
>
>
> On 11/02/11 09:46, Mohamed Shafi wrote:
>>
>> How can i overcome this failure? Can some one suggest a solution?
>>
>
>
> Have you defined TARGET_LEGITIMATE_ADDRESS_P and also BASE_REG_CLASS
> corr
Hi all,
I am trying to add support for hardware loops for a 32bit target. In
the target QImode is 32bit. The loop counter used in hardware loop
construct is 17bit address registers. This is represented using
PQImode. Since mode for the doloop pattern is found out after loop
discovery it need not b
Hi,
I am doing a private port in GCC 4.5.1. For the my target i see some
strange behavior in delay slot scheduling. For my target the
instruction in the delay slots gets executed irrespective of whether
the branch is taken or not. I have generated the following code after
commenting out the call t
On 6 September 2011 20:50, Jeff Law wrote:
>
> On 09/06/11 08:46, Mohamed Shafi wrote:
>> Hi,
>>
>> I am doing a private port in GCC 4.5.1. For the my target i see some
>> strange behavior in delay slot scheduling. For my target the
>> instruction in the delay
Hi,
I am working on a 32bit private target which has the following restriction
1. store/load can happen only through a general purpose register (GP_REGS)
2. base register should be an address register (AD_REGS)
3. moves between GP_REGS and AD_REGS can happen only through PT_REGS
In a PRE_MODIFY
Hello all,
I am doing a port for a private target in GCC 4.4.0. It generates code
for both little & big endian.
The ABI for the target is as follows:
1. All arguments passed in stack are passed using their alignment constrains.
Solution: For this to happen no argument promotion should be done.
Hello all,
Is it possible to emit a assembler directive at the end of each sections?
Say like section_end
Is there any support for doing something like this in the back-end files?
Or should i need to the make changes in the gcc sources?
Is so do does anyone know in which function it should happen?
Hello all,
The change logs says that current_function_outgoing_args_size is no
more available. But it doesnt say with what it is replaced. Looking at
the other targets i find that its replaced with some field in a
structure crtl. Where is this defined/declared.
I am working in GCC 4.4.0. I checke
2009/7/18 Ian Lance Taylor :
> Mohamed Shafi writes:
>
>> The change logs says that current_function_outgoing_args_size is no
>> more available. But it doesnt say with what it is replaced. Looking at
>> the other targets i find that its replaced with some field in a
>
2009/7/18 Dave Korn :
> Mohamed Shafi wrote:
>> Hello all,
>>
>> Is it possible to emit a assembler directive at the end of each sections?
>> Say like section_end
>> Is there any support for doing something like this in the back-end files?
>> Or should i need
2009/8/1 Dave Korn :
> Mohamed Shafi wrote:
>> I am looking for adding something to the end of each section in the
>> generated .s file. Using TARGET_ASM_NAMED_SECTION i will be able to
>> keep track of the sections that are being emitted. But from
>> TARGET_ASM_FILE_
2009/8/1 Dave Korn :
> Mohamed Shafi wrote:
>> 2009/8/1 Dave Korn :
>>> Mohamed Shafi wrote:
>>>> I am looking for adding something to the end of each section in the
>>>> generated .s file. Using TARGET_ASM_NAMED_SECTION i will be able to
>>>>
Hello all,
I am doing a private port in GCC 4.4.0. For my target the following
are the alignment requirements:
int - 4 bytes
short - 2 bytes
char - 1 byte
pointer - 4 bytes
stack pointer - 4 bytes
i am not able to implement the alignment for short.
The following is are the macros that i used fo
2009/8/3 Jim Wilson :
> On 08/03/2009 02:14 AM, Mohamed Shafi wrote:
>>
>> short - 2 bytes
>> i am not able to implement the alignment for short.
>> The following is are the macros that i used for this
>> #define PARM_BOUNDARY 8
>> #define STACK_BOUNDAR
2009/8/5 Jim Wilson :
> On Tue, 2009-08-04 at 11:09 +0530, Mohamed Shafi wrote:
>> >> i am not able to implement the alignment for short.
>> >> The following is are the macros that i used for this
>> >> #define PARM_BOUNDARY 8
>> >> #define STACK
Hello all,
I am trying to port a 32bit target in GCC 4.4.0
Of the addressing modes that are allowed by my target the one with
(base register + offset) is restrictive in QImode.
The restriction is that if the base register is not Stack Pointer then
this kind of address cannot come in a load instruc
2009/7/3 Ian Lance Taylor :
> Mohamed Shafi writes:
>
>> I just want to know about the feasibility of implementing an
>> instruction for a port in gcc 4.4
>> The target has 40 bit register where the normal load/store/move
>> instructions will be able to access t
HI,
I am trying to port a 32bit target in GCC 4.4.0. My target supports
big and little endian. This is selected using a target switch. So i
have defined the macro
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
Currently i have written pattens only for SImode moves. So GCC will
synthesize DImode pa
2009/7/16 Richard Henderson :
> On 07/13/2009 07:35 AM, Mohamed Shafi wrote:
>>
>> So i made both TARGET_STRICT_ARGUMENT_NAMING and
>> PRETEND_OUTGOING_VARARGS_NAMED to return false. Is this correct?
>
> Yes.
>
>> How to make the varargs argument to be p
Hello all,
I am trying to port a 32bit arch in GCC 4.4.0. My target has support
for 1bit, 2bit shift and add operations. I tried to write patterns for
this , but gcc is not generating those. The following are the patterns
that i have written in md file:
(define_insn "shift_add_"
[(set (match_ope
Hello all,
I am doing a port for a 32bit target in GCC 4.4.0. Of the addressing
modes that are allowed by my target the one with (base register +
offset) is restrictive in QImode. The restriction is that if the base
register is not Stack Pointer then this kind of address cannot come in
a load inst
Hi all,
I am doing a GCC port for a 32bit target in GCC 4.4.0. The target uses
hand coded floating point compare routines. Generally the function
returns the values in the general purpose registers. But these fp cmp
routines return the result in the Status Register itself. So there is
no need to
Hello all,
I am doing a port for a 32bit target in GCC 4.4.0. I have to support a
40bit data (_Accum) in the port. The target has 40bit registers which
is a GPR and works as 32bit reg in other modes. The load and store for
_Accum happens in two step. The lower 32bit in one instruction and the
uppe
Hello all,
I am porting a 32bit target in GCC 4.4.0
The target has have distinct signed and unsigned compare instructions,
and only one set of conditional branch instructions. Moreover the
operands cannot be immediate values if the comparison is unsigned. I
have implemented this using compare-and-
I am doing a port for a 32bit target in GCC 4.4.0
I am getting segmentation fault in the function assign_temp in the
following line:
if (DECL_P (type_or_decl))
After analyzing the issue i find that this might be a bug. I just want
to confirm if that is the case or not.
In order to reproduce i thi
Hello all,
I doing a port for a 32bit target for GCC 4.4.0. I am getting the
following error:
rd_er.c:19: error: insn does not satisfy its constraints:
(insn 5 35 34 2 rd_er.c:8 (set (reg:SI 16 r0)
(plus:SI (reg:SI 16 r0)
(reg:SI 2 d2))) 57 {addsi3} (expr_list:REG_EQUAL (plus:
Hello all,
I am doing a port for a 32bit target in GCC 4.4.0.
I have defined memory_constraints in predicates.c like this
(define_memory_constraint "Sr0"
"Memory refrence through base registers"
(match_test "target_mem_constraint (\"r0\", op)"))
In the function target_mem_constraint i have
2009/9/30 Richard Henderson :
> On 09/29/2009 07:32 AM, Mohamed Shafi wrote:
>>
>> My question is my definition of strict correct?
>> or should it be reload_in_progress || reload_completed?
>
> I'm tempted to say it should be the later, but I'm not sure i
2009/9/30 Richard Henderson :
> On 09/29/2009 09:46 PM, Mohamed Shafi wrote:
>>
>> bool strict = reload_completed ? true : false;
>
> What happens if you set "strict = false" here?
> That's what ARM does.
That particular case works, and yes arm does
2009/9/28 Richard Henderson :
> On 09/28/2009 07:25 AM, Mohamed Shafi wrote:
>>
>> Hope someone suggests me a solution.
>
> The solution is almost certainly something involving the
> TARGET_SECONDARY_RELOAD hook. You need to inform reload that it's going to
> need
2009/9/14 Richard Henderson :
> On 09/14/2009 07:24 AM, Mohamed Shafi wrote:
>>
>> Hello all,
>>
>> I am doing a port for a 32bit target in GCC 4.4.0. I have to support a
>> 40bit data (_Accum) in the port. The target has 40bit registers which
>> is a GPR and
HI all,
I am porting GCC 4.4.0 for a 32bit target. The target has 40bit data
registers and 32bit address registers that can be used as general
purpose registers. When 40bit registers are used for arithmetic
operations or comparison operations GCC generates code assuming that
its a 32bit register.
Hi,
The internal doc says :
— Target Hook: bool TARGET_CAN_INLINE_P (tree caller, tree callee)
This target hook returns false if the caller function cannot
inline callee, based on target specific information. By default,
inlining is not allowed if the callee function has function specific
ta
2009/9/14 Richard Henderson :
> Another thing to look at, since you have hand-written routines and may be
> able to specify that e.g. only a subset of the normal call clobbered
> registers are actually modified, is to leave the call as a "compare" insn.
> Something like
>
> (define_insn "*cmpsf"
>
Hi,
I am doing a port for a 32bit target in GCC 4.4.0. The target does not
have support for symbolic address in QImode for load operations. In
order to do this what i have done is in define_expand for moveqi
reject symbolic address it they come in source operands and i have
also written a predicat
2009/10/22 Richard Henderson :
> On 10/21/2009 07:25 AM, Mohamed Shafi wrote:
>>
>> For accessing a->b GCC generates the following code:
>>
>> move.l (sp-16), d3
>> lsrr.l #<16, d3
>> move.l (sp-12),d2
>> asll #&
2009/10/30 Jeff Law :
> On 10/30/09 07:13, Mohamed Shafi wrote:
>>
>> Hi,
>>
>> I am doing a port for a 32bit target in GCC 4.4.0. The target does not
>> have support for symbolic address in QImode for load operations.
>
> You'll need to make
2009/10/30 Ian Lance Taylor :
> Mohamed Shafi writes:
>
>>>From ice4.c.168r.asmcons
>>
>> (insn 5 2 6 2 ice4.c:4 (set (reg:SI 61 [ s ])
>> (mem/c/i:SI (symbol_ref:SI ("s") [flags 0x2] > 0xb7bfd000 s>) [0 s+0 S4 A32])) 2 {*movsi_internal} (n
2009/11/6 Richard Henderson :
> On 11/06/2009 05:29 AM, Mohamed Shafi wrote:
>>
>> The target that i am working on has 1& 2 bit shift-add patterns.
>> GCC is not generating shift-add patterns when the shift count is 1. It
>> is currently generating add ope
2009/11/6 Ian Lance Taylor :
> Mohamed Shafi writes:
>
>> It is generating with data registers. Here is the pattern that i have
>> written:
>>
>>
>> (define_insn "*saddl"
>> [(set (match_operand:SI 0 "register_operand" "=r,d&quo
2009/10/22 Richard Henderson :
> On 10/21/2009 07:25 AM, Mohamed Shafi wrote:
>>
>> For accessing a->b GCC generates the following code:
>>
>> move.l (sp-16), d3
>> lsrr.l #<16, d3
>> move.l (sp-12),d2
>> asll #&
Hello all,
I am doing a port for a 32bit target in GCC 4.4.0. In my target 32bit
multiply instruction is carried out in two instructions.
Dn = Da x Db is executed as
Dn = (Da.L * Db.H + Da.H * Db.L) << 16
Dn = Dn + (Da.L * Db.L)
Currently the pattern that i have for this is as follows:
(define
2009/11/10 Richard Henderson :
> On 11/10/2009 05:48 AM, Mohamed Shafi wrote:
>>
>> (define_insn "mulsi3"
>> [(set (match_operand:SI 0 "register_operand" "=&d")
>> (mult:SI (match_operand:SI 1 "register_operand&
Hello all,
I am porting GCC 4.4.0 for a 32bit target. The target has 40bit data
registers and 32bit address register. Both can be used as general
purpose registers. All load and store operations are 32bit. If 40bit
data register is involved in load/sore the register gets sign
extended. Whenever th
2009/12/18 Hans-Peter Nilsson :
> On Fri, 20 Nov 2009, Mohamed Shafi wrote:
>> I tried implementing the suggestion given by Richard, but got into
>> issues. The GCC frame work is written assuming that there are no modes
>> with HOST_BITS_PER_WIDE_INT < GET
Hi all,
I am doing a port in GCC 4.4.0 for a 32 bit target. As a part of
scheduling framework i have to write the move patterns with more
clarity, so that i could control the scheduling with the help of
attributes. Re-writting the pattern resulted in movsi pattern with 41
alternatives :( When i s
2009/12/22 Richard Earnshaw :
>
> On Mon, 2009-12-21 at 18:44 +, Paul Brook wrote:
>> > > > I am doing a port in GCC 4.4.0 for a 32 bit target. As a part of
>> > > > scheduling framework i have to write the move patterns with more
>> > > > clarity, so that i could control the scheduling with th
Hello all,
I am doing a port for a 32bit a target in GCC 4.4.0. The target
supports (base + offset) addressing mode for QImode store instructions
but not for QImode load instructions. GCC doesn't take the middle
path. It either supports an addressing mode completely and doesn't
support at all. I t
2010/1/22 Richard Henderson :
> On 01/21/2010 06:22 AM, Mohamed Shafi wrote:
>>
>> Hello all,
>>
>> I am doing a port for a 32bit a target in GCC 4.4.0. The target
>> supports (base + offset) addressing mode for QImode store instructions
>> but not for QIm
Hi all,
I am doing a port of a 32bit target in GCC 4.4.0. I have written the
macro legitimize_reload_address which does something similar to what
the target pa does. i.e
For the PA, transform:
memory(X + )
into:
if ( & mask) >= 16
Y = ( & ~mask) + mask + 1 Roun
Hi,
I am doing a port for a 32bit target in GCC 4.4.0. I need a way to
identify that a register is part of a multiword register. I need to
emit an instruction that works on LSW of the double word register on
move instructions. Currently the target splits the DImode and DFmode
moves after reloading
Hi all,
Does GCC support architectures that has Variable Length Execution Set (VLES)?
Are there any developments happening in this direction?
Regards,
Shafi
2009/5/27 Ian Lance Taylor :
> Mohamed Shafi writes:
>
>> Does GCC support architectures that has Variable Length Execution Set (VLES)?
>> Are there any developments happening in this direction?
>
> gcc supports many instruction sets whose instructions are not all the
&g
Hello all,
I just want to know about the feasibility of implementing an
instruction for a port in gcc 4.4
The target has 40 bit register where the normal load/store/move
instructions will be able to access the 32 bits of the register. In
order to move data into the rest of the register [b32 to b39
Hello all,
The GCC 4.4.0 internal says :
[Macro] CALL_REALLY_USED_REGISTERS
Like CALL_USED_REGISTERS except this macro doesn’t require that the
entire set of
FIXED_REGISTERS be included. (CALL_USED_REGISTERS must be a superset of FIXED_
REGISTERS). This macro is optional. If not specifed, it defau
Hello all,
I am trying to port GCC 4.5.1 for a processor that has the following
addressing capability:
The data memory address space of 64K bytes is represented by a total
of 15 bits, with each address selecting a 16-bit element. When using
the address register, the LSB of address reg (AD) points
Hello all,
I am trying to do a port on GCC 4.5. The target has a memory
resolution of 32bits i.e. char is 32bits in the target (addr 0 selects
1st 32bit and addr 1 selects 2nd 32bit). It has only word (32bit)
access.
In terms of address resolution this target is similar to c4x which
became obsole
Hi,
I am doing a port in GCC 4.5.1. For the port
1. there is only (reg + offset) addressing mode only when reg is SP.
Other base registers are not allowed
2. FP cannot be used as a base register. (FP based addressing is done
by copying it into a base register)
In order to take advantage of FP el
On 29 October 2010 00:06, Joern Rennecke wrote:
> Quoting Mohamed Shafi :
>
>> Hi,
>>
>> I am doing a port in GCC 4.5.1. For the port
>>
>> 1. there is only (reg + offset) addressing mode only when reg is SP.
>> Other base registers are not allowed
>&
On 30 October 2010 05:45, Joern Rennecke wrote:
> Quoting Mohamed Shafi :
>
>> On 29 October 2010 00:06, Joern Rennecke
>> wrote:
>>>
>>> Quoting Mohamed Shafi :
>>>
>>>> Hi,
>>>>
>>>> I am doing a port in GCC 4
Hi all,
I need a opinion on a design front. I am doing a port for a private
target in GCC 4.5.1. We are also in the process of designing the
hardware along with the development of the build tools. Currently we
don't have enough bits in the encoding to support conditional
instruction like arm does.
Hi,
For a private target that i am porting in GCC 4.5 I have the following
pattern in my md file for call value:
(define_insn "call_value_op"
[(set (match_operand 0 "register_operand" "=da")
(call (mem:QI (match_operand:QI 1 "call_operand" "Wd"))
(match_operand:QI 2 "" ""
On 12 November 2010 18:39, Joern Rennecke wrote:
> Quoting Mohamed Shafi :
>
>> So i have the following questions:
>>
>> 1. Why is that constraints are not matched here?
>
> Please read the node "Register Classes" in doc/tm.texi .
>
I am sorry , coul
On 30 October 2010 05:45, Joern Rennecke wrote:
> Quoting Mohamed Shafi :
>
>> On 29 October 2010 00:06, Joern Rennecke
>> wrote:
>>>
>>> Quoting Mohamed Shafi :
>>>
>>>> Hi,
>>>>
>>>> I am doing a port in GCC 4
Hi,
I am doing a port in GCC 4.5.1.
The target supports storing immediate values into memory location
represented by a symbolic address. So in the move pattern i have given
constraints to represent this.
(define_insn "movqi_op"
[(set (match_operand:QI 0 "nonimmediate_operand" "=!Q,!Q,d,d,d,d,d,
On 20 December 2010 10:56, Jeff Law wrote:
> On 12/15/10 07:14, Mohamed Shafi wrote:
>>
>> Hi,
>>
>> I am doing a port in GCC 4.5.1.
>> The target supports storing immediate values into memory location
>> represented by a symbolic address. So in the move
On 20 December 2010 19:30, Jeff Law wrote:
> On 12/20/10 01:47, Mohamed Shafi wrote:
>>
>>
>>> I think this is a case where you're going to need a secondary reload to
>>> force the immediate into a register if the destination is a non-symbolic
>>>
Hello everyone,
I am upgrading a cross compiler from 3.2 to 3.4.6
I had to change some of the TARGET description macros
in target.h file
for otherwise while building i am getting "attempt to
use poisoned" errors
Presently what is written in target.h is
1. #define CPP_PREDEFINES \
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