[PATCH] D43189: [DebugInfo] Avoid name conflict of generated VLA expression variable.

sdesmalen created this revision. sdesmalen added reviewers: CarlosAlbertoEnciso, probinson, aprantl. Herald added a subscriber: JDevlieghere. This patch also adds the 'DW_AT_artificial' flag to the generated variable. https://reviews.llvm.org/D43189 Files: lib/CodeGen/CGDecl.cpp test/CodeGe

[PATCH] D33893: Align definition of DW_OP_plus with DWARF spec [2/3]

sdesmalen created this revision. Herald added a subscriber: aprantl. This patch is part of 3 patches that together form a single patch, but must be introduced in stages in order not to break things.   The way that LLVM interprets DW_OP_plus in DIExpression nodes is basically that of the DW_OP_pl

[PATCH] D41698: [DebugInfo] Enable debug information for C99 VLA types

sdesmalen created this revision. sdesmalen added reviewers: echristo, aprantl, dexonsmith, clayborg, pcc, kristof.beyls. Herald added a subscriber: JDevlieghere. This patch enables debugging of C99 VLA types by generating more precise LLVM Debug metadata, using the extended DISubrange 'count' fie

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen created this revision. sdesmalen added reviewers: ributzka, rjmccall, rnk, aaron.ballman. Herald added subscribers: arphaman, kristof.beyls, javed.absar. This is the Clang patch to complement the following LLVM patches: https://reviews.llvm.org/D51477 https://reviews.llvm.org/D51479

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen added inline comments. Comment at: lib/CodeGen/CGDebugInfo.cpp:1101 case CC_AAPCS: + case CC_AArch64VectorCall: return llvm::dwarf::DW_CC_LLVM_AAPCS; I wasn't really sure whether this requires a corresponding DW_CC_LLVM_AAVPCS record in LLVM,

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen marked an inline comment as done. sdesmalen added inline comments. Comment at: include/clang/Basic/Attr.td:1792 + let Spellings = [GNU<"aarch64_vector_pcs">, + CXX11<"clang", "aarch64_vector_pcs">, + Keyword<"__aarch64_vector_pcs">,

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen updated this revision to Diff 173831. sdesmalen added a comment. - Removed `_aarch64_vector_pcs` and `__aarch64_vector_pcs` keywords in favour of supporting only `__attribute__(aarch64_vector_pcs))`. https://reviews.llvm.org/D54425 Files: include/clang-c/Index.h include/clang/Bas

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen updated this revision to Diff 174574. sdesmalen marked an inline comment as done. sdesmalen added a comment. Thanks all for the suggestions and comments! I've updated the patch with a better description of the attribute's behaviour (thanks @rjmccall for the starting point!) and added S

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen added a subscriber: keith.walker.arm. sdesmalen added inline comments. Comment at: lib/CodeGen/CGDebugInfo.cpp:1101 case CC_AAPCS: + case CC_AArch64VectorCall: return llvm::dwarf::DW_CC_LLVM_AAPCS; rjmccall wrote: > rnk wrote: > > sdesmalen wro

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen added a comment. Just to double check before committing, @aaron.ballman are you happy with the tests? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D54425/new/ https://reviews.llvm.org/D54425 ___ cfe-commits mailing list cfe-commi

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

sdesmalen updated this revision to Diff 175236. sdesmalen added a comment. - resolved editorial comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D54425/new/ https://reviews.llvm.org/D54425 Files: include/clang-c/Index.h include/clang/Basic/Attr.td include/clang/Basic/AttrDo

[PATCH] D64739: [SVE][Inline-Asm] Add support to clang for SVE inline assembly

sdesmalen added a comment. Functionally the patch looks good, but the title suggests this adds full inline-asm support for SVE (which would require the ACLE types proposed in D62960 , as well as other changes), where this patch only adds support to specify SVE r

[PATCH] D64739: [SVE][Inline-Asm] Add support to specify SVE registers in the clobber list

sdesmalen added inline comments. Comment at: clang/test/CodeGen/aarch64-sve-inline-asm.c:1 +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -target-feature +sve -o - %s | FileCheck %s + rovka wrote: > Can you also add a test without +sve, to make su

[PATCH] D64739: [SVE][Inline-Asm] Add support to specify SVE registers in the clobber list

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D64739/new/ https://reviews.llvm.org/D64739 ___ cfe-commits mailing list cfe-com

[PATCH] D65404: [AArch64] Disable __ARM_FEATURE_SVE without ACLE.

sdesmalen created this revision. sdesmalen added reviewers: c-rhodes, chill, rengolin, rovka. Herald added subscribers: kristof.beyls, tschuett, javed.absar. The Arm C Language Extensions for SVE document specifies that __ARM_FEATURE_SVE should be set when the compiler supports SVE and implements

[PATCH] D65404: [AArch64] Disable __ARM_FEATURE_SVE without ACLE.

sdesmalen added a comment. Thanks, I see your argument for having the feature enabled even when the ACLE is still partially supported. At the moment however, LLVM still only support the assembler/disassembler and inline asm. We'll be working to add support for the ACLE soon, but for now having t

[PATCH] D66302: [SVE][Inline-Asm] Support for SVE asm operands

sdesmalen added a comment. Thanks for this change @kmclaughlin. Comment at: docs/LangRef.rst:3816 +- ``x``: Like w, but restricted to registers 0 to 15 inclusive. +- ``y``: Like w, but restricted to registers 0 to 7 inclusive. I noticed this comment does not

[PATCH] D67549: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & Subdivide4)

sdesmalen added inline comments. Comment at: include/llvm/IR/DerivedTypes.h:500 +default: + assert(0 && "Cannot create narrower fp vector element type"); + break; nit: Use `llvm_unreachable("message")` instead of `assert(0 && "message")` Repositor

[PATCH] D67549: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & Subdivide4)

sdesmalen added a comment. Thanks for the changes @kmclaughlin! Just a few more nits from me, but looks good otherwise. Comment at: include/llvm/IR/DerivedTypes.h:493 +llvm_unreachable("Cannot create narrower fp vector element type"); +break; + } -

[PATCH] D67549: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & Subdivide4)

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. Thanks, LGTM! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67549/new/ https://reviews.llvm.org/D67549 ___ cfe-commits mailing lis

[PATCH] D67830: [AArch64][SVE] Implement punpk[hi|lo] intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM. Looks like a straightforward fix and support for `punpk(hi|lo)` intrinsics. Comment at: llvm/lib/IR/Function.cpp:1213 // If this is a forward reference, d

[PATCH] D53137: Scalable vector core instruction support + size queries

sdesmalen accepted this revision. sdesmalen added a comment. Thanks @huntergr , I think this interface looks really nice. LGTM! Comment at: llvm/include/llvm/IR/DataLayout.h:456 + TypeSize getTypeStoreSize(Type *Ty) const { +auto BaseSize = getTypeSizeInBits(Ty); +retu

[PATCH] D67551: [AArch64][SVE] Implement sdot and udot (lane) intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D67551/new/ https://reviews.llvm.org/D67551 ___ cfe-commits mailing list cfe-com

[PATCH] D69378: [AArch64][SVE] Implement masked store intrinsics

sdesmalen added a comment. Thanks for the changes to the tests. Comment at: llvm/test/CodeGen/AArch64/sve-masked-ldst-trunc.ll:9 +; CHECK-LABEL: masked_trunc_store_nxv2i8: +; CHECK: st1b { [[IN:z[0-9]]].d }, [[PG:p[0-9]]], [x1] + %trunc = trunc %val to I thi

[PATCH] D69567: [AArch64][SVE] Implement additional integer arithmetic intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. Thanks, LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69567/new/ https://reviews.llvm.org/D69567 _

[PATCH] D80740: [SveEmitter] Add SVE ACLE for svld1ro.

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80740/new/ https://reviews.llvm.org/D80740

[PATCH] D84021: [Driver] Add suppoort for -msve-vector-bits=scalable.

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. nit: s/suppoort/support/ (in title) LGTM otherwise! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84021/new/ https://reviews.llvm.org/D840

[PATCH] D84021: [Driver] Add support for -msve-vector-bits=scalable.

sdesmalen added a comment. Still LGTM :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84021/new/ https://reviews.llvm.org/D84021 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.l

[PATCH] D76680: [SveEmitter] Add immediate checks for lanes and complex imms

sdesmalen added a comment. In D76680#1959217 , @SjoerdMeijer wrote: > Looks good to me, but just one question about the tests. If I haven't > overlooked anything, I don't see tests that check the new diagnostics: > "argument should be the value 90 or 27

[PATCH] D76617: [SveEmitter] Fix encoding/decoding of SVETypeFlags

sdesmalen updated this revision to Diff 254832. sdesmalen marked an inline comment as done. sdesmalen added a comment. - Updated encode functions to take/return uint64_t instead of unsigned. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76617/new/ https://reviews.llvm.org/D76617 Files:

[PATCH] D76617: [SveEmitter] Fix encoding/decoding of SVETypeFlags

sdesmalen added inline comments. Comment at: clang/utils/TableGen/SveEmitter.cpp:229 + // Returns the SVETypeFlags for a given value and mask. + unsigned encodeFlag(unsigned V, StringRef MaskName) const { +auto It = FlagTypes.find(MaskName); SjoerdMeijer wr

[PATCH] D76679: [SveEmitter] Add more immediate operand checks.

sdesmalen added a comment. In D76679#1957399 , @SjoerdMeijer wrote: > I think the float16 discussion is an interesting one, but doesn't necessarily > need to be done here. I am asking some questions offline, but if we ever come > to a different opinion

[PATCH] D76617: [SveEmitter] Fix encoding/decoding of SVETypeFlags

sdesmalen updated this revision to Diff 255276. sdesmalen added a comment. Changed `unsigned` -> `uint64_t` for `encodeMemoryElementType` and `encodeMergeType`. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76617/new/ https://reviews.llvm.org/D76617 Files: clang/include/clang/Basic/

[PATCH] D76678: [SveEmitter] Add range checks for immediates and predicate patterns.

sdesmalen updated this revision to Diff 255278. sdesmalen marked 3 inline comments as done. sdesmalen added a comment. - Renamed `ImmCheckPredicatePattern` -> `ImmCheck0_31` - Updated tests. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76678/new/ https://reviews.llvm.org/D76678 Files:

[PATCH] D76680: [SveEmitter] Add immediate checks for lanes and complex imms

sdesmalen updated this revision to Diff 255282. sdesmalen added a comment. - Updated tests. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76680/new/ https://reviews.llvm.org/D76680 Files: clang/include/clang/Basic/DiagnosticSemaKinds.td clang/include/clang/Basic/arm_sve.td clang/

[PATCH] D76678: [SveEmitter] Add range checks for immediates and predicate patterns.

sdesmalen added a comment. In D76678#1963576 , @SjoerdMeijer wrote: > LGTM, please wait a day in case Eli has more comments. Will do, thanks Sjoerd! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76678/new/ https://reviews.llvm.org/D76678 _

[PATCH] D77257: Clean up usages of asserting vector getters in Type

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM! Comment at: clang/lib/CodeGen/CGBuiltin.cpp:5830 BuiltinID == NEON::BI__builtin_neon_vqrdmulhq_lane_v) - RTy = llvm::VectorType::get(Ty->getVectorEl

[PATCH] D77591: [SveEmitter] Explicitly merge with zero/undef

sdesmalen created this revision. sdesmalen added reviewers: SjoerdMeijer, efriedma, rovka. Herald added a subscriber: tschuett. Herald added a project: clang. sdesmalen added a child revision: D77593: [SveEmitter] Implement zeroing of false lanes. Builtins that have the merge type MergeAnyExp or

[PATCH] D76680: [SveEmitter] Add immediate checks for lanes and complex imms

sdesmalen marked 3 inline comments as done. sdesmalen added inline comments. Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:9208 +def err_rotation_argument_to_cmla +: Error<"argument should be the value 0,90,180 or 270">; def warn_neon_vector_initializer_non_po

[PATCH] D76680: [SveEmitter] Add immediate checks for lanes and complex imms

sdesmalen updated this revision to Diff 255500. sdesmalen added a comment. - Addressed comments - added spaces to `0, 90, 180 or 270` CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76680/new/ https://reviews.llvm.org/D76680 Files: clang/include/clang/Basic/DiagnosticSemaKinds.td cla

[PATCH] D77597: [SveEmitter] Add ExpandOp1SVALL and builtin for svptrue

sdesmalen created this revision. sdesmalen added reviewers: SjoerdMeijer, efriedma, rovka. Herald added a subscriber: tschuett. Herald added a reviewer: rengolin. Herald added a project: clang. sdesmalen added a parent revision: D77596: [SveEmitter] Add NoOverload flag and builtin for svpfalse. S

[PATCH] D77595: [SveEmitter] Add NoAuto flag and builtins for svwhile.

sdesmalen created this revision. sdesmalen added reviewers: SjoerdMeijer, efriedma, rovka. Herald added a subscriber: tschuett. Herald added a project: clang. sdesmalen added a parent revision: D77594: [SveEmitter] Add support for _n form builtins. sdesmalen added a child revision: D77596: [SveEmi

[PATCH] D77596: [SveEmitter] Add NoOverload flag and builtin for svpfalse

sdesmalen created this revision. sdesmalen added reviewers: SjoerdMeijer, efriedma, rovka. Herald added a subscriber: tschuett. Herald added a project: clang. sdesmalen added a parent revision: D77595: [SveEmitter] Add NoAuto flag and builtins for svwhile.. sdesmalen added a child revision: D77597

[PATCH] D76238: [SveEmitter] Implement builtins for contiguous loads/stores

sdesmalen added inline comments. Comment at: clang/include/clang/Basic/arm_sve.td:186 +def SVLDFF1 : MInst<"svldff1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad], MemEltTyDefault, "aarch64_sve_ldff1">; +def SVLDFF1SB : MInst<"svldff1sb_{d}", "dPS", "silUsUiUl",

[PATCH] D76617: [SveEmitter] Fix encoding/decoding of SVETypeFlags

This revision was automatically updated to reflect the committed changes. Closed by commit rGf6ea026f179a: [SveEmitter] Fix encoding/decoding of SVETypeFlags (authored by sdesmalen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D76617/new/ https://r

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

sdesmalen added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11621 + if (VT.isFloatingPoint()) { +SDValue LoadChain = SDValue(Load.getNode(), 1); +Load = DAG.getMergeValues( It seems like the LoadChain is lost if VT is of

[PATCH] D76678: [SveEmitter] Add range checks for immediates and predicate patterns.

This revision was automatically updated to reflect the committed changes. Closed by commit rGc8a5b30bac69: [SveEmitter] Add range checks for immediates and predicate patterns. (authored by sdesmalen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D766

[PATCH] D78131: [SVE] Fix unsigned is always >= 0

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM, thanks for fixing @ctetreau! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78131/new/ https://reviews.llvm.org/D78131 ___

[PATCH] D77940: [AArch64] Add NVIDIA Carmel support

sdesmalen added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64.td:607 + FeatureSVE + ]>; + Not sure how accurate the link you referenced is, but it doesn't mention SVE or Crypto ex

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

sdesmalen added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11622 + if (VT.isFloatingPoint()) +Load = DAG.getNode(ISD::BITCAST, DL, VT, Load); + I'd expect this to then use `Load.getValue(0)` ? CHANGES SINCE LAST ACTION h

[PATCH] D77595: [SveEmitter] Add builtins for svwhile

sdesmalen updated this revision to Diff 257829. sdesmalen retitled this revision from "[SveEmitter] Add NoAuto flag and builtins for svwhile." to "[SveEmitter] Add builtins for svwhile". sdesmalen edited the summary of this revision. sdesmalen added a comment. - The function that returns a list o

[PATCH] D78239: [SveEmitter] Add builtins for FP conversions

sdesmalen created this revision. sdesmalen added reviewers: SjoerdMeijer, efriedma. Herald added a subscriber: tschuett. Herald added a project: clang. sdesmalen added a parent revision: D78238: [SveEmitter] Add builtins for svwhilerw/svwhilewr. sdesmalen added a child revision: D77597: [SveEmitte

[PATCH] D77596: [SveEmitter] Add IsOverloadNone flag and builtins for svpfalse and svcnt[bhwd]_pat

sdesmalen updated this revision to Diff 257824. sdesmalen retitled this revision from "[SveEmitter] Add NoOverload flag and builtin for svpfalse" to "[SveEmitter] Add IsOverloadNone flag and builtins for svpfalse and svcnt[bhwd]_pat". sdesmalen edited the summary of this revision. sdesmalen added

[PATCH] D78238: [SveEmitter] Add builtins for svwhilerw/svwhilewr

sdesmalen created this revision. sdesmalen added reviewers: SjoerdMeijer, efriedma. Herald added a subscriber: tschuett. Herald added a project: clang. sdesmalen added a parent revision: D77595: [SveEmitter] Add builtins for svwhile. sdesmalen added a child revision: D78239: [SveEmitter] Add built

[PATCH] D77597: [SveEmitter] Add ExpandOp1SVALL and builtin for svptrue

sdesmalen updated this revision to Diff 257834. sdesmalen added a comment. rebased patch. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D77597/new/ https://reviews.llvm.org/D77597 Files: clang/include/clang/Basic/TargetBuiltins.h clang/include/clang/Basic/arm_sve.td clang/lib/Code

[PATCH] D81252: [SVE ACLE] Remove redundant bool_t typedef.

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81252/new/ https://reviews.llvm.org/D81252 _

[PATCH] D81304: [llvm][SveEmitter] Emit the bfloat version of `svld1ro`.

sdesmalen added a comment. Thanks @fpetrogalli, the changes look good to me. Just added some minor comments. Comment at: clang/include/clang/Basic/AArch64SVEACLETypes.def:63 -SVE_VECTOR_TYPE("__SVFloat16_t", SveFloat16, SveFloat16Ty, 8, 16, true, true) -SVE_VECTOR_TYPE("__SV

[PATCH] D81459: [SveEmitter] Add SVE tuple types and builtins for svundef.

sdesmalen created this revision. sdesmalen added reviewers: c-rhodes, david-arm, ctetreau, efriedma. Herald added a subscriber: tschuett. Herald added a reviewer: rengolin. Herald added a project: clang. This patch adds new SVE types to Clang that describe tuples of SVE vectors. For example `svint

[PATCH] D81462: [SveEmitter] Add builtins for svtbl2

sdesmalen created this revision. sdesmalen added reviewers: david-arm, efriedma, c-rhodes. Herald added a subscriber: tschuett. Herald added a project: clang. sdesmalen added a parent revision: D81459: [SveEmitter] Add SVE tuple types and builtins for svundef.. Repository: rG LLVM Github Monore

[PATCH] D81464: [SveEmitter] Add builtins to insert/extract subvectors from tuples (svget/svset)

sdesmalen created this revision. Herald added subscribers: cfe-commits, tschuett. Herald added a project: clang. sdesmalen added a parent revision: D81459: [SveEmitter] Add SVE tuple types and builtins for svundef.. For example: svint32_t svget4(svint32x4_t tuple, uint64_t imm_index) returns

[PATCH] D81463: [SveEmitter] Add builtins for tuple creation (svcreate2/svcreate3/etc)

sdesmalen created this revision. Herald added a subscriber: tschuett. Herald added a project: clang. sdesmalen added a parent revision: D81459: [SveEmitter] Add SVE tuple types and builtins for svundef.. The svcreate builtins allow constructing a tuple from individual vectors, e.g. svint32x2_t

[PATCH] D80712: [SVE] Add checks for no warnings in SVE tests

sdesmalen added inline comments. Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c:6 +// ASM-NOT: warning #include Just thinking out loud here; we don't need to test for the specific warnings, because LLVM doesn't emit any other warnings a

[PATCH] D81721: [SVE] Ensure proper mangling of ACLE tuple types

sdesmalen created this revision. sdesmalen added reviewers: rsandifo-arm, c-rhodes, efriedma. Herald added subscribers: cfe-commits, psnobl, rkruppe, kristof.beyls, tschuett. Herald added a reviewer: rengolin. Herald added a project: clang. sdesmalen added a parent revision: D81459: [SveEmitter] Ad

[PATCH] D81721: [SVE] Ensure proper mangling of ACLE tuple types

sdesmalen added a comment. See https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#appendix-c-mangling for details on the mangling rules. I thought it would be easier to review if I kept these changes separate from D81459 . Repository: rG

[PATCH] D81459: [SveEmitter] Add SVE tuple types and builtins for svundef.

This revision was automatically updated to reflect the committed changes. Closed by commit rG91a4a592edb0: [SveEmitter] Add SVE tuple types and builtins for svundef. (authored by sdesmalen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81459/new/ h

[PATCH] D81721: [SVE] Ensure proper mangling of ACLE tuple types

This revision was automatically updated to reflect the committed changes. Closed by commit rG98100353d784: [SVE] Ensure proper mangling of ACLE tuple types (authored by sdesmalen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81721/new/ https://rev

[PATCH] D80851: [llvm][SveEmitter] SVE ACLE for quadword permute intrinsics.

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80851/new/ https://reviews.llvm.org/D80851

[PATCH] D81304: [llvm][SveEmitter] Emit the bfloat version of `svld1ro`.

sdesmalen added inline comments. Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c:1 +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -t

[PATCH] D81304: [llvm][SveEmitter] Emit the bfloat version of `svld1ro`.

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM Comment at: clang/include/clang/Basic/AArch64SVEACLETypes.def:44 #define SVE_VECTOR_TYPE(Name, MangledName, Id, SingletonId, NumEls, ElBits, \ -

[PATCH] D81462: [SveEmitter] Add builtins for svtbl2

This revision was automatically updated to reflect the committed changes. Closed by commit rGe51c1d06a992: [SveEmitter] Add builtins for svtbl2 (authored by sdesmalen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81462/new/ https://reviews.llvm.or

[PATCH] D81463: [SveEmitter] Add builtins for tuple creation (svcreate2/svcreate3/etc)

This revision was automatically updated to reflect the committed changes. Closed by commit rG1d7b4a7e5e4a: [SveEmitter] Add builtins for tuple creation (svcreate2/svcreate3/etc) (authored by sdesmalen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D8

[PATCH] D81464: [SveEmitter] Add builtins to insert/extract subvectors from tuples (svget/svset)

This revision was automatically updated to reflect the committed changes. Closed by commit rG4ea8e27a642c: [SveEmitter] Add builtins to insert/extract subvectors from tuples (svget/svset) (authored by sdesmalen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.l

[PATCH] D81304: [llvm][SveEmitter] Emit the bfloat version of `svld1ro`.

sdesmalen added inline comments. Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c:1 +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -t

[PATCH] D82908: [SVE] ACLE: Fix builtins for svdup_lane_bf16 and svcvtnt_bf16_f32_x

This revision was automatically updated to reflect the committed changes. Closed by commit rGf255656a97f7: [SVE] ACLE: Fix builtins for svdup_lane_bf16 and svcvtnt_bf16_f32_x (authored by sdesmalen). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D8290

[PATCH] D83079: [clang] Default target features implied by `-march` on AArch64.

sdesmalen added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:118 + case llvm::AArch64::ArchKind::ARMV8_6A: +Features.push_back("+i8mm"); +Features.push_back("+bf16"); Looking at what Clang emits for e.g. `-march=armv8.5-a`, i

[PATCH] D83079: [clang][aarch64] Generate preprocessor macros for -march=armv8.6a+sve.

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM Comment at: clang/test/Preprocessor/aarch64-target-features.c:415 // CHECK-BFLOAT: __ARM_FEATURE_BF16_VECTOR_ARITHMETIC 1 - nit: unrelated change

[PATCH] D83079: [clang][aarch64] Generate preprocessor macros for -march=armv8.6a+sve.

sdesmalen added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:369 + if (llvm::is_contained(Features, "+v8.6a")) { +if (!llvm::is_contained(Features, "-i8mm") && +!llvm::is_contained(Features, "+noi8mm")) Is this correct an

[PATCH] D83079: [clang][aarch64] Generate preprocessor macros for -march=armv8.6a+sve.

sdesmalen added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:369 + if (llvm::is_contained(Features, "+v8.6a")) { +if (!llvm::is_contained(Features, "-i8mm") && +!llvm::is_contained(Features, "+noi8mm")) fpetrogalli wrote:

[PATCH] D83079: [clang][aarch64] Generate preprocessor macros for -march=armv8.6a+sve.

sdesmalen added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:370 + if (V8_6Pos != std::end(Features)) { +V8_6Pos = Features.insert(std::next(V8_6Pos), "+i8mm"); +V8_6Pos = Features.insert(V8_6Pos, "+bf16"); Both `+i8mm` and `

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

sdesmalen added a comment. In D83553#2145227 , @efriedma wrote: > What's the tradeoff of representing these in IR as vscale'ed vector types, as > opposed to fixed-wdith vector types? If you mean alloca's for single vectors, then that's partly to do with

[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

sdesmalen added inline comments. Comment at: clang/include/clang/Basic/Attr.td:1541 +def ArmSveVectorBits128 : TypeAttr { + let Spellings = []; nit: Can you add a comment saying why these are undocumented (and have no spellings) Comment at:

[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

sdesmalen added inline comments. Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:2806 +def err_attribute_bad_sve_vector_size : Error< + "unsupported SVE vector size '%0'">; +def err_attribute_arm_feature_sve_bits_macro_not_defined : Error< Do you wa

[PATCH] D83079: [clang][aarch64] Generate preprocessor macros for -march=armv8.6a+sve.

sdesmalen added inline comments. Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:370 + if (V8_6Pos != std::end(Features)) { +V8_6Pos = Features.insert(std::next(V8_6Pos), "+i8mm"); +V8_6Pos = Features.insert(V8_6Pos, "+bf16"); sdesmalen wrote: >

[PATCH] D83079: [clang][aarch64] Generate preprocessor macros for -march=armv8.6a+sve.

sdesmalen accepted this revision. sdesmalen added a comment. LGTM again! Comment at: clang/test/Preprocessor/aarch64-target-features.c:163 + +// RUN: %clang -target aarch64-none-linux-gnu -march=armv8.6-a+sve+noi8mm+nobf16+nof32mm -x c -E -dM %s -o - | FileCheck --check-prefi

[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

sdesmalen added inline comments. Comment at: clang/include/clang/Basic/Attr.td:1541 +def ArmSveVectorBits128 : TypeAttr { + let Spellings = []; aaron.ballman wrote: > sdesmalen wrote: > > nit: Can you add a comment saying why these are undocumented (and have n

[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

sdesmalen added inline comments. Comment at: clang/lib/Sema/SemaType.cpp:7784 + // The __ARM_FEATURE_SVE_BITS macro must be defined when using this attribute. + auto &PP = S.getPreprocessor(); + if (!PP.isMacroDefined("__ARM_FEATURE_SVE_BITS")) { efriedma wro

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

sdesmalen added a comment. In D83553#2148429 , @efriedma wrote: > > If you mean alloca's for single vectors > > I was really referring to the IR values themselves, not the memory > representation. Since the width of the vectors is known, you could emit I

[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. Thanks for the changes @c-rhodes, the use of a LANGOPT for this makes sense to me. With my nits addressed, I'm happy with the patch if @aaron.ballman is. Comment at: c

[PATCH] D82141: [sve][acle] Add SVE BFloat16 extensions.

sdesmalen added inline comments. Comment at: clang/include/clang/Basic/arm_sve.td:494 +let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in { + def SVBFDOT : SInst<"svbfdot[_{0}]", "dd$$", "f", MergeNone, "aarch64_sve_bfdot">; + def SVBFMLALB : SInst<"svbfmlalb[_{0}]", "dd

[PATCH] D82178: [AArch64][SVE] Guard svbfloat16_t with feature macro in ACLE

sdesmalen added inline comments. Comment at: clang/utils/TableGen/SveEmitter.cpp:1091 + OS << "#if defined(__ARM_FEATURE_SVE_BF16)\n"; + OS << "typedef __SVBFloat16_t svbfloat16_t;\n"; + OS << "#endif\n\n"; Can you also add an error if `__ARM_FEATURE_SVE_BF16`

[PATCH] D82187: [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores.

sdesmalen created this revision. sdesmalen added reviewers: stuij, efriedma, c-rhodes, fpetrogalli. Herald added subscribers: llvm-commits, lldb-commits, cfe-commits, danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett. Herald added projects: clang, LLDB, LLVM. sdesmalen added a parent

[PATCH] D82187: [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores.

sdesmalen marked 2 inline comments as done. sdesmalen added inline comments. Comment at: clang/include/clang/Basic/AArch64SVEACLETypes.def:69 -SVE_VECTOR_TYPE("__SVBFloat16_t", "__SVBFloat16_t", SveBFloat16, SveBFloat16Ty, 8, 16, false, false, true) +SVE_VECTOR_TYPE("__SVBFloa

[PATCH] D82141: [sve][acle] Add SVE BFloat16 extensions.

sdesmalen added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1345 +: Intrinsic<[llvm_nxv4f32_ty], +[llvm_nxv4f32_ty, + llvm_nxv8bf16_ty, nit: keep this on one line. Repository: rG LLVM Github Monor

[PATCH] D82141: [sve][acle] Add SVE BFloat16 extensions.

sdesmalen accepted this revision. sdesmalen added a comment. This revision is now accepted and ready to land. LGTM Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1811 +def int_aarch64_sve_cvt_bf16f32 : Builtin_SVCVT<"svcvt_bf16_f32_m", llvm_nxv8bf16_ty, llvm_nxv

[PATCH] D82187: [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores.

sdesmalen updated this revision to Diff 272342. sdesmalen added a comment. - Updated RUN line in tests to fix test failures. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82187/new/ https://reviews.llvm.org/D82187 Files: clang/include/clang/Basic/AArch64SVEACLETypes.def clang/inclu

[PATCH] D82298: [AArch64][SVE] Add bfloat16 support to load intrinsics

sdesmalen added inline comments. Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1.c:2-4 +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve -target-featur

[PATCH] D82182: [AArch64][SVE] Add bfloat16 support to perm and select intrinsics

sdesmalen added inline comments. Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c:2 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -

[PATCH] D82187: [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores.

This revision was automatically updated to reflect the committed changes. Closed by commit rG121e585ec8aa: [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores. (authored by sdesmalen). Changed prior to commit: https://reviews.llvm.org/D82187?vs=272342&id=272678#toc Repository: rG LLVM Gi

[PATCH] D82369: [SveEmitter] Add verify-checks to Clang bfloat16 tests

sdesmalen created this revision. sdesmalen added reviewers: c-rhodes, fpetrogalli, kmclaughlin. Herald added a subscriber: tschuett. Herald added a project: clang. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D82369 Files: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bf

[PATCH] D82298: [AArch64][SVE] Add bfloat16 support to load intrinsics

sdesmalen accepted this revision. sdesmalen added a comment. LGTM Comment at: clang/include/clang/Basic/arm_sve.td:275 +let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in { + def SVLD1_BF : MInst<"svld1[_{2}]", "dPc", "b", [IsLoad], MemEltTyDefault, "aarch64_sve_

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