lenary wrote:
NVM about GlobalISel "Inline asm lowering is not supported for this target yet".
https://github.com/llvm/llvm-project/pull/112983
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https://github.com/lenary approved this pull request.
LGTM.
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@@ -2238,6 +2256,17 @@ MVT
RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
return PartVT;
}
+unsigned
+RISCVTargetLowering::getNumRegisters(LLVMContext &Context, EVT VT,
lenary wrote:
This is to prevent an assert that is hit in
`R
https://github.com/lenary edited
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https://github.com/lenary commented:
> Thanks! I just had a detailed look. Given that you have explained almost all
> the code detailedly, I think this PR looks great to me! Just some overall
> comments:
>
> 1. I personally like your proposal of adding new constraints, but we still
> need the
lenary wrote:
I think we shouldn't do this for RVA22, so as not to break existing users of
that profile, who may have a toolchain that doesn't support B.
This change makes sense to me for the RV*23 profiles, especially since your
change to RVM23 has been accepted.
https://github.com/llvm/llvm
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lenary wrote:
Gentle Ping. I'm looking for answers to two questions:
- [Should I] prepare a fixup commit that [uses `MVT::Untyped`] (and removes the
`riscv_*_pair` MVTs), if we think that's a better target-independent approach?
- Any advice on whether I should be digging deeply into changing
https://github.com/lenary closed
https://github.com/llvm/llvm-project/pull/114524
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lenary wrote:
Today's changes address all the CI failures, by adding better checking before
turning BITCAST into `BuildPairF64` or `SplitF64` - the conditions are derived
from the conditions on `setOperationAction(ISD::BITCAST, MVT::i64, Custom)`
before this patch added more of the same.
htt
https://github.com/lenary edited
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https://github.com/lenary ready_for_review
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lenary wrote:
> I haven't made it so if you enable all extensions that constitute Sha, Sha is
> implied.
Great! I think it's most clear if we have "extensions only require things they
are made up of" (i.e. all the implications/requirements point to earlier/lesser
extensions) and "profiles are
lenary wrote:
Sorry I didn't get to this over the weekend. LGTM.
https://github.com/llvm/llvm-project/pull/113942
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lenary wrote:
> > Gentle Ping. I'm looking for answers to two questions:
> >
> > * [Should I] prepare a fixup commit that [uses `MVT::Untyped`] (and removes
> > the `riscv_*_pair` MVTs), if we think that's a better target-independent
> > approach?
>
> I guess so. I didn't know about the Syste
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/112983
>From a63ead48585be1d6aa5e1b78926ede485e76e2f2 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 22 Oct 2024 12:37:48 -0700
Subject: [PATCH 1/5] [RISCV] GPR Pairs for Inline Asm using `Pr`
This patch adds su
@@ -74,7 +74,10 @@ def sub_gpr_odd : SubRegIndex<32, 32> {
}
} // Namespace = "RISCV"
-// Integer registers
+//===--===//
lenary wrote:
I'll do my best to.
https://github.com/llvm/llvm-pro
lenary wrote:
Two comments:
- I don't think the c-api-doc change is going to be accepted at this rate
- One of the nice things about the monorepo is that you can do a Clang+Backend
change like what this requires in a single PR, rather than committing it
bit-by-bit. Seeing the entire change in o
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/112983
>From 0b98a56337d3210e82cac0f509eb7d3d547083f9 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 22 Oct 2024 12:37:48 -0700
Subject: [PATCH] [RISCV] GPR Pairs for Inline Asm using `Pr`
This patch adds suppor
lenary wrote:
The commit I just pushed up should be the final version, and not fundamentally
different from what was reviewed (but with various NFC patches split out).
I think I do have a route towards merging GPRPair and GPRF64Pair, but I'll do
that in a follow-up, as there's a mystery crash
https://github.com/lenary edited
https://github.com/llvm/llvm-project/pull/112983
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lenary wrote:
I'm not sure this requires re-review, so I plan to land this tomorrow (UK time)
if I don't hear anything else.
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@@ -952,14 +952,43 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
ReplaceNode(Node, Res);
return;
}
+ case RISCVISD::BuildGPRPair: {
+SDValue Ops[] = {
+CurDAG->getTargetConstant(RISCV::GPRPairRegClassID, DL, MVT::i32),
+Node->getOperand(0),
+
@@ -74,7 +74,10 @@ def sub_gpr_odd : SubRegIndex<32, 32> {
}
} // Namespace = "RISCV"
-// Integer registers
+//===--===//
lenary wrote:
Landed as
https://github.com/llvm/llvm-project/commit
https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/116094
This is a stacked PR. Just review 716b3d5055e95f161d8e0fc34c802a059266ffc1 (the
prior commit is #112983).
As suggested by @topperc, this tries to merge the two sets of register classes
created in #112983, GPRPa
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/116094
>From 0b98a56337d3210e82cac0f509eb7d3d547083f9 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 22 Oct 2024 12:37:48 -0700
Subject: [PATCH 1/3] [RISCV] GPR Pairs for Inline Asm using `Pr`
This patch adds su
https://github.com/lenary edited
https://github.com/llvm/llvm-project/pull/116094
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@@ -952,14 +952,43 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
ReplaceNode(Node, Res);
return;
}
+ case RISCVISD::BuildGPRPair: {
+SDValue Ops[] = {
+CurDAG->getTargetConstant(RISCV::GPRPairRegClassID, DL, MVT::i32),
+Node->getOperand(0),
+
lenary wrote:
I will rewrite the description of the PR momentarily, once I've rebased over
the cleanup/comments to RISCVRegisterinfo.td
https://github.com/llvm/llvm-project/pull/112983
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https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/112983
>From a63ead48585be1d6aa5e1b78926ede485e76e2f2 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 22 Oct 2024 12:37:48 -0700
Subject: [PATCH 1/7] [RISCV] GPR Pairs for Inline Asm using `Pr`
This patch adds su
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/112983
>From a63ead48585be1d6aa5e1b78926ede485e76e2f2 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 22 Oct 2024 12:37:48 -0700
Subject: [PATCH 1/8] [RISCV] GPR Pairs for Inline Asm using `Pr`
This patch adds su
@@ -21351,6 +21372,17 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
unsigned NumParts, MVT PartVT, std::optional CC) const {
bool IsABIRegCopy = CC.has_value();
EVT ValueVT = Val.getValueType();
+
+ if (ValueVT == (Subtarget.is64Bit() ? MVT::i128 : MVT::i64
https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/114524
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lenary wrote:
> > I think we shouldn't do this for RVA22, so as not to break existing users
> > of that profile, who may have a toolchain that doesn't support B.
> > This change makes sense to me for the RV*23 profiles, especially since your
> > change to RVM23 has been accepted.
>
> For RVA22
https://github.com/lenary edited
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https://github.com/lenary edited
https://github.com/llvm/llvm-project/pull/117987
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@@ -771,9 +772,11 @@ Error RISCVISAInfo::checkDependency() {
return getIncompatibleError("xwchc", "zcb");
}
- if (Exts.count("xqcicsr") != 0 && (XLen != 32)) {
-return getError("'xqcicsr' is only supported for 'rv32'");
- }
+ for (auto Ext : XqciExts)
+if (E
@@ -22,6 +22,28 @@
// Instruction Class Templates
//===--===//
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+class QCILoad_ScaleIdx func4, string opcodestr>
+: RVInstRBase<0b111, OPC_CUSTOM_0,
https://github.com/lenary commented:
The encodings and functionality here are correct, but we're missing a test and
it would be good to add a comment to the scaled store tablegen class.
https://github.com/llvm/llvm-project/pull/117987
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LGTM
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lenary wrote:
Kito and I have agreed `R` is a good way forwards for GPR pairs, and the
c-api-doc PR is approved (but not landed). I'll reword the description/message
to update our constraint choice when I land this, which I hope to get to later
today.
https://github.com/llvm/llvm-project/pul
@@ -203,9 +203,28 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
// Atomic Extensions
+def FeatureStdExtZaamo
+: RISCVExtension<"zaamo", 1, 0,
+ "'Zaamo' (Atomic Memory Operations)">;
+def HasStdExtAOrZaamo
+: Predicate<"Subtarget->hasSt
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https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/116907
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@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
lenary wrote:
I won't be merging this today. Instead, two changes/updates:
- Moving to use `R` instead of `Pr`, because kito pointed out that GCC cannot
use `P` for anything except immediate values (done as a fixup for the moment,
so we can back it out if we're struggling to agree on letters)
-
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/112983
>From 0b98a56337d3210e82cac0f509eb7d3d547083f9 Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Tue, 22 Oct 2024 12:37:48 -0700
Subject: [PATCH 1/3] [RISCV] GPR Pairs for Inline Asm using `Pr`
This patch adds su
@@ -0,0 +1,208 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v -O2 < %s \
+; RUN: | FileCheck %s -check-prefix=RV64I
lenary wrote:
Why is this only testing rv64?
https://github.com/ll
https://github.com/lenary approved this pull request.
LGTM.
I note Craig has questions about the spec, we will ensure those are relayed to
the spec authors, but they don't relate to encoding/assembling problems, so I'm
not sure if they should block landing this.
https://github.com/llvm/llvm-p
@@ -0,0 +1,87 @@
+//===-- xray_trampoline_riscv32.s --*- ASM
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -0,0 +1,87 @@
+//===-- xray_trampoline_riscv32.s --*- ASM
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
https://github.com/lenary approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/117612
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@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">,
Group,
def mno_save_restore : Flag<["-"], "mno-save-restore">,
Group,
HelpText<"Disable using library calls for save and restore">;
} // let Flags = [TargetSpecific]
+def mload_store_pairs : Flag<["-"]
https://github.com/lenary approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/121752
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https://github.com/lenary approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/110657
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@@ -184,6 +191,37 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
} // Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia"
+let Predicates = [HasVendorXqciac, IsRV32], DecoderNamespace = "Xqciac" in {
+
@@ -184,6 +191,37 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
} // Predicates = [HasVendorXqcia, IsRV32], DecoderNamespace = "Xqcia"
+let Predicates = [HasVendorXqciac, IsRV32], DecoderNamespace = "Xqciac" in {
+
lenary wrote:
> > @rzinsly do you need someone to commit this?
>
> Yes, please.
Please turn off [Keep my email addresses
private](https://github.com/settings/emails) setting in your account. Otherwise
the commit will be from the github hidden email which we don't use in LLVM. See
[LLVM
Disc
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https://github.com/lenary approved this pull request.
LGTM, but please wait for Craig to approve as well.
https://github.com/llvm/llvm-project/pull/119823
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https://github.com/lenary approved this pull request.
I am out of the loop on the discussion in the call today, but I can confirm
this is a correct implementation of Xqcicsr, according to the specification.
https://github.com/llvm/llvm-project/pull/117169
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https://github.com/llvm/llvm-project/pull/124174
This denotes RVC-compatible GPR Pairs, which are used by the Zclsd extension.
C API PR: riscv-non-isa/riscv-c-api-doc#102
>From d26d237f6586b879aab96b5f604e2e85156e778f Mon Sep 17 00:00:00 2001
From: Sam Elliott
https://github.com/lenary updated
https://github.com/llvm/llvm-project/pull/124174
>From d26d237f6586b879aab96b5f604e2e85156e778f Mon Sep 17 00:00:00 2001
From: Sam Elliott
Date: Thu, 23 Jan 2025 10:48:08 -0800
Subject: [PATCH 1/2] [RISCV] Support cR Inline Asm Constraint
This denotes RVC-comp
lenary wrote:
You still have a whitespace change to this file?
https://github.com/llvm/llvm-project/pull/121394
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@@ -238,3 +247,11 @@ void
RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
Policy.OnlyBottomUp = false;
}
}
+
+bool RISCVSubtarget::useLoadStorePairs() const {
+ return UseMIPSLoadStorePairsOpt && HasVendorXMIPSLSP;
+}
lenary wrote:
https://github.com/lenary approved this pull request.
Two tiny issues, but I think I'm happy for this to land.
https://github.com/llvm/llvm-project/pull/121394
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https://github.com/lenary approved this pull request.
Thanks!
https://github.com/llvm/llvm-project/pull/124237
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https://github.com/lenary approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/122256
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https://github.com/lenary approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/121292
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@@ -1448,3 +1448,18 @@ def FeatureTaggedGlobals :
SubtargetFeature<"tagged-globals",
"AllowTaggedGlobals",
"true", "Use an instruction sequence for taking the address of a global "
"that allows a memory tag in the upper address bits">;
+
+def FeatureVendorMIPSCMove
lenary wrote:
Please can you undo these whitespace changes, given you're not really making
changes to this file
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https://github.com/lenary commented:
Some small notes, the one about using RISCVExtension will probably have the
most knock-on work (run both the llvm and the clang test suites after that
change, to see where that info gets to)
https://github.com/llvm/llvm-project/pull/121394
_
@@ -313,6 +313,7 @@ enum OperandType : unsigned {
OPERAND_UIMM8_LSB000,
OPERAND_UIMM8_GE32,
OPERAND_UIMM9_LSB000,
+ OPERAND_UIMM10,
lenary wrote:
Please can you add `CASE_OPERAND_UIMM(10)` to the right place in
`RISCVInstrInfo::verifyInstruction`?
htt
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https://github.com/llvm/llvm-project/pull/132259
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@@ -25,8 +25,8 @@ addi a0, a1, 0
# CHECK: # encoding: [0xe0,0x1f]
addi s0, sp, 1020
-# CHECK: .option arch, -c
-.option arch, -c
+# CHECK: .option arch, -c, -zca
+.option arch, -c, -zca
lenary wrote:
This is because your predicates need a little bit of work,
@@ -856,6 +856,19 @@ void RISCVISAInfo::updateImplication() {
});
}
+ // Add Zcd if C and D are enabled.
+ if (Exts.count("c") && Exts.count("d") && !Exts.count("zcd")) {
+auto Version = findDefaultVersion("zcd");
+Exts["zcd"] = *Version;
+ }
+
+
lenary wrote:
> Is there a reason why these aren't lowercase like the rest?
They match the existing names documented in
https://starfivetech.com/uploads/sifive-interrupt-cookbook-v1p2.pdf - we could
check them in clang case-insensitively, though.
https://github.com/llvm/llvm-project/pull/1324
lenary wrote:
For Info, the last time this was proposed was in 2020:
https://reviews.llvm.org/D79521 - at that time, no vendor extensions had been
accepted upstream, and there was not yet a policy for upstream supporting
vendor extensions.
https://github.com/llvm/llvm-project/pull/132481
https://github.com/lenary created
https://github.com/llvm/llvm-project/pull/132481
This Change adds support for two SiFive vendor attributes in clang:
- "SiFive-CLIC-preemptible"
- "SiFive-CLIC-stack-swap"
These can be given together, and can be combined with "machine", but
cannot be combined w
@@ -378,6 +370,14 @@ def FeatureStdExtZca
"part of the C extension, excluding compressed "
"floating point loads/stores">;
+def FeatureStdExtC
+: RISCVExtension<2, 0, "Compressed Instructions", [FeatureStdExtZca]>,
+ RISCVExte
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https://github.com/lenary approved this pull request.
LGTM, with one comment.
https://github.com/llvm/llvm-project/pull/132259
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https://github.com/lenary approved this pull request.
LGTM. Thanks Harsh!
https://github.com/llvm/llvm-project/pull/132184
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@@ -230,10 +230,16 @@ bool PEI::runOnMachineFunction(MachineFunction &MF) {
// with stack arguments.
TFI->spillFPBP(MF);
+ LLVM_DEBUG(llvm::dbgs() << "Before calculateCallFrameInfo \n");
lenary wrote:
Oh yeah, oops, lots of it. will remove.
https://gith
@@ -1502,6 +1659,9 @@ void
RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
auto *RVFI = MF.getInfo();
if (RVFI->isPushable(MF) && SavedRegs.test(RISCV::X26))
SavedRegs.set(RISCV::X27);
+
+ // SiFive Preemptible Interrupt Handlers need additional frame en
@@ -1502,6 +1659,9 @@ void
RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
auto *RVFI = MF.getInfo();
if (RVFI->isPushable(MF) && SavedRegs.test(RISCV::X26))
SavedRegs.set(RISCV::X27);
+
+ // SiFive Preemptible Interrupt Handlers need additional frame en
https://github.com/lenary approved this pull request.
https://github.com/llvm/llvm-project/pull/128833
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https://github.com/lenary closed
https://github.com/llvm/llvm-project/pull/128833
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@@ -780,6 +780,14 @@ Error RISCVISAInfo::checkDependency() {
return getIncompatibleError("xwchc", "zcb");
}
+ if (Exts.count("zclsd") != 0) {
+if (XLen != 32)
+ return getError("'zclsd' is only supported for 'rv32'");
+
+if (Exts.count("zcf") != 0)
+
@@ -401,6 +408,14 @@ def FeatureStdExtZcf
"Compressed Single-Precision Floating-Point Instructions",
[FeatureStdExtF, FeatureStdExtZca]>;
+def FeatureStdExtZclsd
+: RISCVExtension<1, 0,
+ "Compressed Load/Store
https://github.com/lenary closed
https://github.com/llvm/llvm-project/pull/131094
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https://github.com/lenary approved this pull request.
LGTM. Thanks!
https://github.com/llvm/llvm-project/pull/131094
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@@ -96,6 +96,21 @@ def simm32 : RISCVOp {
}];
}
+// A 32-bit signed immediate where the least significant bit is zero.
+def simm32_lsb0 : Operand {
+ let ParserMatchClass = SImmAsmOperand<32, "Lsb0">;
+ let PrintMethod = "printBranchOperand";
+ let EncoderMethod = "getImm
@@ -741,6 +750,28 @@ def QC_C_MILEAVERET : QCIRVInst16CI_NONE<0b10100,
"qc.c.mileaveret">;
} // Predicates = [HasVendorXqciint, IsRV32], hasSideEffects = 1
+let Predicates = [HasVendorXqciio, IsRV32] in {
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
+ def QC_OU
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