[PATCH] D43814: [x86][CET] Introduce _get_ssp, _inc_ssp intrinsics

craig.topper added inline comments. Comment at: lib/Headers/cetintrin.h:44 + +static __inline__ void __DEFAULT_FN_ATTRS _inc_ssp(unsigned int __a) { + __builtin_ia32_incsspq(__a); Start a new #ifdef __x86_64__ here that is just for your new intrinsics. That way

[PATCH] D43815: CodeGen tests - typo fixes

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D43815 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D43817: [x86] wbnoinvd intrinsic

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D43817 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D43814: [x86][CET] Introduce _get_ssp, _inc_ssp intrinsics

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Comment at: lib/Headers/cetintrin.h:45 +static __inline__ void __DEFAULT_FN_ATTRS _inc_ssp(unsigned int __a) { + __builtin_ia32_incsspq(__a); +} ---

[PATCH] D41517: mmintrin.h documentation fixes and updates

craig.topper added a comment. I'm happy. https://reviews.llvm.org/D41517 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D44559: [Sema] Wrong width of result of mul operation

craig.topper added a comment. gcc also warns for this short foo(char a) { return a * a; } Despite the fact that the char would be promoted to int, the upper bits are just sign bits and the multiply result still fits in a short. Repository: rC Clang https://reviews.llvm.org/D44559 __

[PATCH] D44559: [Sema] Wrong width of result of mul operation

craig.topper added a comment. Fair point, what is the default signedness of char? FWIW, all these warn in gcc. So they seem to be just checking purely based on the int promotion without any concern for the original size? unsigned short foo(unsigned char a) { return a * a; } signed

[PATCH] D44559: [Sema] Wrong width of result of mul operation

craig.topper added a comment. icc seems to match gcc for those last 4 cases i sent. And MSVC is throwing an odd signed/unsigned mismatch https://godbolt.org/g/s5FUTv Repository: rC Clang https://reviews.llvm.org/D44559 ___ cfe-commits mailing l

[PATCH] D47693: [X86] Use target independent masked expandload and compressstore intrinsics to implement expandload/compressstore builtins.

craig.topper created this revision. craig.topper added reviewers: RKSimon, delena, spatel, GBuella. Herald added a subscriber: cfe-commits. We've had these target independent intrinsics for at least a year and a half. Looks like they do exactly what we need here and the backend already supports

[PATCH] D47724: [X86] Add back _mask, _maskz, and _mask3 builtins for some 512-bit fmadd/fmsub/fmaddsub/fmsubadd builtins.

craig.topper created this revision. craig.topper added reviewers: tkrupa, RKSimon, spatel, GBuella. We recently switch to using a selects in the intrinsics header files for FMA instructions. But the 512-bit versions support flavors with rounding mode which must be an Integer Constant Expression.

[PATCH] D47401: [X86] Rewrite the max and min reduction intrinsics to make better use of other functions and to reduce width to 256 and 128 bits were possible.

craig.topper added a comment. Ping Repository: rL LLVM https://reviews.llvm.org/D47401 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D46541: [CodeGen] Improve diagnostics related to target attributes

craig.topper added inline comments. Comment at: test/CodeGen/target-features-error-2.c:39 __m128d need_avx(__m128d a, __m128d b) { return _mm_cmp_sd(a, b, 0); // expected-error {{'__builtin_ia32_cmpsd' needs target feature avx}} } The 4 compare functions he

[PATCH] D46541: [CodeGen] Improve diagnostics related to target attributes

craig.topper added inline comments. Comment at: test/CodeGen/target-features-error-2.c:39 __m128d need_avx(__m128d a, __m128d b) { return _mm_cmp_sd(a, b, 0); // expected-error {{'__builtin_ia32_cmpsd' needs target feature avx}} } GBuella wrote: > craig.top

[PATCH] D47724: [X86] Add back _mask, _maskz, and _mask3 builtins for some 512-bit fmadd/fmsub/fmaddsub/fmsubadd builtins.

craig.topper updated this revision to Diff 150027. craig.topper added a comment. Add subtract builtins to SemaChecking.cpp Repository: rC Clang https://reviews.llvm.org/D47724 Files: include/clang/Basic/BuiltinsX86.def lib/CodeGen/CGBuiltin.cpp lib/Headers/avx512fintrin.h lib/Sema/Se

[PATCH] D46541: [CodeGen] Improve diagnostics related to target attributes

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D46541 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D47672: [Headers] Add _Interlocked*_HLEAcquire/_HLERelease

craig.topper added a comment. We (Intel) have discussed this a little internally. I'll be responding more shortly. Comment at: lib/Headers/immintrin.h:386 +\**/ +#if defined(__i386__) || defined(__x86_

[PATCH] D47672: [Headers] Add _Interlocked*_HLEAcquire/_HLERelease

craig.topper added a comment. Fair enough, Then I think we should have a #ifdef _MSC_VER around them so they are only available when pretending to be MSVC. I believe intrin.h does that check very early in the file. Repository: rC Clang https://reviews.llvm.org/D47672

[PATCH] D47672: [Headers] Add _Interlocked*_HLEAcquire/_HLERelease

craig.topper added inline comments. Comment at: lib/Headers/immintrin.h:387 +#if defined(__i386__) || defined(__x86_64__) +static __inline__ long __DEFAULT_FN_ATTRS +_InterlockedExchange_HLEAcquire(long volatile *_Target, long _Value) { what is __DEFAULT_FN_ATTRS

[PATCH] D47672: [Headers] Add _Interlocked*_HLEAcquire/_HLERelease

craig.topper added a comment. It looks like gcc implements additional bits that can be passed to _atomic_exchange and friends, __ATOMIC_HLE_ACQUIRE(1 << 16) and __ATOMIC_HLE_RELEASE(1 << 17). Basically they're using bits above bit 16 in the order/memory_model as target specific flags. These con

[PATCH] D45202: [X86] Replacing X86-specific floor and ceil vector intrinsics with generic LLVM intrinsics

craig.topper added a comment. I'm not sure whether we should be doing this here or in InstCombine. @spatel, what do you think? https://reviews.llvm.org/D45202 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mai

[PATCH] D47979: [X86] Lowering Mask Scalar add/sub/mul/div intrinsics to native IR (Clang part)

craig.topper added inline comments. Comment at: lib/CodeGen/CGBuiltin.cpp:9926 +Value *Div = Builder.CreateFDiv(A, B); +llvm::VectorType *MaskTy = llvm::VectorType::get(Builder.getInt1Ty(), + cast(Mask->getType())->getBitWidth());

[PATCH] D47979: [X86] Lowering Mask Scalar add/sub/mul/div intrinsics to native IR (Clang part)

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D47979 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D45616: [X86] Lower _mm[256|512]_cmp[.]_mask intrinsics to native llvm IR

craig.topper added inline comments. Comment at: lib/CodeGen/CGBuiltin.cpp:10071 + // is _MM_FROUND_CUR_DIRECTION + if (cast(Ops[4])->getZExtValue() != 4) +UsesNonDefaultRounding = true; GBuella wrote: > efriedma wrote: > > Given we're ignoring f

[PATCH] D47672: [Headers] Add _Interlocked*_HLEAcquire/_HLERelease

craig.topper added a comment. I'll give the inline assembly a shot. Repository: rC Clang https://reviews.llvm.org/D47672 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D47672: [Headers] Add _Interlocked*_HLEAcquire/_HLERelease

craig.topper updated this revision to Diff 151100. craig.topper added a comment. Inline assembly implementations. https://reviews.llvm.org/D47672 Files: lib/Headers/immintrin.h lib/Headers/intrin.h test/CodeGen/ms-intrinsics.c Index: test/CodeGen/ms-intrinsics.c =

[PATCH] D47672: [Headers] Add _Interlocked*_HLEAcquire/_HLERelease

craig.topper added a comment. FWIW, I found a cfe-dev thread about adding HLE support http://lists.llvm.org/pipermail/cfe-dev/2013-February/028031.html And a bunch of dead patches in phabricator https://reviews.llvm.org/people/revisions/110/ I also spoke to Andi Kleen here at Intel to make sure

[PATCH] D47401: [X86] Rewrite the max and min reduction intrinsics to make better use of other functions and to reduce width to 256 and 128 bits were possible.

craig.topper added a comment. Ping Repository: rL LLVM https://reviews.llvm.org/D47401 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D41168: [X86] Lowering X86 avx512 sqrt intrinsics to IR

craig.topper added inline comments. Comment at: lib/CodeGen/CGBuiltin.cpp:9222 +if (CC != 4) + return nullptr; +Value *A = Builder.CreateExtractElement(Ops[0], (uint64_t)0); What does returning nullptr here do? Comment at: lib/Code

[PATCH] D41168: [X86] Lowering X86 avx512 sqrt intrinsics to IR

craig.topper accepted this revision. craig.topper added a comment. LGTM Repository: rC Clang https://reviews.llvm.org/D41168 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D48187: [Intrinsics] Add/move some builtin declarations in intrin.h to get ms-intrinsics.c to not issue warnings

craig.topper created this revision. craig.topper added a reviewer: rnk. Herald added a reviewer: javed.absar. Herald added a subscriber: kristof.beyls. __ud2 and __int2c were missing declarations entirely. And the bitscans were only under __x86_64__, but they seem to be in BuiltinsARM.def as well

[PATCH] D45616: [X86] Lower _mm[256|512]_cmp[.]_mask intrinsics to native llvm IR

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM with that one comment. Comment at: lib/CodeGen/CGBuiltin.cpp:10070 + +assert(CC < 0x20 && "condition code should be validated by sema checking"); + -

[PATCH] D45616: [X86] Lower _mm[256|512]_cmp[.]_mask intrinsics to native llvm IR

craig.topper added a comment. We should probably just leave them around. Leave a NOTE so they don't get deleted. https://reviews.llvm.org/D45616 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/

[PATCH] D48288: Fix a bug introduced by rL334850

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D48288 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D45616: [X86] Lower _mm[256|512]_cmp[.]_mask intrinsics to native llvm IR

craig.topper requested changes to this revision. craig.topper added inline comments. This revision now requires changes to proceed. Comment at: test/CodeGen/avx-builtins.c:241 // CHECK-LABEL: test_mm_cmp_sd - // CHECK: call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %{{.

[PATCH] D47401: [X86] Rewrite the max and min reduction intrinsics to make better use of other functions and to reduce width to 256 and 128 bits were possible.

craig.topper added a comment. Fast-isel tests were added for previous codegen in r335068 and updated for new codegen in r335071. One addtiional observation I didn't catch before. The epi32 and epu32 min/max intrinsics were doing a 64-bit element extract as the final step previously because the

[PATCH] D48346: [X86] Rewrite the add/mul/or/and reduction intrinsics to make better use of other intrinsics and remove undef shuffle indices.

craig.topper created this revision. craig.topper added a reviewer: RKSimon. Herald added a subscriber: cfe-commits. Similar to what was done to max/min recently. These already reduced the vector width to 256 and 128 bit as we go unlike the original max/min code. Repository: rC Clang https:/

[PATCH] D45616: [X86] Lower _mm[256|512]_cmp[.]_mask intrinsics to native llvm IR

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D45616 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D48346: [X86] Rewrite the add/mul/or/and reduction intrinsics to make better use of other intrinsics and remove undef shuffle indices.

craig.topper updated this revision to Diff 152146. craig.topper added a comment. Change test to -O0 https://reviews.llvm.org/D48346 Files: lib/Headers/avx512fintrin.h test/CodeGen/avx512-reduceIntrin.c Index: test/CodeGen/avx512-reduceIntrin.c ==

[PATCH] D48187: [Intrinsics] Add/move some builtin declarations in intrin.h to get ms-intrinsics.c to not issue warnings

craig.topper added a comment. Ping https://reviews.llvm.org/D48187 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D48448: [X86] Correct the inline assembly implementations of __movsb/w/d/q and __stosw/d/q to mark registers/memory as modified

craig.topper created this revision. craig.topper added reviewers: rnk, echristo. The inline assembly for these didn't mark that edi, esi, ecx are modified by movs/stos instruction. It also didn't mark that memory is modified. This issue was reported to llvm-dev last year http://lists.llvm.org/p

[PATCH] D48462: [X86] Update handling in CGBuiltin to be tolerant of out of range immediates.

craig.topper created this revision. craig.topper added reviewers: chandlerc, RKSimon, spatel. Chandler is working changes that will loosen some of the range checks in SemaChecking to only be warning that can be disabled. This patch adds explicit masking to avoid using the upper bits of immediate

[PATCH] D48462: [X86] Update handling in CGBuiltin to be tolerant of out of range immediates.

craig.topper added inline comments. Comment at: lib/CodeGen/CGBuiltin.cpp:9322 unsigned Index = BuiltinID == X86::BI__builtin_ia32_storelps ? 0 : 1; -llvm::Value *Idx = llvm::ConstantInt::get(SizeTy, Index); -Ops[1] = Builder.CreateExtractElement(Ops[1], Idx, "extrac

[PATCH] D48464: [x86] Teach the builtin argument range check to allow invalid ranges in dead code.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM https://reviews.llvm.org/D48464 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm

[PATCH] D48462: [X86] Update handling in CGBuiltin to be tolerant of out of range immediates.

craig.topper closed this revision. craig.topper added a comment. Committed in r335308, https://reviews.llvm.org/D48462 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D53042: [X86] Remove FeatureRTM from Skylake processor list

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang https://reviews.llvm.org/D53042 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llv

[PATCH] D53042: [X86] Remove FeatureRTM from Skylake processor list

craig.topper added inline comments. Comment at: lib/Basic/Targets/X86.cpp:169 setFeatureEnabledImpl(Features, "mpx", true); if (Kind != CK_SkylakeServer) // SKX inherits all SKL features, except SGX setFeatureEnabledImpl(Features, "sgx", true); l

[PATCH] D53042: [X86] Remove FeatureRTM from Skylake processor list

craig.topper requested changes to this revision. craig.topper added a comment. This revision now requires changes to proceed. But there is definitely at least one test that needs to be updated. @thiagomacieira, can update them or would you like me to? Comment at: lib/Basic/Tar

[PATCH] D53042: [X86] Remove FeatureRTM from Skylake processor list

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D53042 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D53102: Support for the mno-tls-direct-seg-refs flag

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM with that one style comment fixed. Comment at: lib/Driver/ToolChains/Clang.cpp:1743 + if (!Args.hasFlag(options::OPT_mtls_direct_seg_refs, + options::O

[PATCH] D53460: [X86] When checking the bits in cpu_features for function multiversioning dispatcher in the resolver, make sure all the required bits are set. Not just one of them

craig.topper created this revision. craig.topper added reviewers: erichkeane, echristo. The multiversioning code repurposed the code from __builtin_cpu_supports for checking if a single feature is enabled. That code essentially performed (_cpu_features & (1 << C)) != 0. But with the multiversion

[PATCH] D52441: [CodeGen] Update min-legal-vector width based on function argument and return types

craig.topper added a comment. Ping https://reviews.llvm.org/D52441 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D53665: [X86] Add a common-avx512 CPU to match icc's -xCOMMON-AVX512 option

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel. This adds a common-avx512 CPU to target the avx512 features common between skylake-avx512 and knl. This is the clang version of https://reviews.llvm.org/D53663 https://reviews.llvm.org/D53665 Files: include/c

[PATCH] D53665: [X86] Add a common-avx512 CPU to match icc's -xCOMMON-AVX512 option

craig.topper abandoned this revision. craig.topper added a comment. Abandoning after an internal conversation. https://reviews.llvm.org/D53665 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe

[PATCH] D53850: Declares __cpu_model as hidden symbol

craig.topper added inline comments. Comment at: lib/CodeGen/CGBuiltin.cpp:9013 Features, llvm::ConstantInt::get(Int32Ty, FeaturesMask)); return Builder.CreateICmpNE(Bitset, llvm::ConstantInt::get(Int32Ty, 0)); } This code looks to be out of date. It's

[PATCH] D53919: [X86] Don't allow illegal vector types to return by direct value.

craig.topper created this revision. craig.topper added reviewers: efriedma, rnk, echristo. The backend can't lower this correctly and will try to split the return value into multiple registers. This patches forces it to return via memory similar to what was already done for arguments. Fixes PR

[PATCH] D56686: [X86] Make _xgetbv/_xsetbv on non-windows platforms

craig.topper created this revision. craig.topper added reviewers: rnk, RKSimon, spatel. This patch attempts to redo what was tried in r278783, but was reverted. These intrinsics should be available on non-windows platforms with "xsave" feature check. But on Windows platforms they shouldn't have

[PATCH] D56686: [X86] Make _xgetbv/_xsetbv on non-windows platforms

craig.topper updated this revision to Diff 181672. craig.topper added a comment. Remove guard from include of xsaveintrin.h. We can't have any check because we need it to always include on non-windows platforms due to target attribute. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D56686

[PATCH] D56686: [X86] Make _xgetbv/_xsetbv on non-windows platforms

craig.topper marked an inline comment as done. craig.topper added inline comments. Comment at: test/Headers/ms-intrin.cpp:37 void f() { __movsb(0, 0, 0); __movsd(0, 0, 0); rnk wrote: > Surely `__movsb` and `__readmsr` should all be x86-only as well, at lea

[PATCH] D56690: [Nios2] Remove Nios2 backend

craig.topper created this revision. craig.topper added reviewers: chandlerc, hans, efriedma. Herald added subscribers: jfb, mgorny. As mentioned here. This backend is incomplete and has not been maintained in several months. http://lists.llvm.org/pipermail/llvm-dev/2019-January/129121.html htt

[PATCH] D56965: [X86] Remove the cvtuqq2ps256/cvtqq2ps256 mask builtins. Replace with uitofp/sitofp and select.

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel. Herald added a subscriber: kristina. Repository: rC Clang https://reviews.llvm.org/D56965 Files: include/clang/Basic/BuiltinsX86.def lib/Headers/avx512vldqintrin.h test/CodeGen/avx512vldq-builtins.c Index

[PATCH] D56965: [X86] Remove the cvtuqq2ps256/cvtqq2ps256 mask builtins. Replace with uitofp/sitofp and select.

craig.topper added a comment. It uses current rounding mode for inexact conversions. cvtsi642ss should do the same. As does (u)dq2ps and (u)qq2pd. I think we use sitofp/uitofp for some lengths of those already. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D56965

[PATCH] D56998: [X86] Custom codegen 512 integer to fp conversion intrinsics.

craig.topper created this revision. craig.topper added a reviewer: RKSimon. Herald added a subscriber: cfe-commits. The 512-bit cvt(u)qq2tops, cvt(u)qqtopd, and cvt(u)dqtops intrinsics all have the possibility of taking an explicit rounding mode argument. If the rounding mode is CUR_DIRECTION we

[PATCH] D56998: [X86] Custom codegen 512-bit cvt(u)qq2tops, cvt(u)qqtopd, and cvt(u)dqtops intrinsics.

craig.topper updated this revision to Diff 182837. craig.topper added a comment. Rename the intrinics to include avx512 prefix Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D56998/new/ https://reviews.llvm.org/D56998 Files: lib/CodeGen/CGBuiltin.cpp test/Code

[PATCH] D56998: [X86] Custom codegen 512-bit cvt(u)qq2tops, cvt(u)qqtopd, and cvt(u)dqtops intrinsics.

craig.topper added a comment. Ping Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D56998/new/ https://reviews.llvm.org/D56998 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailm

[PATCH] D56571: [RFC prototype] Implementation of asm-goto support in clang

craig.topper updated this revision to Diff 184447. craig.topper added a comment. Pass FunctionType into the IRBuilder::CreateCallBr to avoid needing to make an opaque pointer update later CHANGES SINCE LAST ACTION https://reviews.llvm.org/D56571/new/ https://reviews.llvm.org/D56571 Files:

[PATCH] D56571: [RFC prototype] Implementation of asm-goto support in clang

craig.topper commandeered this revision. craig.topper edited reviewers, added: jyu2; removed: craig.topper. craig.topper added a comment. Commandeering so I can update to match an IRBuilder interface change in the llvm patch CHANGES SINCE LAST ACTION https://reviews.llvm.org/D56571/new/ http

[PATCH] D53919: [X86] Don't allow illegal vector types to return by direct value on x86-64.

craig.topper added a comment. Retitling to just the x86-64 case. 32-bit mode has issues on arguments too I think and will need more work. The IsIllegalVectorType function is a member of the X86_64ABIInfo so we need to refactor or add a new one for 32-bit. Repository: rC Clang https://review

[PATCH] D54171: [MS] Zero out ECX in __cpuid in intrin.h

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM https://reviews.llvm.org/D54171 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/li

[PATCH] D54792: add -march=cascadelake support in clang

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D54792/new/ https://reviews.llvm.org/D54792 ___ cf

[PATCH] D53850: Declares __cpu_model as dso local

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D53850/new/ https://reviews.llvm.org/D53850 ___ cf

[PATCH] D54355: Use is.constant intrinsic for __builtin_constant_p

craig.topper added a comment. I'm seeing a case where an inline assembly 'n' constraint is behaving differently in -O0 now. Previously we would evaluate the __builtin_constant_p as part of the EvaluateAsInt call in CodeGenFunction::EmitAsmInput, but I think we're not doing that now. This causes

[PATCH] D54355: Use is.constant intrinsic for __builtin_constant_p

craig.topper added a comment. Here's the test case that we have https://reviews.llvm.org/P8123 gcc seems to accept it at O0 Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D54355/new/ https://reviews.llvm.org/D54355

[PATCH] D56571: [RFC prototype] Implementation of asm-goto support in clang

craig.topper added a comment. @rsmith, @efriedma, @chandlerc, is this in good enough shape that we can commit and move to incremental fixes/improvement? Jennifer has had to rebase this a couple times which is making things hard for the folks testing this with the Linux kernel and needing to app

[PATCH] D59287: [X86] Only define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 in 64-bit mode.

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel, efriedma, jyknight. Herald added subscribers: cfe-commits, jfb. Herald added a project: clang. This define should correspond to CMPXCHG16B being available which requires 64-bit mode. I checked and gcc also seems t

[PATCH] D59287: [X86] Only define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 in 64-bit mode.

craig.topper added a comment. Isn’t that setMaxAtomicWidth in the x86-64 derived class? As far as preventing “cx16” from being set in 32-bit mode, we’ll need to check the behavior of CPUID in 32-bit mode or -march=native might still end up setting it. Repository: rC Clang CHANGES SINCE LAS

[PATCH] D59287: [X86] Only define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 in 64-bit mode.

craig.topper added a comment. Most if not all of the test cases in test/CodeGen/X86/atomic128.ll fail with a fatal error if you run it in 32-bit mode with -mattr=+cx16 Looks like the backend is also bad at checking 64 bit mode. Repository: rC Clang CHANGES SINCE LAST ACTION https://revie

[PATCH] D59287: [X86] Only define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 in 64-bit mode.

craig.topper added a comment. Is this ok with the backend fixed? Or do you want me factor this into HasCX16 which I think is only used by the defineMacro and the return for hasFeature("cx16")? And I think hasFeature("cx16") is only used by that getMaxAtomicWidth() code which is only called on 6

[PATCH] D59287: [X86] Only define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 in 64-bit mode.

craig.topper added a comment. I think the only error we have for X86 is trying to use a -march for a cpu that only supports 32 bit but compiling 64 bit code. I dont' think we can error for -mcx16 on a 32-bit target. For -march=native, the driver will call getHostCPUFeatures and get a list of fe

[PATCH] D59346: [X86] Add gcc rotate intrinsics to ia32intrin.h

craig.topper created this revision. craig.topper added reviewers: rnk, jyknight, RKSimon, spatel, erichkeane. Herald added a subscriber: jdoerfert. Herald added a project: clang. craig.topper updated this revision to Diff 190567. craig.topper added a comment. Add the test file This is another at

[PATCH] D59346: [X86] Add gcc rotate intrinsics to ia32intrin.h

craig.topper updated this revision to Diff 190567. craig.topper added a comment. Add the test file Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59346/new/ https://reviews.llvm.org/D59346 Files: lib/Headers/ia32intrin.h test/CodeGen/rot-intrinsics.c Index:

[PATCH] D59346: [X86] Add gcc rotate intrinsics to ia32intrin.h

craig.topper updated this revision to Diff 190568. craig.topper added a comment. Fix bad comment copy/paste Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59346/new/ https://reviews.llvm.org/D59346 Files: lib/Headers/ia32intrin.h test/CodeGen/rot-intrinsics.c

[PATCH] D59346: [X86] Add gcc rotate intrinsics to ia32intrin.h

craig.topper updated this revision to Diff 190943. craig.topper added a comment. Add comments based on rnk's review Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59346/new/ https://reviews.llvm.org/D59346 Files: lib/Headers/ia32intrin.h test/CodeGen/rot-intr

[PATCH] D59448: [WebAssembly] Change wasm.throw's first argument to an immediate

craig.topper added a comment. Shouldn't the definition in BuiltinsWebAssembly.def be updated to include an 'I' in the type string so that this will be properly diagnosed in the frontend? Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59448/new/ https://reviews.ll

[PATCH] D59533: [X86] Add __crc32b/__crc32w/__crc32d/__crc32q intrinsics to match gcc and icc.

craig.topper created this revision. craig.topper added reviewers: spatel, RKSimon. Herald added a project: clang. craig.topper updated this revision to Diff 191251. craig.topper added a comment. Add the test file that I forgot to git add before running arcanist gcc has these intrinsics in ia32in

[PATCH] D59533: [X86] Add __crc32b/__crc32w/__crc32d/__crc32q intrinsics to match gcc and icc.

craig.topper updated this revision to Diff 191251. craig.topper added a comment. Add the test file that I forgot to git add before running arcanist Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59533/new/ https://reviews.llvm.org/D59533 Files: lib/Headers/ia32

[PATCH] D28213: [Frontend] Correct values of ATOMIC_*_LOCK_FREE to match builtin

craig.topper added a comment. It's still wrong. I think this might fix it? --- a/clang/lib/Basic/Targets/X86.h +++ b/clang/lib/Basic/Targets/X86.h @@ -346,9 +346,8 @@ public: (1 << TargetInfo::LongDouble)); // x86-32 has atomics up to 8 bytes -// FIXME: Check tha

[PATCH] D28213: [Frontend] Correct values of ATOMIC_*_LOCK_FREE to match builtin

craig.topper added a comment. In D28213#1435542 , @efriedma wrote: > It's kind of awkward to use ">=" on a CPU enum, but yes, that's the right > idea. I agree, but we do the same thing on the "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8" define in X86.cpp. App

[PATCH] D28213: [Frontend] Correct values of ATOMIC_*_LOCK_FREE to match builtin

craig.topper added a comment. Patch here https://reviews.llvm.org/D59566 Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D28213/new/ https://reviews.llvm.org/D28213 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D59567: [X86] Add __popcntd and __popcntq to ia32intrin.h to match gcc and icc. Remove popcnt feature flag from _popcnt32/_popcnt64 and move to ia32intrin.h to match gcc

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel, andreadb. gcc and icc both implement __popcntd and __popcntq which we did not. gcc doesn't seem to require a feature flag for the _popcnt32/_popcnt64 spelling and will use a libcall if its not supported. https:/

[PATCH] D59578: [X86] Remove getCPUKindCanonicalName which seems to be unused.

craig.topper created this revision. craig.topper added a reviewer: erichkeane. Herald added a project: clang. Repository: rC Clang https://reviews.llvm.org/D59578 Files: lib/Basic/Targets/X86.cpp lib/Basic/Targets/X86.h Index: lib/Basic/Targets/X86.h =

[PATCH] D59624: [Driver] Pass -malign-double from the driver to the cc1 command line

craig.topper created this revision. craig.topper added a reviewer: rnk. -malign-double is currently only implemented in the -cc1 interface. But its declared in Options.td so it is a driver option too. But you try to use it with the driver you'll get a message about the option being unused. This

[PATCH] D59567: [X86] Add __popcntd and __popcntq to ia32intrin.h to match gcc and icc. Remove popcnt feature flag from _popcnt32/_popcnt64 and move to ia32intrin.h to match gcc

craig.topper updated this revision to Diff 191625. craig.topper added a comment. Update doxygen comments CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59567/new/ https://reviews.llvm.org/D59567 Files: lib/Headers/ia32intrin.h lib/Headers/popcntintrin.h test/CodeGen/popcnt-builtin

[PATCH] D59567: [X86] Add __popcntd and __popcntq to ia32intrin.h to match gcc and icc. Remove popcnt feature flag from _popcnt32/_popcnt64 and move to ia32intrin.h to match gcc

craig.topper added a comment. In D59567#1436035 , @RKSimon wrote: > IIRC we don't use libcalls for popcnt - we just expand Yeah we expand. gcc uses libcall. I think icc also expands. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59567/new/ htt

[PATCH] D59566: [X86] Correct the value of MaxAtomicInlineWidth for pre-586 cpus

craig.topper updated this revision to Diff 191643. craig.topper added a comment. Herald added subscribers: cfe-commits, jdoerfert. Herald added a project: clang. Rewrite to use a "cx8" feature flag that is set for all i586 and greater CPUs as well as generic. This assumes generic is never passed

[PATCH] D59682: [X86] Add BSR/BSF/BSWAP intrinsics to ia32intrin.h to match gcc.

craig.topper created this revision. craig.topper added reviewers: RKSimon, spatel. Herald added a project: clang. Herald added a subscriber: cfe-commits. These are all implemented by icc as well. I made bit_scan_forward/reverse forward to the __bsfd/__bsrq since we also have __bsfq/__bsrq. Note,

[PATCH] D59682: [X86] Add BSR/BSF/BSWAP intrinsics to ia32intrin.h to match gcc.

craig.topper updated this revision to Diff 192010. craig.topper added a comment. Add doxygen comments. Check the zero_undef flag. Repository: rC Clang CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59682/new/ https://reviews.llvm.org/D59682 Files: lib/Headers/ia32intrin.h lib/Hea

[PATCH] D60674: [X86] Restore the pavg intrinsics.

craig.topper updated this revision to Diff 195090. craig.topper added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Add the clang changes Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60674/new/ https://reviews.l

[PATCH] D56571: [RFC prototype] Implementation of asm-goto support in clang

craig.topper added a comment. In D56571#1467333 , @void wrote: > This code: > > ; ModuleID = 'arch_static_branch.bc' > source_filename = "arch/x86/entry/vsyscall/vsyscall_64.c" > target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" > target

[PATCH] D60674: [X86] Restore the pavg intrinsics.

craig.topper added a comment. In D60674#1467349 , @efriedma wrote: > > Though I modified the avx512 intrinsics to not have masking built in. > > Do we need autoupgrade support from the old avx512 intrinsics to the new > avx512 intrinsics? Yes, and the c

[PATCH] D59712: [APSInt][OpenMP] Fix isNegative, etc. for unsigned types

craig.topper added a comment. Wondering if it would be better to assert for asking for the sign of an unsigned APSInt. I could see a caller just wanting to get the msb for some reason and not knowing that isNegative won’t work. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D59712/new/

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