[PATCH] D117432: [RISCV] Implement support for the Zicbom and Zicboz extensions

asb added a comment. In D117432#3599255 , @craig.topper wrote: > Reverse ping. Is anything blocking this being merged? No, thanks for the ping - now landed. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D1

[PATCH] D128612: RISC-V big-endian support implementation

asb added a comment. Thanks for this patch Guy. As just discussed in the RISC-V sync-up call, it would be helpful from a review perspective to write down at least a simple plain-text description of the changes to the psABI doc needed to reflect the BE ABI implemented by GCC (and soon LLVM), per

[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

asb added a comment. I don't feel very qualified on the current state of strict FP, but I've left a couple of minor comments inline. I'm happy to trust your knowledge the state of strictfp and the patch looks good to me otherwise. Comment at: clang/lib/Basic/Targets/RISCV.cpp

[PATCH] D130311: [RISCV] Enable strict FP in clang as long as Zve* or V are not enabled.

asb added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:232 +bool RISCVISAInfo::hasVInstructions() const { + return hasExtension("zve32x"); +} Given the other sub-thread showed that hasExtennsion("zve32x") == hasVInstructions isn't completely o

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

asb added a comment. @zixuan-wu we discussed this a bit in the last community sync call . One aspect that makes this patch a little hard to review is the lack of a clear patch description summarising the behaviour befo

[PATCH] D105555: [PoC][RISCV][Clang] Compute the default target-abi if it's empty.

asb added a comment. This looks like a good improvement to me - anything that still makes it a "[PoC]" proof of concept? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D10/new/ https://reviews.llvm.org/D10 __

[PATCH] D105555: [RISCV][Clang] Compute the default target-abi if it's empty.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. This looks good to me, and as Jessica says this patch improves robustness and correctness so it would be great to land it for 13.x. @jrtc27 - I think @khchen has reflected all of your comments, but

[PATCH] D106701: [clang] Add -falign-loops=N where N is a power of 2

asb added inline comments. Comment at: llvm/test/CodeGen/RISCV/loop-alignment.ll:3-4 +; RUN: llc < %s -mtriple=riscv64 | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 -align-loops=16 | FileCheck %s -check-prefix=ALIGN_16 +; RUN: llc < %s -mtriple=riscv64 -align-loops=32 | FileC

[PATCH] D121578: [RISCV][NFC] Add tests to address invalid arch dependencies.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Herald added subscribers: s, arichardson. Thanks, this looks good to me. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121578/new/ https://reviews.llv

[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. It would be good to have someone else who's reviewed earlier versions of this patch to confirm, but this LGTM. Thanks. If you were editing it anyway, you could change "has passed" to "is passed" (t

[PATCH] D122215: [WebAssembly] Initial support for reference types in clang

asb added inline comments. Comment at: clang/test/CodeGen/WebAssembly/wasm-externref.c:1 +// RUN: %clang_cc1 -triple wasm32-unknown-unknown -target-feature +reference-types -o - -emit-llvm %s | FileCheck %s + It might be worth using update_cc_test_checks.py for

[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

asb added a comment. @maskray: Are you happy all your comments are addressed? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D120639/new/ https://reviews.llvm.org/D120639 ___ cfe-commits mailing list cfe-c

[PATCH] D119837: [RISCV] Fix the include search path order between sysroot and resource folder

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Thanks Kito. This LGTM, but I'd appreciate someone else reviewing and approving as well. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119837/new/ ht

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. I think all my comments have been addressed. @craig.topper - are you happy your RegInfo question is addressed? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D93298/new/ https://reviews.llvm.org/D93298 _

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. In that case, LGTM (needs a rebase though). Thanks for your patience on this @achieveartificialintelligence. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.

[PATCH] D118333: [RISCV] Use computeTargetABI from llc as well as clang

asb added a comment. Thanks, I've put this on the agenda for the RISC-V LLVM sync call today. I think this is more attractive than the previous proposal due to unifying logic between llc and Clang. I could see a counter-argument about llc being a low-level tool that should be controlled very ex

[PATCH] D129802: [DRAFT] Implementing new atomic orderings in LLVM and generate barriers for legacy __sync builtins. Support corresponding memory model in outline atomics as well.

asb added a comment. In D129802#3653544 , @efriedma wrote: > If we do decide we need to do something here, I'd prefer to model this using > explicit fences in the IR, as opposed to a new atomic ordering. Adding extra > atomic orderings just makes every

[PATCH] D103313: [RISCV][Clang] Add support for Zmmul extension

asb added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:80 +{"zmmul", RISCVExtensionVersion{0, 1}}, + craig.topper wrote: > If it is ratified, is the version really 0.1? It looks like it should be 1.0 now https://github.com/riscv/riscv-isa

[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

asb added a comment. Thanks for the patch - can you add test coverage for this please? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D125765/new/ https://reviews.llvm.org/D125765 ___ cfe-commits mailing l

[PATCH] D125728: [WebAssembly] Update supported features in -mcpu=generic

asb added a comment. Based on the discussion we had, I think this makes sense. It's a bit repetitive, but could you please add a test to clang/test/Driver that checks the list of enabled features for generic (and for completeness, probably bleeding-edge as well). Thanks. Repository: rG LLVM

[PATCH] D125728: [WebAssembly] Update supported features in -mcpu=generic

asb added a comment. Oh, and per recent updates to the LLVM Developer policy I think it would be worth updating the Clang ReleaseNotes.rst to mention this change. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION http

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

asb added a comment. First of all, thank you to everyone who has been trying to nudge this forward and apologies it must have been a frustrating experience. I appreciate there are users who want to see this and I don't like that LLVM doesn't serve them right now - I think it's unfortunate that

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

asb added a comment. This LGTM, but given how much discussion there has been about MaxPromoteWidth it would be great to get some test coverage for it. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57450/new/ https://reviews.llvm.org/D57450

[PATCH] D57450: [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D57450/new/ https://reviews.llvm.org/D57450

[PATCH] D69590: [RISCV] Fix ILP32D lowering for double+double/double+int return types

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Herald added a subscriber: luismarques. This looks good to me, thanks James. I had a closer step through of the logic here to convince myself. Repository: rG LLVM Github Monorepo CHANGES SINCE L

[PATCH] D84414: [RISCV] Support Shadow Call Stack

asb accepted this revision. asb added a comment. I think once @jrtc27 confirms all her issues are addressed this is good to land. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84414/new/ https://reviews.llvm.org/D84414

[PATCH] D92715: [Clang][RISCV] Define RISC-V V builtin types

asb added a comment. In D92715#2443376 , @craig.topper wrote: > Can we discuss this patch in tomorrows RISC-V meeting? @jrtc27 @kito-cheng > @khchen @liaolucy I've added it to the agenda CHANGES SINCE LAST ACTION https://reviews.llvm.org/D92715/new

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

asb added a comment. In D70401#2733003 , @khchen wrote: > Hi, I would like to add ilp32e ABI support in llvm > Is there anyone working on this? > It seem the one thing missed is ilp32e ABI should disallow D ISA extension. > Is there anything else? Nobody

[PATCH] D102839: [RISCV][Clang] Add -mno-div option to disable hardware int division

asb added a comment. In D102839#2784585 , @kito-cheng wrote: > Personally I prefer to deprecate `-mno-div` soon, but based on the rule for > RISC-V GNU toolchain, it need to wait `Zmmul` extension frozen. > My plan is deprecate the `-mno-div` and emit w

[PATCH] D95680: [RISCV] Update the version number to v0.10 for vector.

asb accepted this revision. asb added a comment. LGTM modulo one additional request: please update the comment at the top of RISCVInstrInfoV.td to say "0.10" rather than "0.9". Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95680/new/ https://revie

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. I started reviewing this alongside the specification in https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc. At the time of writing, it seems to define "zfinx" but not "zfhinx" and "zfdinx" as seem to be used in this patch. I think intent is that rv32ifd_zfinx

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

asb added a comment. In D93298#2544459 , @StephenFan wrote: > According to @jrtc27 's review that is > "As for Zfinx itself, well, the idea is fine, but I really detest the way > it's being done as an extension to F/D/Zfh. Running F code on an FZfh core

[PATCH] D106888: [RISC-V] Implement jump tables for CFI-icall

asb added a comment. Is it possible to write a test case for this? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106888/new/ https://reviews.llvm.org/D106888 ___ cfe-commits mailing list cfe-commits@list

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

asb added a comment. I'm getting a build error (building with clang 12.0.1): FAILED: lib/Support/CMakeFiles/LLVMSupport.dir/RISCVISAInfo.cpp.o /usr/bin/clang++ -DGTEST_HAS_RTTI=0 -D_DEBUG -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -I/home/asb/llvm-p

[PATCH] D111062: [RISCV] Rename some assembler mnemonic and intrinsic functions for RVV 1.0.

asb added a comment. Is this blocked on anything or is it good to land? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111062/new/ https://reviews.llvm.org/D111062 ___ cfe-commits mailing list cfe-commits

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

asb added a comment. Herald added a reviewer: luke957. This doesn't apply cleanly to current HEAD, could you please rebase? I think the second part of this that you list, where the ISA extension version becomes optional is undesirable. We made the explicit choice of requiring the version string

[PATCH] D111866: [RISCV] Support Zfhmin extension

asb added a comment. Herald added a reviewer: luke957. From an initial look, I think this is almost ready to land - thank you. One suggestion would be to review the various `Subtarget.hasStdExtZfhmin() || Subtarget.hasStdExtZfh()`. I'd first thought adding a new helper to RISCVSubtarget to be c

[PATCH] D111866: [RISCV] Support Zfhmin extension

asb added inline comments. Herald added a subscriber: luke957. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1153 bool ForCodeSize) const { - if (VT == MVT::f16 && !Subtarget.hasStdExtZfh()) + if (VT == MVT::f16 && !Subtarget.ha

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

asb added a comment. In D112359#3098960 , @eopXD wrote: > > Add version numbers for test case in `attribute-arch.s` Thanks for updating the patch. Why change this test case? I thought those lines were verifying that .attribute arch without a version

[PATCH] D111866: [RISCV] Support Zfhmin extension

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, modulo one tiny nit on a comment. Thanks! Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td:253 def PseudoFSH : PseudoStore<"fsh", FPR16>; } // Predicates = [HasStdEx

[PATCH] D109215: [RISCV] Fix arch string parsing for multi-character extensions

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. This seems to match the emerging consensus in the various RISC-V GitHub issue threads and as you point out, is needed to support extensions in the 1.0 V spec. Looks good to me - thanks! =

[PATCH] D97896: [Clang][RISCV][RFC] Add byval parameter attribute?

asb added a comment. I think I may have had the impression from some previous discussions that byval may have limited positive impact, and that letting Clang add the copies to the IR might in some cases help optimisations (that may not be written to reason about byval). You've got a good exampl

[PATCH] D112359: [RISCV] Unify depedency check and extension implication parsing logics

asb added a comment. OK, that reasoning makes sense. I think my only outstanding request would be to ensure there's some test coverage for the case of .attribute arch with an experimental extension without version info. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https:/

[PATCH] D136817: [RISCV] Add H extension

asb added a comment. Thanks for this patch Kito - I'm thinking that perhaps we erred in not treating the hypervisor instructions (e.g. HLV* and HSV*) as being gated on the H extension, so a sensible follow-on to this patch would be to mark those instructions as requiring FeatureStdExtH - what d

[PATCH] D136812: [RISCV] Drop single letter b extension support

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM, thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136812/new/ https://reviews.llvm.org/D136812

[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

asb added a comment. I've put it on the agenda for the call today so we can close this off (I figure given it's been sitting so long, waiting a few extra days to cover it in the call is no big deal). But if the data shows this overall improves things, I think it's a sensible change to make. R

[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. There were no objections on the call. Looks good to me - two minor changes before landing that would make sense: - Fraser suggested tweaking the patch description - Probably worth adding this to `do

[PATCH] D131677: [clang][RISCV][WIP] Fix incorrect ABI lowering for inherited structs with hard-float ABIs

asb updated this revision to Diff 451915. asb added reviewers: kito-cheng, craig.topper, reames. asb added a comment. Herald added subscribers: frasercrmck, apazos, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, MaskRay, jrtc27, niosHD, sabuasal, johnrusso, rbar. Add test

[PATCH] D131677: [clang][RISCV] Fix incorrect ABI lowering for inherited structs under hard-float ABIs

asb updated this revision to Diff 452090. asb added a comment. Add additional tests for diamond and virtual inheritance. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131677/new/ https://reviews.llvm.org/D131677 Files: clang/lib/CodeGen/TargetInfo.cpp clang/test/CodeGen/RISCV/riscv

[PATCH] D131708: [RISCV] Change how mtune aliases are implemented.

asb added a comment. This seems like a sensible direction to me - let's discuss in the sync-up call this Thursday to check everyone is on-board and doesn't have concerns. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D131708/new/ https://reviews.ll

[PATCH] D131677: [clang][RISCV] Fix incorrect ABI lowering for inherited structs under hard-float ABIs

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGbc538320809f: [clang][RISCV] Fix incorrect ABI lowering for inherited structs under hard… (authored by asb). Herald added a project: clang. Changed

[PATCH] D134050: [clang][RISCV][NFC][WIP/RFC] Move riscv-abi.cpp and riscv32-*abi.c tests to use update_cc_test_checks.py

asb created this revision. asb added reviewers: reames, craig.topper, luismarques, kito-cheng. Herald added subscribers: wingo, sunshaoce, pmatos, VincentWu, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosb

[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

asb requested changes to this revision. asb added a comment. This revision now requires changes to proceed. Everything that's in this patch looks good to me - it's just missing some simple round-trip tests in the style of rv32zicboz-valid.s (and perhaps an -invalid.s that shows a sensible error

[PATCH] D133443: [RISCV][MC] Add support for experimental Zawrs extension

asb added a comment. It looks like they're still missing in this updated version of the patch? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D133443/new/ https://reviews.llvm.org/D133443 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D133834: [RISCV] Remove support for the unratified Zbt extension.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. There seemed to be consensus on this in last week's meeting, and there's no upstream activity on the spec, so removing zbt makes sense to me. Comment at: llvm/docs/ReleaseNotes.rs

[PATCH] D141380: [clang-repl] XFAIL riscv targets in simple-exception test case

asb created this revision. asb added reviewers: sunho, lhames. Herald added subscribers: wingo, sunshaoce, pmatos, VincentWu, vkmr, evandro, luismarques, sameer.abuasal, s.egerton, Jim, benna, psnobl, PkmX, rogfer01, shiva0217, kito-cheng, simoncook, kristof.beyls, arichardson. Herald added a pro

[PATCH] D137309: [clang] Added Swift support for RISCV64

asb added a comment. First of all, thanks for the contribution. I've not looked at all into the Swift calling convention requirements, but at a minimum this patch is going to need test coverage. I also think RV32 should be handled somehow - either by adding equivalent support, or at least error

[PATCH] D136817: [RISCV] Add H extension

asb added a comment. Thanks Kito, I think my only remaining request would be to add at least some test coverage for using a H extensions when h isn't included in the ISA string. I don't think such tests are handled very cleanly or consistently right now, but adding something to rv32i-invalid.s

[PATCH] D137309: [clang] Added Swift support for RISCV

asb added a comment. In D137309#3914494 , @colemancda wrote: > RV32 is enabled as well. I'll add unit tests. Great, thanks. Is it really the case that shouldPassIndirectlyForSwift has the same result regardless of native word size? Repository: rG L

[PATCH] D142373: [Utils] Add --full-function-signature to update_cc_test_checks.py to match return type as well as args

asb added a comment. In D142373#4076198 , @luismarques wrote: > Do we actually want to include the `dso_local` in the full signature? That's a fair question. I could imagine it's useful to include these attributes in some test scenarios and not in othe

[PATCH] D142373: [Utils] Add --full-function-signature to update_cc_test_checks.py to match return type as well as args

asb added a comment. In D142373#4076584 , @nikic wrote: > Please give me a day to propose another alternative... Seeing D142452 > we now have three different patches that > would like to change UTC output, so I really

[PATCH] D140401: [clang][RISCV] Fix ABI mismatch between GCC and Clang (extension of integers on stack)

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGe0a28188d2b5: [clang][RISCV] Fix ABI mismatch between GCC and Clang (extension of integers on… (authored by asb). Herald added a project: clang. Hera

[PATCH] D142326: [clang][RISCV][test] Add test cases for empty structs and the FP calling conventions

asb updated this revision to Diff 491780. asb marked an inline comment as done. asb added a comment. Add zero-length array test cases. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142326/new/ https://reviews.llvm.org/D142326 Files: clang/test/CodeGen/RISCV/abi-empty-structs.c Index

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

asb updated this revision to Diff 491781. asb marked an inline comment as done. asb added a comment. - Address review comments - Refresh after adding zero-length array tests (and fix a bug this unearthed). - Add to release notes CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142327/new/

[PATCH] D142094: [Clang][Doc] Add release note for changes for the RVV intrinsics

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. In D142094#4070856 , @eopXD wrote: > In D142094#4065611 , @asb wrote: > >> In D142094#4065175

[PATCH] D142326: [clang][RISCV][test] Add test cases for empty structs and the FP calling conventions

asb added inline comments. Comment at: clang/test/CodeGen/RISCV/abi-empty-structs.c:1 +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --full-function-signature --filter "^define |^entry:" +// RUN: %clang_cc1 -triple

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

asb added a comment. Thanks Luis for the quick review. As an important part of this is trying to align with gcc/g++ I'd really appreciate a review from @kito-cheng too if you have the time (thanks in advance!). CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142327/new/ https://reviews.

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

asb added a comment. In D142327#4080044 , @asb wrote: > Thanks Luis for the quick review. As an important part of this is trying to > align with gcc/g++ I'd really appreciate a review from @kito-cheng too if you > have the time (thanks in advance!). Fr

[PATCH] D141380: [clang-repl] XFAIL riscv targets in simple-exception test case

asb added a comment. In D141380#4053535 , @Hahnfeld wrote: > Yes, this is correct: The JITLink backend for RISC-V doesn't (yet) register > the eh frames into libunwind, so throwing and catching exceptions through > JITted code doesn't work (yet). I know

[PATCH] D141666: [RISCV] Proper support of extensions Zicsr and Zifencei

asb added a comment. Herald added a subscriber: luke. In D141666#4050692 , @eklepilkina wrote: > We are interested in proper support for `Zicsr` and `Zifencei`. Could someone > look at patch or explain why these extensions were included by default? As

[PATCH] D141380: [clang-repl] XFAIL riscv targets in simple-exception test case

This revision was automatically updated to reflect the committed changes. Closed by commit rG123223ab87ca: [clang-repl] XFAIL riscv targets in simple-exception test case (authored by asb). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141380/new/ ht

[PATCH] D142094: [Clang][Doc] Add release note for changes for the RVV intrinsics

asb added a comment. In D142094#4065175 , @eopXD wrote: > @asb I just saw the cancellation of the sync-up call today. Regarding the > branch out on 01/24 I think it would be good to have these incompatible > changes into LLVM 16. Sorry for missing ther

[PATCH] D142326: [clang][RISCV][test] Add test cases for empty structs and the FP calling conventions

asb created this revision. asb added reviewers: kito-cheng, reames, jrtc27, craig.topper, luke. Herald added subscribers: wingo, pmatos, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogf

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

asb created this revision. asb added reviewers: kito-cheng, jrtc27, reames, craig.topper, uweigand, luke. Herald added subscribers: wingo, pmatos, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMos

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

asb updated this revision to Diff 491237. asb added a comment. Removed FIXME missed in initial version. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D142327/new/ https://reviews.llvm.org/D142327 Files: clang/lib/CodeGen/TargetInfo.cpp clang/test/CodeGen/RISCV/abi-empty-structs.c I

[PATCH] D139010: [clang][WebAssembly] Implement support for table types and builtins

asb added inline comments. Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:11827 +def err_wasm_builtin_arg_must_be_integer_type : Error < + "%ordinal0 argument must be an integer">; } // end of sema component. aaron.ballman wrote: > I'm a bit shock

[PATCH] D142373: [Utils] Add --full-function-signature to update_cc_test_checks.pyh to match return type as well as args

asb created this revision. asb added reviewers: arichardson, nikic, mtrofin. Herald added subscribers: wingo, pmatos, StephenFan, luismarques, sameer.abuasal, s.egerton, PkmX, simoncook. Herald added a project: All. asb requested review of this revision. Herald added projects: clang, LLVM. Herald

[PATCH] D142326: [clang][RISCV][test] Add test cases for empty structs and the FP calling conventions

asb added inline comments. Comment at: clang/test/CodeGen/RISCV/abi-empty-structs.c:101 + +struct s5 { struct empty e[1]; float f; }; + luismarques wrote: > Should we also test a case with an array size 0 like `ct s { struct empty > e[0]; float f; };`? I think t

[PATCH] D122215: [WebAssembly] Initial support for reference type externref in clang

asb added a comment. I've left one minor comment. My other suggestion would be to absorb in the semantic restrictions work from here . Comment at: llvm/lib/IR/Type.cpp:307 +Type *Type::getWasm_ExternrefTy(LLVMCon

[PATCH] D125728: [WebAssembly] Update supported features in -mcpu=generic

asb added a comment. One thing that's not ideal about this test case is that it still passes if you delete the changes to WebAssembly.cpp. At least for RISC-V, selecting the -mcpu also emits the relevant `-target-feature +foo` for features supported by that CPU, which doesn't seem to happen her

[PATCH] D128235: [RISCV] Add support for the Zawrs extension

asb added a comment. > This is still some sort of very early draft and I'm not sure what the rules > are in LLVM land for merging that sort of code. It's a fast track extension > so it should be done soon The policy we ended up with is that support for not-yet-ratified extensions can be merged

[PATCH] D128282: [WebAssembly] Update test to run it in opaque pointers mode

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM. Though it also looks like all the WEBASSEMBLY32/WEBASSEMBLY64 lines you're modifying match each other, so could be combined to single `WEBASSEMBLY:` lines. It might be worth doing that while y

[PATCH] D128282: [WebAssembly] Update test to run it in opaque pointers mode

asb added a comment. In D128282#3600355 , @tlively wrote: > I think the lines still differ in that one tests wasm32 and the other tests > wasm64 (the triples are different). Yeah, but the convention used elsewhere in this test file is to use `WEBASSEMB

[PATCH] D155668: [RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. Should add a release note as well, but otherwise LGTM. My understanding is that all of the intrinsics this exposes have the same level of stability / finalisation as the other vector intrinsics, but

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

asb added a comment. I remain concerned about exposing the intrinsics if they're not yet agreed as finalised. I see there is now a PR to add them to riscv-c-api doc https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47 I'd be OK with merging this now if the intrinsics were temporarily remove

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

asb added a comment. @jacquesguan yes I agree, let's hold off on merging this until that PR is merged as it looks like it's quite close. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151547/new/ https://reviews.llvm.org/D151547 __

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG17a58b3ca7ec: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling… (authored by asb). Herald added a subscriber: wangpc. Changed p

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

asb reopened this revision. asb added a comment. This revision is now accepted and ready to land. Reopening as I've reverted following Roger's bug report. Comment at: clang/lib/CodeGen/Targets/RISCV.cpp:178 return false; -if (isEmptyRecord(getContext(), Ty, true)) +

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

asb added a comment. In D151547#4531062 , @jacquesguan wrote: > https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47 is already merged, > any more advice about this patch? Just that it needs a release note, and we need the newly defined overloaded

[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies

asb added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948 - // TODO: The 'q' extension requires rv64. - // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'. imkiva wrote: > wangpc wrote: > > I think the comment is outdated her

[PATCH] D156221: [RISCV] Support overloaded version ntlh intrinsic function

asb added a comment. This seems functionally correct to me, but I'd welcome opinions from others who work more with the C intrinsics on if this is the best way to implement the overloading. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156221/new/

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

asb updated this revision to Diff 544349. asb added a comment. I've updated the patch to fix the reported issue (adding an additional check to detectFPCCEligibleStruct). What I haven't been able to do so far is to extract a test case that shows the issue indicated by @SixWeining without relying

[PATCH] D157497: feat: Migrate isArch16Bit

asb added a comment. Is there some separate discussion thread or proposal about this refactoring and its motivations? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D157497/new/ https://reviews.llvm.org/D157497 _

[PATCH] D157663: [Driver] Default riscv*- triples to -fdebug-default-version=4

asb accepted this revision. asb added a comment. LGTM, this seems like a good workaround. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D157663/new/ https://reviews.llvm.org/D157663 ___ cfe-commits mailin

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

asb updated this revision to Diff 546012. asb added a comment. This update includes test coverage for the bug that was fixed in the reverted version of the patch. Thanks @rogfer01 for the smaller test case. To my surprise, cvise stripped out almost everything and test_s9 in abi-empty-structs.c

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

This revision was automatically updated to reflect the committed changes. Closed by commit rGe3c57fdd8439: [clang][RISCV] Fix bug in ABI handling of empty structs with hard FP calling… (authored by asb). Changed prior to commit: https://reviews.llvm.org/D142327?vs=546012&id=547684#toc Reposito

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

asb added a comment. @jacquesguan: I think this is good to go if you rebase now D156221 landed and add a release note. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D151547/new/ https://reviews.llvm.org/D151547 _

[PATCH] D154576: [RISCV] RISCV vector calling convention (1/2)

asb added a comment. Putting this behind an attribute for now makes sense given that we don't seem to have consensus on https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389 let alone how to manage any migration. I'm slightly wary of merging this with a generic attribute (currently 'ri

[PATCH] D151547: [RISCV] Remove experimental for zihintntl

asb accepted this revision. asb added a comment. This revision is now accepted and ready to land. LGTM - just see the very minor corrections inline. Thanks! Comment at: clang/test/Preprocessor/riscv-target-features.c:146 // RUN: %clang -target riscv32-unknown-linux-gnu -men

[PATCH] D157580: [RISCV][NFC] Use named arguments in newly added changes

asb accepted this revision. asb added a comment. I just wanted to say thank you for your work on the named arguments tablegen feature. This and D154067 are good showcases of the readability improvement. Repository: rG LLVM Github Monorepo CHANGES SINCE LAS

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