This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGbc538320809f: [clang][RISCV] Fix incorrect ABI lowering for
inherited structs under hard… (authored by asb).
Herald added a project: clang.
Changed prior to commit:
https://reviews.llvm.org/D131677?vs=452090&id=454080#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D131677/new/
https://reviews.llvm.org/D131677
Files:
clang/lib/CodeGen/TargetInfo.cpp
clang/test/CodeGen/RISCV/riscv-abi.cpp
Index: clang/test/CodeGen/RISCV/riscv-abi.cpp
===================================================================
--- clang/test/CodeGen/RISCV/riscv-abi.cpp
+++ clang/test/CodeGen/RISCV/riscv-abi.cpp
@@ -1,15 +1,15 @@
-// RUN: %clang_cc1 -triple riscv32 -emit-llvm -x c++ %s -o - \
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm %s -o - \
// RUN: | FileCheck -check-prefixes=ILP32,ILP32-ILP32F,ILP32-ILP32F-ILP32D %s
-// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm -x c++ %s -o - \
+// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm %s -o - \
// RUN: | FileCheck -check-prefixes=ILP32F,ILP32-ILP32F,ILP32F-ILP32D,ILP32-ILP32F-ILP32D %s
-// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-abi ilp32d -emit-llvm %s -x c++ -o - \
+// RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-abi ilp32d -emit-llvm %s -o - \
// RUN: | FileCheck -check-prefixes=ILP32D,ILP32F-ILP32D,ILP32-ILP32F-ILP32D %s
-// RUN: %clang_cc1 -triple riscv64 -emit-llvm -x c++ %s -o - \
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm %s -o - \
// RUN: | FileCheck -check-prefixes=LP64,LP64-LP64F,LP64-LP64F-LP64D %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-abi lp64f -emit-llvm -x c++ %s -o - \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-abi lp64f -emit-llvm %s -o - \
// RUN: | FileCheck -check-prefixes=LP64F,LP64-LP64F,LP64F-LP64D,LP64-LP64F-LP64D %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-abi lp64d -emit-llvm %s -x c++ -o - \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-abi lp64d -emit-llvm %s -o - \
// RUN: | FileCheck -check-prefixes=LP64D,LP64F-LP64D,LP64-LP64F-LP64D %s
#include <stdint.h>
@@ -39,12 +39,10 @@
float f1;
};
-// TODO: Fix incorrect lowering for hard-float ABIs.
-
// ILP32: define{{.*}} [2 x i32] @_Z30int32_float_struct_inheritance14child2_float_s([2 x i32] %a.coerce)
-// ILP32F-ILP32D: define{{.*}} float @_Z30int32_float_struct_inheritance14child2_float_s(float %0)
+// ILP32F-ILP32D: define{{.*}} { i32, float } @_Z30int32_float_struct_inheritance14child2_float_s(i32 %0, float %1)
// LP64: define{{.*}} i64 @_Z30int32_float_struct_inheritance14child2_float_s(i64 %a.coerce)
-// LP64F-LP64D: define{{.*}} float @_Z30int32_float_struct_inheritance14child2_float_s(float %0)
+// LP64F-LP64D: define{{.*}} { i32, float } @_Z30int32_float_struct_inheritance14child2_float_s(i32 %0, float %1)
struct child2_float_s int32_float_struct_inheritance(struct child2_float_s a) {
return a;
}
@@ -57,10 +55,9 @@
int64_t i1;
};
-// TODO: Fix incorrect lowering for lp64f/lp64d ABIs.
-
// ILP32-ILP32F-ILP32D-LABEL: define{{.*}} void @_Z30float_int64_struct_inheritance14child3_int64_s(ptr noalias sret(%struct.child3_int64_s)
-// LP64-LP64F-LP64D-LABEL: define{{.*}} [2 x i64] @_Z30float_int64_struct_inheritance14child3_int64_s([2 x i64] %a.coerce)
+// LP64-LABEL: define{{.*}} [2 x i64] @_Z30float_int64_struct_inheritance14child3_int64_s([2 x i64] %a.coerce)
+// LP64F-LP64D-LABEL: define{{.*}} { float, i64 } @_Z30float_int64_struct_inheritance14child3_int64_s(float %0, i64 %1)
struct child3_int64_s float_int64_struct_inheritance(struct child3_int64_s a) {
return a;
}
@@ -73,16 +70,54 @@
double d1;
};
-// TODO: Fix incorrect lowering for ilp32d/lp64d ABIs.
-
// ILP32-ILP32F-LABEL: define{{.*}} void @_Z32double_double_struct_inheritance15child4_double_s(ptr noalias sret(%struct.child4_double_s)
-// ILP32D-LABEL: define{{.*}} double @_Z32double_double_struct_inheritance15child4_double_s(double %0)
+// ILP32D-LABEL: define{{.*}} { double, double } @_Z32double_double_struct_inheritance15child4_double_s(double %0, double %1)
// LP64-LP64F-LABEL: define{{.*}} [2 x i64] @_Z32double_double_struct_inheritance15child4_double_s([2 x i64] %a.coerce)
-// LP64D-LABEL: define{{.*}} double @_Z32double_double_struct_inheritance15child4_double_s(double %0)
+// LP64D-LABEL: define{{.*}} { double, double } @_Z32double_double_struct_inheritance15child4_double_s(double %0, double %1)
struct child4_double_s double_double_struct_inheritance(struct child4_double_s a) {
return a;
}
+// When virtual inheritance is used, the resulting struct isn't eligible for
+// passing in registers.
+
+struct parent5_virtual_s {
+ int32_t i1;
+};
+
+struct child5_virtual_s : virtual parent5_virtual_s {
+ float f1;
+};
+
+// ILP32-ILP32F-ILP32D-LABEL: define{{.*}} void @_ZN16child5_virtual_sC1EOS_(ptr noundef nonnull align 4 dereferenceable(8) %this, ptr noundef nonnull align 4 dereferenceable(8) %0)
+// LP64-LP64F-LP64D-LABEL: define{{.*}} void @_ZN16child5_virtual_sC1EOS_(ptr noundef nonnull align 8 dereferenceable(12) %this, ptr noundef nonnull align 8 dereferenceable(12) %0)
+struct child5_virtual_s int32_float_virtual_struct_inheritance(struct child5_virtual_s a) {
+ return a;
+}
+
+// Check for correct lowering in the presence of diamond inheritance.
+
+struct parent6_float_s {
+ float f1;
+};
+
+struct child6a_s : parent6_float_s {
+};
+
+struct child6b_s : parent6_float_s {
+};
+
+struct grandchild_6_s : child6a_s, child6b_s {
+};
+
+// ILP32: define{{.*}} [2 x i32] @_Z38float_float_diamond_struct_inheritance14grandchild_6_s([2 x i32] %a.coerce)
+// ILP32F-ILP64D: define{{.*}} { float, float } @_Z38float_float_diamond_struct_inheritance14grandchild_6_s(float %0, float %1)
+// LP64: define{{.*}} i64 @_Z38float_float_diamond_struct_inheritance14grandchild_6_s(i64 %a.coerce)
+// LP64F-LP64D: define{{.*}} { float, float } @_Z38float_float_diamond_struct_inheritance14grandchild_6_s(float %0, float %1)
+struct grandchild_6_s float_float_diamond_struct_inheritance(struct grandchild_6_s a) {
+ return a;
+}
+
// NOTE: These prefixes are unused. Do not add tests below this line:
// ILP32F: {{.*}}
// LP64F: {{.*}}
Index: clang/lib/CodeGen/TargetInfo.cpp
===================================================================
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10979,9 +10979,22 @@
// Unions aren't eligible unless they're empty (which is caught above).
if (RD->isUnion())
return false;
+ const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
+ // If this is a C++ record, check the bases first.
+ if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
+ for (const CXXBaseSpecifier &B : CXXRD->bases()) {
+ const auto *BDecl =
+ cast<CXXRecordDecl>(B.getType()->castAs<RecordType>()->getDecl());
+ CharUnits BaseOff = Layout.getBaseClassOffset(BDecl);
+ bool Ret = detectFPCCEligibleStructHelper(B.getType(), CurOff + BaseOff,
+ Field1Ty, Field1Off, Field2Ty,
+ Field2Off);
+ if (!Ret)
+ return false;
+ }
+ }
int ZeroWidthBitFieldCount = 0;
for (const FieldDecl *FD : RD->fields()) {
- const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
uint64_t FieldOffInBits = Layout.getFieldOffset(FD->getFieldIndex());
QualType QTy = FD->getType();
if (FD->isBitField()) {
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