asb updated this revision to Diff 451915.
asb added reviewers: kito-cheng, craig.topper, reames.
asb added a comment.
Herald added subscribers: frasercrmck, apazos, jocewei, PkmX, the_o,
brucehoult, MartinMosbeck, edward-jones, zzheng, MaskRay, jrtc27, niosHD,
sabuasal, johnrusso, rbar.
Add test (I've pre-committed the current behaviour).
Now that update_cc_test_checks.py supports both `--function-signature` and
`--filter '^define '` I'd hoped I could massively improve the maintainability
of the tests by using it. Unfortunately it seems that merging identical output
under common CHECK lines isn't working as it does for update_llc_test_checks.py
and the generated CHECK lines don't match against the function return type. It
would definitely be good to address these issues and move all the RISC-V ABI
tests to using update_cc_test_checks.py, but obviously I leave that for future
work in favour of landing a fix quickly.
The previous lowering was broken (as opposed to being working but not in
compliance with the official ABI). As such, I don't think there's any argument
for providing a flag for the old behaviour (as sometimes happens with other
targets after fixing ABI issues).
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D131677/new/
https://reviews.llvm.org/D131677
Files:
clang/lib/CodeGen/TargetInfo.cpp
clang/test/CodeGen/RISCV/riscv-abi.cpp
Index: clang/test/CodeGen/RISCV/riscv-abi.cpp
===================================================================
--- clang/test/CodeGen/RISCV/riscv-abi.cpp
+++ clang/test/CodeGen/RISCV/riscv-abi.cpp
@@ -39,12 +39,10 @@
float f1;
};
-// TODO: Fix incorrect lowering for hard-float ABIs.
-
// ILP32: define{{.*}} [2 x i32]
@_Z30int32_float_struct_inheritance14child2_float_s([2 x i32] %a.coerce)
-// ILP32F-ILP32D: define{{.*}} float
@_Z30int32_float_struct_inheritance14child2_float_s(float %0)
+// ILP32F-ILP32D: define{{.*}} { i32, float }
@_Z30int32_float_struct_inheritance14child2_float_s(i32 %0, float %1)
// LP64: define{{.*}} i64
@_Z30int32_float_struct_inheritance14child2_float_s(i64 %a.coerce)
-// LP64F-LP64D: define{{.*}} float
@_Z30int32_float_struct_inheritance14child2_float_s(float %0)
+// LP64F-LP64D: define{{.*}} { i32, float }
@_Z30int32_float_struct_inheritance14child2_float_s(i32 %0, float %1)
struct child2_float_s int32_float_struct_inheritance(struct child2_float_s a) {
return a;
}
@@ -57,10 +55,9 @@
int64_t i1;
};
-// TODO: Fix incorrect lowering for lp64f/lp64d ABIs.
-
// ILP32-ILP32F-ILP32D-LABEL: define{{.*}} void
@_Z30float_int64_struct_inheritance14child3_int64_s(ptr noalias
sret(%struct.child3_int64_s)
-// LP64-LP64F-LP64D-LABEL: define{{.*}} [2 x i64]
@_Z30float_int64_struct_inheritance14child3_int64_s([2 x i64] %a.coerce)
+// LP64-LABEL: define{{.*}} [2 x i64]
@_Z30float_int64_struct_inheritance14child3_int64_s([2 x i64] %a.coerce)
+// LP64F-LP64D-LABEL: define{{.*}} { float, i64 }
@_Z30float_int64_struct_inheritance14child3_int64_s(float %0, i64 %1)
struct child3_int64_s float_int64_struct_inheritance(struct child3_int64_s a) {
return a;
}
@@ -73,12 +70,10 @@
double d1;
};
-// TODO: Fix incorrect lowering for ilp32d/lp64d ABIs.
-
// ILP32-ILP32F-LABEL: define{{.*}} void
@_Z32double_double_struct_inheritance15child4_double_s(ptr noalias
sret(%struct.child4_double_s)
-// ILP32D-LABEL: define{{.*}} double
@_Z32double_double_struct_inheritance15child4_double_s(double %0)
+// ILP32D-LABEL: define{{.*}} { double, double }
@_Z32double_double_struct_inheritance15child4_double_s(double %0, double %1)
// LP64-LP64F-LABEL: define{{.*}} [2 x i64]
@_Z32double_double_struct_inheritance15child4_double_s([2 x i64] %a.coerce)
-// LP64D-LABEL: define{{.*}} double
@_Z32double_double_struct_inheritance15child4_double_s(double %0)
+// LP64D-LABEL: define{{.*}} { double, double }
@_Z32double_double_struct_inheritance15child4_double_s(double %0, double %1)
struct child4_double_s double_double_struct_inheritance(struct child4_double_s
a) {
return a;
}
Index: clang/lib/CodeGen/TargetInfo.cpp
===================================================================
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10979,6 +10979,15 @@
// Unions aren't eligible unless they're empty (which is caught above).
if (RD->isUnion())
return false;
+ // If this is a C++ record, check the bases first.
+ if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
+ for (const CXXBaseSpecifier &B : CXXRD->bases()) {
+ bool Ret = detectFPCCEligibleStructHelper(
+ B.getType(), CurOff, Field1Ty, Field1Off, Field2Ty, Field2Off);
+ if (!Ret)
+ return false;
+ }
+ }
int ZeroWidthBitFieldCount = 0;
for (const FieldDecl *FD : RD->fields()) {
const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
Index: clang/test/CodeGen/RISCV/riscv-abi.cpp
===================================================================
--- clang/test/CodeGen/RISCV/riscv-abi.cpp
+++ clang/test/CodeGen/RISCV/riscv-abi.cpp
@@ -39,12 +39,10 @@
float f1;
};
-// TODO: Fix incorrect lowering for hard-float ABIs.
-
// ILP32: define{{.*}} [2 x i32] @_Z30int32_float_struct_inheritance14child2_float_s([2 x i32] %a.coerce)
-// ILP32F-ILP32D: define{{.*}} float @_Z30int32_float_struct_inheritance14child2_float_s(float %0)
+// ILP32F-ILP32D: define{{.*}} { i32, float } @_Z30int32_float_struct_inheritance14child2_float_s(i32 %0, float %1)
// LP64: define{{.*}} i64 @_Z30int32_float_struct_inheritance14child2_float_s(i64 %a.coerce)
-// LP64F-LP64D: define{{.*}} float @_Z30int32_float_struct_inheritance14child2_float_s(float %0)
+// LP64F-LP64D: define{{.*}} { i32, float } @_Z30int32_float_struct_inheritance14child2_float_s(i32 %0, float %1)
struct child2_float_s int32_float_struct_inheritance(struct child2_float_s a) {
return a;
}
@@ -57,10 +55,9 @@
int64_t i1;
};
-// TODO: Fix incorrect lowering for lp64f/lp64d ABIs.
-
// ILP32-ILP32F-ILP32D-LABEL: define{{.*}} void @_Z30float_int64_struct_inheritance14child3_int64_s(ptr noalias sret(%struct.child3_int64_s)
-// LP64-LP64F-LP64D-LABEL: define{{.*}} [2 x i64] @_Z30float_int64_struct_inheritance14child3_int64_s([2 x i64] %a.coerce)
+// LP64-LABEL: define{{.*}} [2 x i64] @_Z30float_int64_struct_inheritance14child3_int64_s([2 x i64] %a.coerce)
+// LP64F-LP64D-LABEL: define{{.*}} { float, i64 } @_Z30float_int64_struct_inheritance14child3_int64_s(float %0, i64 %1)
struct child3_int64_s float_int64_struct_inheritance(struct child3_int64_s a) {
return a;
}
@@ -73,12 +70,10 @@
double d1;
};
-// TODO: Fix incorrect lowering for ilp32d/lp64d ABIs.
-
// ILP32-ILP32F-LABEL: define{{.*}} void @_Z32double_double_struct_inheritance15child4_double_s(ptr noalias sret(%struct.child4_double_s)
-// ILP32D-LABEL: define{{.*}} double @_Z32double_double_struct_inheritance15child4_double_s(double %0)
+// ILP32D-LABEL: define{{.*}} { double, double } @_Z32double_double_struct_inheritance15child4_double_s(double %0, double %1)
// LP64-LP64F-LABEL: define{{.*}} [2 x i64] @_Z32double_double_struct_inheritance15child4_double_s([2 x i64] %a.coerce)
-// LP64D-LABEL: define{{.*}} double @_Z32double_double_struct_inheritance15child4_double_s(double %0)
+// LP64D-LABEL: define{{.*}} { double, double } @_Z32double_double_struct_inheritance15child4_double_s(double %0, double %1)
struct child4_double_s double_double_struct_inheritance(struct child4_double_s a) {
return a;
}
Index: clang/lib/CodeGen/TargetInfo.cpp
===================================================================
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -10979,6 +10979,15 @@
// Unions aren't eligible unless they're empty (which is caught above).
if (RD->isUnion())
return false;
+ // If this is a C++ record, check the bases first.
+ if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
+ for (const CXXBaseSpecifier &B : CXXRD->bases()) {
+ bool Ret = detectFPCCEligibleStructHelper(
+ B.getType(), CurOff, Field1Ty, Field1Off, Field2Ty, Field2Off);
+ if (!Ret)
+ return false;
+ }
+ }
int ZeroWidthBitFieldCount = 0;
for (const FieldDecl *FD : RD->fields()) {
const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
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