[PATCH] D117468: [RISCV] Add intrinsic for Zbt extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117468/new/ https://reviews.llvm.org/D117468 ___

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:137 + +def GPR : RegisterClass<"RISCV", [XLenVT], 32, GPRAllocationList> { let RegInfos = XLenRI; Does putting this back the way it was and using "(add GPR)" in GPRF16,

[PATCH] D117791: [X86] Remove __builtin_ia32_pabs intrinsics and use generic __builtin_elementwise_abs

craig.topper added a comment. Just to confirm since I can't see the tests. builtin_elementwise_abs is not undefined for INT_MIN? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117791/new/ https://reviews.llvm.org/D117791 __

[PATCH] D117798: [X86] Remove __builtin_ia32_pmax/min intrinsics and use generic __builtin_elementwise_max/min

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117798/new/ https://reviews.llvm.org/D117798 ___

[PATCH] D112987: [RISCV] Bump rvv-related extensions from 0.10 to 1.0

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Comment at: clang/test/Preprocessor/riscv-target-features.c:221 // RUN: -o - | FileCheck --check-prefix=CHECK-V-EXT %s -// CHECK-V-EXT: __riscv_v 1 +//

[PATCH] D117808: [NFC][RISCV] Add end-of-line symbol in target-feature testcases

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117808/new/ https://reviews.llvm.org/D117808 ___

[PATCH] D117791: [X86] Remove __builtin_ia32_pabs intrinsics and use generic __builtin_elementwise_abs

craig.topper added a comment. In D117791#3258785 , @RKSimon wrote: > In D117791#3258602 , @craig.topper > wrote: > >> Just to confirm since I can't see the test CHECK lines. >> builtin_elementwise_abs is not und

[PATCH] D117791: [X86] Remove __builtin_ia32_pabs intrinsics and use generic __builtin_elementwise_abs

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117791/new/ https://reviews.llvm.org/D117791 ___

[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:149 RV64 = 1 << 5, + VectorMaxELen32 = 1 << 6, + VectorMaxELen64 = 1 << 7, Do we need VectorMaxELen32 isn't that the minimum? Comment at: clang/utils/Ta

[PATCH] D117829: [Clang] Add integer add/mul reduction builtins

craig.topper added a comment. In D117829#3259588 , @RKSimon wrote: > I should mention - according to > https://clang.llvm.org/docs/LanguageExtensions.html `__builtin_reduce_add()` > already exists, which I don't think is true. Does that documentation n

[PATCH] D117791: [X86] Remove __builtin_ia32_pabs intrinsics and use generic __builtin_elementwise_abs

craig.topper added inline comments. Comment at: clang/lib/Headers/avx512fintrin.h:31 + * appear in the interface though. */ +typedef signed char __v64qs __attribute__((__vector_size__(64))); + pengfei wrote: > Do we need to declare explicit `signed`? The signedne

[PATCH] D107290: [PoC][RISCV] Add support for the vscale_range attribute

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:101 + } else { +RVVBitsMin = RVVVectorBitsMinOpt; +RVVBitsMax = RVVVectorBitsMaxOpt; frasercrmck wrote: > frasercrmck wrote: > > craig.topper wrote: > > > If cla

[PATCH] D117860: [RISCV] Remove experimental prefix from rvv-related extensions.

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:429 StringRef ExtName = Feature; +dbgs() << ExtName << "\n"; bool Experimental = false; Drop this? Or wrap it in LLVM_DEBUG Repository: rG LLVM Github Monorepo CH

[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:144 Basic = 0, F = 1 << 1, D = 1 << 2, Drop F and D here? Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1319 ListSeparator LS(" && "); - if

[PATCH] D112986: [Clang][RISCV] Restrict rvv builtin-s with zve macro-s

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112986/new/ https://reviews.llvm.org/D112986 ___

[PATCH] D117913: [Clang][RISCV] Guard vmulh, vsmul correctly

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:812 RISCVPredefinedMacros |= RISCVPredefinedMacro::RV64; +if (Extension == "FullMultiply" && +(RISCVPredefinedMacros & RISCVPredefinedMacro::VectorMaxELen64)) ---

[PATCH] D117854: [RISCV] Decouple Zve* extensions and the V extension.

craig.topper added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:3978 for (StringRef F : ReqFeatures) { -if (TI.hasFeature(F)) - continue; - -// If the feature is 64bit, alter the string so it will print better in -// the diagnostic. -if (F

[PATCH] D117881: [X86] Remove avx512f integer and/or/xor/min/max reduction intrinsics and use generic equivalents

craig.topper added a comment. In D117881#3263152 , @pengfei wrote: > What's the difference between `__builtin_reduce_and` and generating a > `Intrinsic::vector_reduce_and` in code? If this is just a simplification, why > can't be applied to `add` too?

[PATCH] D117881: [X86] Remove avx512f integer and/or/xor/min/max reduction intrinsics and use generic equivalents

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117881/new/ https://reviews.llvm.org/D117881 ___

[PATCH] D117913: [Clang][RISCV] Guard vmulh, vsmul correctly

craig.topper added inline comments. Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:1321 ListSeparator LS(" && "); + // Full multiplies for EEW=64 require V. + if (PredefinedMacros & RISCVPredefinedMacro::V) It's not as useful here. Should put it on line

[PATCH] D117898: [Clang] Add elementwise saturated add/sub builtins

craig.topper added inline comments. Comment at: clang/docs/LanguageExtensions.rst:549 + T __builtin_elementwise_add_sat(T x, T y) return the sum of x and y, clamped to the range of signed or integer types + values representable by th

[PATCH] D117860: [RISCV] Remove experimental prefix from rvv-related extensions.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117860/new/ https://reviews.llvm.org/D117860 ___

[PATCH] D117913: [Clang][RISCV] Guard vmulh, vsmul correctly

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117913/new/ https://reviews.llvm.org/D117913 ___

[PATCH] D117854: [RISCV] Decouple Zve* extensions and the V extension.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:185 + bool hasVInstructionsF16() const { +return HasStdExtV || (HasStdExtZve32f && HasStdExtZfh); + } This should be `(HasStdExtV || HasStdExtZve32f) && HasStdExtZfh`. V

[PATCH] D117854: [RISCV] Decouple Zve* extensions and the V extension.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117854/new/ https://reviews.llvm.org/D117854 ___

[PATCH] D118011: [RISCV] Adjust predicates and update intrinsic for clmul and clmulh in Zbkc extension

craig.topper added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsRISCV.td:91 - // Zbc + // ZbcorZbkc def int_riscv_clmul : BitManipGPRGPRIntrinsics; Add spaces around “or” Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D118011: [RISCV] Adjust predicates and update intrinsic for clmul and clmulh in Zbkc extension

craig.topper added a comment. In D118011#3266014 , @alextsao1999 wrote: > In D118011#3265374 , @Jimerlife > wrote: > >> In D118011#3265071 , @craig.topper >> wrote: >>

[PATCH] D118011: [RISCV] Adjust predicates and update intrinsic for clmul and clmulh in Zbkc extension

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:28 +// Zbkc extension +TARGET_BUILTIN(__builtin_riscv_clmul_kc, "LiLiLi", "nc", "zbkc") +TARGET_BUILTIN(__builtin_riscv_clmulh_kc, "LiLiLi", "nc", "zbkc") After D117854, i

[PATCH] D117913: [Clang][RISCV] Guard vmulh, vsmul correctly

craig.topper accepted this revision. craig.topper added a comment. Still LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117913/new/ https://reviews.llvm.org/D117913 ___ cfe-commits mailing list cfe-c

[PATCH] D89105: [X86] Support Intel avxvnni

craig.topper added inline comments. Comment at: clang/lib/Headers/cpuid.h:199 /* Features in %eax for leaf 7 sub-leaf 1 */ +#define bit_AVXVNNI 0x0008 #define bit_AVX512BF160x0020 RKSimon wrote: > @liuchen3 https://github.com/llvm/llvm-project

[PATCH] D117647: [RISCV] Add passthru operand for RVV nomask load intrinsics.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117647/new/ https://reviews.llvm.org/D117647 ___

[PATCH] D117681: [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

craig.topper added inline comments. Herald added a subscriber: pcwang-thead. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:2342 defm _VS : VPseudoTernary, - Sched<[WriteVIRedV, ReadVIRedV, ReadVIRedV, ReadVIRedV, ReadVMask]>; + Sche

[PATCH] D117913: [Clang][RISCV] Guard vmulh, vsmul correctly

craig.topper accepted this revision. craig.topper added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D117913/new/ https://reviews.llvm.org/D117913 ___ cfe-commits mailing list cfe-commits

[PATCH] D118225: [RISCV] Decouple Zve* extensions.

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:747 // Could not implement Zve* extension and the V extension at the same time. - if (HasZve32x && HasV) + if (HasZve && HasV) return createStringError( Now we need to che

[PATCH] D118527: [X86] Promote default mtune from generic to sandybridge

craig.topper added a comment. I believe the design here was supposed to be that "generic" would be updated in X86.td on an ongoing basis to be more modern. So that if users pass -mtune=generic it would evolve over time. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https:/

[PATCH] D118578: [RISCV] Make Zfhmin in march imply F.

craig.topper created this revision. craig.topper added reviewers: asb, achieveartificialintelligence, luismarques, kito-cheng. Herald added subscribers: VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, bruceh

[PATCH] D118578: [RISCV] Make Zfhmin in march imply F.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG20875fe8a5b1: [RISCV] Make Zfhmin in march imply F. (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION h

[PATCH] D110869: [X86] Implement -fzero-call-used-regs option

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86RegisterInfo.td:647 +def GeneralPurposeRegisters : RegisterCategory<[GR64, GR32, GR16, GR8]>; +def FixedRegisters : RegisterCategory<[DEBUG_REG, CONTROL_REG, CCR, FPCCR, +

[PATCH] D110869: [X86] Implement -fzero-call-used-regs option

craig.topper added inline comments. Comment at: llvm/lib/CodeGen/PrologEpilogInserter.cpp:1182 + + if (!F.hasFnAttribute("zero-call-used-regs") || + // No need to zero call regs in main(). Should the frontend avoid putting the attribute on "main" instead of

[PATCH] D110869: [X86] Implement -fzero-call-used-regs option

craig.topper added inline comments. Comment at: llvm/test/CodeGen/X86/zero-call-used-regs-fmod.ll:15 +; CHECK-NEXT:xorps %xmm1, %xmm1 +; CHECK-NEXT:popq %rax +; CHECK-NEXT:.cfi_def_cfa_offset 8 void wrote: > craig.topper wrote: > > Is it ok that this

[PATCH] D120228: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics.

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/vmsif.ll:34 ; CHECK-NEXT:vmv1r.v v10, v0 -; CHECK-NEXT:vsetvli zero, a0, e8, mf8, tu, mu +; CHECK-NEXT:vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT:vmv1r.v v0, v9 Shou

[PATCH] D120228: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics.

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/rvv/vmsif.ll:34 ; CHECK-NEXT:vmv1r.v v10, v0 -; CHECK-NEXT:vsetvli zero, a0, e8, mf8, tu, mu +; CHECK-NEXT:vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT:vmv1r.v v0, v9 crai

[PATCH] D120307: [X86] Add helper enum for ternary intrinsics

craig.topper added inline comments. Comment at: clang/lib/Headers/avx512fintrin.h:5944 + (__v16si)(__m512i)(A), (__v16si)(__m512i)(B), (__v16si)(__m512i)(C), \ + (unsigned char)(imm), (__mmask16)-1)) + Why do we need to change the type on `imm` her

[PATCH] D120395: [X86] Prohibit arithmatic operations on type `__bfloat16`

craig.topper added a comment. In D120395#3340891 , @andrew.w.kaylor wrote: > In D120395#3340496 , @pengfei wrote: > >> Update LangRef. We use `i16` type to represent bfloat16. > > Why are we using i16 to represen

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added a comment. Here's a fix that I tested on the original repreoduce. It detects that we picked one of the new register classes and tries to redirect back to the normal GPR register class if the GPR register class has the same width. I also checked for MVT::Other to use the GPR c

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

craig.topper added a comment. Any intrinsic that takes an immediate that needs to be in certain range, needs to have code added to SemaChecking.cpp to validate the range. Look for the other places we call SemaBuiltinConstantArgRange in Sema::CheckRISCVBuiltinFunctionCall Com

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/zfinx-types.ll:5 +; RUN:| FileCheck --check-prefix=RV32IF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfh -target-abi=ilp32f < %s \ +; RUN:| FileCheck --check-prefix=RV32IF %s I'm not sur

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/test/CodeGen/RISCV/zfinx-types.ll:5 +; RUN:| FileCheck --check-prefix=RV32IF %s +; RUN: llc -mtriple=riscv32 -mattr=+zfh -target-abi=ilp32f < %s \ +; RUN:| FileCheck --check-prefix=RV32IF %s craig.toppe

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added a comment. In D93298#3354313 , @krasimir wrote: > @achieveartificialintelligence thank you for looking into this, sorry for the > late reply! > > It looks like the latest version addresses @nikic's IR reproducer with > `-mtriple=riscv3

[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

craig.topper added a comment. In D93298#3355088 , @craig.topper wrote: > In D93298#3354313 , @krasimir wrote: > >> @achieveartificialintelligence thank you for looking into this, sorry for >> the late reply! >> >>

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

craig.topper added inline comments. Herald added a project: All. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:75 +// Zbkb extension +TARGET_BUILTIN(__builtin_riscv_brev8, "ZiZi", "nc", "zbkb") +TARGET_BUILTIN(__builtin_riscv_zip, "ZiZi", "nc", "zbkb")

[PATCH] D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4671 + if (HasMask) { +for (size_t i = 2; i < NumOperands; i++) { + Ops.push_back(Op.getOperand(i)); Drop curly braces Comment at: llvm/lib/Ta

[PATCH] D120395: [X86] Prohibit arithmetic operations on type `__bfloat16`

craig.topper added a comment. In D120395#3358453 , @andrew.w.kaylor wrote: > In D120395#3356355 , @pengfei wrote: > >> Good question! This is actually the scope of ABI. Unfortunately, we don't >> have the BF16 A

[PATCH] D120395: [X86] Prohibit arithmetic operations on type `__bfloat16`

craig.topper added a comment. In D120395#3358533 , @craig.topper wrote: > In D120395#3358453 , > @andrew.w.kaylor wrote: > >> In D120395#3356355 , @pengfei >> wrote: >>

[PATCH] D103313: [RISCV][Clang] Implement support for zmmul-experimental

craig.topper added a comment. In D103313#3359628 , @ksyx wrote: > In D103313#3359310 , > @JiahaoChenConor wrote: > >> Hi, do you still continue working on this patch? > > In fact, not pretty sure what else I need

[PATCH] D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:624 + (mask_type true_mask), + VLOpFrag, (XLenVT undef))), +(!cast(inst#"_"#kind#"_"#vlmul.MX)

[PATCH] D112774: [RISCV] Support k-ext clang intrinsics

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112774/new/ https://reviews.llvm.org/D112774 ___

[PATCH] D120395: [X86] Prohibit arithmetic operations on type `__bfloat16`

craig.topper added a comment. > So at this point we have these options: > > 1. Make the `__m[128|256|512]bh` types aliases of `__m[128|256|512]i` > 2. Deprecate the `__m[128|256|512]bh` types and replace them with > `__m[128|256|512]i` > 3. Add load/store/insert/extract intrinsics for the `__bflo

[PATCH] D100830: [RISCV] [1/2] Add IR intrinsic for Zbp extension

This revision was automatically updated to reflect the committed changes. Closed by commit rGb49337bbb9de: [RISCV] [1/2] Add IR intrinsic for Zbp extension (authored by LevyHsu, committed by craig.topper). Changed prior to commit: https://reviews.llvm.org/D100830?vs=339150&id=339818#toc Reposi

[PATCH] D100819: [RISCV] Implement the vneg.v builtin.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100819/new/ https://reviews.llvm.org/D100819 ___

[PATCH] D101143: [RISCV] [1/2] Add IR intrinsic for Zbe extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:36 def riscv_unshflw: SDNode<"RISCVISD::UNSHFLW",SDT_RISCVIntBinOpW>; +def riscv_bcompress: SDNode<"RISCVISD::BCOMPRESS", SDTIntBinOp>; +def riscv_bcompressw : SDNode<"RISCVISD::BCOM

[PATCH] D100823: [RISCV] Implement the pseudo compare builtin.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100823/new/ https://reviews.llvm.org/D100823 ___

[PATCH] D101143: [RISCV] [1/2] Add IR intrinsic for Zbe extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D101143/new/ https://reviews.llvm.org/D101143 ___

[PATCH] D101248: [RISCV] [1/2] Add IR intrinsic for Zbm extension

craig.topper added inline comments. Comment at: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbm.c:16 +// +long clmul(long a, long b) { + return __builtin_riscv_bmator(a, b); clmul? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://

[PATCH] D101143: [RISCV] [1/2] Add IR intrinsic for Zbe extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG8cf54c7ff50c: [RISCV] [1/2] Add IR intrinsic for Zbe extension (authored by LevyHsu, committed by craig.topper). Changed prior to commit: https://

[PATCH] D101338: [MS] Fix crash when calling __cpuid with /EHsc and -mavx2

craig.topper added a comment. If I remember correctly cpuid.h implementation handles this. Can we copy that? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D101338/new/ https://reviews.llvm.org/D101338 ___

[PATCH] D99741: [RISCV][Clang] Add some RVV Floating-Point intrinsic functions. (vfclass, vfmerge, vfrec7, vfrsqrt7, vfsqrt)

craig.topper added a comment. I believe we had reductions at builds 7601 and 8175. It looks like there may have been an increase between builds 7979 and 7991 the build failed for a while there. I suspect "e951b04 [AArch64][S

[PATCH] D99741: [RISCV][Clang] Add some RVV Floating-Point intrinsic functions. (vfclass, vfmerge, vfrec7, vfrsqrt7, vfsqrt)

craig.topper added a comment. In D99741#2721596 , @thakis wrote: > In D99741#2721235 , @craig.topper > wrote: > >> I believe we had reductions at builds 7601 and 8175. >> >> It looks like there may have been an inc

[PATCH] D101248: [RISCV] [1/2] Add IR intrinsic for Zbm extension

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D101248/new/ https://reviews.llvm.org/D101248 ___

[PATCH] D101700: [RISCV] Reoreder masked builtin operands. Use clang_builtin_alias for all overloaded vector builtins.

craig.topper created this revision. craig.topper added reviewers: arcbbb, khchen, HsiangKai, evandro, rogfer01, frasercrmck. Herald added subscribers: StephenFan, vkmr, dexonsmith, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck

[PATCH] D101700: [RISCV] Reoreder masked builtin operands. Use clang_builtin_alias for all overloaded vector builtins.

craig.topper added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:192 - // When the order of the parameters of clang builtin do not match the order of - // C/C++ api, we use permutation index to mapping the operand from clang I remove

[PATCH] D99741: [RISCV][Clang] Add some RVV Floating-Point intrinsic functions. (vfclass, vfmerge, vfrec7, vfrsqrt7, vfsqrt)

craig.topper added a comment. In D99741#2730989 , @thakis wrote: >> ! In D99741#2721669 , @craig.topper >> wrote: >> We're preparing a patch to remove to stop testing both rv32 and rv64 on >> every test. That sho

[PATCH] D101700: [RISCV] Reorder masked builtin operands. Use clang_builtin_alias for all overloaded vector builtins.

This revision was automatically updated to reflect the committed changes. Closed by commit rGcfe3b0005f6e: [RISCV] Reorder masked builtin operands. Use clang_builtin_alias for all… (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.

[PATCH] D102051: [RISCV] Consider scalar types for required extensions.

craig.topper added a comment. LGTM too Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D102051/new/ https://reviews.llvm.org/D102051 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llv

[PATCH] D102086: [RISCV] Validate the SEW and LMUL operands to __builtin_rvv_vsetvli(max)

craig.topper created this revision. craig.topper added reviewers: evandro, HsiangKai, arcbbb, frasercrmck, rogfer01, khchen. Herald added subscribers: StephenFan, vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jon

[PATCH] D101601: [SelectionDAG] Make fast and linearize visible by clang -pre-RA-sched

craig.topper added inline comments. Comment at: llvm/test/CodeGen/Generic/pre-ra-sched.c:1 +// RUN: clang %s -mllvm -pre-RA-sched=fast -c -o - | FileCheck %s +// RUN: clang %s -mllvm -pre-RA-sched=linearize -c -o - | FileCheck %s You can't run clang from an llvm

[PATCH] D101601: [SelectionDAG] Make fast and linearize visible by clang -pre-RA-sched

craig.topper added inline comments. Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:273-276 +if (TLI->getSchedulingPreference() == Sched::Fast) + return createFastDAGScheduler(IS, OptLevel); +if (TLI->getSchedulingPreference() == Sched::Linearize) +

[PATCH] D101601: [SelectionDAG] Make fast and linearize visible by clang -pre-RA-sched

craig.topper added inline comments. Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:273-276 +if (TLI->getSchedulingPreference() == Sched::Fast) + return createFastDAGScheduler(IS, OptLevel); +if (TLI->getSchedulingPreference() == Sched::Linearize) +

[PATCH] D102086: [RISCV] Validate the SEW and LMUL operands to __builtin_rvv_vsetvli(max)

This revision was automatically updated to reflect the committed changes. Closed by commit rG18f3a14e1328: [RISCV] Validate the SEW and LMUL operands to __builtin_rvv_vsetvli(max) (authored by craig.topper). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.o

[PATCH] D102238: [TableGen] [Clang] Clean up arm_mve.td file

craig.topper added inline comments. Comment at: clang/include/clang/Basic/arm_mve.td:579 + defvar halfconst = !ne(half, "b"); + defvar halfconst = !if(!eq(half, "b"), 0, 1); Did you intend to leave the old lines commented out? Repository: rG LLVM Gith

[PATCH] D114425: [clang] Add __builtin_bswap128

craig.topper added a comment. In D114425#3216231 , @philnik wrote: > In D114425#3209794 , @craig.topper > wrote: > >> What does the builtin due if __int128 isn't supported? Even though the type >> isn't legal th

[PATCH] D114425: [clang] Add __builtin_bswap128

craig.topper added a comment. In D114425#3216531 , @Quuxplusone wrote: > In D114425#3216490 , @craig.topper > wrote: > >> In D114425#3216231 , @philnik >> wrote: >> >>>

[PATCH] D114425: [clang] Add __builtin_bswap128

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:2930 + } + [[fallthrough]]; case Builtin::BI__builtin_bswap16: Quuxplusone wrote: > Re clang-format's complaint: I would either move `[[fallthrough]];` inside > the curly braces

[PATCH] D114425: [clang] Add __builtin_bswap128

craig.topper added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:2930 + } + [[fallthrough]]; case Builtin::BI__builtin_bswap16: craig.topper wrote: > Quuxplusone wrote: > > Re clang-format's complaint: I would either move `[[fallthrough]];` in

[PATCH] D93298: [RISCV] add the part of MC layer support of Zfinx extension

craig.topper added a subscriber: khchen. craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:290 +if (ExtName == "zdinx") + Features.push_back("+zfinx"); @kito-cheng or @khchen is the right way to do this? Or should it be

[PATCH] D93298: [RISCV] add the part of MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:170 + +static DecodeStatus DecodeGPRF32RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, Can we mak

[PATCH] D93298: [RISCV] add the part of MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoF.td:124 class FPFMA_rrr_frm funct2, string opcodestr, -RegisterClass rty> +RegisterOperand rty> : RVInstR4Frmhttps://reviews.llvm.org/D93298/new/ ht

[PATCH] D93298: [RISCV] add the part of MC layer support of Zfinx extension

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoF.td:217 +let Predicates = [HasStdExtF] in { +def : FPFMADynFrmAlias; +def : FPFMADynFrmAlias; Why do the aliases not apply to Zfinx? Repository: rG LLVM Github Monorepo CHAN

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5475 + if (IndexVT.getVectorElementType() == MVT::i64 && XLenVT == MVT::i32) { +report_fatal_error("The V extension does not support EEW=64 for index " Can we trunc

[PATCH] D114425: [clang] Add __builtin_bswap128

craig.topper added reviewers: aaron.ballman, erichkeane. craig.topper added a comment. I kind of wonder if we should detect the __int128 type being requested in ASTContext::GetBuiltinType and return an error up to Sema::LazilyCreateBuiltin. Probably requires a new error code and handling for it

[PATCH] D115942: [X86][MS] Change the alignment of f80 to 16 bytes on Windows 32bits to match with ICC

craig.topper added a subscriber: efriedma. craig.topper added a comment. Does this have the same autoupgrade issues as @efriedma raised in https://reviews.llvm.org/D86310 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115942/new/ https://reviews.ll

[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106518/new/ https://reviews.llvm.org/D106518 ___

[PATCH] D116856: [docs] Fix documentation of -fstrict-float-cast-overflow after D115804.

craig.topper created this revision. craig.topper added reviewers: spatel, nikic. craig.topper requested review of this revision. Herald added a project: clang. Previously this was documented as having the behavior of the "target's native float-to-int conversion". After D115804

[PATCH] D116856: [docs] Fix documentation of -fno-strict-float-cast-overflow after D115804.

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGdb4cb4668b04: [docs] Fix documentation of -fno-strict-float-cast-overflow after D115804. (authored by craig.topper). Repository: rG LLVM Github Mo

[PATCH] D116935: [IRBuilder] Introduce folder using inst-simplify, use for Or fold.

craig.topper added a comment. If I remember correctly, the Or and And folds for 0 and all 1s are there to optimize bitfield codegen for the frontend. Are we losing that optimization if this patch goes in before switching clang to InstSimplifyFolder? Repository: rG LLVM Github Monorepo CHANG

[PATCH] D116935: [IRBuilder] Introduce folder using inst-simplify, use for Or fold.

craig.topper added a comment. In D116935#3232203 , @lebedev.ri wrote: > In D116935#3232126 , @craig.topper > wrote: > >> If I remember correctly, the Or and And folds for 0 and all 1s are there to >> optimize b

[PATCH] D116935: [IRBuilder] Introduce folder using inst-simplify, use for Or fold.

craig.topper added a comment. In D116935#3232584 , @fhahn wrote: > Rebased and made sure comments are consistent between different folders. > > In D116935#3232227 , @craig.topper > wrote: > >> In D116935#3232203

[PATCH] D116994: [RISCV] Add bfp and bfpw intrinsic in zbf extension

craig.topper added inline comments. Comment at: clang/include/clang/Basic/BuiltinsRISCV.def:36 +// zbf extension +TARGET_BUILTIN(__builtin_riscv_bfp, "LiLiLi", "nc", "experimental-zbf") Capital Z Comment at: clang/include/clang/Basic/Builtins

[PATCH] D116935: [IRBuilder] Introduce folder using inst-simplify, use for Or fold.

craig.topper added a comment. In D116935#3233751 , @fhahn wrote: > Another rebase. I am planning to land this later today, unless there are > additional concerns with respect to the fold in Clang after my latest > response. Thanks, Florian. I have no a

[PATCH] D108694: [RISCV] Add the zvl extension according to the v1.0 spec

craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:774 + while (!WorkList.empty()) { +auto ExtName = WorkList.pop_back_val(); +auto I = llvm::lower_bound(ImpliedExts, ExtName); Use StringRef instead of auto here.

<    14   15   16   17   18   19   20   21   22   >