https://github.com/djtodoro closed
https://github.com/llvm/llvm-project/pull/117865
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@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1,
(AddiPair:$rs2)),
}
//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Pre
@@ -426,6 +426,12 @@ The current vendor extensions supported are:
``Xwchc``
LLVM implements `the custom compressed opcodes present in some QingKe cores`
by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes
by the name "XW".
+``xmipscmove``
@@ -367,6 +372,16 @@ class RISCVPassConfig : public TargetPassConfig {
DAG->addMutation(createStoreClusterDAGMutation(
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
}
+
+const RISCVSubtarget &ST = C->MF->getSubtarget();
+if (!ST.getMacroFusi
@@ -62,6 +62,20 @@ static cl::opt RISCVMinimumJumpTableEntries(
"riscv-min-jump-table-entries", cl::Hidden,
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
+static cl::opt
djtodoro wrote:
Well, I do not think so.
https://gith
@@ -1447,6 +1447,23 @@ def TuneConditionalCompressedMoveFusion
def HasConditionalMoveFusion :
Predicate<"Subtarget->hasConditionalMoveFusion()">;
def NoConditionalMoveFusion :
Predicate<"!Subtarget->hasConditionalMoveFusion()">;
+def TuneMIPSP8700
+: SubtargetFeature<"m
@@ -2710,6 +2713,45 @@ MachineInstr
*RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI,
.setMemRefs(MemI.memoperands())
.setMIFlags(MemI.getFlags());
}
+bool RISCVInstrInfo::isPairableLdStInstOpc(unsigned Opc) {
+ switch (Opc) {
+ default:
+return false;
+
@@ -1447,6 +1447,23 @@ def TuneConditionalCompressedMoveFusion
def HasConditionalMoveFusion :
Predicate<"Subtarget->hasConditionalMoveFusion()">;
def NoConditionalMoveFusion :
Predicate<"!Subtarget->hasConditionalMoveFusion()">;
+def TuneMIPSP8700
+: SubtargetFeature<"m
@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1,
(AddiPair:$rs2)),
}
//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Pre
@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1,
(AddiPair:$rs2)),
}
//===--===//
+
djtodoro wrote:
Addressed in https://github.com/llvm/llvm-project/pull/121394
https://github.
@@ -514,6 +514,78 @@ class RVInstJhttps://github.com/llvm/llvm-project/pull/121394
https://github.com/llvm/llvm-project/pull/117865
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@@ -298,6 +298,15 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
+ /// Return true if pairing the given load or store may be paired with
another.
+ static bool isPairableLdStInstOpc(unsigned Op
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -78,6 +78,19 @@ def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
// to change to the appropriate rv32/rv64 version.
def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>,
GenericTuneInfo;
+def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
+
@@ -78,6 +78,19 @@ def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
// to change to the appropriate rv32/rv64 version.
def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>,
GenericTuneInfo;
+def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
+
@@ -252,9 +252,17 @@ static const char *getLDMOption(const llvm::Triple &T,
const ArgList &Args) {
case llvm::Triple::ppc64le:
return "elf64lppc";
case llvm::Triple::riscv32:
-return "elf32lriscv";
- case llvm::Triple::riscv64:
-return "elf64lriscv";
+ case l
@@ -22,6 +22,7 @@ def WriteIMul32 : SchedWrite;// 32-bit multiply on
RV64I
def WriteJmp: SchedWrite;// Jump
def WriteJal: SchedWrite;// Jump and link
def WriteJalr : SchedWrite;// Jump and link register
+def WriteJmpReg : SchedWrit
@@ -0,0 +1,279 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
asb wrote:
> RFC:
> https://discourse.llvm.org/t/rfc-risc-v-add-support-for-mips-p8700-cpu/83365
Thank you Djordje - I've left some high level comments in response to your RFC
post
https://github.com/llvm/llvm-project/pull/117865
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@@ -3137,6 +3205,45 @@ bool Generic_GCC::IsIntegratedAssemblerDefault() const {
case llvm::Triple::nvptx64:
case llvm::Triple::xcore:
return false;
+ case llvm::Triple::aarch64:
+ case llvm::Triple::aarch64_be:
+ case llvm::Triple::amdgcn:
+ case llvm::Triple::arm:
@@ -252,9 +252,17 @@ static const char *getLDMOption(const llvm::Triple &T,
const ArgList &Args) {
case llvm::Triple::ppc64le:
return "elf64lppc";
case llvm::Triple::riscv32:
-return "elf32lriscv";
- case llvm::Triple::riscv64:
-return "elf64lriscv";
+ case l
https://github.com/alexrp edited
https://github.com/llvm/llvm-project/pull/117865
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@@ -252,9 +252,17 @@ static const char *getLDMOption(const llvm::Triple &T,
const ArgList &Args) {
case llvm::Triple::ppc64le:
return "elf64lppc";
case llvm::Triple::riscv32:
-return "elf32lriscv";
- case llvm::Triple::riscv64:
-return "elf64lriscv";
+ case l
@@ -22,6 +22,7 @@ def WriteIMul32 : SchedWrite;// 32-bit multiply on
RV64I
def WriteJmp: SchedWrite;// Jump
def WriteJal: SchedWrite;// Jump and link
def WriteJalr : SchedWrite;// Jump and link register
+def WriteJmpReg : SchedWrit
@@ -0,0 +1,279 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -298,6 +298,15 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
+ /// Return true if pairing the given load or store may be paired with
another.
+ static bool isPairableLdStInstOpc(unsigned Op
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1,
(AddiPair:$rs2)),
}
//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Pre
@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1,
(AddiPair:$rs2)),
}
//===--===//
+
topperc wrote:
please add these to a new MIPS specific file like other vendor extensions.
htt
@@ -2017,6 +2169,74 @@ def : Pat<(binop_allwusers GPR:$rs1,
(AddiPair:$rs2)),
}
//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Pre
@@ -514,6 +514,78 @@ class RVInstJhttps://github.com/llvm/llvm-project/pull/117865
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@@ -367,6 +372,16 @@ class RISCVPassConfig : public TargetPassConfig {
DAG->addMutation(createStoreClusterDAGMutation(
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
}
+
+const RISCVSubtarget &ST = C->MF->getSubtarget();
+if (!ST.getMacroFusi
@@ -427,7 +427,7 @@ def UNZIP_RV32 : Unary_r<0b1000, 0b101, "unzip">,
// Pseudo Instructions
//===--===//
-let Predicates = [HasStdExtZba, IsRV64] in {
+let Predicates = [HasStdExtZba, IsRV64], EmitPr
@@ -2710,6 +2713,45 @@ MachineInstr
*RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI,
.setMemRefs(MemI.memoperands())
.setMIFlags(MemI.getFlags());
}
+bool RISCVInstrInfo::isPairableLdStInstOpc(unsigned Opc) {
+ switch (Opc) {
+ default:
+return false;
+
@@ -62,6 +62,20 @@ static cl::opt RISCVMinimumJumpTableEntries(
"riscv-min-jump-table-entries", cl::Hidden,
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
+static cl::opt
michaelmaitland wrote:
Is this a duplicate of `EnableM
@@ -1447,6 +1447,23 @@ def TuneConditionalCompressedMoveFusion
def HasConditionalMoveFusion :
Predicate<"Subtarget->hasConditionalMoveFusion()">;
def NoConditionalMoveFusion :
Predicate<"!Subtarget->hasConditionalMoveFusion()">;
+def TuneMIPSP8700
+: SubtargetFeature<"m
@@ -0,0 +1,371 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -1447,6 +1447,23 @@ def TuneConditionalCompressedMoveFusion
def HasConditionalMoveFusion :
Predicate<"Subtarget->hasConditionalMoveFusion()">;
def NoConditionalMoveFusion :
Predicate<"!Subtarget->hasConditionalMoveFusion()">;
+def TuneMIPSP8700
+: SubtargetFeature<"m
@@ -426,6 +426,12 @@ The current vendor extensions supported are:
``Xwchc``
LLVM implements `the custom compressed opcodes present in some QingKe cores`
by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes
by the name "XW".
+``xmipscmove``
@@ -0,0 +1,279 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
michaelmaitland wrote:
Please split a3ed3550aed41e102bf41ec347f19f9a3c339b2b into multiple commits
(and eventually PRs). One for CPU definition and one for scheduler model.
https://github.com/llvm/llvm-project/pull/117865
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@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,158 @@
+//===--- RISCVRemoveBackToBackBranches.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/djtodoro edited
https://github.com/llvm/llvm-project/pull/117865
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jrtc27 wrote:
Extensions belong in their own PRs, ditto CPU/scheduler, driver and any
additional passes. Each PR is one commit and this is not one commit's worth of
changes.
https://github.com/llvm/llvm-project/pull/117865
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djtodoro wrote:
> Extensions belong in their own PRs, ditto CPU/scheduler, driver and any
> additional passes. Each PR is one commit and this is not one commit's worth
> of changes.
@jrtc27 Yes! I agree. That is why I marked it as `Draft`. The next step is to
divide it into multiple commits.
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 86b69c31642e98f8357df62c09d118ad1da4e16a
7dea5e91019402c5d78349f44f2b33a4f02c2b90 --e
llvmbot wrote:
@llvm/pr-subscribers-mc
Author: Djordje Todorovic (djtodoro)
Changes
The P8700 is a high-performance processor from MIPS designed to meet the
demands of modern workloads, offering exceptional scalability and efficiency.
It builds on MIPS's established architectural strengt
llvmbot wrote:
@llvm/pr-subscribers-llvm-globalisel
Author: Djordje Todorovic (djtodoro)
Changes
The P8700 is a high-performance processor from MIPS designed to meet the
demands of modern workloads, offering exceptional scalability and efficiency.
It builds on MIPS's established architec
https://github.com/djtodoro converted_to_draft
https://github.com/llvm/llvm-project/pull/117865
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