================ @@ -0,0 +1,279 @@ +//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -----*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// RISC-V processor by MIPS. +//===----------------------------------------------------------------------===// + +def MIPSP8700Model : SchedMachineModel { + int IssueWidth = 4; + int MicroOpBufferSize = 96; // as per the specification + int LoadLatency = 4; + int MispredictPenalty = 8; // TODO: Estimated + let CompleteModel = 0; +} + +let SchedModel = MIPSP8700Model in { + +// Handle ALQ Pipelines. +def p8700ALQ : ProcResource<1> { let BufferSize = 16; } +def p8700IssueALU : ProcResource<1> { let Super = p8700ALQ; } ---------------- djtodoro wrote:
Not needed. Addressed in https://github.com/llvm/llvm-project/pull/119885. https://github.com/llvm/llvm-project/pull/117865 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
