================ @@ -78,6 +78,19 @@ def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64", // to change to the appropriate rv32/rv64 version. def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo; +def MIPS_P8700 : RISCVProcessorModel<"mips-p8700", + MIPSP8700Model, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtA, ---------------- jrtc27 wrote:
Yeah, if you're only implementing AMOs through trap-and-emulate then there's really little point telling software they exist. LR/SC will be orders of magnitude faster. You don't have an RV64GCZba_Zbb core, you have an RV64IMFDCZba_Zbb_Zalrsc core, and bodge in Zaamo in order to emulate being able to run RV64GC software. But claiming RV64GCZba_Zbb is just misleading to software, it'll perform atrociously if it's actually using atomics. https://github.com/llvm/llvm-project/pull/117865 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
