preames wrote:
We have discussed whether to accept non-conforming vendor extensions in the
past. Our consensus was clearly documented in RISCVUsage.rst in the statement
" In particular, we expect to eventually accept both custom extensions and
non-conforming extensions."
This is a non-confor
https://github.com/preames approved this pull request.
LGTM
One point of possible concern is that the version number collapses to 0.0 in
all of our tracking. I'm fine with this, but it's unfortunate, and possible
confusing. If the next version is 0.1, we're fine. If the next version is
0.0
https://github.com/preames closed
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@@ -10,6 +10,46 @@
//
//===--===//
+class RVInstVXI funct6, RISCVVFormat opv, dag outs, dag ins,
+string opcodestr, string argstr>
+: RVInst {
+ bits<5> imm;
+ bits<5> rs1;
+ bits<5> vd
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/128773
>From 7eab3c685c23c477cbeb3df13fb9e01eacf2378c Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Tue, 25 Feb 2025 11:16:41 -0800
Subject: [PATCH 1/4] [RISCV][MC] Add assembler support for XRivosVisni
This impl
@@ -10,6 +10,46 @@
//
//===--===//
+class RVInstVXI funct6, RISCVVFormat opv, dag outs, dag ins,
+string opcodestr, string argstr>
+: RVInst {
+ bits<5> imm;
+ bits<5> rs1;
+ bits<5> vd
@@ -1376,6 +1376,13 @@ def HasVendorXqcilo
// Rivos Extension(s)
+def FeatureVendorXRivosVisni
+: RISCVExperimentalExtension<0, 1, "Rivos Vector Small Integer New">;
+def HasVendorXRivosVisni
+: Predicate<"Subtarget->hasVendorXRivosVisni()">,
+ AssemblerPredicat
@@ -25,3 +65,27 @@ defm RI_VZIP2B_V : VALU_IV_V<"ri.vzip2b", 0b010100>;
defm RI_VUNZIP2A_V : VALU_IV_V<"ri.vunzip2a", 0b001000>;
defm RI_VUNZIP2B_V : VALU_IV_V<"ri.vunzip2b", 0b011000>;
}
+
+//===--===//
+// XR
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/128773
>From 7eab3c685c23c477cbeb3df13fb9e01eacf2378c Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Tue, 25 Feb 2025 11:16:41 -0800
Subject: [PATCH 1/3] [RISCV][MC] Add assembler support for XRivosVisni
This impl
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/128773
>From 7eab3c685c23c477cbeb3df13fb9e01eacf2378c Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Tue, 25 Feb 2025 11:16:41 -0800
Subject: [PATCH 1/2] [RISCV][MC] Add assembler support for XRivosVisni
This impl
https://github.com/preames created
https://github.com/llvm/llvm-project/pull/128773
This implements assembler support for the XRivosVisni custom/vendor extension
from Rivos Inc. which is defined in:
https://github.com/rivosinc/rivos-custom-extensions (See src/xrivosvisni.adoc)
Codegen support
preames wrote:
> But the purpose we add vl/vtype dependencies is to prevent the Post-RA
> scheduler moving vsetvl instruction across inline assembly. I'm not sure if
> there's better approach to solve this problem.
Maybe have RISCVInsertVSETVLI add implicit use operands to the inline assembly
https://github.com/preames closed
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preames wrote:
> LGTM
@topperc Could you double check to make sure this still holds? I'd missed the
register overlap constraint, so I added that plus testing both for that case,
and the masked instruction case which I'd not previously had tests for.
https://github.com/llvm/llvm-project/pul
@@ -0,0 +1,27 @@
+//===-- RISCVInstrInfoXRivos.td *- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/127694
>From 81e50773d34f788df750bf6d4a4cd8c727a6b148 Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Wed, 22 Jan 2025 12:54:24 -0800
Subject: [PATCH 1/3] [RISCV] Assembler support for XRivosVizip
This implements a
preames wrote:
> > > I am kind of confused now. So the situation here is that RVIOS has
> > > already implemented these vendor extensions in cores and RVIOS is also
> > > trying to make these extensions official RVI standards, right?
> >
> >
> > You're confusing two things. We (Rivos) have de
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/127694
>From 81e50773d34f788df750bf6d4a4cd8c727a6b148 Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Wed, 22 Jan 2025 12:54:24 -0800
Subject: [PATCH 1/2] [RISCV] Assembler support for XRivosVizip
This implements a
@@ -0,0 +1,27 @@
+//===-- RISCVInstrInfoXRivos.td --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache
preames wrote:
> I am kind of confused now. So the situation here is that RVIOS has already
> implemented these vendor extensions in cores and RVIOS is also trying to make
> these extensions official RVI standards, right?
You're confusing two things. We (Rivos) have defined a set of custom ve
@@ -721,6 +721,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst
&MI, uint64_t &Size,
"Qualcomm uC Conditional Move custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciint, DecoderTableXqciint32,
"Qu
@@ -202,6 +202,7 @@
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large
Offset Load Store Extension)
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load
Store Multiple Extension)
// CHECK-NEXT: xqcisls 0.2
@@ -202,6 +202,7 @@
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large
Offset Load Store Extension)
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load
Store Multiple Extension)
// CHECK-NEXT: xqcisls 0.2
https://github.com/preames commented:
(inline comments on possible discussion points)
https://github.com/llvm/llvm-project/pull/127694
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@@ -721,6 +721,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst
&MI, uint64_t &Size,
"Qualcomm uC Conditional Move custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciint, DecoderTableXqciint32,
"Qu
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/127694
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https://github.com/preames created
https://github.com/llvm/llvm-project/pull/127694
This implements assembler support for the XRivosVizip custom/vendor extension
from Rivos Inc. which is defined in:
https://github.com/rivosinc/rivos-custom-extensions (See src/xrivosvizip.adoc)
Codegen support
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/126352
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https://github.com/preames approved this pull request.
LGTM w/requested change.
Another option would be to expand a section on joining discord somewhere, and
then scatter links to that in the docs instead of the invite link itself.
https://github.com/llvm/llvm-project/pull/126352
@@ -149,7 +149,7 @@ Open Clang Projects
If you hit a bug with Clang, it is very useful for us if you reduce the code
that demonstrates the problem down to something small. There are many ways to
do this; ask on https://discourse.llvm.org/c/clang";>Discourse,
-https://discord.co
https://github.com/preames approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/122164
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@@ -0,0 +1,494 @@
+//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,494 @@
+//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,494 @@
+//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
preames wrote:
> I am not sue about the acceptance of the "tt" naming here given we use full
> names for all other vendors in this context. Can you raise that point
> specifically at the next RISCV sync up call for discussion?
Just to close the loop. We did briefly touch on this in the sync u
preames wrote:
I am not sue about the acceptance of the "tt" naming here given we use full
names for all other vendors in this context. Can you raise that point
specifically at the next RISCV sync up call for discussion?
https://github.com/llvm/llvm-project/pull/115100
_
preames wrote:
Why? There has only ever been one version of the features array, and that has
not yet been published. Why do we need a version check here at all?
https://github.com/llvm/llvm-project/pull/110098
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https://github.com/preames approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/109651
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@@ -10319,8 +10319,10 @@ Sema::ActOnFunctionDeclarator(Scope *S, Declarator &D,
DeclContext *DC,
// Handle attributes.
ProcessDeclAttributes(S, NewFD, D);
const auto *NewTVA = NewFD->getAttr();
- if (NewTVA && !NewTVA->isDefaultVersion() &&
- !Context.getTargetInfo
@@ -11027,13 +11029,27 @@ static bool CheckMultiVersionValue(Sema &S, const
FunctionDecl *FD) {
}
if (TVA) {
-llvm::SmallVector Feats;
-TVA->getFeatures(Feats);
-for (const auto &Feat : Feats) {
- if (!TargetInfo.validateCpuSupports(Feat)) {
-S.Di
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/99040
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https://github.com/preames approved this pull request.
LGTM
(I only did a quick pass on this version assuming mostly unchanged from prior.
Wanted to explicitly chime in with support for the priority syntax.)
https://github.com/llvm/llvm-project/pull/85786
_
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/85786
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preames wrote:
@BeMg Can you rebase over commit
[d1e28e2](https://github.com/llvm/llvm-project/commit/d1e28e2a7bd4642e6a5ec963a5ca2ad2ba1b2b59)?
https://github.com/llvm/llvm-project/pull/85786
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ht
preames wrote:
I've gone ahead and merged this into main. We have missed the branch creation,
so without further action this will not be included in 19.x. We need to ensure
the constructor change for compiler-rt lands, and then backport them together
if we choose to.
https://github.com/ll
https://github.com/preames closed
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https://github.com/preames approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/99898
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@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/99700
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https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/99700
>From ddf2c58a864576586b89cc611e2bea15b8cf18ba Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Fri, 19 Jul 2024 10:46:19 -0700
Subject: [PATCH 1/4] [WIP][RISCV] Support __builtin_cpu_init and
__builtin_cpu_su
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/99700
>From ddf2c58a864576586b89cc611e2bea15b8cf18ba Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Fri, 19 Jul 2024 10:46:19 -0700
Subject: [PATCH 1/3] [WIP][RISCV] Support __builtin_cpu_init and
__builtin_cpu_su
@@ -1020,3 +1020,64 @@ std::string
RISCVISAInfo::getTargetFeatureForExtension(StringRef Ext) {
return isExperimentalExtension(Name) ? "experimental-" + Name.str()
: Name.str();
}
+
+struct RISCVExtBit {
+ const StringRef ext;
+ uint64
https://github.com/preames updated
https://github.com/llvm/llvm-project/pull/99700
>From ddf2c58a864576586b89cc611e2bea15b8cf18ba Mon Sep 17 00:00:00 2001
From: Philip Reames
Date: Fri, 19 Jul 2024 10:46:19 -0700
Subject: [PATCH 1/2] [WIP][RISCV] Support __builtin_cpu_init and
__builtin_cpu_su
preames wrote:
I have posted a cut down version of this which implements
__builtin_cpu_supports and __builtin_cpu_init. I posted an early draft to
avoid potentially duplicated work. If we're going to get any part of this in
for the release branch, we don't have much time. See
https://githu
https://github.com/preames created
https://github.com/llvm/llvm-project/pull/99700
This implements the __builtin_cpu_init and __builtin_cpu_supports builtin
routines based on the compiler runtime changes in
https://github.com/llvm/llvm-project/pull/85790.
This is inspired by https://github.co
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned Feat
https://github.com/preames requested changes to this pull request.
At a high level, I think this is a quite a ways from being ready to land.
There's both code style issues (mostly false generality), and missing bits of
the user interface on the clang side. I do not think this has any real ser
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
@@ -63,9 +63,32 @@ class RISCVABIInfo : public DefaultABIInfo {
CharUnits Field2Off) const;
ABIArgInfo coerceVLSVector(QualType Ty) const;
+
+ using ABIInfo::appendAttributeMangling;
+ void appendAttributeMangling(TargetClones
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
@@ -2854,10 +2854,121 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+EmitRISCVMultiVersionResolver(Resolver,
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned Feat
@@ -119,6 +119,51 @@ void getFeaturesForCPU(StringRef CPU,
else
EnabledFeatures.push_back(F.substr(1));
}
+
+namespace RISCVExtensionBitmaskTable {
+#define GET_RISCVExtensionBitmaskTable_IMPL
+#include "llvm/TargetParser/RISCVTargetParserDef.inc"
+
+} // namespace RI
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/85786
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@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned Feat
@@ -14266,6 +14277,71 @@
CodeGenFunction::EmitAArch64CpuSupports(ArrayRef FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned Feat
https://github.com/preames approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/99070
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preames wrote:
All of the dependent pieces have landed. For ease of future reference:
* https://github.com/llvm/llvm-project/pull/90266 is the attributes emission
(off by default).
* https://github.com/llvm/llvm-project/pull/97347 is the LLD change.
* https://github.com/llvm/llvm-project/pull/8
Author: Philip Reames
Date: 2024-07-09T10:45:56-07:00
New Revision: 90d79e258ee9c6935ffeac405b3e9b74542068aa
URL:
https://github.com/llvm/llvm-project/commit/90d79e258ee9c6935ffeac405b3e9b74542068aa
DIFF:
https://github.com/llvm/llvm-project/commit/90d79e258ee9c6935ffeac405b3e9b74542068aa.diff
@@ -290,8 +290,24 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList
&Args,
// 2. Get march (isa string) based on `-mcpu=`
if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef CPU = A->getValue();
-if (CPU == "native")
+if (CPU == "nativ
https://github.com/preames approved this pull request.
LGTM w/minor comments
https://github.com/llvm/llvm-project/pull/94352
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@@ -83,8 +83,14 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
// and other features (ex. mirco architecture feature) from mcpu
if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
StringRef CPU = A->getValue();
-if (CPU == "nat
@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap &Features) {
@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap &Features) {
@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
return true;
}
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+ int64_t Key;
+ uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap &Features) {
https://github.com/preames edited
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preames wrote:
Once https://github.com/llvm/llvm-project/pull/90266 lands with the attributes
off by default, I think we should move forward with relanding this. We do need
one change though - our TSO lowering unconditionally uses the A6S ABI variant -
right? - so we need to adjust the attrib
preames wrote:
Chatted with @patrick-rivos on the status of TSO. The following is my summary:
* psABI changes have landed which change the default for WMO to what we used to
call the "A6/A7 compatibility table". The TSO change which landed to psABI
defines a mapping which is compatible with t
Author: Philip Reames
Date: 2024-06-24T08:32:28-07:00
New Revision: f985a8826bfa4ca3d23e654185de35e30ea6dc79
URL:
https://github.com/llvm/llvm-project/commit/f985a8826bfa4ca3d23e654185de35e30ea6dc79
DIFF:
https://github.com/llvm/llvm-project/commit/f985a8826bfa4ca3d23e654185de35e30ea6dc79.diff
preames wrote:
> I think @preames told me he was keeping this experimental for a reason.
Yes, revert pending.
The concern here is that there are multiple possible ABIs here, and at the
point I implemented this, the ABI chosen in my initial set of patches was
compatible with the then current W
preames wrote:
Given the concern about breaking configurations w/no-integrated-as and older
binutils, can someone summarize here which versions of binutils are known to
work/not work after this change? This will likely become the key search result
for such breakage, and having it well documen
@@ -326,6 +326,27 @@ def SYNTACORE_SCR1_MAX :
RISCVProcessorModel<"syntacore-scr1-max",
FeatureStdExtC],
[TuneNoDefaultUnroll]>;
+def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacor
preames wrote:
> Will this core have active support on the LLVM side?
I can't speak for the vendor, but I'll say that I'm interested in having this
supported upstream. This looks to be a reasonable rva22 dev board w/V1.0, and
having in tree support seems worthwhile. I've ordered one of these
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/94564
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@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+
https://github.com/preames edited
https://github.com/llvm/llvm-project/pull/94564
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https://github.com/preames requested changes to this pull request.
https://github.com/llvm/llvm-project/pull/94564
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@@ -8,7 +8,8 @@
// CHECK: entry:
// CHECK-NEXT: %retval = alloca i32
// CHECK-NEXT: store i32 0, ptr %retval
-// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 true to i32
+// CHECK-NEXT: [[CMP:%.*]] = icmp ne ptr @b, @a
+// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32
@@ -8,7 +8,8 @@
// CHECK: entry:
// CHECK-NEXT: %retval = alloca i32
// CHECK-NEXT: store i32 0, ptr %retval
-// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 true to i32
+// CHECK-NEXT: [[CMP:%.*]] = icmp ne ptr @b, @a
+// CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32
https://github.com/preames approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/88538
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https://github.com/preames approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/88954
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@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("r
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("r
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("r
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("r
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