https://github.com/mshockwave approved this pull request.
https://github.com/llvm/llvm-project/pull/140979
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https://github.com/mshockwave approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/140681
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@@ -648,6 +648,38 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
FeatureStdExtZcb,
FeatureStdExtZcmp]>;
+def ANDES_A25 : RISCVProcessorModel<"andes-a25",
+
@@ -648,6 +648,38 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
FeatureStdExtZcb,
FeatureStdExtZcmp]>;
+def ANDES_A25 : RISCVProcessorModel<"andes-a25",
+
mshockwave wrote:
I propose writing `test/Driver/print-enabled-extensions` tests instead for
testing extensions.
https://github.com/llvm/llvm-project/pull/140681
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https://github.com/mshockwave approved this pull request.
LGTM, thanks
https://github.com/llvm/llvm-project/pull/134985
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mshockwave wrote:
> LLVM Buildbot has detected a new failure on builder `arc-builder` running on
> `arc-worker` while building `clang,llvm` at step 6
> "test-build-unified-tree-check-all".
>
> Full details are available at:
> https://lab.llvm.org/buildbot/#/builders/3/builds/15497
>
> Here i
https://github.com/mshockwave closed
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@@ -0,0 +1,724 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips64 -mcpu=i6500 < %s | FileCheck %s --check-prefixes=ALL
+; RUN: llc -mtriple=mips64 -mcpu=i6400 < %s | FileCheck %s --check-prefixes=ALL
mshoc
mshockwave wrote:
I just noticed there is already `test/CodeGen/Mips/msa/arithmetic.ll` (which
this file is probably based on), could add additional `RUN` lines to that file
instead, in order to reuse it?
https://github.com/llvm/llvm-project/pull/134985
_
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https://github.com/mshockwave commented:
Sorry I missed the update. I only have some minor comments
https://github.com/llvm/llvm-project/pull/134985
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https://github.com/llvm/llvm-project/pull/137865
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mshockwave wrote:
> If the `"-target-feature" "+sscofpmf"` was already present in the test
> output, just not looked for, then I think you should just mark this as
> `[NFC]`.
Agree. It's updated now.
https://github.com/llvm/llvm-project/pull/137865
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@@ -365,6 +365,32 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670",
SiFiveP600Model,
TuneVXRMPipelineFlush,
TunePostRAScheduler]>;
+def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSched
https://github.com/mshockwave created
https://github.com/llvm/llvm-project/pull/137865
Sscofpmf is already in RVA23S64 and Zicsr is in RVA20U64. I also added a test
to check Sscofpmf. This is effectively an NFC.
---
This is found by #137864
>From 3ac537e4fe391464870254d0a9c81fe9f58c195a
@@ -365,6 +365,32 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670",
SiFiveP600Model,
TuneVXRMPipelineFlush,
TunePostRAScheduler]>;
+def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSched
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/137725
>From c8584c12408bcf8739558b3d9e0c2190f1d95bea Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Mon, 28 Apr 2025 14:12:13 -0700
Subject: [PATCH 1/2] [RISCV] Add processor definition for SiFive P870
---
.../
https://github.com/mshockwave approved this pull request.
https://github.com/llvm/llvm-project/pull/123193
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@@ -0,0 +1,9 @@
+// Check target CPUs are correctly passed.
+
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 -mmsa | FileCheck
-check-prefix=MCPU-I6400 %s
+// MCPU-I6400: "-target-cpu" "i6400"
mshockwave wrote:
usually we will check all the features
@@ -0,0 +1,358 @@
+//===-- RISCVInstrInfoXAndes.td *- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
mshockwave wrote:
> If only `CGBuiltin.cpp` and `ARM.cpp` is touched/updated, I see a large
> difference
This. IMHO I think quality-of-life improvements on incremental build --
especially for LLVM developers -- is already a big thing that can justify this
patch by itself.
Regarding the margi
mshockwave wrote:
> @pawosm-arm - I've removed the reviewers because it is not quite ready yet. I
> need to investigate the potential regressions shown by the RISCV tests.
you can also turn this PR into a draft if you want
https://github.com/llvm/llvm-project/pull/130973
__
@@ -1376,6 +1376,13 @@ def HasVendorXqcilo
// Rivos Extension(s)
+def FeatureVendorXRivosVisni
+: RISCVExperimentalExtension<0, 1, "Rivos Vector Small Integer New">;
+def HasVendorXRivosVisni
+: Predicate<"Subtarget->hasVendorXRivosVisni()">,
+ AssemblerPredicat
@@ -1376,6 +1376,13 @@ def HasVendorXqcilo
// Rivos Extension(s)
+def FeatureVendorXRivosVisni
+: RISCVExperimentalExtension<0, 1, "Rivos Vector Small Integer New">;
+def HasVendorXRivosVisni
+: Predicate<"Subtarget->hasVendorXRivosVisni()">,
+ AssemblerPredicat
mshockwave wrote:
I think what @wangpc-pp advocated here (please correct me if I'm wrong) was
that user should be responsible annotating these registers as clobbered so that
we have more freedom on scheduling when the inline assembly is not using any
vector instructions. While other approaches
mshockwave wrote:
> > LLVM Buildbot has detected a new failure on builder `flang-x86_64-windows`
> > running on `minipc-ryzen-win` while building `clang,llvm` at step 7
> > "test-build-unified-tree-check-flang".
> > Full details are available at:
> > https://lab.llvm.org/buildbot/#/builders/16
@@ -582,4 +586,15 @@ unsigned RISCVMCCodeEmitter::getRegReg(const MCInst &MI,
unsigned OpNo,
return Op | Op1 << 5;
}
+unsigned RISCVMCCodeEmitter::getRVPGPRPair(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl &Fixups,
+
@@ -224,6 +224,13 @@ static DecodeStatus DecodeGPRPairRegisterClass(MCInst
&Inst, uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus decodeRVPGPRPair(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+
https://github.com/mshockwave approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/123072
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@@ -3415,10 +3419,11 @@ namespace {
AttrClass *findSuperClass(const Record *R) const {
// TableGen flattens the superclass list, so we just need to walk it
// in reverse.
- auto SuperClasses = R->getSuperClasses();
- for (signed i = 0, e = SuperClasses
@@ -1718,15 +1719,30 @@ class Record {
ArrayRef getAssertions() const { return Assertions; }
ArrayRef getDumps() const { return Dumps; }
- ArrayRef> getSuperClasses() const {
-return SuperClasses;
+ /// Append all superclasses in post-order to \p Classes.
+ void get
@@ -1630,9 +1630,9 @@ class Record {
SmallVector Assertions;
SmallVector Dumps;
- // All superclasses in the inheritance forest in post-order (yes, it
+ // Direct superclasses, which are roots of the inheritance forest (yes, it
// must be a forest; diamond-shaped inhe
@@ -1017,11 +1018,13 @@ lltok::Kind LLLexer::LexIdentifier() {
}
// Check for [us]0x[0-9A-Fa-f]+ which are Hexadecimal constant generated by
- // the CFE to avoid forcing it to deal with 64-bit numbers.
- if ((TokStart[0] == 'u' || TokStart[0] == 's') &&
+ // the CFE to
@@ -3829,10 +3829,40 @@ bool LLParser::parseValID(ValID &ID, PerFunctionState
*PFS, Type *ExpectedTy) {
ID.APSIntVal = Lex.getAPSIntVal();
ID.Kind = ValID::t_APSInt;
break;
- case lltok::APFloat:
+ case lltok::APFloat: {
+assert(ExpectedTy && "Need type to pa
https://github.com/mshockwave edited
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@@ -0,0 +1,494 @@
+//===-- RISCVSchedGenericOOO.td - Generic O3 Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,601 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mattr=+rva23u64,+zabha -mcpu=generic-ooo
--all-stats -iterations=1 < %s | FileCheck %s
mshockwave wrote:
nit: `--all-stats` shows
@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
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@@ -0,0 +1,266 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -1575,6 +1575,26 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const
MachineInstr &MI) const {
// No patch bytes means at most a PseudoCall is emitted
return std::max(NumBytes, 8U);
}
+ case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
+ case TargetOpcode::PATCHABLE
@@ -0,0 +1,266 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/117368
>From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Wed, 20 Nov 2024 14:37:57 -0800
Subject: [PATCH 1/8] [XRay][RISCV] RISCV support for XRay
Add RISC-V support fo
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/117368
>From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Wed, 20 Nov 2024 14:37:57 -0800
Subject: [PATCH 1/6] [XRay][RISCV] RISCV support for XRay
Add RISC-V support fo
@@ -0,0 +1,266 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -453,11 +475,71 @@ bool
RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
SetupMachineFunction(MF);
emitFunctionBody();
+ // Emit the XRay table
+ emitXRayTable();
+
if (EmittedOptionArch)
RTS.emitDirectiveOptionPop();
return false;
}
+void R
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/117368
>From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Wed, 20 Nov 2024 14:37:57 -0800
Subject: [PATCH 1/4] [XRay][RISCV] RISCV support for XRay
Add RISC-V support fo
@@ -0,0 +1,87 @@
+//===-- xray_trampoline_riscv32.s --*- ASM
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/117368
>From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Wed, 20 Nov 2024 14:37:57 -0800
Subject: [PATCH 1/5] [XRay][RISCV] RISCV support for XRay
Add RISC-V support fo
@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64;
static const int16_t cSledLength = 8;
#elif defined(__hexagon__)
static const int16_t cSledLength = 20;
+#elif SANITIZER_RISCV64
+static const int16_t cSledLength = 76;
+#elif defined(__riscv) && (__riscv_xlen == 32)
---
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/117368
>From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Wed, 20 Nov 2024 14:37:57 -0800
Subject: [PATCH 1/3] [XRay][RISCV] RISCV support for XRay
Add RISC-V support fo
https://github.com/mshockwave edited
https://github.com/llvm/llvm-project/pull/117368
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@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64;
static const int16_t cSledLength = 8;
#elif defined(__hexagon__)
static const int16_t cSledLength = 20;
+#elif SANITIZER_RISCV64
+static const int16_t cSledLength = 76;
+#elif defined(__riscv) && (__riscv_xlen == 32)
---
mshockwave wrote:
Close this PR in favor of #117921
https://github.com/llvm/llvm-project/pull/116878
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mshockwave wrote:
> Perhaps `__xray_default_options()` like `__asan_default_options()`? The user
> would need to provide a `.o` that defines the function, but there is more
> flexibility (e.g. the function can inspect a config file).
I think this will be a better idea. It simplifies the design
@@ -22,6 +22,7 @@ def WriteIMul32 : SchedWrite;// 32-bit multiply on
RV64I
def WriteJmp: SchedWrite;// Jump
def WriteJal: SchedWrite;// Jump and link
def WriteJalr : SchedWrite;// Jump and link register
+def WriteJmpReg : SchedWrit
@@ -0,0 +1,279 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,279 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
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@@ -0,0 +1,83 @@
+//===-- xray_trampoline_riscv32.s --*- ASM
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -453,11 +475,71 @@ bool
RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
SetupMachineFunction(MF);
emitFunctionBody();
+ // Emit the XRay table
+ emitXRayTable();
+
if (EmittedOptionArch)
RTS.emitDirectiveOptionPop();
return false;
}
+void R
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,97 @@
+//===-- xray_trampoline_riscv_common.s --*- ASM
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,83 @@
+//===-- xray_trampoline_riscv64.s --*- ASM
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -0,0 +1,296 @@
+//===-- xray_riscv.cpp *- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apach
@@ -57,6 +57,10 @@ static const int16_t cSledLength = 64;
static const int16_t cSledLength = 8;
#elif defined(__hexagon__)
static const int16_t cSledLength = 20;
+#elif SANITIZER_RISCV64
+static const int16_t cSledLength = 76;
+#elif defined(__riscv) && (__riscv_xlen == 32)
---
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/117368
>From 599370a06008092f6aa883bf11600d0b66707bc0 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Wed, 20 Nov 2024 14:37:57 -0800
Subject: [PATCH 1/2] [XRay][RISCV] RISCV support for XRay
Add RISC-V support fo
mshockwave wrote:
ping
https://github.com/llvm/llvm-project/pull/116878
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https://github.com/mshockwave edited
https://github.com/llvm/llvm-project/pull/117368
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https://github.com/mshockwave created
https://github.com/llvm/llvm-project/pull/117368
Add RISC-V support for XRay. The RV64 implementation has been tested in both
QEMU and in our production environment.
Currently this requires D and C extensions, but since both RV64GC and
RVA22/RVA23 are bec
https://github.com/mshockwave updated
https://github.com/llvm/llvm-project/pull/116878
>From 95ee4bd09aa48d4f0c2c4f5fc1e81e20cd57c7e2 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu
Date: Mon, 11 Nov 2024 11:40:43 -0800
Subject: [PATCH 1/2] [XRay] Add `-fxray-default-options` to pass build-time
def
https://github.com/mshockwave created
https://github.com/llvm/llvm-project/pull/116878
This flag specifies XRay options that will automatically be applied to the
instrumented binaries during run-time even without setting `XRAY_OPTIONS`. This
is useful in cases where setting the `XRAY_OPTIONS`
https://github.com/mshockwave closed
https://github.com/llvm/llvm-project/pull/115100
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https://github.com/mshockwave approved this pull request.
LGTM.
I don't have any strong opinion on the CPU name
https://github.com/llvm/llvm-project/pull/115100
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https://github.com/mshockwave approved this pull request.
> I propose the following next steps (once this is committed):
this timeline looks fine, do you also want to add `[[deprecated]]` once the PSA
is out?
Also, I can help on other LLVM TableGen backends if they haven't been updated.
https:
mshockwave wrote:
> So for this particular PR, we just need a name people are happy with (perhaps
> check if the vendor has a preference?). Something like `-mcpu=rp2350-hazard3`
> perhaps?
+1 on `-mcpu=rp2350-hazard3` over `-mcpu=raspberrypi-rp2350` because the former
is more specific to the
@@ -335,7 +335,7 @@ define void @cannot_sink_reduction(i32 %x, ptr %ptr, i64
%tc) {
-; CHECK-NET: ret void
+; CHECK-NEXT:ret void
mshockwave wrote:
please remove this line as it has been covered by line 333 (which was probably
generated by UTC).
@@ -96,7 +96,7 @@ for.end: ; preds =
%for.end.loopexit, %
; Specify a smaller minimum VF (via `-epilogue-vectorization-minimum-VF=4`) and
; make sure the epilogue gets vectorized in that case.
-; CHECK-MIN-D-LABLE: @f3
+; CHECK-MIN-D-L
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