https://github.com/mshockwave created
https://github.com/llvm/llvm-project/pull/137865
Sscofpmf is already in RVA23S64 and Zicsr is in RVA20U64. I also added a test
to check Sscofpmf. This is effectively an NFC.
-------
This is found by #137864
>From 3ac537e4fe391464870254d0a9c81fe9f58c195a Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min....@sifive.com>
Date: Tue, 29 Apr 2025 11:46:28 -0700
Subject: [PATCH] [RISCV] Remove duplicate extensions from tt-ascalon-d8 CPU
---
clang/test/Driver/riscv-cpus.c | 1 +
llvm/lib/Target/RISCV/RISCVProcessors.td | 2 --
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index bb3a9d38be673..6fa401203361e 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -251,6 +251,7 @@
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl256b"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl32b"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl64b"
+// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+sscofpmf"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svinval"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svnapot"
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svpbmt"
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td
b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 1ad94228bcbaa..822c25a4e1130 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -480,11 +480,9 @@ def TENSTORRENT_ASCALON_D8 :
RISCVProcessorModel<"tt-ascalon-d8",
!listconcat(RVA23S64Features,
[FeatureStdExtSmaia,
FeatureStdExtSsaia,
- FeatureStdExtSscofpmf,
FeatureStdExtSsstrict,
FeatureStdExtZfbfmin,
FeatureStdExtZfh,
- FeatureStdExtZicsr,
FeatureStdExtZvbc,
FeatureStdExtZvfbfmin,
FeatureStdExtZvfbfwma,
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