================ @@ -0,0 +1,358 @@ +//===-- RISCVInstrInfoXAndes.td ----------------------------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the vendor extensions defined by Andes Technology. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Operand and SDNode transformation definitions. +//===----------------------------------------------------------------------===// + +// A 11-bit signed immediate where the least significant bit is zero. +def simm11_lsb0 : Operand<OtherVT> { + let ParserMatchClass = SImmAsmOperand<11, "Lsb0">; + let PrintMethod = "printBranchOperand"; + let EncoderMethod = "getImmOpValueAsr1"; + let DecoderMethod = "decodeSImmOperandAndLsl1<11>"; + let MCOperandPredicate = [{ + int64_t Imm; + if (MCOp.evaluateAsConstantImm(Imm)) + return isShiftedInt<10, 1>(Imm); + return MCOp.isBareSymbolRef(); + }]; + let OperandType = "OPERAND_PCREL"; +} + +def simm18 : Operand<XLenVT> { + let ParserMatchClass = SImmAsmOperand<18>; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeSImmOperand<18>"; +} + +def simm18_lsb0 : Operand<XLenVT> { + let ParserMatchClass = SImmAsmOperand<18, "Lsb0">; + let EncoderMethod = "getImmOpValueAsr1"; + let DecoderMethod = "decodeSImmOperandAndLsl1<18>"; +} + +def simm19_lsb00 : Operand<XLenVT> { + let ParserMatchClass = SImmAsmOperand<19, "Lsb00">; + let EncoderMethod = "getImmOpValueAsrN<2>"; + let DecoderMethod = "decodeSImmOperandAndLslN<19, 2>"; +} + +def simm20_lsb000 : Operand<XLenVT> { + let ParserMatchClass = SImmAsmOperand<20, "Lsb000">; + let EncoderMethod = "getImmOpValueAsrN<3>"; + let DecoderMethod = "decodeSImmOperandAndLslN<20, 3>"; +} + +//===----------------------------------------------------------------------===// +// Instruction Class Templates +//===----------------------------------------------------------------------===// + +class NDSRVInstBB<bit cs, string opcodestr> + : RVInst<(outs), (ins GPR:$rs1, uimmlog2xlen:$cimm, simm11_lsb0:$imm10), + opcodestr, "$rs1, $cimm, $imm10", [], InstFormatOther>, + Sched<[WriteJmp, ReadIALU]> { + bits<10> imm10; + bits<5> rs1; + bits<6> cimm; + + let Inst{31} = imm10{9}; + let Inst{30} = cs; + let Inst{29-25} = imm10{8-4}; + let Inst{24-20} = cimm{4-0}; + let Inst{19-15} = rs1; + let Inst{14-12} = 0b111; + let Inst{11-8} = imm10{3-0}; + let Inst{7} = cimm{5}; + let Inst{6-0} = OPC_CUSTOM_2.Value; + let hasSideEffects = 0; + let mayLoad = 0; + let mayStore = 0; + let isBranch = 1; + let isTerminator = 1; +} + +class NDSRVInstBC<bits<3> funct3, string opcodestr> + : RVInst<(outs), (ins GPR:$rs1, uimm7:$cimm, simm11_lsb0:$imm10), + opcodestr, "$rs1, $cimm, $imm10", [], InstFormatOther>, + Sched<[WriteJmp, ReadIALU]> { + bits<10> imm10; + bits<5> rs1; + bits<7> cimm; + + let Inst{31} = imm10{9}; + let Inst{30} = cimm{6}; + let Inst{29-25} = imm10{8-4}; + let Inst{24-20} = cimm{4-0}; + let Inst{19-15} = rs1; + let Inst{14-12} = funct3; + let Inst{11-8} = imm10{3-0}; + let Inst{7} = cimm{5}; + let Inst{6-0} = OPC_CUSTOM_2.Value; + let hasSideEffects = 0; + let mayLoad = 0; + let mayStore = 0; + let isBranch = 1; + let isTerminator = 1; +} + +class NDSRVInstBFO<bits<3> funct3, string opcodestr> + : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb), + opcodestr, "$rd, $rs1, $msb, $lsb", [], InstFormatOther>, + Sched<[WriteIALU, ReadIALU]> { + bits<5> rd; + bits<5> rs1; + bits<6> msb; + bits<6> lsb; + + let Inst{31-26} = msb; + let Inst{25-20} = lsb; + let Inst{19-15} = rs1; + let Inst{14-12} = funct3; + let Inst{11-7} = rd; + let Inst{6-0} = OPC_CUSTOM_2.Value; + let hasSideEffects = 0; + let mayLoad = 0; + let mayStore = 0; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class NDSRVInstRR<bits<7> funct7, string opcodestr> + : RVInstR<funct7, 0b000, OPC_CUSTOM_2, + (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), + opcodestr, "$rd, $rs1, $rs2">, + Sched<[WriteIALU, ReadIALU, ReadIALU]> { + let hasSideEffects = 0; + let mayLoad = 0; + let mayStore = 0; ---------------- mshockwave wrote:
duplicated with line 128 I believe. https://github.com/llvm/llvm-project/pull/135110 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
