https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/141172
None
>From 036a3bd7024fe358d670b49d1d62bfe3cc0bc6d4 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Thu, 22 May 2025 15:05:30 +0800
Subject: [PATCH] [RISCV] Add pre-defined macro tests for Andes vendor
extension
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/141007
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https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/141007
Andes N45/NX45/A45/AX45 also support XAndesPerf.
>From 655b5cb2fe3d2950757fd4b5c3ccac679033bf57 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Thu, 22 May 2025 09:42:55 +0800
Subject: [PATCH] [RISCV] Add Feature
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/140979
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https://github.com/llvm/llvm-project/pull/140681
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https://github.com/llvm/llvm-project/pull/140681
>From 80f55eaaead598b0b557aa32756f59b201fc0fcd Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Tue, 20 May 2025 10:13:26 +0800
Subject: [PATCH 1/4] [RISCV] Add Andes A25/AX25 processor definition
Andes A25/AX25 a
https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/140681
>From 98bdcfd0b57b482f31be098e069e610897cc1425 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Tue, 20 May 2025 10:13:26 +0800
Subject: [PATCH 1/4] [RISCV] Add Andes A25/AX25 processor definition
Andes A25/AX25 a
@@ -648,6 +648,38 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
FeatureStdExtZcb,
FeatureStdExtZcmp]>;
+def ANDES_A25 : RISCVProcessorModel<"andes-a25",
+
@@ -648,6 +648,38 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
FeatureStdExtZcb,
FeatureStdExtZcmp]>;
+def ANDES_A25 : RISCVProcessorModel<"andes-a25",
+
https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/140681
>From 98bdcfd0b57b482f31be098e069e610897cc1425 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Tue, 20 May 2025 10:13:26 +0800
Subject: [PATCH 1/4] [RISCV] Add Andes A25/AX25 processor definition
Andes A25/AX25 a
tclin914 wrote:
Done.
https://github.com/llvm/llvm-project/pull/140681
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>From 98bdcfd0b57b482f31be098e069e610897cc1425 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Tue, 20 May 2025 10:13:26 +0800
Subject: [PATCH 1/4] [RISCV] Add Andes A25/AX25 processor definition
Andes A25/AX25 a
tclin914 wrote:
> I thought it should have xandesperf extension?
Added it. Thanks.
https://github.com/llvm/llvm-project/pull/140681
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https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/140681
Andes A25/AX25 are 32/64bit, 5-stage pipeline, linux-capable CPUs that
implement the RV[32|64]IMAFDC_Zba_Zbb_Zbc_Zbs ISA extensions. They are
developed by Andes Technology https://www.andestech.com, a RISC-V I
https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/139849
The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.
This patch only supports assembler.
Intrinsics support will be added in a later patch.
>From bc8ae48aa392d2
Author: Jim Lin
Date: 2025-05-13T14:46:08+08:00
New Revision: 9f274a95b13a7c3fbd95d8f80f915a5548df2629
URL:
https://github.com/llvm/llvm-project/commit/9f274a95b13a7c3fbd95d8f80f915a5548df2629
DIFF:
https://github.com/llvm/llvm-project/commit/9f274a95b13a7c3fbd95d8f80f915a5548df2629.diff
LOG:
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/138827
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Rate limit · GitHub
body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
UI,Helvetica,Arial,sans-
https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/138827
The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.
This patch only supports assembler.
Intrinsics support will be added in a later patch.
>From 034d5c463c8616
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/138498
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The instruction name and intrinsic name have been renamed to sle(u). The `t`
was removed. Please refer to
https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md.
>From dc6363
Author: Jim Lin
Date: 2025-05-05T16:40:49+08:00
New Revision: 56097bce97b4f0a9717268e9ddc1bb72bc49390c
URL:
https://github.com/llvm/llvm-project/commit/56097bce97b4f0a9717268e9ddc1bb72bc49390c
DIFF:
https://github.com/llvm/llvm-project/commit/56097bce97b4f0a9717268e9ddc1bb72bc49390c.diff
LOG:
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/135110
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>From 032d4cffd6b0157f4a563986af760a89411026e3 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Wed, 9 Apr 2025 09:44:47 +0800
Subject: [PATCH 01/12] [RISCV] Add Andes XAndesperf (Andes Performance)
extension.
Th
tclin914 wrote:
Kindly ping.
https://github.com/llvm/llvm-project/pull/135110
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https://github.com/llvm/llvm-project/pull/136832
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https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/136832
Andes A45/AX45 are 32/64bit in-order dual-issue 8-stage pipeline linux-capable
CPU implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions. They are
developed by Andes Technology https://www.andestech.com,
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/136670
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@@ -625,3 +625,33 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
FeatureStdExtZbkb,
FeatureStdExtZcb,
FeatureStdExtZcmp]>;
+
+def ANDES_N
@@ -625,3 +625,33 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
FeatureStdExtZbkb,
FeatureStdExtZcb,
FeatureStdExtZcmp]>;
+
+def ANDES_N
https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/136670
>From df3a0b2bd9cb31fc8e252e250d3107dd1ac2cc0b Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Tue, 22 Apr 2025 10:12:23 +0800
Subject: [PATCH 1/2] [RISCV] Add Andes N45/NX45 processor definition
Andes N45/NX45 a
https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/136670
Andes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU
architecture implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions. They
are developed by Andes Technology https://www.andestech.com,
@@ -1453,6 +1454,14 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCSRIND-EXT %s
// CHECK-SMCSRIND-EXT: __riscv_smcsrind 100{{$}}
+// RUN: %clang --target=riscv32 \
tclin914 wrote:
Put the test for `smcntrpmf` above for `smcsrind`
https://github.
@@ -0,0 +1,56 @@
+# XAndesPerf - Andes Performance Extension
+# RUN: not llvm-mc -triple riscv32 -mattr=+xandesperf < %s 2>&1 \
+# RUN: | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+xandesperf < %s 2>&1 \
+# RUN: | FileCheck %s -check-prefix=CHECK-64
+
+# Out
https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/135110
>From b23dec1163f300189f1a2ce28f20c07d3cb9d5fe Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Wed, 9 Apr 2025 09:44:47 +0800
Subject: [PATCH 01/12] [RISCV] Add Andes XAndesperf (Andes Performance)
extension.
Th
tclin914 wrote:
Rebased
https://github.com/llvm/llvm-project/pull/135110
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https://github.com/llvm/llvm-project/pull/135110
>From b23dec1163f300189f1a2ce28f20c07d3cb9d5fe Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Wed, 9 Apr 2025 09:44:47 +0800
Subject: [PATCH 01/11] [RISCV] Add Andes XAndesperf (Andes Performance)
extension.
Th
tclin914 wrote:
> Do you have plan send PR to
> https://github.com/riscv-non-isa/riscv-toolchain-conventions?
PR:
[https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/84](https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/84)
https://github.com/llvm/llvm-project/
@@ -558,6 +558,34 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunmi
@@ -447,18 +447,25 @@ static DecodeStatus decodeSImmNonZeroOperand(MCInst
&Inst, uint32_t Imm,
return decodeSImmOperand(Inst, Imm, Address, Decoder);
}
-template
-static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm,
+template
+static DecodeStatus decod
@@ -0,0 +1,358 @@
+//===-- RISCVInstrInfoXAndes.td *- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,358 @@
+//===-- RISCVInstrInfoXAndes.td *- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/135110
>From 1615cb987f60d8c6123f7c95bc7bd7f22d897ea1 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Wed, 9 Apr 2025 09:44:47 +0800
Subject: [PATCH 01/11] [RISCV] Add Andes XAndesperf (Andes Performance)
extension.
Th
https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/135110
>From 1615cb987f60d8c6123f7c95bc7bd7f22d897ea1 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Wed, 9 Apr 2025 09:44:47 +0800
Subject: [PATCH 1/8] [RISCV] Add Andes XAndesperf (Andes Performance)
extension.
The
https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/135110
>From 1615cb987f60d8c6123f7c95bc7bd7f22d897ea1 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Wed, 9 Apr 2025 09:44:47 +0800
Subject: [PATCH 1/7] [RISCV] Add Andes XAndesperf (Andes Performance)
extension.
The
@@ -0,0 +1,358 @@
+//===-- RISCVInstrInfoXAndes.td *- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -535,21 +540,29 @@ RISCVMCCodeEmitter::getImmOpValueSlist(const MCInst &MI,
unsigned OpNo,
}
}
-uint64_t
-RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
+template
+unsigned
+RISCVMCCodeEmitter::getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,
@@ -940,6 +947,14 @@ struct RISCVOperand final : public MCParsedAsmOperand {
[](int64_t Imm) { return Imm != INT64_MIN && isInt<5>(Imm - 1); });
}
+ bool isSImm18() const { return isBareSimmNLsbK<18, 0>(); }
+
+ bool isSImm18Lsb0() const { return isBareSimmNLsb0<18
https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/135110
>From 1615cb987f60d8c6123f7c95bc7bd7f22d897ea1 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Wed, 9 Apr 2025 09:44:47 +0800
Subject: [PATCH 1/4] [RISCV] Add Andes XAndesperf (Andes Performance)
extension.
The
https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/135110
The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.
This patch only supports assembler.
Relocation and fixup for the branch and gp-implied instructions will be
@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
}
}
+ auto checkVsetvl = [&](unsigned SEWOffset,
+unsigned LMULOffset) -> bool {
+const FunctionDecl *FD = SemaRef.getCurFunctionDecl();
+
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/116907
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>From 08523139b789c836b22677f8e16b79910de601e4 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Wed, 20 Nov 2024 10:31:58 +0800
Subject: [PATCH 1/4] [RISCV] Make A implies Zaamo and Zalrsc
Ref: https://github.com/
https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/116907
>From 08523139b789c836b22677f8e16b79910de601e4 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Wed, 20 Nov 2024 10:31:58 +0800
Subject: [PATCH 1/3] [RISCV] Make A implies Zaamo and Zalrsc
Ref: https://github.com/
https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/116907
Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/a-st-ext.adoc.
>From 91aea6122d192d72e078408366b46b3dab5a37a9 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Wed, 20 Nov 2024 10:31:58 +0800
Subject:
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/115436
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https://github.com/llvm/llvm-project/pull/115269
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None
>From d6a33142b94a6ad0ca747d330a4ac4b3f7a476af Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Thu, 7 Nov 2024 13:47:09 +0800
Subject: [PATCH] [RISCV][Clang] Reuse RVVOutBuiltinSet multiclass for builtin
vf
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/112827
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>From a1b6a764dd93ecb33b493c14c396c5c040be0412 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Fri, 18 Oct 2024 11:11:02 +0800
Subject: [PATCH 1/2] [RISCV] Check if v extension is enabled by the function
features
https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/112827
>From a1b6a764dd93ecb33b493c14c396c5c040be0412 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Fri, 18 Oct 2024 11:11:02 +0800
Subject: [PATCH 1/3] [RISCV] Check if v extension is enabled by the function
features
https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/112827
>From a1b6a764dd93ecb33b493c14c396c5c040be0412 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Fri, 18 Oct 2024 11:11:02 +0800
Subject: [PATCH 1/2] [RISCV] Check if v extension is enabled by the function
features
https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/112827
Fixes: https://github.com/llvm/llvm-project/issues/109694
>From a1b6a764dd93ecb33b493c14c396c5c040be0412 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Fri, 18 Oct 2024 11:11:02 +0800
Subject: [PATCH] [RISCV] Ch
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/111653
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>From 80768f580d4ef6b9841b22ee5b287a87d9f25951 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Wed, 9 Oct 2024 11:37:46 +0800
Subject: [PATCH 1/2] [RISCV] Add support for inline asm constraint vd
It constrains ve
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/109390
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None
>From 6de7650ee341546d5f67c4918bce4f6901452818 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Fri, 20 Sep 2024 16:39:05 +0800
Subject: [PATCH] [RISCV] Fix incorrect check prefix in riscv32-toolchain.c and
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/108131
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https://github.com/llvm/llvm-project/pull/108131
>From 5874d7163114eda6e3c5b0fa50839af0eec4e48b Mon Sep 17 00:00:00 2001
From: patrick
Date: Fri, 26 Nov 2021 15:09:08 +0800
Subject: [PATCH] [RISCV] Emit predefined macro __riscv_cmodel_large for large
code mo
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/107817
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tclin914 wrote:
> What I am missing is:
>
> * adjustments in `clang/lib/Basic/Targets/RISCV.cpp` to emit the macro
> `__riscv_cmodel_large`
> * new tests in `clang/test/Preprocessor/riscv-cmodel.c`
>
> Related PRs:
>
> * [Add __riscv_cmodel_large define for large code model
> riscv-non-isa/r
https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/108131
None
>From e394e7ca9e769deb3f286f53a48a049340bd51bd Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Mon, 9 Sep 2024 13:09:23 +0800
Subject: [PATCH 1/4] [RISCV] Allow -mcmodel= to accept large for RV64
---
clang
https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/107817
>From e394e7ca9e769deb3f286f53a48a049340bd51bd Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Mon, 9 Sep 2024 13:09:23 +0800
Subject: [PATCH 1/3] [RISCV] Allow -mcmodel= to accept large for RV64
---
clang/lib/D
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/107816
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https://github.com/tclin914 edited
https://github.com/llvm/llvm-project/pull/107816
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https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/107817
None
>From f6da0096e4dcf3f7b5c8da4e8e170e88b7ebb471 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Mon, 9 Sep 2024 12:59:30 +0800
Subject: [PATCH 1/2] [RISCV] Add testcase for -mcmodel=
---
clang/test/Driver/r
https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/107816
None
>From f6da0096e4dcf3f7b5c8da4e8e170e88b7ebb471 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Mon, 9 Sep 2024 12:59:30 +0800
Subject: [PATCH] [RISCV] Add testcase for -mcmodel=
---
clang/test/Driver/riscv
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/87095
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tclin914 wrote:
> Is it possible use `TargetInfo::getGCCRegAliases` to model the aliasing
> between a7 and sp? Also, could you add a simple test?
Implement getGCCRegAliases and add testcase.
https://github.com/llvm/llvm-project/pull/87095
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https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/87095
>From dec6021133f67304bfc9942a1a4985cce6a15645 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Sat, 30 Mar 2024 01:37:49 +0800
Subject: [PATCH 1/3] [M68k] Change gcc register name from a7 to sp
In M68kRegisterInfo
https://github.com/tclin914 updated
https://github.com/llvm/llvm-project/pull/87095
>From dec6021133f67304bfc9942a1a4985cce6a15645 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Sat, 30 Mar 2024 01:37:49 +0800
Subject: [PATCH 1/2] [M68k] Change gcc register name from a7 to sp
In M68kRegisterInfo
https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/87264
Enable frame pointer optimization by default to match it with gcc.
Fixes: https://github.com/llvm/llvm-project/issues/75013
>From 4eeb31d4ad8503db9a1cc079eeb9aa4186136719 Mon Sep 17 00:00:00 2001
From: Jim Lin
https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/87095
In M68kRegisterInfo.td, register SP is defined with name sp and alternate name
a7.
Fixes: https://github.com/llvm/llvm-project/issues/78620
>From dec6021133f67304bfc9942a1a4985cce6a15645 Mon Sep 17 00:00:00 20
https://github.com/tclin914 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/79615
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@@ -0,0 +1,66 @@
+//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*-
tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Ident
@@ -0,0 +1,66 @@
+//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*-
tablegen -*-===//
tclin914 wrote:
exceed 80 characters
https://github.com/llvm/llvm-project/pull/79911
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@@ -797,6 +797,13 @@ def FeatureStdExtSvpbmt
: SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
"'Svpbmt' (Page-Based Memory Types)">;
+def FeatureStdExtZalasr
tclin914 wrote:
Could we put this definition after Zacas.
https://
https://github.com/tclin914 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/79618
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@@ -21189,6 +21189,10 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned
BuiltinID,
case RISCV::BI__builtin_riscv_clmulh_64:
case RISCV::BI__builtin_riscv_clmulr_32:
case RISCV::BI__builtin_riscv_clmulr_64:
+ case RISCV::BI__builtin_riscv_mopr_32:
@@ -282,6 +282,9 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
}
}
+ if (BaseType == BasicType::BFloat16 && !TI.hasFeature("zvfbfmin"))
tclin914 wrote:
bfloat vector is only valid when zvfbfmin is enabled. So it doesn't need to
@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL = [-
@@ -0,0 +1,218 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN: -target-feature +zvfh -target-feat
@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL = [-
@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL = [-
@@ -0,0 +1,479 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN: -target-feature +zvfh -target-feat
https://github.com/tclin914 closed
https://github.com/llvm/llvm-project/pull/77866
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>From #75735, Zvfh implies Zvfhmin.
>From be8d27cf8a3cf511598437a401a2277b36752137 Mon Sep 17 00:00:00 2001
From: Jim Lin
Date: Fri, 12 Jan 2024 09:58:49 +0800
Subject: [PATCH] [RISCV] Change required features
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