[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

@@ -0,0 +1,358 @@ +//===-- RISCVInstrInfoXAndes.td *- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Ap

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

@@ -535,21 +540,29 @@ RISCVMCCodeEmitter::getImmOpValueSlist(const MCInst &MI, unsigned OpNo, } } -uint64_t -RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo, +template +unsigned +RISCVMCCodeEmitter::getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

@@ -940,6 +947,14 @@ struct RISCVOperand final : public MCParsedAsmOperand { [](int64_t Imm) { return Imm != INT64_MIN && isInt<5>(Imm - 1); }); } + bool isSImm18() const { return isBareSimmNLsbK<18, 0>(); } + + bool isSImm18Lsb0() const { return isBareSimmNLsb0<18

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/135110 >From 1615cb987f60d8c6123f7c95bc7bd7f22d897ea1 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Wed, 9 Apr 2025 09:44:47 +0800 Subject: [PATCH 1/4] [RISCV] Add Andes XAndesperf (Andes Performance) extension. The

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/135110 The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. Relocation and fixup for the branch and gp-implied instructions will be

[clang] [RISCV][Sema] Add feature check for target attribute to VSETVL intrinsics (PR #126064)

@@ -623,13 +623,37 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo &TI, } } + auto checkVsetvl = [&](unsigned SEWOffset, +unsigned LMULOffset) -> bool { +const FunctionDecl *FD = SemaRef.getCurFunctionDecl(); +

[clang] [lld] [llvm] [RISCV] Make A implies Zaamo and Zalrsc (PR #116907)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/116907 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [lld] [llvm] [RISCV] Make A implies Zaamo and Zalrsc (PR #116907)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/116907 >From 08523139b789c836b22677f8e16b79910de601e4 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Wed, 20 Nov 2024 10:31:58 +0800 Subject: [PATCH 1/4] [RISCV] Make A implies Zaamo and Zalrsc Ref: https://github.com/

[clang] [lld] [llvm] [RISCV] Make A implies Zaamo and Zalrsc (PR #116907)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/116907 >From 08523139b789c836b22677f8e16b79910de601e4 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Wed, 20 Nov 2024 10:31:58 +0800 Subject: [PATCH 1/3] [RISCV] Make A implies Zaamo and Zalrsc Ref: https://github.com/

[clang] [lld] [llvm] [RISCV] Make A implies Zaamo and Zalrsc (PR #116907)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/116907 Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/a-st-ext.adoc. >From 91aea6122d192d72e078408366b46b3dab5a37a9 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Wed, 20 Nov 2024 10:31:58 +0800 Subject:

[clang] [RISCV][Clang] Add RequiredFeatures to zvfh intrinsics (PR #115436)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/115436 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][Clang] Add RequiredFeatures to zvfh intrinsics (PR #115436)

https://github.com/tclin914 edited https://github.com/llvm/llvm-project/pull/115436 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][Clang] Reuse RVVOutBuiltinSet multiclass for builtin vfrsqrt7. NFC (PR #115269)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/115269 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][Clang] Reuse RVVOutBuiltinSet multiclass for builtin vfrsqrt7. NFC (PR #115269)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/115269 None >From d6a33142b94a6ad0ca747d330a4ac4b3f7a476af Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Thu, 7 Nov 2024 13:47:09 +0800 Subject: [PATCH] [RISCV][Clang] Reuse RVVOutBuiltinSet multiclass for builtin vf

[clang] [RISCV] Check if v extension is enabled by the function features for the builtins not in Zve64*. (PR #112827)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/112827 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Check if v extension is enabled by the function features for the builtins not in Zve64*. (PR #112827)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/112827 >From a1b6a764dd93ecb33b493c14c396c5c040be0412 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Fri, 18 Oct 2024 11:11:02 +0800 Subject: [PATCH 1/2] [RISCV] Check if v extension is enabled by the function features

[clang] [RISCV] Check if v extension is enabled by the function features for the builtins not in Zve64*. (PR #112827)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/112827 >From a1b6a764dd93ecb33b493c14c396c5c040be0412 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Fri, 18 Oct 2024 11:11:02 +0800 Subject: [PATCH 1/3] [RISCV] Check if v extension is enabled by the function features

[clang] [RISCV] Check if v extension is enabled by the function features for the builtins not in Zve64*. (PR #112827)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/112827 >From a1b6a764dd93ecb33b493c14c396c5c040be0412 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Fri, 18 Oct 2024 11:11:02 +0800 Subject: [PATCH 1/2] [RISCV] Check if v extension is enabled by the function features

[clang] [RISCV] Check if v extension is enabled by the function features for the builtins not in Zve64*. (PR #112827)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/112827 Fixes: https://github.com/llvm/llvm-project/issues/109694 >From a1b6a764dd93ecb33b493c14c396c5c040be0412 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Fri, 18 Oct 2024 11:11:02 +0800 Subject: [PATCH] [RISCV] Ch

[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/111653 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add support for inline asm constraint vd (PR #111653)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/111653 >From 80768f580d4ef6b9841b22ee5b287a87d9f25951 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Wed, 9 Oct 2024 11:37:46 +0800 Subject: [PATCH 1/2] [RISCV] Add support for inline asm constraint vd It constrains ve

[clang] [RISCV][test] Fix incorrect check prefix in riscv32-toolchain.c and riscv64-toolchain.c. (PR #109390)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/109390 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][test] Fix incorrect check prefix in riscv32-toolchain.c and riscv64-toolchain.c. (PR #109390)

https://github.com/tclin914 edited https://github.com/llvm/llvm-project/pull/109390 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Fix incorrect check prefix in riscv32-toolchain.c and riscv64-toolchain.c. NFC. (PR #109390)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/109390 None >From 6de7650ee341546d5f67c4918bce4f6901452818 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Fri, 20 Sep 2024 16:39:05 +0800 Subject: [PATCH] [RISCV] Fix incorrect check prefix in riscv32-toolchain.c and

[clang] [RISCV] Emit predefined macro __riscv_cmodel_large for large code model (PR #108131)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/108131 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Emit predefined macro __riscv_cmodel_large for large code model (PR #108131)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/108131 >From 5874d7163114eda6e3c5b0fa50839af0eec4e48b Mon Sep 17 00:00:00 2001 From: patrick Date: Fri, 26 Nov 2021 15:09:08 +0800 Subject: [PATCH] [RISCV] Emit predefined macro __riscv_cmodel_large for large code mo

[clang] [RISCV] Allow -mcmodel= to accept large for RV64 (PR #107817)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/107817 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Allow -mcmodel= to accept large for RV64 (PR #107817)

tclin914 wrote: > What I am missing is: > > * adjustments in `clang/lib/Basic/Targets/RISCV.cpp` to emit the macro > `__riscv_cmodel_large` > * new tests in `clang/test/Preprocessor/riscv-cmodel.c` > > Related PRs: > > * [Add __riscv_cmodel_large define for large code model  > riscv-non-isa/r

[clang] [RISCV] Emit predefined macro __riscv_cmodel_large for large code model (PR #108131)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/108131 None >From e394e7ca9e769deb3f286f53a48a049340bd51bd Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Mon, 9 Sep 2024 13:09:23 +0800 Subject: [PATCH 1/4] [RISCV] Allow -mcmodel= to accept large for RV64 --- clang

[clang] [RISCV] Allow -mcmodel= to accept large for RV64 (PR #107817)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/107817 >From e394e7ca9e769deb3f286f53a48a049340bd51bd Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Mon, 9 Sep 2024 13:09:23 +0800 Subject: [PATCH 1/3] [RISCV] Allow -mcmodel= to accept large for RV64 --- clang/lib/D

[clang] [RISCV] Add testcase for -mcmodel= (PR #107816)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/107816 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add testcase for -mcmodel= (PR #107816)

https://github.com/tclin914 edited https://github.com/llvm/llvm-project/pull/107816 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Allow -mcmodel= to accept large for RV64 (PR #107817)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/107817 None >From f6da0096e4dcf3f7b5c8da4e8e170e88b7ebb471 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Mon, 9 Sep 2024 12:59:30 +0800 Subject: [PATCH 1/2] [RISCV] Add testcase for -mcmodel= --- clang/test/Driver/r

[clang] [RISCV] Add testcase for -mcmodel= (PR #107816)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/107816 None >From f6da0096e4dcf3f7b5c8da4e8e170e88b7ebb471 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Mon, 9 Sep 2024 12:59:30 +0800 Subject: [PATCH] [RISCV] Add testcase for -mcmodel= --- clang/test/Driver/riscv

[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/87095 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)

tclin914 wrote: > Is it possible use `TargetInfo::getGCCRegAliases` to model the aliasing > between a7 and sp? Also, could you add a simple test? Implement getGCCRegAliases and add testcase. https://github.com/llvm/llvm-project/pull/87095 ___ cfe-com

[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/87095 >From dec6021133f67304bfc9942a1a4985cce6a15645 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Sat, 30 Mar 2024 01:37:49 +0800 Subject: [PATCH 1/3] [M68k] Change gcc register name from a7 to sp In M68kRegisterInfo

[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/87095 >From dec6021133f67304bfc9942a1a4985cce6a15645 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Sat, 30 Mar 2024 01:37:49 +0800 Subject: [PATCH 1/2] [M68k] Change gcc register name from a7 to sp In M68kRegisterInfo

[clang] [M68k][clang] Enable frame pointer optimization by default (PR #87264)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/87264 Enable frame pointer optimization by default to match it with gcc. Fixes: https://github.com/llvm/llvm-project/issues/75013 >From 4eeb31d4ad8503db9a1cc079eeb9aa4186136719 Mon Sep 17 00:00:00 2001 From: Jim Lin

[clang] [M68k] Change gcc register name from a7 to sp. (PR #87095)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/87095 In M68kRegisterInfo.td, register SP is defined with name sp and alternate name a7. Fixes: https://github.com/llvm/llvm-project/issues/78620 >From dec6021133f67304bfc9942a1a4985cce6a15645 Mon Sep 17 00:00:00 20

[clang] [RISCV][clang] Add Zvfbfwma C intrinsics support (PR #79615)

https://github.com/tclin914 approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/79615 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

@@ -0,0 +1,66 @@ +//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Ident

[llvm] [clang] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

@@ -0,0 +1,66 @@ +//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*- tablegen -*-===// tclin914 wrote: exceed 80 characters https://github.com/llvm/llvm-project/pull/79911 ___ cfe-commits mailing

[clang] [llvm] [RISCV][MC] MC layer support for the experimental zalasr extension (PR #79911)

@@ -797,6 +797,13 @@ def FeatureStdExtSvpbmt : SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true", "'Svpbmt' (Page-Based Memory Types)">; +def FeatureStdExtZalasr tclin914 wrote: Could we put this definition after Zacas. https://

[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)

https://github.com/tclin914 approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/79618 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV][Clang] Added builtin support for experimental Zimop extension (PR #79971)

@@ -21189,6 +21189,10 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, case RISCV::BI__builtin_riscv_clmulh_64: case RISCV::BI__builtin_riscv_clmulr_32: case RISCV::BI__builtin_riscv_clmulr_64: + case RISCV::BI__builtin_riscv_mopr_32:

[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)

@@ -282,6 +282,9 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics( } } + if (BaseType == BasicType::BFloat16 && !TI.hasFeature("zvfbfmin")) tclin914 wrote: bfloat vector is only valid when zvfbfmin is enabled. So it doesn't need to

[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)

@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">; def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">; } + +// Zvfbfmin - Vector convert BF16 to FP32 +let Log2LMUL = [-

[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)

@@ -0,0 +1,218 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ +// RUN: -target-feature +zvfh -target-feat

[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)

@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">; def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">; } + +// Zvfbfmin - Vector convert BF16 to FP32 +let Log2LMUL = [-

[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)

@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">; def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">; } + +// Zvfbfmin - Vector convert BF16 to FP32 +let Log2LMUL = [-

[clang] [RISCV][clang] Add Zvfbfwma C intrinsics support (PR #79615)

@@ -0,0 +1,479 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ +// RUN: -target-feature +zvfh -target-feat

[clang] [RISCV] Change required features for Zvfhmin intrinsics from ZvfhminOrZvfh to Zvfhmin (PR #77866)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/77866 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Change required features for Zvfhmin intrinsics from ZvfhminOrZvfh to Zvfhmin (PR #77866)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/77866 >From #75735, Zvfh implies Zvfhmin. >From be8d27cf8a3cf511598437a401a2277b36752137 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Fri, 12 Jan 2024 09:58:49 +0800 Subject: [PATCH] [RISCV] Change required features

[clang] [llvm] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

@@ -386,6 +393,11 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector &Features, if (llvm::is_contained(Features, "+experimental")) HasExperimental = true; + if (ABI == "ilp32e" && ISAInfo->hasExtension("d")) { +Diags.Report(diag::err_invalid_feature_combinat

[clang] [RISCV] Remove redundant variable Log2LMUL from vset intrinsic. NFC (PR #76422)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/76422 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Remove redundant variable Log2LMUL from vset intrinsic. NFC (PR #76422)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/76422 None >From 460d1b9ece1fb208047a8c35088bd5dcb12279b2 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Wed, 27 Dec 2023 11:19:21 +0800 Subject: [PATCH] [RISCV] Remove redundant variable Log2LMUL for vset intrinsic.

[clang] [RISCV] Add MC layer support for Zicfiss. (PR #66043)

@@ -165,6 +167,10 @@ def SP : GPRRegisterClass<(add X2)>; def SR07 : GPRRegisterClass<(add (sequence "X%u", 8, 9), (sequence "X%u", 18, 23))>; +def GPRRA : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> { tclin914 wrote: I

[clang] c1dda0f - [AST] Remove unneeded `return false` from UseExcessPrecision. NFC.

Author: Jim Lin Date: 2023-08-30T16:05:55+08:00 New Revision: c1dda0f7934d28eb8dfc92206c49b188a1a091de URL: https://github.com/llvm/llvm-project/commit/c1dda0f7934d28eb8dfc92206c49b188a1a091de DIFF: https://github.com/llvm/llvm-project/commit/c1dda0f7934d28eb8dfc92206c49b188a1a091de.diff LOG:

[clang] d099dbb - [git-clang-format] Fix typo in help message

Author: Jim Lin Date: 2023-08-30T14:09:31+08:00 New Revision: d099dbb221a4c3474a15117b1658dedc5dcd6ebf URL: https://github.com/llvm/llvm-project/commit/d099dbb221a4c3474a15117b1658dedc5dcd6ebf DIFF: https://github.com/llvm/llvm-project/commit/d099dbb221a4c3474a15117b1658dedc5dcd6ebf.diff LOG:

[clang] af7231d - [RISCV] Make the order of tests in riscv-target-features.c eqaul to the extensions listed in the table in RISCVISAInfo.cpp. NFC.

Author: Jim Lin Date: 2023-08-18T12:56:12+08:00 New Revision: af7231d1835b3dbfd938c7fdff8188ce49a3b58b URL: https://github.com/llvm/llvm-project/commit/af7231d1835b3dbfd938c7fdff8188ce49a3b58b DIFF: https://github.com/llvm/llvm-project/commit/af7231d1835b3dbfd938c7fdff8188ce49a3b58b.diff LOG:

[clang] 767ca3a - [RISCV] Remove pre-defined macro test for b extension. NFC.

Author: Jim Lin Date: 2023-08-08T13:01:34+08:00 New Revision: 767ca3a70d6d60bd52ff0829335942aa6dafcc28 URL: https://github.com/llvm/llvm-project/commit/767ca3a70d6d60bd52ff0829335942aa6dafcc28 DIFF: https://github.com/llvm/llvm-project/commit/767ca3a70d6d60bd52ff0829335942aa6dafcc28.diff LOG:

[clang] d7abafa - [RISCV] Remove -menable-experimental-extensions option for zc extension in riscv-target-features.c. NFC.

Author: Jim Lin Date: 2023-08-07T14:03:33+08:00 New Revision: d7abafa6a03f3aa66b18b16cb040795201870845 URL: https://github.com/llvm/llvm-project/commit/d7abafa6a03f3aa66b18b16cb040795201870845 DIFF: https://github.com/llvm/llvm-project/commit/d7abafa6a03f3aa66b18b16cb040795201870845.diff LOG:

[clang] 1c10667 - [AST] Simplify Type::isSizelessBuiltinType(). NFC.

Author: Jim Lin Date: 2023-08-02T10:46:42+08:00 New Revision: 1c1066797c5bb56616dc485b596fd40d5f03ece2 URL: https://github.com/llvm/llvm-project/commit/1c1066797c5bb56616dc485b596fd40d5f03ece2 DIFF: https://github.com/llvm/llvm-project/commit/1c1066797c5bb56616dc485b596fd40d5f03ece2.diff LOG:

[clang] 8fe0449 - [RISCV] Fix required features checking with empty string

Author: Jim Lin Date: 2023-07-14T16:09:11+08:00 New Revision: 8fe0449ac99087c74f785ddbdd4fbba65b396b3b URL: https://github.com/llvm/llvm-project/commit/8fe0449ac99087c74f785ddbdd4fbba65b396b3b DIFF: https://github.com/llvm/llvm-project/commit/8fe0449ac99087c74f785ddbdd4fbba65b396b3b.diff LOG:

[clang] 612b7e1 - [RISCV] Change the type of argument to clz and ctz from ZiZi/WiWi to iUZi/iUWi

Author: Jim Lin Date: 2023-06-26T13:15:37+08:00 New Revision: 612b7e10a9afa797d41e134bc62a8ef87a014caf URL: https://github.com/llvm/llvm-project/commit/612b7e10a9afa797d41e134bc62a8ef87a014caf DIFF: https://github.com/llvm/llvm-project/commit/612b7e10a9afa797d41e134bc62a8ef87a014caf.diff LOG:

[clang] dc895d0 - [RISCV] Remove redundant line `NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py` from riscv64-zknd-zkne.c

Author: Jim Lin Date: 2023-06-15T10:22:06+08:00 New Revision: dc895d023e63fd9276fe493eded776e101015c86 URL: https://github.com/llvm/llvm-project/commit/dc895d023e63fd9276fe493eded776e101015c86 DIFF: https://github.com/llvm/llvm-project/commit/dc895d023e63fd9276fe493eded776e101015c86.diff LOG:

[clang] d4c5b45 - [NFC] Remove unneeded semicolon after function definition

Author: Jim Lin Date: 2023-06-07T09:29:49+08:00 New Revision: d4c5b452934a31f9b3685cf58bd682104b686d1a URL: https://github.com/llvm/llvm-project/commit/d4c5b452934a31f9b3685cf58bd682104b686d1a DIFF: https://github.com/llvm/llvm-project/commit/d4c5b452934a31f9b3685cf58bd682104b686d1a.diff LOG:

[clang] 33d3d51 - [RISCV] Add missing test for ctz_32 on RV64

Author: Jim Lin Date: 2023-05-22T10:28:27+08:00 New Revision: 33d3d51d77a7fb7ca6b919f9ba47999cd8531844 URL: https://github.com/llvm/llvm-project/commit/33d3d51d77a7fb7ca6b919f9ba47999cd8531844 DIFF: https://github.com/llvm/llvm-project/commit/33d3d51d77a7fb7ca6b919f9ba47999cd8531844.diff LOG:

[clang] ad39b5b - [NFC] Remove duplicate include

Author: Jim Lin Date: 2022-01-27T13:56:13+08:00 New Revision: ad39b5bc59b0e71c86f8cf290ead2d9dd09e5c3e URL: https://github.com/llvm/llvm-project/commit/ad39b5bc59b0e71c86f8cf290ead2d9dd09e5c3e DIFF: https://github.com/llvm/llvm-project/commit/ad39b5bc59b0e71c86f8cf290ead2d9dd09e5c3e.diff LOG:

[clang-tools-extra] f3314e3 - [clang-tidy] Pop Files only if FileChangeReason is ExitFile

Author: Jim Lin Date: 2022-01-25T22:46:12+08:00 New Revision: f3314e3747873fdf026a28742a30f372503baf32 URL: https://github.com/llvm/llvm-project/commit/f3314e3747873fdf026a28742a30f372503baf32 DIFF: https://github.com/llvm/llvm-project/commit/f3314e3747873fdf026a28742a30f372503baf32.diff LOG:

[clang] 9b70dda - [Builtins] Add missing the macro 'y' description in comments

Author: Jim Lin Date: 2022-01-10T10:43:13+08:00 New Revision: 9b70ddaff6e1d1ffc538ac74aa43b4fd6f73bb02 URL: https://github.com/llvm/llvm-project/commit/9b70ddaff6e1d1ffc538ac74aa43b4fd6f73bb02 DIFF: https://github.com/llvm/llvm-project/commit/9b70ddaff6e1d1ffc538ac74aa43b4fd6f73bb02.diff LOG:

[clang] 8a2d375 - [NFC] [Clang]: fix spelling mistake in assert message

Author: Jim Lin Date: 2021-04-12T14:10:52+08:00 New Revision: 8a2d375a77bfd9d73f7dbb12bed5c8a014aa2a53 URL: https://github.com/llvm/llvm-project/commit/8a2d375a77bfd9d73f7dbb12bed5c8a014aa2a53 DIFF: https://github.com/llvm/llvm-project/commit/8a2d375a77bfd9d73f7dbb12bed5c8a014aa2a53.diff LOG:

[clang] 32ca5a0 - [RISCV] Refine pre-define macro tests

Author: Jim Lin Date: 2021-03-31T14:06:20+08:00 New Revision: 32ca5a037ab9191d570bf9b5e0f13e28c3db27d9 URL: https://github.com/llvm/llvm-project/commit/32ca5a037ab9191d570bf9b5e0f13e28c3db27d9 DIFF: https://github.com/llvm/llvm-project/commit/32ca5a037ab9191d570bf9b5e0f13e28c3db27d9.diff LOG:

[clang] 6782417 - [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp

Author: Jim Lin Date: 2021-03-16T14:57:45+08:00 New Revision: 678241795c957b18bc473045e48abe3f2a61ff5c URL: https://github.com/llvm/llvm-project/commit/678241795c957b18bc473045e48abe3f2a61ff5c DIFF: https://github.com/llvm/llvm-project/commit/678241795c957b18bc473045e48abe3f2a61ff5c.diff LOG:

[clang] 7ee479a - [RISCV] Fix passing two floating-point values in complex separately by two GPRs on RV64

Author: Jim Lin Date: 2020-05-18T13:13:22+08:00 New Revision: 7ee479a760e0a4402b4eb7fb6168768a44f66945 URL: https://github.com/llvm/llvm-project/commit/7ee479a760e0a4402b4eb7fb6168768a44f66945 DIFF: https://github.com/llvm/llvm-project/commit/7ee479a760e0a4402b4eb7fb6168768a44f66945.diff LOG:

[clang] d40afad - [git-clang-format] Fix typo in help message

Author: Jim Lin Date: 2020-03-02T18:16:35+08:00 New Revision: d40afadec0acd5f093a5f46fa2362312aef54189 URL: https://github.com/llvm/llvm-project/commit/d40afadec0acd5f093a5f46fa2362312aef54189 DIFF: https://github.com/llvm/llvm-project/commit/d40afadec0acd5f093a5f46fa2362312aef54189.diff LOG:

[clang] 492d4a9 - [NFC] Update the testcase clang_f_opts.c for the removed options

Author: Jim Lin Date: 2020-02-19T09:28:41+08:00 New Revision: 492d4a992d88516da471b60ecd9a37ea80dbf9a4 URL: https://github.com/llvm/llvm-project/commit/492d4a992d88516da471b60ecd9a37ea80dbf9a4 DIFF: https://github.com/llvm/llvm-project/commit/492d4a992d88516da471b60ecd9a37ea80dbf9a4.diff LOG:

[clang] ea789f8 - Remove unused option that gcc ignored

Author: Jim Lin Date: 2020-02-19T08:36:07+08:00 New Revision: ea789f819f26a1b003a1bf07466fc9fa2fe558ec URL: https://github.com/llvm/llvm-project/commit/ea789f819f26a1b003a1bf07466fc9fa2fe558ec DIFF: https://github.com/llvm/llvm-project/commit/ea789f819f26a1b003a1bf07466fc9fa2fe558ec.diff LOG:

[clang] 466f884 - [NFC] Remove trailing space

Author: Jim Lin Date: 2020-02-18T10:49:13+08:00 New Revision: 466f8843f526b03c8944a46af5ebb374133b5389 URL: https://github.com/llvm/llvm-project/commit/466f8843f526b03c8944a46af5ebb374133b5389 DIFF: https://github.com/llvm/llvm-project/commit/466f8843f526b03c8944a46af5ebb374133b5389.diff LOG:

[clang] ab1bcda - [NFC] Use isX86() instead of getArch()

Author: Jim Lin Date: 2020-01-07T17:35:44+08:00 New Revision: ab1bcda851d95aeec03ffc1218bf9cae261a9280 URL: https://github.com/llvm/llvm-project/commit/ab1bcda851d95aeec03ffc1218bf9cae261a9280 DIFF: https://github.com/llvm/llvm-project/commit/ab1bcda851d95aeec03ffc1218bf9cae261a9280.diff LOG:

[clang-tools-extra] 8188c99 - [docs] Update path to clang-tools-extra

Author: Alexander Lanin Date: 2020-01-02T19:30:29+08:00 New Revision: 8188c998ffa4d20253444b257402907d2aa74dc2 URL: https://github.com/llvm/llvm-project/commit/8188c998ffa4d20253444b257402907d2aa74dc2 DIFF: https://github.com/llvm/llvm-project/commit/8188c998ffa4d20253444b257402907d2aa74dc2.dif

[clang] 4daa8d1 - Correct inf typo

Author: Andrew Gaul Date: 2019-12-13T11:02:40+08:00 New Revision: 4daa8d1de6dda58aebfa7b19547ed3ce4e9bc91a URL: https://github.com/llvm/llvm-project/commit/4daa8d1de6dda58aebfa7b19547ed3ce4e9bc91a DIFF: https://github.com/llvm/llvm-project/commit/4daa8d1de6dda58aebfa7b19547ed3ce4e9bc91a.diff L

[clang] 9c39663 - Only Remove implicit conversion for the target that support fp16

Author: Jim Lin Date: 2019-12-10T19:15:11+08:00 New Revision: 9c3966379813c198129c57aa3ebecd68d6af1ebd URL: https://github.com/llvm/llvm-project/commit/9c3966379813c198129c57aa3ebecd68d6af1ebd DIFF: https://github.com/llvm/llvm-project/commit/9c3966379813c198129c57aa3ebecd68d6af1ebd.diff LOG:

[clang] cefac9d - Remove implicit conversion that promotes half to other larger precision types for fp classification builtins

Author: Jim Lin Date: 2019-12-10T13:24:21+08:00 New Revision: cefac9dfaac9c806433ad88cca85bd2f3ba1edad URL: https://github.com/llvm/llvm-project/commit/cefac9dfaac9c806433ad88cca85bd2f3ba1edad DIFF: https://github.com/llvm/llvm-project/commit/cefac9dfaac9c806433ad88cca85bd2f3ba1edad.diff LOG: