[clang] [llvm] [RISCV] Implement Clang Builtins for XAndesPerf Extension (PR #147018)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/147018 >From 4ee3cbce0032f57c30692654be160e2745955f04 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Mon, 5 May 2025 13:58:59 +0800 Subject: [PATCH 1/3] [RISCV] Implement Clang Builtins for XAndesPerf Extension This pa

[clang] [RISCV] Split out the intrinsic tests for bfloat16 into a separate directory named zvfbfmin. NFC. (PR #147644)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/147644 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Split out the intrinsic tests for bfloat16 into a separate directory named zvfbfmin. NFC. (PR #147644)

tclin914 wrote: > I agree with you that it's easier to maintain, btw are you going to do that > for all extensions? For now, I'm going to do this for zvfh/zvfhmin/zvfbfmin/zvfbfwma. https://github.com/llvm/llvm-project/pull/147644 ___ cfe-commits mai

[clang] [RISCV] Add missing intrinsicis vrgatherei16/vslideup/vslidedown support for Zvfbfmin (PR #146309)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/146309 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] 862c2fc - [RISCV] Run mem2reg for riscv-xcvalu-c-api.c and riscv-xcvalu.c. NFC.

Author: Jim Lin Date: 2025-07-08T11:04:10+08:00 New Revision: 862c2fc26eb1611e1c06dccaaa650fc29f2546de URL: https://github.com/llvm/llvm-project/commit/862c2fc26eb1611e1c06dccaaa650fc29f2546de DIFF: https://github.com/llvm/llvm-project/commit/862c2fc26eb1611e1c06dccaaa650fc29f2546de.diff LOG:

[clang] [llvm] [RISCV] Implement Clang Builtins for XAndesPerf Extension (PR #147018)

@@ -0,0 +1,29 @@ +//==- BuiltinsRISCVXAndes.td - RISC-V Andes Builtin database -*- C++ -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[clang] [llvm] [RISCV] Implement Clang Builtins for XAndesPerf Extension (PR #147018)

@@ -0,0 +1,159 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +xandesperf -emit-llvm %s -o - \ tclin914 wrote: Done. Thanks. https://github.com/llvm/llvm-project/pull/147018

[clang] [llvm] [RISCV] Implement Clang Builtins for XAndesPerf Extension (PR #147018)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/147018 >From 4ee3cbce0032f57c30692654be160e2745955f04 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Mon, 5 May 2025 13:58:59 +0800 Subject: [PATCH 1/2] [RISCV] Implement Clang Builtins for XAndesPerf Extension This pa

[clang] [llvm] [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (PR #147005)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/147005 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add missing intrinsicis vrgatherei16/vslideup/vslidedown support for Zvfbfmin (PR #146309)

tclin914 wrote: Kindly ping. https://github.com/llvm/llvm-project/pull/146309 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (PR #147005)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/147005 >From a8b04339f8056e868fe2347d3af421f48c2d8308 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Thu, 3 Jul 2025 09:22:48 +0800 Subject: [PATCH 1/2] [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extens

[clang] [llvm] [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (PR #147005)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/147005 The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only implements MC support for XAndesVSIntLoad. >From a8b04339f8056e868fe2347d3af421f48c2d8308 Mo

[clang] [RISCV] Move vendor clang intrinsics tests to seperate directory. NFC. (PR #146862)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/146862 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Move vendor clang intrinsics tests to seperate directory. NFC. (PR #146862)

tclin914 wrote: Rebased. https://github.com/llvm/llvm-project/pull/146862 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Move vendor clang intrinsics tests to seperate directory. NFC. (PR #146862)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/146862 >From b187647420e85d0d038a30dcdf477d0cd6bce917 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Thu, 3 Jul 2025 19:34:49 +0800 Subject: [PATCH] [RISCV] Move vendor clang intrinsics tests to seperate directory. NFC

[clang] [llvm] [RISCV] Remove implied extension Zvfhmin for XAndesVPackFPH (PR #146861)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/146861 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV][MC] Add MC support of Zibi experimental extension (PR #127463)

@@ -0,0 +1,42 @@ +//===-- RISCVInstrInfoZibi.td - 'Zibi' instructions --*- tablegen -*-===// tclin914 wrote: The width of this line is not the same as in the other .td file. https://github.com/llvm/llvm-project/pull/127463 ___

[clang] [RISCV] Move vendor clang intrinsics tests to seperate directory. NFC. (PR #146862)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/146862 I'd like to ensure that the tests under clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/ only come from https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/main/auto-generated >From fde61340ea3ce043

[clang] [llvm] [RISCV] Remove implied extension Zvfhmin for XAndesVPackFPH (PR #146861)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/146861 XAndesVPackFPH can actually be used independently without requiring Zvfhmin. Therefore, we remove the implicitly required Zvfhmin extension from XAndesVPackFPH and imply that the f extension is sufficient. >F

[clang] 44bed1a - [RISCV] Add negative pre-defined macro test for XAndesVBFHCvt

Author: Jim Lin Date: 2025-07-03T09:06:01+08:00 New Revision: 44bed1af0fb641ce169262ab9fdb15ad76fe72a1 URL: https://github.com/llvm/llvm-project/commit/44bed1af0fb641ce169262ab9fdb15ad76fe72a1 DIFF: https://github.com/llvm/llvm-project/commit/44bed1af0fb641ce169262ab9fdb15ad76fe72a1.diff LOG:

[clang] [RISCV] Add missing intrinsicis vrgatherei16/vslideup/vslidedown support for Zvfbfmin (PR #146309)

tclin914 wrote: Rebased https://github.com/llvm/llvm-project/pull/146309 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] ce159d2 - [RISCV] Put REQUIRES: riscv-registered-target in the first line of the file. NFC.

Author: Jim Lin Date: 2025-07-01T12:18:16+08:00 New Revision: ce159d20e52add25e51f2aa8c504726221b204ba URL: https://github.com/llvm/llvm-project/commit/ce159d20e52add25e51f2aa8c504726221b204ba DIFF: https://github.com/llvm/llvm-project/commit/ce159d20e52add25e51f2aa8c504726221b204ba.diff LOG:

[clang] [RISCV] Add missing intrinsicis vrgatherei16/vslideup/vslidedown support for Zvfbfmin (PR #146309)

tclin914 wrote: > > LLVM IR intrinsicis for vrgatherei16/vslideup/vslidedown have been > > supported. > > Sorry, I found LLVM IR intrinsicis for vrgatherei16/vslideup/vslidedown > actually haven't been supported. LLVM IR intrinsicis for vrgatherei16/vslideup/vslidedown have been supported no

[clang] [RISCV] Add missing intrinsicis vrgatherei16/vslideup/vslidedown support for Zvfbfmin (PR #146309)

https://github.com/tclin914 edited https://github.com/llvm/llvm-project/pull/146309 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add missing intrinsicis vrgatherei16/vslideup/vslidedown support for Zvfbfmin (PR #146309)

https://github.com/tclin914 edited https://github.com/llvm/llvm-project/pull/146309 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add missing intrinsicis vrgatherei16/vslideup/vslidedown support for Zvfbfhmin (PR #146309)

tclin914 wrote: > LLVM IR intrinsicis for vrgatherei16/vslideup/vslidedown have been supported. Sorry, I found LLVM IR intrinsicis for vrgatherei16/vslideup/vslidedown actually haven't been supported. https://github.com/llvm/llvm-project/pull/146309

[clang] 59eaffe - [RISCV] Remove required features zvfhmin from vslideup/vslidedown

Author: Jim Lin Date: 2025-06-30T11:14:46+08:00 New Revision: 59eaffe93aec6dc116ab7db5ebfee84a6e36112d URL: https://github.com/llvm/llvm-project/commit/59eaffe93aec6dc116ab7db5ebfee84a6e36112d DIFF: https://github.com/llvm/llvm-project/commit/59eaffe93aec6dc116ab7db5ebfee84a6e36112d.diff LOG:

[clang] [RISCV] Remove required features zvfhmin/zvfbfmin from plain f16/bf16 intrinsics (PR #145891)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/145891 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Remove required features zvfhmin/zvfbfmin from plain f16/bf16 intrinsics (PR #145891)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/145891 We've checked f16/bf16 vector type support using `checkRVVTypeSupport`. So it's not necessary to add the required features for plain f16/bf16 intrinsics that do not use actual instructions from zvfhmin/zvfbfmi

[clang] [RISCV] Implement intrinsics for XAndesVBFHCVT (PR #145634)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/145634 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add missing required features for Zvfbfmin intrinsics (PR #145646)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/145646 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Decrease the capacity of SmallVector to 6. NFC. (PR #145650)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/145650 The maximum usage of these SmallVectors is only 6 elements. >From 233cb3f6c7bfa26d2c9010bb3d6108229a5002fc Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Wed, 25 Jun 2025 16:04:07 +0800 Subject: [PATCH] [RISCV]

[clang] [RISCV] Add missing required features for Zvfbfmin intrinsics (PR #145646)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/145646 Although `checkRVVTypeSupport` can prevent the use of bf16 vector types without Zvfbfmin, the required features for Zvfbfmin intrinsics may still be needed if bf16 vector types can someday be enabled by other

[clang] [RISCV] Implement intrinsics for XAndesVBFHCVT (PR #145634)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/145634 This patch implements clang intrinsic support for XAndesVBFHCVT. The clang intrinsicis for XAndesVBFHCVT is similar to Zvfbfmin, but it doesn't have mask variants. The document for the intrinsics can be found

[clang] [llvm] [RISCV] Add Andes AX45MPV processor definition (PR #145267)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/145267 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes AX45MPV processor definition (PR #145267)

@@ -0,0 +1,33 @@ +// RUN: %clang --target=riscv64 -mcpu=andes-ax45mpv --print-enabled-extensions | FileCheck %s tclin914 wrote: The style under `clang/test/Driver/print-enabled-extensions/` is one file per CPU https://github.com/llvm/llvm-project/pull/145267 _

[clang] [llvm] [RISCV] Add Andes AX45MPV processor definition (PR #145267)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/145267 Andes AX45MPV is 64-bit in-order dual-issue 8-stage pipeline linux-capable CPU implementing the RV64IMAFDCV ISA extension. That is developed by Andes Technology https://www.andestech.com, a RISC-V IP provider.

[clang] [llvm] Revert "[RISCV] Remove B and Zbc extension from Andes series cpus." (PR #144402)

tclin914 wrote: Since https://github.com/llvm/llvm-project/pull/144848 has landed, I reverted this reverted commit by https://github.com/llvm/llvm-project/commit/f78819aeef32e50ac3fec9a175b70a971b7c10e5. https://github.com/llvm/llvm-project/pull/144402 _

[clang] f78819a - Revert "Revert "[RISCV] Remove B and Zbc extension from Andes series cpus." (#144402)"

Author: Jim Lin Date: 2025-06-22T17:54:37+08:00 New Revision: f78819aeef32e50ac3fec9a175b70a971b7c10e5 URL: https://github.com/llvm/llvm-project/commit/f78819aeef32e50ac3fec9a175b70a971b7c10e5 DIFF: https://github.com/llvm/llvm-project/commit/f78819aeef32e50ac3fec9a175b70a971b7c10e5.diff LOG:

[clang] [llvm] [RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension (PR #144320)

tclin914 wrote: > LLVM Buildbot has detected a new failure on builder `arc-builder` running on > `arc-worker` while building `clang,llvm` at step 6 > "test-build-unified-tree-check-all". > > Full details are available at: > https://lab.llvm.org/buildbot/#/builders/3/builds/17667 > > Here is

[clang] [llvm] Revert "[RISCV] Remove B and Zbc extension from Andes series cpus." (PR #144402)

tclin914 wrote: I've summarized the issue in [#144639](https://github.com/llvm/llvm-project/issues/144639). https://github.com/llvm/llvm-project/pull/144402 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman

[clang] [llvm] [RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension (PR #144320)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/144320 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion) extension (PR #144320)

https://github.com/tclin914 edited https://github.com/llvm/llvm-project/pull/144320 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes XAndesVBFHCvt (Andes Vector BFLOAT16 Conversion Product) extension (PR #144320)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/144320 The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. The instructions are similar to `Zvfbfmin` and the only difference with

[clang] [llvm] [RISCV] Fix incorrect predicates for fp16 permutation intrinsics (PR #144063)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/144063 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Remove B and Zbc extension from Andes series cpus. (PR #144022)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/144022 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Remove B and Zbc extension from Andes series cpus. (PR #144022)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/144022 >From 9ac0064460dd2db6246a1f9b7d57b1d6c90006c4 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Thu, 12 Jun 2025 15:18:09 +0800 Subject: [PATCH] [RISCV] Remove B and Zbc extension from Andes series cpus. The Andes

[clang] [llvm] [RISCV] Fix incorrect predicates for fp16 permutation intrinsics (PR #144063)

@@ -7405,8 +7405,12 @@ defm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllInteger defm : VPatBinaryV_VX<"int_riscv_vslide1up", "PseudoVSLIDE1UP", AllIntegerVectors>; defm : VPatBinaryV_VX<"int_riscv_vslide1down", "PseudoVSLIDE1DOWN", AllIntegerVectors>;

[clang] [llvm] [RISCV] Fix incorrect predicates for fp16 permutation intrinsics (PR #144063)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/144063 >From 2efc3784e8a253c5e6c4737d11758a5597a8cff2 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Fri, 13 Jun 2025 15:58:41 +0800 Subject: [PATCH 1/2] [RISCV] Fix incorrect predicates for fp16 permutation intrinsics

[clang] [llvm] [RISCV] Remove B and Zbc extension from Andes series cpus. (PR #144022)

tclin914 wrote: > Not related to this PR, but I'd like to raise the question here: > > For configurable cores, what is the best way to specify the features? `-mcpu` > is meant to support the base configuration, but how can we specify the > additional optional extensions? Apparently, failing ba

[clang] [llvm] [RISCV] Fix incorrect predicates for fp16 permutation intrinsics (PR #144063)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/144063 vrgatherei16, vslideup and vslidedown should be supported with fp16 type for Zvfhmin. Fixes https://github.com/llvm/llvm-project/issues/143975. >From 2efc3784e8a253c5e6c4737d11758a5597a8cff2 Mon Sep 17 00:00:

[clang] [llvm] [RISCV] Remove B and Zbc extension from Andes series cpus. (PR #144022)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/144022 >From f1fdf9d521e1af3c0b96bedde95ac27d6ed3c58e Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Thu, 12 Jun 2025 15:18:09 +0800 Subject: [PATCH] [RISCV] Remove B and Zbc extension from Andes series cpus. The Andes

[clang] [llvm] [RISCV] Remove B and Zbc extension from Andes series cpus. (PR #144022)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/144022 The Andes CPU is configurable with optional extensions. The minimal required extension set does not include `B` and `Zbc` extensions. So we decided to remove them. >From 3ac3e3ec2a9fb1f69e75969bde5eae1ebadb16

[clang] [llvm][RISCV] Handle required features of intrinsic correctly (PR #143062)

https://github.com/tclin914 approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/143062 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm][RISCV] Handle required features of intrinsic correctly (PR #143062)

@@ -768,35 +768,13 @@ void RVVEmitter::createRVVIntrinsics( Log2LMULMask |= 1 << (Log2LMUL + 3); SR.Log2LMULMask = Log2LMULMask; - -for (auto RequiredFeature : RequiredFeatures) { - unsigned RequireExt = - StringSwitch(RequiredFeature) -

[clang] [llvm] [RISCV] Add support for -mtune=andes-45-series (PR #142900)

tclin914 wrote: > LLVM Buildbot has detected a new failure on builder `arc-builder` running on > `arc-worker` while building `clang,llvm` at step 6 > "test-build-unified-tree-check-all". > > Full details are available at: > https://lab.llvm.org/buildbot/#/builders/3/builds/17084 > > Here is

[clang] [llvm] [RISCV] Add support for -mtune=andes-45-series (PR #142900)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/142900 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [llvm][RISCV] Make zvknhb imply zvknha (PR #142896)

https://github.com/tclin914 approved this pull request. Refer to https://github.com/riscv/riscv-crypto/blob/main/doc/vector/riscv-crypto-vector-zvknh.adoc. LGTM https://github.com/llvm/llvm-project/pull/142896 ___ cfe-commits mailing list cfe-commits

[clang] [RISCV] Add pre-defined macro tests for Andes vendor extension. NFC. (PR #141172)

tclin914 wrote: Kindly ping. https://github.com/llvm/llvm-project/pull/141172 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Implement intrinsics for XAndesVDot (PR #141441)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/141441 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Add pre-defined macro tests for Andes vendor extension. NFC. (PR #141172)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/141172 None >From 036a3bd7024fe358d670b49d1d62bfe3cc0bc6d4 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Thu, 22 May 2025 15:05:30 +0800 Subject: [PATCH] [RISCV] Add pre-defined macro tests for Andes vendor extension

[clang] [llvm] [RISCV] Add FeatureVendorXAndesPerf to Andes N45/NX45/A45/AX45 (PR #141007)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/141007 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add FeatureVendorXAndesPerf to Andes N45/NX45/A45/AX45 (PR #141007)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/141007 Andes N45/NX45/A45/AX45 also support XAndesPerf. >From 655b5cb2fe3d2950757fd4b5c3ccac679033bf57 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Thu, 22 May 2025 09:42:55 +0800 Subject: [PATCH] [RISCV] Add Feature

[clang] [RISCV] Use print-enabled-extensions to check the extensions of Andes n45/nx45/a45/ax45 cpus. NFC. (PR #140979)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/140979 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Use print-enabled-extensions to check the extensions of Andes n45/nx45/a45/ax45 cpus. NFC. (PR #140979)

https://github.com/tclin914 edited https://github.com/llvm/llvm-project/pull/140979 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/140681 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/140681 >From 80f55eaaead598b0b557aa32756f59b201fc0fcd Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Tue, 20 May 2025 10:13:26 +0800 Subject: [PATCH 1/4] [RISCV] Add Andes A25/AX25 processor definition Andes A25/AX25 a

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/140681 >From 98bdcfd0b57b482f31be098e069e610897cc1425 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Tue, 20 May 2025 10:13:26 +0800 Subject: [PATCH 1/4] [RISCV] Add Andes A25/AX25 processor definition Andes A25/AX25 a

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

@@ -648,6 +648,38 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3", FeatureStdExtZcb, FeatureStdExtZcmp]>; +def ANDES_A25 : RISCVProcessorModel<"andes-a25", +

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

@@ -648,6 +648,38 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3", FeatureStdExtZcb, FeatureStdExtZcmp]>; +def ANDES_A25 : RISCVProcessorModel<"andes-a25", +

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/140681 >From 98bdcfd0b57b482f31be098e069e610897cc1425 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Tue, 20 May 2025 10:13:26 +0800 Subject: [PATCH 1/4] [RISCV] Add Andes A25/AX25 processor definition Andes A25/AX25 a

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

tclin914 wrote: Done. https://github.com/llvm/llvm-project/pull/140681 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/140681 >From 98bdcfd0b57b482f31be098e069e610897cc1425 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Tue, 20 May 2025 10:13:26 +0800 Subject: [PATCH 1/4] [RISCV] Add Andes A25/AX25 processor definition Andes A25/AX25 a

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

tclin914 wrote: > I thought it should have xandesperf extension? Added it. Thanks. https://github.com/llvm/llvm-project/pull/140681 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes A25/AX25 processor definition (PR #140681)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/140681 Andes A25/AX25 are 32/64bit, 5-stage pipeline, linux-capable CPUs that implement the RV[32|64]IMAFDC_Zba_Zbb_Zbc_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com, a RISC-V I

[clang] [llvm] [RISCV] Add Andes XAndesVDot (Andes Vector Dot Product) extension. (PR #139849)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/139849 The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. Intrinsics support will be added in a later patch. >From bc8ae48aa392d2

[clang] 9f274a9 - [RISCV] Fix indentation for riscv_corev_alu.h in CMakeLists.txt. NFC.

Author: Jim Lin Date: 2025-05-13T14:46:08+08:00 New Revision: 9f274a95b13a7c3fbd95d8f80f915a5548df2629 URL: https://github.com/llvm/llvm-project/commit/9f274a95b13a7c3fbd95d8f80f915a5548df2629 DIFF: https://github.com/llvm/llvm-project/commit/9f274a95b13a7c3fbd95d8f80f915a5548df2629.diff LOG:

[clang] [llvm] [RISCV] Add Andes XAndesVPackFPH (Andes Vector Packed FP16) extension. (PR #138827)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/138827 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes XAndesVPackFPH (Andes Vector Packed FP16) extension. (PR #138827)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/138827 Rate limit · GitHub body { background-color: #f6f8fa; color: #24292e; font-family: -apple-system,BlinkMacSystemFont,Segoe UI,Helvetica,Arial,sans-

[clang] [llvm] [RISCV] Add Andes XAndesVPackFPH (Andes Vector Packed FP16) extension. (PR #138827)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/138827 The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. Intrinsics support will be added in a later patch. >From 034d5c463c8616

[clang] [llvm] [RISCV] Rename XCValu intrinsic name *_slet(u) to *_sle(u)) (PR #138498)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/138498 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Rename XCValu intrinsic name *_slet(u) to *_sle(u)) (PR #138498)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/138498 The instruction name and intrinsic name have been renamed to sle(u). The `t` was removed. Please refer to https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md. >From dc6363

[clang] 56097bc - [RISCV][Clang] Fix typo: RISCXCVBuiltin -> RISCVXCVBuiltin. NFC.

Author: Jim Lin Date: 2025-05-05T16:40:49+08:00 New Revision: 56097bce97b4f0a9717268e9ddc1bb72bc49390c URL: https://github.com/llvm/llvm-project/commit/56097bce97b4f0a9717268e9ddc1bb72bc49390c DIFF: https://github.com/llvm/llvm-project/commit/56097bce97b4f0a9717268e9ddc1bb72bc49390c.diff LOG:

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/135110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/135110 >From 032d4cffd6b0157f4a563986af760a89411026e3 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Wed, 9 Apr 2025 09:44:47 +0800 Subject: [PATCH 01/12] [RISCV] Add Andes XAndesperf (Andes Performance) extension. Th

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

tclin914 wrote: Kindly ping. https://github.com/llvm/llvm-project/pull/135110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes A45/AX45 processor definition (PR #136832)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/136832 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes A45/AX45 processor definition (PR #136832)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/136832 Andes A45/AX45 are 32/64bit in-order dual-issue 8-stage pipeline linux-capable CPU implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com,

[clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)

https://github.com/tclin914 closed https://github.com/llvm/llvm-project/pull/136670 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)

@@ -625,3 +625,33 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3", FeatureStdExtZbkb, FeatureStdExtZcb, FeatureStdExtZcmp]>; + +def ANDES_N

[clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)

@@ -625,3 +625,33 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3", FeatureStdExtZbkb, FeatureStdExtZcb, FeatureStdExtZcmp]>; + +def ANDES_N

[clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/136670 >From df3a0b2bd9cb31fc8e252e250d3107dd1ac2cc0b Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Tue, 22 Apr 2025 10:12:23 +0800 Subject: [PATCH 1/2] [RISCV] Add Andes N45/NX45 processor definition Andes N45/NX45 a

[clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)

https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/136670 Andes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU architecture implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com,

[clang] [llvm] [RISCV] Add smcntrpmf extension (PR #136556)

@@ -1453,6 +1454,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SMCSRIND-EXT %s // CHECK-SMCSRIND-EXT: __riscv_smcsrind 100{{$}} +// RUN: %clang --target=riscv32 \ tclin914 wrote: Put the test for `smcntrpmf` above for `smcsrind` https://github.

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

@@ -0,0 +1,56 @@ +# XAndesPerf - Andes Performance Extension +# RUN: not llvm-mc -triple riscv32 -mattr=+xandesperf < %s 2>&1 \ +# RUN: | FileCheck %s +# RUN: not llvm-mc -triple riscv64 -mattr=+xandesperf < %s 2>&1 \ +# RUN: | FileCheck %s -check-prefix=CHECK-64 + +# Out

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/135110 >From b23dec1163f300189f1a2ce28f20c07d3cb9d5fe Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Wed, 9 Apr 2025 09:44:47 +0800 Subject: [PATCH 01/12] [RISCV] Add Andes XAndesperf (Andes Performance) extension. Th

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

tclin914 wrote: Rebased https://github.com/llvm/llvm-project/pull/135110 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/135110 >From b23dec1163f300189f1a2ce28f20c07d3cb9d5fe Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Wed, 9 Apr 2025 09:44:47 +0800 Subject: [PATCH 01/11] [RISCV] Add Andes XAndesperf (Andes Performance) extension. Th

[clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)

tclin914 wrote: > Do you have plan send PR to > https://github.com/riscv-non-isa/riscv-toolchain-conventions? PR: [https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/84](https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/84) https://github.com/llvm/llvm-project/

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

@@ -558,6 +558,34 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", TuneZExtWFusion, TuneShiftedZExtWFusion]>; +def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunmi

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