Author: Jim Lin Date: 2025-07-08T11:04:10+08:00 New Revision: 862c2fc26eb1611e1c06dccaaa650fc29f2546de
URL: https://github.com/llvm/llvm-project/commit/862c2fc26eb1611e1c06dccaaa650fc29f2546de DIFF: https://github.com/llvm/llvm-project/commit/862c2fc26eb1611e1c06dccaaa650fc29f2546de.diff LOG: [RISCV] Run mem2reg for riscv-xcvalu-c-api.c and riscv-xcvalu.c. NFC. Added: Modified: clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c clang/test/CodeGen/RISCV/riscv-xcvalu.c Removed: ################################################################################ diff --git a/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c b/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c index a0409e346d708..04dc5a78e4cea 100644 --- a/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c +++ b/clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c @@ -1,26 +1,14 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple riscv32 -target-feature +xcvalu -emit-llvm %s -o - \ -// RUN: | FileCheck %s +// RUN: -disable-O0-optnone | opt -S -passes=mem2reg | FileCheck %s #include <stdint.h> #include <riscv_corev_alu.h> // CHECK-LABEL: @test_alu_sle( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP4:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]] -// CHECK-NEXT: [[SLE_I:%.*]] = zext i1 [[TMP4]] to i32 +// CHECK-NEXT: [[TMP0:%.*]] = icmp sle i32 [[A:%.*]], [[B:%.*]] +// CHECK-NEXT: [[SLE_I:%.*]] = zext i1 [[TMP0]] to i32 // CHECK-NEXT: ret i32 [[SLE_I]] // int test_alu_sle(int32_t a, int32_t b) { @@ -29,20 +17,8 @@ int test_alu_sle(int32_t a, int32_t b) { // CHECK-LABEL: @test_alu_sleu( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP4:%.*]] = icmp ule i32 [[TMP2]], [[TMP3]] -// CHECK-NEXT: [[SLEU_I:%.*]] = zext i1 [[TMP4]] to i32 +// CHECK-NEXT: [[TMP0:%.*]] = icmp ule i32 [[A:%.*]], [[B:%.*]] +// CHECK-NEXT: [[SLEU_I:%.*]] = zext i1 [[TMP0]] to i32 // CHECK-NEXT: ret i32 [[SLEU_I]] // int test_alu_sleu(uint32_t a, uint32_t b) { @@ -51,19 +27,7 @@ int test_alu_sleu(uint32_t a, uint32_t b) { // CHECK-LABEL: @test_alu_min( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[ELT_MIN_I:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP2]], i32 [[TMP3]]) +// CHECK-NEXT: [[ELT_MIN_I:%.*]] = call i32 @llvm.smin.i32(i32 [[A:%.*]], i32 [[B:%.*]]) // CHECK-NEXT: ret i32 [[ELT_MIN_I]] // int test_alu_min(int32_t a, int32_t b) { @@ -72,19 +36,7 @@ int test_alu_min(int32_t a, int32_t b) { // CHECK-LABEL: @test_alu_minu( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[ELT_MIN_I:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP2]], i32 [[TMP3]]) +// CHECK-NEXT: [[ELT_MIN_I:%.*]] = call i32 @llvm.umin.i32(i32 [[A:%.*]], i32 [[B:%.*]]) // CHECK-NEXT: ret i32 [[ELT_MIN_I]] // int test_alu_minu(uint32_t a, uint32_t b) { @@ -93,19 +45,7 @@ int test_alu_minu(uint32_t a, uint32_t b) { // CHECK-LABEL: @test_alu_max( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[ELT_MAX_I:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP2]], i32 [[TMP3]]) +// CHECK-NEXT: [[ELT_MAX_I:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 [[B:%.*]]) // CHECK-NEXT: ret i32 [[ELT_MAX_I]] // int test_alu_max(int32_t a, int32_t b) { @@ -114,19 +54,7 @@ int test_alu_max(int32_t a, int32_t b) { // CHECK-LABEL: @test_alu_maxu( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[ELT_MAX_I:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP2]], i32 [[TMP3]]) +// CHECK-NEXT: [[ELT_MAX_I:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 [[B:%.*]]) // CHECK-NEXT: ret i32 [[ELT_MAX_I]] // int test_alu_maxu(uint32_t a, uint32_t b) { @@ -135,14 +63,8 @@ int test_alu_maxu(uint32_t a, uint32_t b) { // CHECK-LABEL: @test_alu_exths( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i16, align 2 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK-NEXT: store i16 [[A:%.*]], ptr [[A_ADDR]], align 2 -// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A_ADDR]], align 2 -// CHECK-NEXT: store i16 [[TMP0]], ptr [[A_ADDR_I]], align 2 -// CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[A_ADDR_I]], align 2 -// CHECK-NEXT: [[CONV_I:%.*]] = sext i16 [[TMP1]] to i32 -// CHECK-NEXT: [[EXTHS_I:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK-NEXT: [[CONV_I:%.*]] = sext i16 [[A:%.*]] to i32 +// CHECK-NEXT: [[EXTHS_I:%.*]] = sext i16 [[A]] to i32 // CHECK-NEXT: ret i32 [[EXTHS_I]] // int test_alu_exths(int16_t a) { @@ -151,14 +73,8 @@ int test_alu_exths(int16_t a) { // CHECK-LABEL: @test_alu_exthz( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i16, align 2 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK-NEXT: store i16 [[A:%.*]], ptr [[A_ADDR]], align 2 -// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A_ADDR]], align 2 -// CHECK-NEXT: store i16 [[TMP0]], ptr [[A_ADDR_I]], align 2 -// CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[A_ADDR_I]], align 2 -// CHECK-NEXT: [[CONV_I:%.*]] = zext i16 [[TMP1]] to i32 -// CHECK-NEXT: [[EXTHZ_I:%.*]] = zext i16 [[TMP1]] to i32 +// CHECK-NEXT: [[CONV_I:%.*]] = zext i16 [[A:%.*]] to i32 +// CHECK-NEXT: [[EXTHZ_I:%.*]] = zext i16 [[A]] to i32 // CHECK-NEXT: ret i32 [[EXTHZ_I]] // int test_alu_exthz(uint16_t a) { @@ -167,14 +83,8 @@ int test_alu_exthz(uint16_t a) { // CHECK-LABEL: @test_alu_extbs( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i8, align 1 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i8, align 1 -// CHECK-NEXT: store i8 [[A:%.*]], ptr [[A_ADDR]], align 1 -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1 -// CHECK-NEXT: store i8 [[TMP0]], ptr [[A_ADDR_I]], align 1 -// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[A_ADDR_I]], align 1 -// CHECK-NEXT: [[CONV_I:%.*]] = sext i8 [[TMP1]] to i32 -// CHECK-NEXT: [[EXTBS_I:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK-NEXT: [[CONV_I:%.*]] = sext i8 [[A:%.*]] to i32 +// CHECK-NEXT: [[EXTBS_I:%.*]] = sext i8 [[A]] to i32 // CHECK-NEXT: ret i32 [[EXTBS_I]] // int test_alu_extbs(int8_t a) { @@ -183,14 +93,8 @@ int test_alu_extbs(int8_t a) { // CHECK-LABEL: @test_alu_extbz( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i8, align 1 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i8, align 1 -// CHECK-NEXT: store i8 [[A:%.*]], ptr [[A_ADDR]], align 1 -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1 -// CHECK-NEXT: store i8 [[TMP0]], ptr [[A_ADDR_I]], align 1 -// CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[A_ADDR_I]], align 1 -// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 [[TMP1]] to i32 -// CHECK-NEXT: [[EXTBZ_I:%.*]] = zext i8 [[TMP1]] to i32 +// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 [[A:%.*]] to i32 +// CHECK-NEXT: [[EXTBZ_I:%.*]] = zext i8 [[A]] to i32 // CHECK-NEXT: ret i32 [[EXTBZ_I]] // int test_alu_extbz(uint8_t a) { @@ -199,17 +103,8 @@ int test_alu_extbz(uint8_t a) { // CHECK-LABEL: @test_alu_clip( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 0, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.alu.clip(i32 [[TMP1]], i32 [[TMP2]]) -// CHECK-NEXT: ret i32 [[TMP3]] +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.clip(i32 [[A:%.*]], i32 0) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_clip(int32_t a) { return __riscv_cv_alu_clip(a, 0); @@ -217,17 +112,8 @@ int test_alu_clip(int32_t a) { // CHECK-LABEL: @test_alu_clipu( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 0, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.alu.clipu(i32 [[TMP1]], i32 [[TMP2]]) -// CHECK-NEXT: ret i32 [[TMP3]] +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.clipu(i32 [[A:%.*]], i32 0) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_clipu(uint32_t a) { return __riscv_cv_alu_clipu(a, 0); @@ -235,24 +121,9 @@ int test_alu_clipu(uint32_t a) { // CHECK-LABEL: @test_alu_addN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[SHFT_ADDR_I:%.*]] = alloca i8, align 1 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: store i8 0, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 [[TMP4]] to i32 -// CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.riscv.cv.alu.addN(i32 [[TMP2]], i32 [[TMP3]], i32 [[CONV_I]]) -// CHECK-NEXT: ret i32 [[TMP5]] +// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 0 to i32 +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.addN(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[CONV_I]]) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_addN(int32_t a, int32_t b) { return __riscv_cv_alu_addN(a, b, 0); @@ -260,24 +131,9 @@ int test_alu_addN(int32_t a, int32_t b) { // CHECK-LABEL: @test_alu_adduN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[SHFT_ADDR_I:%.*]] = alloca i8, align 1 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: store i8 0, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 [[TMP4]] to i32 -// CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.riscv.cv.alu.adduN(i32 [[TMP2]], i32 [[TMP3]], i32 [[CONV_I]]) -// CHECK-NEXT: ret i32 [[TMP5]] +// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 0 to i32 +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.adduN(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[CONV_I]]) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_adduN(uint32_t a, uint32_t b) { return __riscv_cv_alu_adduN(a, b, 0); @@ -285,24 +141,9 @@ int test_alu_adduN(uint32_t a, uint32_t b) { // CHECK-LABEL: @test_alu_addRN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[SHFT_ADDR_I:%.*]] = alloca i8, align 1 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: store i8 0, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 [[TMP4]] to i32 -// CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.riscv.cv.alu.addRN(i32 [[TMP2]], i32 [[TMP3]], i32 [[CONV_I]]) -// CHECK-NEXT: ret i32 [[TMP5]] +// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 0 to i32 +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.addRN(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[CONV_I]]) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_addRN(int32_t a, int32_t b) { return __riscv_cv_alu_addRN(a, b, 0); @@ -310,24 +151,9 @@ int test_alu_addRN(int32_t a, int32_t b) { // CHECK-LABEL: @test_alu_adduRN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[SHFT_ADDR_I:%.*]] = alloca i8, align 1 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: store i8 0, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 [[TMP4]] to i32 -// CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.riscv.cv.alu.adduRN(i32 [[TMP2]], i32 [[TMP3]], i32 [[CONV_I]]) -// CHECK-NEXT: ret i32 [[TMP5]] +// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 0 to i32 +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.adduRN(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[CONV_I]]) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_adduRN(uint32_t a, uint32_t b) { return __riscv_cv_alu_adduRN(a, b, 0); @@ -335,24 +161,9 @@ int test_alu_adduRN(uint32_t a, uint32_t b) { // CHECK-LABEL: @test_alu_subN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[SHFT_ADDR_I:%.*]] = alloca i8, align 1 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: store i8 0, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 [[TMP4]] to i32 -// CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.riscv.cv.alu.subN(i32 [[TMP2]], i32 [[TMP3]], i32 [[CONV_I]]) -// CHECK-NEXT: ret i32 [[TMP5]] +// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 0 to i32 +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.subN(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[CONV_I]]) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_subN(int32_t a, int32_t b) { return __riscv_cv_alu_subN(a, b, 0); @@ -360,24 +171,9 @@ int test_alu_subN(int32_t a, int32_t b) { // CHECK-LABEL: @test_alu_subuN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[SHFT_ADDR_I:%.*]] = alloca i8, align 1 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: store i8 0, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 [[TMP4]] to i32 -// CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.riscv.cv.alu.subuN(i32 [[TMP2]], i32 [[TMP3]], i32 [[CONV_I]]) -// CHECK-NEXT: ret i32 [[TMP5]] +// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 0 to i32 +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.subuN(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[CONV_I]]) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_subuN(uint32_t a, uint32_t b) { return __riscv_cv_alu_subuN(a, b, 0); @@ -385,24 +181,9 @@ int test_alu_subuN(uint32_t a, uint32_t b) { // CHECK-LABEL: @test_alu_subRN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[SHFT_ADDR_I:%.*]] = alloca i8, align 1 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: store i8 0, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 [[TMP4]] to i32 -// CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.riscv.cv.alu.subRN(i32 [[TMP2]], i32 [[TMP3]], i32 [[CONV_I]]) -// CHECK-NEXT: ret i32 [[TMP5]] +// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 0 to i32 +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.subRN(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[CONV_I]]) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_subRN(int32_t a, int32_t b) { return __riscv_cv_alu_subRN(a, b, 0); @@ -410,24 +191,9 @@ int test_alu_subRN(int32_t a, int32_t b) { // CHECK-LABEL: @test_alu_subuRN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR_I:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[SHFT_ADDR_I:%.*]] = alloca i8, align 1 -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: store i32 [[TMP0]], ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: store i8 0, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[B_ADDR_I]], align 4 -// CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr [[SHFT_ADDR_I]], align 1 -// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 [[TMP4]] to i32 -// CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.riscv.cv.alu.subuRN(i32 [[TMP2]], i32 [[TMP3]], i32 [[CONV_I]]) -// CHECK-NEXT: ret i32 [[TMP5]] +// CHECK-NEXT: [[CONV_I:%.*]] = zext i8 0 to i32 +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.subuRN(i32 [[A:%.*]], i32 [[B:%.*]], i32 [[CONV_I]]) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_subuRN(uint32_t a, uint32_t b) { return __riscv_cv_alu_subuRN(a, b, 0); diff --git a/clang/test/CodeGen/RISCV/riscv-xcvalu.c b/clang/test/CodeGen/RISCV/riscv-xcvalu.c index 858f53ac49ba0..8a4fbbc3a115e 100644 --- a/clang/test/CodeGen/RISCV/riscv-xcvalu.c +++ b/clang/test/CodeGen/RISCV/riscv-xcvalu.c @@ -1,16 +1,13 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple riscv32 -target-feature +xcvalu -emit-llvm %s -o - \ -// RUN: | FileCheck %s +// RUN: -disable-O0-optnone | opt -S -passes=mem2reg | FileCheck %s #include <stdint.h> // CHECK-LABEL: @test_abs( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[TMP0]], i1 true) -// CHECK-NEXT: ret i32 [[TMP1]] +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.abs.i32(i32 [[A:%.*]], i1 true) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_abs(int a) { return __builtin_abs(a); @@ -18,14 +15,8 @@ int test_abs(int a) { // CHECK-LABEL: @test_alu_sle( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = icmp sle i32 [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SLE:%.*]] = zext i1 [[TMP2]] to i32 +// CHECK-NEXT: [[TMP0:%.*]] = icmp sle i32 [[A:%.*]], [[B:%.*]] +// CHECK-NEXT: [[SLE:%.*]] = zext i1 [[TMP0]] to i32 // CHECK-NEXT: ret i32 [[SLE]] // int test_alu_sle(int32_t a, int32_t b) { @@ -34,14 +25,8 @@ int test_alu_sle(int32_t a, int32_t b) { // CHECK-LABEL: @test_alu_sleu( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = icmp ule i32 [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[SLEU:%.*]] = zext i1 [[TMP2]] to i32 +// CHECK-NEXT: [[TMP0:%.*]] = icmp ule i32 [[A:%.*]], [[B:%.*]] +// CHECK-NEXT: [[SLEU:%.*]] = zext i1 [[TMP0]] to i32 // CHECK-NEXT: ret i32 [[SLEU]] // int test_alu_sleu(uint32_t a, uint32_t b) { @@ -50,12 +35,9 @@ int test_alu_sleu(uint32_t a, uint32_t b) { // CHECK-LABEL: @test_alu_exths( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK-NEXT: store i16 [[A:%.*]], ptr [[A_ADDR]], align 2 -// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A_ADDR]], align 2 -// CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP0]] to i32 -// CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[CONV]] to i16 -// CHECK-NEXT: [[EXTHS:%.*]] = sext i16 [[TMP1]] to i32 +// CHECK-NEXT: [[CONV:%.*]] = sext i16 [[A:%.*]] to i32 +// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[CONV]] to i16 +// CHECK-NEXT: [[EXTHS:%.*]] = sext i16 [[TMP0]] to i32 // CHECK-NEXT: ret i32 [[EXTHS]] // int test_alu_exths(int16_t a) { @@ -64,12 +46,9 @@ int test_alu_exths(int16_t a) { // CHECK-LABEL: @test_alu_exthz( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i16, align 2 -// CHECK-NEXT: store i16 [[A:%.*]], ptr [[A_ADDR]], align 2 -// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A_ADDR]], align 2 -// CHECK-NEXT: [[CONV:%.*]] = zext i16 [[TMP0]] to i32 -// CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[CONV]] to i16 -// CHECK-NEXT: [[EXTHZ:%.*]] = zext i16 [[TMP1]] to i32 +// CHECK-NEXT: [[CONV:%.*]] = zext i16 [[A:%.*]] to i32 +// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[CONV]] to i16 +// CHECK-NEXT: [[EXTHZ:%.*]] = zext i16 [[TMP0]] to i32 // CHECK-NEXT: ret i32 [[EXTHZ]] // int test_alu_exthz(uint16_t a) { @@ -78,12 +57,9 @@ int test_alu_exthz(uint16_t a) { // CHECK-LABEL: @test_alu_extbs( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i8, align 1 -// CHECK-NEXT: store i8 [[A:%.*]], ptr [[A_ADDR]], align 1 -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1 -// CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP0]] to i32 -// CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[CONV]] to i8 -// CHECK-NEXT: [[EXTBS:%.*]] = sext i8 [[TMP1]] to i32 +// CHECK-NEXT: [[CONV:%.*]] = sext i8 [[A:%.*]] to i32 +// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[CONV]] to i8 +// CHECK-NEXT: [[EXTBS:%.*]] = sext i8 [[TMP0]] to i32 // CHECK-NEXT: ret i32 [[EXTBS]] // int test_alu_extbs(int8_t a) { @@ -92,12 +68,9 @@ int test_alu_extbs(int8_t a) { // CHECK-LABEL: @test_alu_extbz( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i8, align 1 -// CHECK-NEXT: store i8 [[A:%.*]], ptr [[A_ADDR]], align 1 -// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1 -// CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 -// CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[CONV]] to i8 -// CHECK-NEXT: [[EXTBZ:%.*]] = zext i8 [[TMP1]] to i32 +// CHECK-NEXT: [[CONV:%.*]] = zext i8 [[A:%.*]] to i32 +// CHECK-NEXT: [[TMP0:%.*]] = trunc i32 [[CONV]] to i8 +// CHECK-NEXT: [[EXTBZ:%.*]] = zext i8 [[TMP0]] to i32 // CHECK-NEXT: ret i32 [[EXTBZ]] // int test_alu_extbz(uint8_t a) { @@ -106,11 +79,8 @@ int test_alu_extbz(uint8_t a) { // CHECK-LABEL: @test_alu_clip( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.alu.clip(i32 [[TMP0]], i32 15) -// CHECK-NEXT: ret i32 [[TMP1]] +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.clip(i32 [[A:%.*]], i32 15) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_clip(int32_t a) { return __builtin_riscv_cv_alu_clip(a, 15); @@ -118,11 +88,8 @@ int test_alu_clip(int32_t a) { // CHECK-LABEL: @test_alu_clipu( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.alu.clipu(i32 [[TMP0]], i32 15) -// CHECK-NEXT: ret i32 [[TMP1]] +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.clipu(i32 [[A:%.*]], i32 15) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_clipu(uint32_t a) { return __builtin_riscv_cv_alu_clipu(a, 15); @@ -130,14 +97,8 @@ int test_alu_clipu(uint32_t a) { // CHECK-LABEL: @test_alu_addN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.addN(i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK-NEXT: ret i32 [[TMP2]] +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.addN(i32 [[A:%.*]], i32 [[B:%.*]], i32 0) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_addN(int32_t a, int32_t b) { return __builtin_riscv_cv_alu_addN(a, b, 0); @@ -145,14 +106,8 @@ int test_alu_addN(int32_t a, int32_t b) { // CHECK-LABEL: @test_alu_adduN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.adduN(i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK-NEXT: ret i32 [[TMP2]] +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.adduN(i32 [[A:%.*]], i32 [[B:%.*]], i32 0) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_adduN(uint32_t a, uint32_t b) { return __builtin_riscv_cv_alu_adduN(a, b, 0); @@ -160,14 +115,8 @@ int test_alu_adduN(uint32_t a, uint32_t b) { // CHECK-LABEL: @test_alu_addRN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.addRN(i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK-NEXT: ret i32 [[TMP2]] +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.addRN(i32 [[A:%.*]], i32 [[B:%.*]], i32 0) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_addRN(int32_t a, int32_t b) { return __builtin_riscv_cv_alu_addRN(a, b, 0); @@ -175,14 +124,8 @@ int test_alu_addRN(int32_t a, int32_t b) { // CHECK-LABEL: @test_alu_adduRN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.adduRN(i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK-NEXT: ret i32 [[TMP2]] +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.adduRN(i32 [[A:%.*]], i32 [[B:%.*]], i32 0) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_adduRN(uint32_t a, uint32_t b) { return __builtin_riscv_cv_alu_adduRN(a, b, 0); @@ -190,14 +133,8 @@ int test_alu_adduRN(uint32_t a, uint32_t b) { // CHECK-LABEL: @test_alu_subN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.subN(i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK-NEXT: ret i32 [[TMP2]] +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.subN(i32 [[A:%.*]], i32 [[B:%.*]], i32 0) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_subN(int32_t a, int32_t b) { return __builtin_riscv_cv_alu_subN(a, b, 0); @@ -205,14 +142,8 @@ int test_alu_subN(int32_t a, int32_t b) { // CHECK-LABEL: @test_alu_subuN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.subuN(i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK-NEXT: ret i32 [[TMP2]] +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.subuN(i32 [[A:%.*]], i32 [[B:%.*]], i32 0) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_subuN(uint32_t a, uint32_t b) { return __builtin_riscv_cv_alu_subuN(a, b, 0); @@ -220,14 +151,8 @@ int test_alu_subuN(uint32_t a, uint32_t b) { // CHECK-LABEL: @test_alu_subRN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.subRN(i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK-NEXT: ret i32 [[TMP2]] +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.subRN(i32 [[A:%.*]], i32 [[B:%.*]], i32 0) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_subRN(int32_t a, int32_t b) { return __builtin_riscv_cv_alu_subRN(a, b, 0); @@ -235,14 +160,8 @@ int test_alu_subRN(int32_t a, int32_t b) { // CHECK-LABEL: @test_alu_subuRN( // CHECK-NEXT: entry: -// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 -// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 -// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4 -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.subuRN(i32 [[TMP0]], i32 [[TMP1]], i32 0) -// CHECK-NEXT: ret i32 [[TMP2]] +// CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.riscv.cv.alu.subuRN(i32 [[A:%.*]], i32 [[B:%.*]], i32 0) +// CHECK-NEXT: ret i32 [[TMP0]] // int test_alu_subuRN(uint32_t a, uint32_t b) { return __builtin_riscv_cv_alu_subuRN(a, b, 0); _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org 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