https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/147005
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only implements MC support for XAndesVSIntLoad. >From a8b04339f8056e868fe2347d3af421f48c2d8308 Mon Sep 17 00:00:00 2001 From: Jim Lin <j...@andestech.com> Date: Thu, 3 Jul 2025 09:22:48 +0800 Subject: [PATCH] [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only implements MC support for XAndesVSIntLoad. Co-authored-by: Lino Hsing-Yu Peng <linop...@andestech.com> --- .../Driver/print-supported-extensions-riscv.c | 1 + .../riscv-target-features-andes.c | 9 +++++ llvm/docs/RISCVUsage.rst | 3 ++ llvm/docs/ReleaseNotes.md | 1 + .../RISCV/Disassembler/RISCVDisassembler.cpp | 3 +- llvm/lib/Target/RISCV/RISCVFeatures.td | 8 ++++ llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td | 32 +++++++++++++++ llvm/test/CodeGen/RISCV/attributes.ll | 4 ++ llvm/test/CodeGen/RISCV/features-info.ll | 1 + llvm/test/MC/RISCV/xandesvsintload-valid.s | 39 +++++++++++++++++++ .../TargetParser/RISCVISAInfoTest.cpp | 1 + 11 files changed, 101 insertions(+), 1 deletion(-) create mode 100644 llvm/test/MC/RISCV/xandesvsintload-valid.s diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 2a9d4f3f9d1ba..b87f0cb568e00 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -162,6 +162,7 @@ // CHECK-NEXT: xandesvbfhcvt 5.0 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension) // CHECK-NEXT: xandesvdot 5.0 'XAndesVDot' (Andes Vector Dot Product Extension) // CHECK-NEXT: xandesvpackfph 5.0 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension) +// CHECK-NEXT: xandesvsintload 5.0 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension) // CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations) // CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching) // CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit Manipulation) diff --git a/clang/test/Preprocessor/riscv-target-features-andes.c b/clang/test/Preprocessor/riscv-target-features-andes.c index e2b783f200766..083deb02a2679 100644 --- a/clang/test/Preprocessor/riscv-target-features-andes.c +++ b/clang/test/Preprocessor/riscv-target-features-andes.c @@ -5,6 +5,7 @@ // CHECK-NOT: __riscv_xandesperf {{.*$}} // CHECK-NOT: __riscv_xandesvbfhcvt {{.*$}} +// CHECK-NOT: __riscv_xandesvsintload {{.*$}} // CHECK-NOT: __riscv_xandesvpackfph {{.*$}} // CHECK-NOT: __riscv_xandesvdot {{.*$}} @@ -24,6 +25,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVBFHCVT %s // CHECK-XANDESVBFHCVT: __riscv_xandesvbfhcvt 5000000{{$}} +// RUN: %clang --target=riscv32 \ +// RUN: -march=rv32i_xandesvsintload -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVSINTLOAD %s +// RUN: %clang --target=riscv64 \ +// RUN: -march=rv64i_xandesvsintload -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVSINTLOAD %s +// CHECK-XANDESVSINTLOAD: __riscv_xandesvsintload 5000000{{$}} + // RUN: %clang --target=riscv32 \ // RUN: -march=rv32i_xandesvpackfph -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVPACKFPH %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 82114791b3c0c..158a20cce7f85 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -519,6 +519,9 @@ The current vendor extensions supported are: ``XAndesVBFHCvt`` LLVM implements `version 5.0.0 of the Andes Vector BFLOAT16 Conversion Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification. +``XAndesVSINTLoad`` + LLVM implements `version 5.0.0 of the Andes Vector INT4 Load Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification. + ``XAndesVPackFPH`` LLVM implements `version 5.0.0 of the Andes Vector Packed FP16 Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification. diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 26384d94d04fc..daf822388a2ff 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -213,6 +213,7 @@ Changes to the RISC-V Backend * Adds assembler support for the Andes `XAndesvbfhcvt` (Andes Vector BFLOAT16 Conversion extension). * `-mcpu=andes-ax45mpv` was added. * Removed -mattr=+no-rvc-hints that could be used to disable parsing and generation of RVC hints. +* Adds assembler support for the Andes `XAndesvsintload` (Andes Vector INT4 Load extension). Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index aa45e7eeca56f..b723958a6ff28 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -775,7 +775,8 @@ static constexpr FeatureBitset XTHeadGroup = { static constexpr FeatureBitset XAndesGroup = { RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesVBFHCvt, - RISCV::FeatureVendorXAndesVPackFPH, RISCV::FeatureVendorXAndesVDot}; + RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH, + RISCV::FeatureVendorXAndesVDot}; static constexpr DecoderListEntry DecoderList32[]{ // Vendor Extensions diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index e42cd1a35cc06..addeab8d9aba6 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1607,6 +1607,14 @@ def HasVendorXAndesVBFHCvt AssemblerPredicate<(all_of FeatureVendorXAndesVBFHCvt), "'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)">; +def FeatureVendorXAndesVSIntLoad + : RISCVExtension<5, 0, "Andes Vector INT4 Load Extension", + [FeatureStdExtZve32x]>; +def HasVendorXAndesVSIntLoad + : Predicate<"Subtarget->hasVendorXAndesVSIntLoad()">, + AssemblerPredicate<(all_of FeatureVendorXAndesVSIntLoad), + "'XAndesVSIntLoad' (Andes Vector INT4 Load Extension)">; + def FeatureVendorXAndesVPackFPH : RISCVExtension<5, 0, "Andes Vector Packed FP16 Extension", [FeatureStdExtF]>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td index c7aa8cd5162b3..da417ed875142 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td @@ -391,6 +391,29 @@ class NDSRVInstVBFHCvt<bits<7> funct7, bits<5> vs1, string opcodestr> let Uses = [VL, VTYPE]; } +class NDSRVInstVLN<bits<5> funct5, string opcodestr> + : RVInst<(outs VR:$vd), (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), + opcodestr, "$vd, ${rs1}$vm", [], InstFormatR>, + VLESchedMC { + bits<5> rs1; + bits<5> vd; + bit vm; + + let Inst{31-26} = 0b000001; + let Inst{25} = vm; + let Inst{24-20} = funct5; + let Inst{19-15} = rs1; + let Inst{14-12} = 0b100; + let Inst{11-7} = vd; + let Inst{6-0} = OPC_CUSTOM_2.Value; + let hasSideEffects = 0; + let mayLoad = 0; + let mayStore = 0; + + let Uses = [VTYPE, VL]; + let RVVConstraint = VMConstraint; +} + //===----------------------------------------------------------------------===// // Multiclass //===----------------------------------------------------------------------===// @@ -542,6 +565,15 @@ let Uses = [FRM, VL, VTYPE] in def NDS_VFNCVT_BF16_S : NDSRVInstVBFHCvt<0b0000000, 0b00001, "nds.vfncvt.bf16.s">; } +//===----------------------------------------------------------------------===// +// XAndesVSIntLoad +//===----------------------------------------------------------------------===// + +let Predicates = [HasVendorXAndesVSIntLoad] in { +def NDS_VLN8_V : NDSRVInstVLN<0b00010, "nds.vln8.v">; +def NDS_VLNU8_V : NDSRVInstVLN<0b00011, "nds.vlnu8.v">; +} + //===----------------------------------------------------------------------===// // XAndesVPackFPH //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 750b152943cc6..43e16606aae73 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -107,6 +107,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisync %s -o - | FileCheck --check-prefix=RV32XQCISYNC %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV32XANDESPERF %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV32XANDESVBFHCVT %s +; RUN: llc -mtriple=riscv32 -mattr=+xandesvsintload %s -o - | FileCheck --check-prefix=RV32XANDESVSINTLOAD %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV32XANDESVDOT %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV32XANDESVPACKFPH %s ; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s @@ -262,6 +263,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV64XANDESPERF %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV64XANDESVBFHCVT %s +; RUN: llc -mtriple=riscv64 -mattr=+xandesvsintload %s -o - | FileCheck --check-prefix=RV64XANDESVSINTLOAD %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV64XANDESVDOT %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV64XANDESVPACKFPH %s ; RUN: llc -mtriple=riscv64 -mattr=+za64rs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZA64RS %s @@ -461,6 +463,7 @@ ; RV32XQCISYNC: attribute 5, "rv32i2p1_zca1p0_xqcisync0p3" ; RV32XANDESPERF: .attribute 5, "rv32i2p1_xandesperf5p0" ; RV32XANDESVBFHCVT: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0" +; RV32XANDESVSINTLOAD: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsintload5p0" ; RV32XANDESVDOT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0" ; RV32XANDESVPACKFPH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xandesvpackfph5p0" ; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0" @@ -618,6 +621,7 @@ ; RV64XTHEADVDOT: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0" ; RV64XANDESPERF: .attribute 5, "rv64i2p1_xandesperf5p0" ; RV64XANDESVBFHCVT: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0" +; RV64XANDESVSINTLOAD: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsintload5p0" ; RV64XANDESVDOT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0" ; RV64XANDESVPACKFPH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_xandesvpackfph5p0" ; RV64ZTSO: .attribute 5, "rv64i2p1_ztso1p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index ed8753eee130a..95d330889d2c0 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -176,6 +176,7 @@ ; CHECK-NEXT: xandesvbfhcvt - 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension). ; CHECK-NEXT: xandesvdot - 'XAndesVDot' (Andes Vector Dot Product Extension). ; CHECK-NEXT: xandesvpackfph - 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension). +; CHECK-NEXT: xandesvsintload - 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension). ; CHECK-NEXT: xcvalu - 'XCValu' (CORE-V ALU Operations). ; CHECK-NEXT: xcvbi - 'XCVbi' (CORE-V Immediate Branching). ; CHECK-NEXT: xcvbitmanip - 'XCVbitmanip' (CORE-V Bit Manipulation). diff --git a/llvm/test/MC/RISCV/xandesvsintload-valid.s b/llvm/test/MC/RISCV/xandesvsintload-valid.s new file mode 100644 index 0000000000000..19efba86a6104 --- /dev/null +++ b/llvm/test/MC/RISCV/xandesvsintload-valid.s @@ -0,0 +1,39 @@ +# XAndesVSIntLoad - Andes Vector INT4 Load Extension +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xandesvsintload -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xandesvsintload < %s \ +# RUN: | llvm-objdump --mattr=+xandesvsintload -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc %s -triple=riscv64 -mattr=+xandesvsintload -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xandesvsintload < %s \ +# RUN: | llvm-objdump --mattr=+xandesvsintload -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +# CHECK-OBJ: nds.vln8.v v8, (a0) +# CHECK-ASM: nds.vln8.v v8, (a0) +# CHECK-ASM: encoding: [0x5b,0x44,0x25,0x06] +# CHECK-ERROR: instruction requires the following: 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension){{$}} +nds.vln8.v v8, (a0) + +# CHECK-OBJ: nds.vln8.v v8, (a0), v0.t +# CHECK-ASM: nds.vln8.v v8, (a0), v0.t +# CHECK-ASM: encoding: [0x5b,0x44,0x25,0x04] +# CHECK-ERROR: instruction requires the following: 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension){{$}} +nds.vln8.v v8, (a0), v0.t + +# CHECK-OBJ: nds.vlnu8.v v8, (a0) +# CHECK-ASM: nds.vlnu8.v v8, (a0) +# CHECK-ASM: encoding: [0x5b,0x44,0x35,0x06] +# CHECK-ERROR: instruction requires the following: 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension){{$}} +nds.vlnu8.v v8, (a0) + +# CHECK-OBJ: nds.vlnu8.v v8, (a0), v0.t +# CHECK-ASM: nds.vlnu8.v v8, (a0), v0.t +# CHECK-ASM: encoding: [0x5b,0x44,0x35,0x04] +# CHECK-ERROR: instruction requires the following: 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension){{$}} +nds.vlnu8.v v8, (a0), v0.t diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 55314d6261fdf..9780eba5dc7a7 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1133,6 +1133,7 @@ R"(All available -march extensions for RISC-V xandesvbfhcvt 5.0 xandesvdot 5.0 xandesvpackfph 5.0 + xandesvsintload 5.0 xcvalu 1.0 xcvbi 1.0 xcvbitmanip 1.0 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
