https://github.com/tclin914 created
https://github.com/llvm/llvm-project/pull/146861
XAndesVPackFPH can actually be used independently without requiring Zvfhmin.
Therefore, we remove the implicitly required Zvfhmin extension from
XAndesVPackFPH and imply that the f extension is sufficient.
>From 6bd88ea3968f48149b478c5c42d600ce01529cda Mon Sep 17 00:00:00 2001
From: Jim Lin <j...@andestech.com>
Date: Thu, 3 Jul 2025 13:52:40 +0800
Subject: [PATCH] [RISCV] Remove implied extension Zvfhmin for XAndesVPackFPH
XAndesVPackFPH can actually be used independently without requiring
Zvfhmin. Therefore, we remove the implicitly required Zvfhmin extension
from XAndesVPackFPH and imply that the f extension is sufficient.
---
clang/lib/Sema/SemaRISCV.cpp | 12 +++++++++---
.../non-policy/non-overloaded/nds_vfpmadb.c | 1 -
.../non-policy/non-overloaded/nds_vfpmadt.c | 1 -
.../non-policy/overloaded/nds_vfpmadb.c | 1 -
.../non-policy/overloaded/nds_vfpmadt.c | 1 -
.../policy/non-overloaded/nds_vfpmadb.c | 1 -
.../policy/non-overloaded/nds_vfpmadt.c | 1 -
.../policy/overloaded/nds_vfpmadb.c | 1 -
.../policy/overloaded/nds_vfpmadt.c | 1 -
.../test/Sema/rvv-andes-required-features-invalid.c | 9 +++++++++
llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++--
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 ++-
llvm/test/CodeGen/RISCV/attributes.ll | 4 ++--
13 files changed, 24 insertions(+), 16 deletions(-)
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 37e7468103752..cc110e1115ed5 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -1435,9 +1435,15 @@ void SemaRISCV::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D,
!FeatureMap.lookup("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
else if (Info.ElementType->isFloat16Type() && !FeatureMap.lookup("zvfh") &&
- !FeatureMap.lookup("zvfhmin"))
- Diag(Loc, diag::err_riscv_type_requires_extension, D)
- << Ty << "zvfh or zvfhmin";
+ !FeatureMap.lookup("zvfhmin") &&
+ !FeatureMap.lookup("xandesvpackfph"))
+ if (DeclareAndesVectorBuiltins) {
+ Diag(Loc, diag::err_riscv_type_requires_extension, D)
+ << Ty << "zvfh, zvfhmin or xandesvpackfph";
+ } else {
+ Diag(Loc, diag::err_riscv_type_requires_extension, D)
+ << Ty << "zvfh or zvfhmin";
+ }
else if (Info.ElementType->isBFloat16Type() &&
!FeatureMap.lookup("zvfbfmin") &&
!FeatureMap.lookup("xandesvbfhcvt"))
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadb.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadb.c
index 48e3a1b0fc295..ec0ad7d23ac8b 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadb.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadb.c
@@ -1,7 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \
-// RUN: -target-feature +zvfhmin \
// RUN: -target-feature +xandesvpackfph -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadt.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadt.c
index e435a31eb3314..e0627b3e0f6cc 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadt.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/nds_vfpmadt.c
@@ -1,7 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \
-// RUN: -target-feature +zvfhmin \
// RUN: -target-feature +xandesvpackfph -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/nds_vfpmadb.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/nds_vfpmadb.c
index 46c6648bc7a82..686b476b0d594 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/nds_vfpmadb.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/nds_vfpmadb.c
@@ -1,7 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \
-// RUN: -target-feature +zvfhmin \
// RUN: -target-feature +xandesvpackfph -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/nds_vfpmadt.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/nds_vfpmadt.c
index 62fe9b7bc10e7..228d474f2c221 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/nds_vfpmadt.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/nds_vfpmadt.c
@@ -1,7 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \
-// RUN: -target-feature +zvfhmin \
// RUN: -target-feature +xandesvpackfph -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/nds_vfpmadb.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/nds_vfpmadb.c
index bda6a5292ae3d..3c6143dc32606 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/nds_vfpmadb.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/nds_vfpmadb.c
@@ -1,7 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \
-// RUN: -target-feature +zvfhmin \
// RUN: -target-feature +xandesvpackfph -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/nds_vfpmadt.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/nds_vfpmadt.c
index bfcc1e18bd351..f8852fba2f991 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/nds_vfpmadt.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/nds_vfpmadt.c
@@ -1,7 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \
-// RUN: -target-feature +zvfhmin \
// RUN: -target-feature +xandesvpackfph -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/nds_vfpmadb.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/nds_vfpmadb.c
index c7e6abc7a7e19..69e025709ec46 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/nds_vfpmadb.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/nds_vfpmadb.c
@@ -1,7 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \
-// RUN: -target-feature +zvfhmin \
// RUN: -target-feature +xandesvpackfph -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/nds_vfpmadt.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/nds_vfpmadt.c
index 7e351e096821e..a8270fa18cc7e 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/nds_vfpmadt.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/nds_vfpmadt.c
@@ -1,7 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \
-// RUN: -target-feature +zvfhmin \
// RUN: -target-feature +xandesvpackfph -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
diff --git a/clang/test/Sema/rvv-andes-required-features-invalid.c
b/clang/test/Sema/rvv-andes-required-features-invalid.c
index dbb8b2895bedf..cd59322225e05 100644
--- a/clang/test/Sema/rvv-andes-required-features-invalid.c
+++ b/clang/test/Sema/rvv-andes-required-features-invalid.c
@@ -9,3 +9,12 @@ vfloat32mf2_t test_nds_vfwcvt_s_bf16_f32mf2(vbfloat16mf4_t
vs2, size_t vl) {
// expected-error@-1 {{RISC-V type 'vbfloat16mf4_t' (aka
'__rvv_bfloat16mf4_t') requires the 'zvfbfmin or xandesvbfhcvt' extension}}
// expected-error@-2 {{builtin requires at least one of the following
extensions: xandesvbfhcvt}}
}
+
+vfloat16mf4_t test_nds_vfpmadb_vf_f16mf4(vfloat16mf4_t op1, float op2, size_t
vl) {
+ // expected-error@-1 {{RISC-V type 'vfloat16mf4_t' (aka
'__rvv_float16mf4_t') requires the 'zvfh, zvfhmin or xandesvpackfph' extension}}
+ // expected-error@-2 {{RISC-V type 'vfloat16mf4_t' (aka
'__rvv_float16mf4_t') requires the 'zvfh, zvfhmin or xandesvpackfph' extension}}
+ return __riscv_nds_vfpmadb_vf_f16mf4(op1, op2, vl); // expected-error
{{RISC-V type '__rvv_float16mf4_t' requires the 'zvfh, zvfhmin or
xandesvpackfph' extension}}
+ // expected-error@-1 {{RISC-V type '__rvv_float16mf4_t' requires the 'zvfh,
zvfhmin or xandesvpackfph' extension}}
+ // expected-error@-2 {{RISC-V type 'vfloat16mf4_t' (aka
'__rvv_float16mf4_t') requires the 'zvfh, zvfhmin or xandesvpackfph' extension}}
+ // expected-error@-3 {{builtin requires at least one of the following
extensions: xandesvpackfph}}
+}
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 6e103dd7d8c44..db6d6828306b7 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1602,8 +1602,8 @@ def HasVendorXAndesVBFHCvt
def FeatureVendorXAndesVPackFPH
- : RISCVExtension<5, 0, "Andes Vector Packed FP16 Extension",
- [FeatureStdExtZvfhmin]>;
+ : RISCVExtension<5, 0,
+ "Andes Vector Packed FP16 Extension", [FeatureStdExtF]>;
def HasVendorXAndesVPackFPH
: Predicate<"Subtarget->hasVendorXAndesVPackFPH()">,
AssemblerPredicate<(all_of FeatureVendorXAndesVPackFPH),
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 30758345ab0f6..40cb29c5b1f54 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -211,7 +211,8 @@ RISCVTargetLowering::RISCVTargetLowering(const
TargetMachine &TM,
addRegClassForRVV(VT);
}
- if (Subtarget.hasVInstructionsF16Minimal())
+ if (Subtarget.hasVInstructionsF16Minimal() ||
+ Subtarget.hasVendorXAndesVPackFPH())
for (MVT VT : F16VecVTs)
addRegClassForRVV(VT);
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index d0afea9754aa0..750b152943cc6 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -462,7 +462,7 @@
; RV32XANDESPERF: .attribute 5, "rv32i2p1_xandesperf5p0"
; RV32XANDESVBFHCVT: .attribute 5,
"rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0"
; RV32XANDESVDOT: .attribute 5,
"rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0"
-; RV32XANDESVPACKFPH: .attribute 5,
"rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0_xandesvpackfph5p0"
+; RV32XANDESVPACKFPH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xandesvpackfph5p0"
; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0"
; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc1p0"
; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0"
@@ -619,7 +619,7 @@
; RV64XANDESPERF: .attribute 5, "rv64i2p1_xandesperf5p0"
; RV64XANDESVBFHCVT: .attribute 5,
"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0"
; RV64XANDESVDOT: .attribute 5,
"rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0"
-; RV64XANDESVPACKFPH: .attribute 5,
"rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0_xandesvpackfph5p0"
+; RV64XANDESVPACKFPH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_xandesvpackfph5p0"
; RV64ZTSO: .attribute 5, "rv64i2p1_ztso1p0"
; RV64ZAAMO: .attribute 5, "rv64i2p1_zaamo1p0"
; RV64ZALRSC: .attribute 5, "rv64i2p1_zalrsc1p0"
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
