LGTM,
Cheers,
Claudiu
On Tue, Mar 18, 2025 at 6:23 PM Luis Silva wrote:
>
> This patch handles both signed and unsigned
> builtin multiplication overflow.
>
> Uses the "mpy.f" instruction to set the condition
> codes based on the result. In the event of an
> overflow, the V flag is set, trigger
LGTM, I'll merge it once stage 1 is open.
Cheers,
Claudiu
On Tue, Mar 18, 2025 at 6:22 PM Luis Silva wrote:
>
> This patch introduces two new instruction patterns:
>
> `*mulsi3_cmp0`: This pattern performs a multiplication
> and sets the CC_Z register based on the result, while
> al
LGTM. I'll merge it once stage one is open.
Cheers,
Claudiu
On Tue, Mar 18, 2025 at 6:23 PM Luis Silva wrote:
>
> Due to the patch by Roger Sayle,
> 09881218137f4af9b7c894c2d350cf2ff8e0ee23, which
> introduces the use of the `rlc rX,0` instruction in place
> of the `mov.hs`, the add overflow tes
I'll include your comment in my second patch where I clean some
patterns used by reload.
Thank you,
claudiu
On Mon, Sep 23, 2024 at 5:05 PM Andreas Schwab wrote:
>
> On Sep 23 2024, Claudiu Zissulescu wrote:
>
> > diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
&
:
* config/arc/arc.cc (TARGET_LRA_P): Always return true.
(arc_lra_p): Remove.
* config/arc/arc.h (TARGET_LRA): Remove.
* config/arc/arc.opt (mlra): Change it to do nothing.
* doc/invoke.texi (mlra): Update option description.
Signed-off-by: Claudiu Zissulescu
---
gcc
https://gcc.gnu.org/g:ffd861c808f307c865659b556dd5a8c922bd6a51
commit r15-3798-gffd861c808f307c865659b556dd5a8c922bd6a51
Author: Claudiu Zissulescu
Date: Mon Sep 23 15:49:36 2024 +0300
arc: Remove mlra option [PR113954]
The target dependent mlra option was designed to be able to
mize_tls_address works. If you have any pointers on how to manipulate
> > RTL to get the assembly required as seen above, I would be very much
> > grateful :)
> >
> > best regards,
> > Julian
> >
> > On Tue, Jul 16, 2024 at 8:16 PM Claudiu Zissulescu Ianc
Hi Julian,
You can check how we did it for ARC. In a nutshell, you need to define
HAVS_AS_TLS macro, you need to legitimize the new TLS address and
calls. Please have a look in arc.cc and search for TLS, also use git
blame to see the original patches. Of course, there are different ways
to impleme
https://gcc.gnu.org/g:382e2123c402edb6123f0c4669fa298d4140edd8
commit r15-1744-g382e2123c402edb6123f0c4669fa298d4140edd8
Author: Claudiu Zissulescu
Date: Mon Jul 1 10:49:29 2024 +0300
[MAINTAINERS] Update my email address
Update my email address.
ChangeLog
Update my email address.
ChangeLog:
* MAINTAINERS: Update claziss email address.
Signed-off-by: Claudiu Zissulescu
---
MAINTAINERS | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 41319595bb5..ddeea7b497f 100644
--- a/MAINTAINERS
HI Roger,
It looks good.
Thank you for your contribution,
Claudiu
-Original Message-
From: Roger Sayle
Sent: Sunday, December 24, 2023 1:38 AM
To: gcc-patches@gcc.gnu.org
Cc: 'Claudiu Zissulescu' ; 'Jeff Law'
Subject: [ARC PATCH] Table-driven ashlsi implementat
Hi Roger,
It looks good to me.
Thank you for your contribution,
Claudiu
-Original Message-
From: Roger Sayle
Sent: Tuesday, December 5, 2023 4:00 PM
To: gcc-patches@gcc.gnu.org
Cc: 'Claudiu Zissulescu'
Subject: [ARC PATCH] Add *extvsi_n_0 define_insn_and_split for PR 1107
Sayle
Sent: Monday, November 6, 2023 8:37 PM
To: gcc-patches@gcc.gnu.org
Cc: 'Claudiu Zissulescu'
Subject: [ARC PATCH] Consistent use of whitespace in assembler templates.
This minor clean-up patch tweaks arc.md to use whitespace consistently in
output templates, always using a TAB b
Looks good too. Please proceed with your commit.
Thank you for your contribution,
//Claudiu
-Original Message-
From: Roger Sayle
Sent: Monday, November 6, 2023 7:30 PM
To: gcc-patches@gcc.gnu.org
Cc: 'Claudiu Zissulescu'
Subject: [ARC PATCH] Improved DImode rotates and right
Hi Roger,
Looks good. Please proceed with your commit.
Thank you,
Claudiu
-Original Message-
From: Roger Sayle
Sent: Friday, November 3, 2023 9:43 PM
To: gcc-patches@gcc.gnu.org
Cc: 'Claudiu Zissulescu'
Subject: [ARC PATCH] Provide a TARGET_FOLD_BUILTIN target hook.
Missed this one.
Ok, please proceed with the commit.
Thank you for your contribution,
Claudiu
On Sat, Oct 28, 2023 at 4:05 PM Roger Sayle wrote:
>
>
> This patch improves the code generated for X << 1 (and for X + X) when
> X is 64-bit DImode, using the same two instruction code sequence used
>
Hi Roger,
Do you want to say bmsk_s instead of msk_s here:
+/* { dg-final { scan-assembler "msk_s\\s+r0,r0,0" } } */
Anyhow, the patch looks good. Proceed with your commit.
Thank you,
Claudiu
On Mon, Oct 30, 2023 at 5:05 AM Jeff Law wrote:
>
>
>
> On 10/28/23 10:47, Roger Sayle wrote:
> >
> >
Hi Roger,
You have a block of 8 spaces that needs to be replaced by tabs:
gcc/config/arc/arc.cc:5538:0: if (n < 4)
Please fix the above, and proceed with your commit.
Thank you,
Claudiu
On Sun, Oct 29, 2023 at 11:16 AM Roger Sayle wrote:
>
>
> This patch overhauls the ARC backend's insn_
Hi Roger,
+(define_insn "si2_cnt16"
+ [(set (match_operand:SI 0 "dest_reg_operand" "=w")
Please use "register_operand", and "r" constraint.
+(ANY_ROTATE:SI (match_operand:SI 1 "register_operand" "c")
Please use "r" constraint instead of "c".
+ (const_int 16)))]
+ "TARGET_SW
The mpy_dest_reg_operand is just a wrapper for
register_operand. Remove it.
gcc/
* config/arc/arc.md (mulsi3_700): Update pattern.
(mulsi3_v2): Likewise.
* config/arc/predicates.md (mpy_dest_reg_operand): Remove it.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc
Hi Roger,
Your patch doesn't introduce new regressions. However, before pushing
to the mainline you need to fix some issues:
1. Please fix the trailing spaces and blocks of 8 spaces which should
be replaced with tabs. You can use check_GNU_style.py script to spot
them.
2. Please use capital letter
Hi Roger,
Indeed, I was missing the patch file.
Approved.
Thank you for your contribution,
Claudiu
On Sun, Oct 15, 2023 at 11:14 AM Roger Sayle wrote:
>
> I’ve done it again. ENOPATCH.
>
>
>
> From: Roger Sayle
> Sent: 15 October 2023 09:13
> To: 'gcc-patches
ke pattern canonical.
(addsi_compare_2): Fix identation, constraint letters.
(addsi_compare_3): Likewise.
gcc/testsuite/
* gcc.target/arc/add_f-combine.c: New test.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc| 2 +-
g
.
(arc_output_libcall): Likewise.
* config/arc/arc.md: Remove ccfsm references and update related
instruction patterns.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc-passes.def | 6 -
gcc/config/arc/arc-protos.h | 7 -
gcc/config/arc/arc.cc | 830
gcc/testsuite:
* gcc.target/arc/enter-dw2-1.c: Remove tests when using linux
build.
* gcc.target/arc/tls-ld.c: Update test.
* gcc.target/arc/tls-le.c: Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/testsuite/gcc.target/arc/enter-dw2-1.c | 18
/arc.md: Update patterns which uses '%&'.
gcc/testsuite/
* gcc.target/arc/loop-3.c: Update test.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 9 -
gcc/config/arc/arc.md | 18 +-
gcc/testsuite/gcc.targ
.c: Set it to XFAIL.
Signed-off-by: Claudiu Zissulescu
---
gcc/testsuite/gcc.target/arc/add_n-combine.c | 2 +-
gcc/testsuite/gcc.target/arc/firq-4.c | 1 -
gcc/testsuite/gcc.target/arc/firq-6.c | 1 -
gcc/testsuite/gcc.target/arc/mtune-ARC600.c| 4
gcc/testsuite
Update description.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc-protos.h | 2 -
gcc/config/arc/arc.cc | 33 ++
gcc/config/arc/arc.h| 16 -
gcc/config/arc/arc.md | 125 ++--
gcc/config/arc/arc.opt | 4 +-
gc
Hi Roger,
The patch as it is passed the validation, and it is in general OK.
Although it doesn't address the elephant in the room, namely
output_shift function, it is a welcome cleanup.
I would like you to split the patch in two. One which deals with
improvements on shifts in absence of a barrel s
;m happy to update/revise my patch based on this
> and your feedback, for example preferring add over
> asl_s (or controlling this choice with -Os).
>
> Thanks again.
> Roger
> --
>
> > -Original Message-
> > From: Claudiu Zissulescu
> > Sent: 03 Octob
: gcc-patches@gcc.gnu.org
Cc: Claudiu Zissulescu
Subject: [ARC PATCH] Split SImode shifts pre-reload on !TARGET_BARREL_SHIFTER.
Hi Claudiu,
It was great meeting up with you and the Synopsys ARC team at the GNU tools
Cauldron in Cambridge.
This patch is the first in a series to improve SImod
Hi Roger,
Everything is good. Ok for mainline.
Thank you for your contribution,
Claudiu
-Original Message-
From: Claudiu Zissulescu
Sent: Sunday, October 1, 2023 5:33 PM
To: Jeff Law ; Roger Sayle
Cc: gcc-patches@gcc.gnu.org
Subject: RE: [ARC PATCH] Use rlc r0, 0 to implement scc_ltu
1:02 AM
To: Roger Sayle ; Claudiu Zissulescu
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [ARC PATCH] Use rlc r0, 0 to implement scc_ltu (i.e. carry_flag ?
1 : 0)
On 9/29/23 15:11, Roger Sayle wrote:
>
> Hi Claudiu,
>> The patch looks sane. Have you run dejagnu test suite?
>
> I
Hi Roger,
The patch looks sane. Have you run dejagnu test suite?
Thanks,
Claudiu
-Original Message-
From: Roger Sayle
Sent: Friday, September 29, 2023 6:54 PM
To: gcc-patches@gcc.gnu.org
Cc: Claudiu Zissulescu
Subject: [ARC PATCH] Use rlc r0,0 to implement scc_ltu (i.e. carry_flag
OK,
Thank you for your contribution,
Claudiu
On Wed, Sep 6, 2023 at 3:50 PM Shahab Vahedi wrote:
>
> This patch covers signed and unsigned subtractions. The generated code
> would be something along these lines:
>
> signed:
> sub.f r0, r1, r2
> b.v @label
>
> unsigned:
> sub.f r0,
Ok.
Thank you for your contribution,
Claudiu
On Wed, Sep 6, 2023 at 3:50 PM Shahab Vahedi wrote:
>
> This patch covers signed and unsigned additions. The generated code
> would be something along these lines:
>
> signed:
> add.f r0, r1, r2
> b.v @label
>
> unsigned:
> add.f r0, r1
nge code letter from 'S' to 'J'.
* config/arc/arc700.md: Add newly introduced types.
* config/arc/arcHS.md: Likewsie.
* config/arc/arcHS4x.md: Likewise.
* config/arc/constraints.md (Cca, CL2, Csp, C2a): Remove it.
(CM4): Update descrip
option.
* doc/invoke.texi (mbbit-peephole): Update document.
Signed-off-by: Claudiu Zissulescu
---
gcc/common/config/arc/arc-common.cc | 1 -
gcc/config/arc/arc.md | 31 -
gcc/config/arc/arc.opt | 4 ++--
gcc/doc/invoke.texi
The LSL16 instruction is only available if SWAP (-mswap) option is
turned on.
gcc/ChangeLog:
* config/arc/arc.cc (arc_split_mov_const): Use LSL16 only when
SWAP option is enabled.
* config/arc/arc.md (ashlsi2_cnt16): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc
gcc/ChangeLog:
* doc/extend.texi (ARC Built-in Functions): Update documentation
with missing builtins.
---
gcc/doc/extend.texi | 55 +
1 file changed, 55 insertions(+)
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index d701b4d1
rc.cc (arc_call_tls_get_addr): Simplify access using
TLS Local Dynamic.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 24 +---
1 file changed, 1 insertion(+), 23 deletions(-)
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index dd012f
ARC has enter_s/leave_s instructions which can save/restore the entire
function context. It is not needed the millicode thunks anylonger when
compiling for size, thus, make their usage optional.
gcc/
* common/config/arc/arc-common.cc (arc_option_optimization_table):
Remove millico
+ gcc mailing list
-- Forwarded message -
From: Claudiu Zissulescu Ianculescu
Date: Tue, Dec 20, 2022 at 2:31 PM
Subject: Re: Possible regression in DF analysis
To: Jeff Law
Hi Jeff,
> Or is that the core of the problem -- that life analysis is inaccurate
> or unava
ec 14, 2022 at 11:37 AM Claudiu Zissulescu Ianculescu
> wrote:
> >
> > I have update the fix to this one:
> >
> > diff --git a/gcc/df-core.cc b/gcc/df-core.cc
> > index a901b84878f..cc6383990a1 100644
> > --- a/gcc/df-core.cc
> > +++ b/gcc/df-core.cc
>
ug_bitmap_file (dump_file, df->blocks_to_analyze);
+
+ df_analyze ();
}
I still need to validate it for x86
Best,
Claudiu
On Tue, Dec 13, 2022 at 7:38 PM Claudiu Zissulescu Ianculescu
wrote:
>
> >
> > Maybe you want to iterate over the loops exit edges and include their
> &
>
> Maybe you want to iterate over the loops exit edges and include their
> destination block instead?
>
This is better approach, let me try it and I will be back to you.
Thanks,
Claudiu
->index);
+
+ if (dump_file)
+debug_bitmap_file (dump_file, df->blocks_to_analyze);
+ df_analyze ();
}
What do you think,
Claudiu
On Tue, Dec 13, 2022 at 2:30 PM Claudiu Zissulescu Ianculescu
wrote:
>
> It looks like that. The df_analyze_loop is only looking at the loop
> BB
It looks like that. The df_analyze_loop is only looking at the loop
BBs, and it is not clear for me if df_analyze_loop is required to have
all the df_live_outs correctly computed or not. Do you know if it is
true?
If the df_analyze_loop is not supposed to compute all the df_live_outs
correctly, th
Hi Eric,
The problem shows in loop-doloop.c when I introduce a loop end pattern
that replaces the first jump instruction (JUMP_INSN 15) with a pattern
that clobbers CC reg. However, the DF doesn't look like it works as
the doloop step cannot find the CC reg alive. Please see
loop-doloop.c:766. Henc
Hi,
I've stumbled over a potential issue related to Dataflow analysis,
and maybe you can help me with it. It can be reproduced for AARCH64
but other architectures are affected as well.
I have the next snip before CSE1 pass:
(insn 14 11 15 3 (set (reg:CC 66 cc)
(compare:CC (reg/v:SI 98 [
): Likewise.
(abssf2): Likewise.
(ashlsi2_cnt1): Likewise.
(lshrsi3_cnt1): Likewise.
(ashrsi3_cnt1): Likewise.
* config/arc/constraints.md (Rcq): Remove.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 48 +++
gcc/config/arc/arc.md
.
(negsf2): Likewise.
* config/arc/constraints.md(Rcw): Remove it.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md | 220 +-
gcc/config/arc/constraints.md | 14 ---
2 files changed, 110 insertions(+), 124 deletions(-)
diff --git
document.
Signed-off-by: Claudiu Zissulescu
---
gcc/common/config/arc/arc-common.cc | 2 --
gcc/config/arc/arc.opt | 10 ++
gcc/doc/invoke.texi | 8 ++--
3 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/gcc/common/config/arc/arc-common.cc
b/gcc
.
gcc/testsuite/ChangeLog:
* gcc.target/arc/tmac-2.c: Update test.
Signed-off-by: Claudiu Zissulescu
fix
---
gcc/config/arc/arc.md | 36 +--
gcc/config/arc/constraints.md | 10
gcc/testsuite/gcc.target/arc/tmac-2.c | 2 +-
3 files
/testsuite
* gcc.target/arc/enter-dw2-1.c: New file.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 6 ++---
gcc/testsuite/gcc.target/arc/enter-dw2-1.c | 28 ++
2 files changed, 31 insertions(+), 3 deletions(-)
create mode 100644 gcc
Max page size is defined in the ARC's BFD file, and the common page
size is also set by the appropriate binutils macros. Remove them from
LINK_SPEC.
2022-10-06 Claudiu Zissulescu
* config/arc/linux.h (LINK_SPEC): Remove max-page-size and
common-pave-size.
Signed-o
Thanks, I haven't observed it.
Waiting for it,
Claudiu
On Mon, Sep 26, 2022 at 2:49 PM Thomas Neumann wrote:
>
> Hi Claudiu,
>
> > This change prohibits compiling of ARC backend:
> >
> >> + gcc_assert (in_shutdown || ob);
> >
> > in_shutdown is only defined when ATOMIC_FDE_FAST_PATH is defined,
Hi Thomas,
This change prohibits compiling of ARC backend:
> + gcc_assert (in_shutdown || ob);
in_shutdown is only defined when ATOMIC_FDE_FAST_PATH is defined,
while gcc_assert is outside of any ifdef. Please can you revisit this
line and change it accordingly.
Thanks,
Claudiu
mcpu and tune sections.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc-arch.h | 3 +-
gcc/config/arc/arc-cpus.def | 1 +
gcc/config/arc/arc-tables.opt | 3 +
gcc/config/arc/arc.cc | 192 +-
gcc/config/arc/arc.md | 32
From: Claudiu Zissulescu
The ARC soft udivmodsi4 algorithm and as well as using umodsi3
for reduced register set configurations are wrong.
libgcc/
* config/arc/lib2funcs.c (udivmodsi4): Update AND mask.
* config/arc/lib1funcs.S (umodsi3): Don't use it for
: New file.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 2 +-
gcc/testsuite/gcc.target/arc/interrupt-13.c | 15 +++
2 files changed, 16 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/arc/interrupt-13.c
diff --git a
: New file.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 2 +-
gcc/testsuite/gcc.target/arc/interrupt-13.c | 15 +++
2 files changed, 16 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/arc/interrupt-13.c
diff --git a
Hi Robin,
The patch looks good. Please go ahead and merge it, please let me know if
you cannot.
Thank you,
Claudiu
On Mon, Feb 21, 2022 at 9:57 AM Robin Dapp via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:
> Hi,
>
> I figured I'd just go ahead and post this patch as well since it seems
> to h
Hi Robin,
I don't know how I missed your arc related patch, I'll bootstrap and test
your patch asap.
Thanks,
Claudiu
On Fri, Feb 25, 2022 at 3:29 PM Robin Dapp wrote:
> > If the movcc comparison is not valid it triggers an assert in the
> > current implementation. This behavior is not needed
(movsicc): Fail if comparison is not valid.
(movdicc): Likewise.
(movsfcc): Likewise.
(movdfcc): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 3 ++-
gcc/config/arc/arc.md | 25 -
2 files changed, 22 insertions(+), 6
DWARF_ALT_FRAME_RETURN_COLUMN macro.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.h| 11 ++---
gcc/testsuite/gcc.target/arc/cancel-1.c | 31 +
libgcc/config/arc/linux-unwind.h| 9 +++
3 files changed, 44 insertions(+), 7 deletions(-)
create mode
computin checking accumulator regs.
(arc_expand_prologue): Update comments.
(arc_expand_epilogue): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc
e a single move to accumulator.
(umaddhisi4): Likewise.
(machi): Update pattern.
(umachi): Likewise.
gcc/testsuite/
* gcc.target/arc/tmac-4.c: New test.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md | 34 +-
: Claudiu Zissulescu
---
gcc/testsuite/gcc.target/arc/add_n-combine.c | 4 ++--
gcc/testsuite/gcc.target/arc/builtin_eh.c| 3 ++-
gcc/testsuite/gcc.target/arc/mul64-1.c | 2 +-
gcc/testsuite/gcc.target/arc/tls-gd.c| 4 ++--
gcc/testsuite/gcc.target/arc/tls-ie.c| 4 ++--
gcc
The ZOL pattern is missing modes which may lead to errors during
var_tracking. Add them.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.md (doloop_end): Add missing mode.
(loop_end): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md | 8
1
ARC backend is defaulting to -fcommon. This is not anylonger needed, remove it.
gcc/
2021-08-12 Claudiu Zissulescu
* common/config/arc/arc-common.c (arc_option_init_struct): Remove
fno-common reference.
* config/arc/arc.c (arc_override_options): Remove overriding of
&& !TARGET_NO_SDATA_SET)
g_switch_value = TARGET_LL64 ? 8 : 4;
From: Florian Weimer
Sent: Wednesday, July 7, 2021 1:06 PM
To: Richard Biener
Cc: GCC Development ; Joern Wolfgang Rennecke
; Claudiu Zissulescu
Subject: Re: GCC arc port defaults to -fcommon
* R
ener
Sent: Wednesday, July 7, 2021 12:58 PM
To: Florian Weimer
Cc: GCC Development ; Joern Wolfgang Rennecke
; Claudiu Zissulescu
Subject: Re: GCC arc port defaults to -fcommon
On Wed, Jul 7, 2021 at 11:56 AM Richard Biener
wrote:
>
> On Wed, Jul 7, 2021 at 11:00 AM Florian Weimer v
Thanks a lot guys. Patch is pushed.
//Claudiu
On Mon, Jun 14, 2021 at 12:34 AM Jeff Law wrote:
>
>
>
> On 6/13/2021 4:06 AM, Bernhard Reutner-Fischer wrote:
> > On Fri, 11 Jun 2021 14:25:24 +0300
> > Claudiu Zissulescu wrote:
> >
> >> Hi Bernhard,
> &g
Hi Bernhard,
Please find attached my latest patch, it includes (hopefully) all your
feedback.
Thank you for comments,
Claudiu
>From 03075b3d9194120d7adb3cdc2aa0f58e3ea9dd1d Mon Sep 17 00:00:00 2001
From: Claudiu Zissulescu
Date: Wed, 21 Oct 2020 16:11:43 +0300
Subject: [PATCH] arc:
way, thanks for not using grep -P :)
thanks,
I thank you!
Claudiu
>From 1f895d277752277fb51e8436903a94949bd5c7bd Mon Sep 17 00:00:00 2001
From: Claudiu Zissulescu
Date: Wed, 21 Oct 2020 16:11:43 +0300
Subject: [PATCH] arc: Add --with-fpu support for ARCv2 cpus
Support for a compile-time defau
gcc11.
gcc/
-dd-mm Claudiu Zissulescu
* config/arc/arc.md (loop_end): Change it to
define_insn_and_split.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md | 46 +++
1 file changed, 20 insertions(+), 26 deletions(-)
diff --
execution test
Backported to gcc11 too.
gcc/
2021-06-09 Claudiu Zissulescu
* config/arc/arc.md (maddhisi4): Use VMAC2H instruction.
(machi): New pattern.
(umaddhisi4): Use VMAC2HU instruction.
(umachi): New pattern.
Signed-off-by: Claudiu Zissulescu
---
gcc/config
restriction.
This patch is cleaning up those move patterns, and updates splits
instruction lengths.
Backported to gcc11 too.
gcc/
2021-06-09 Claudiu Zissulescu
* config/arc/arc-protos.h (arc_split_move_p): New prototype.
* config/arc/arc.c (arc_split_move_p): New function
Thank you for your input.
I have made an update using grep's ERE. Please let me know if it is ok.
//Claudiu
>From 3f598e0fc9bc88c3f40f3e381c2955ab36e77ce0 Mon Sep 17 00:00:00 2001
From: Claudiu Zissulescu
Date: Wed, 21 Oct 2020 16:11:43 +0300
Subject: [PATCH] arc: Add --with-fpu sup
Zissulescu
* config.gcc (arc): Add support for with_cpu option.
* config/arc/arc.h (OPTION_DEFAULT_SPECS): Add fpu.
Signed-off-by: Claudiu Zissulescu
---
gcc/config.gcc | 56 ++--
gcc/config/arc/arc.h | 4
2 files changed, 58
The millicode thunks are not reduced register set safe. Disable them
for CPUs having this option on.
gcc/
2021-06-04 Claudiu Zissulescu
* config/arc/arc.c (arc_override_options): Disable millicode
thunks when RF16 is on.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc
-code
The ARC's options are marked as obsolete and ignored for backwards
compatibility.
gcc/
2021-06-03 Claudiu Zissulescu
* common/config/arc/arc-common.c (arc_option_optimization_table):
Remove malign-call.
* config/arc/arc.c (arc_unalign_branch_p): Remove u
Right, we can consider this cpu switch missing in gcc11.
Best,
Claudiu
From: Vineet Gupta
Sent: Wednesday, June 2, 2021 8:36 PM
To: Claudiu Zissulescu ; gcc-patches@gcc.gnu.org
Cc: linux-snps-...@lists.infradead.org
Subject: Re: [PATCH] ARC: gcc driver default
Approved.
//Claudiu
From: Vineet Gupta
Sent: Tuesday, June 1, 2021 10:42 PM
To: gcc-patches@gcc.gnu.org
Cc: Claudiu Zissulescu ;
linux-snps-...@lists.infradead.org ; Vineet
Gupta
Subject: [PATCH] ARC: gcc driver default to hs38_linux
arc700 is legacy and
Looks good :) You can go ahead and commit it.
Thank you for your contribution,
Claudiu
From: Kewen.Lin
Sent: Wednesday, June 2, 2021 10:43 AM
To: Claudiu Zissulescu
Cc: g...@amylaar.uk ; andrew.burg...@embecosm.com
; gcc-patches@gcc.gnu.org
Subject: [PATCH 02
Sent: Wednesday, June 2, 2021 10:05 AM
To: Claudiu Zissulescu ; gcc-patches@gcc.gnu.org
Cc: g...@amylaar.uk ; andrew.burg...@embecosm.com
Subject: Re: [PATCH 02/11] arc: Update unexpected empty split condition
Hi Claudiu,
on 2021/6/2 下午2:52, Claudiu Zissulescu wrote:
> Hi,
>
> Indeed, the s
@gcc.gnu.org
Cc: Kewen Lin ; g...@amylaar.uk ; Claudiu
Zissulescu ; andrew.burg...@embecosm.com
Subject: [PATCH 02/11] arc: Update unexpected empty split condition
gcc/ChangeLog:
* config/arc/arc.md (*bbit_di): Fix empty split condition.
---
gcc/config/arc/arc.md | 2 +-
1 file changed
gcc/
2021-05-18 Claudiu Zissulescu
* config/arc/simdext.md (negv2si2): Remove round bracket.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/simdext.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
Textual cleanup of the simdext.md file. Format the output assembly
instructions.
gcc/
2021-05-10 Claudiu Zissulescu
* config/arc/simdext.md: Format and cleanup file.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/simdext.md | 730 +-
1
further analize a loop.
gcc/
2021-05-10 Claudiu Zissulescu
* config/arc/arc.md (UNSPEC_ARC_DMPYWH): Define.
* config/arc/simdext.md (VCT): Add predicates for iterator
elements.
(EMUVEC): Define.
(voptab): Likewise.
(vec_widen_mult_hi_v4hi): Change
Disable movmisalign patterns when aligned access is required.
gcc/
2021-05-10 Claudiu Zissulescu
* config/arc/simdext.md (movmisalignv2hi): Allow misaligned access
only when munaligned-access option is on.
(movmisalign): Likewise.
Signed-off-by: Claudiu Zissulescu
gcc/
2021-05-10 Claudiu Zissulescu
* common/config/arc/arc-common.c (arc_handle_option): Remove dot
from string.
* config/arc/arc.c (arc_reorg): Remove underscore from string.
Signed-off-by: Claudiu Zissulescu
---
gcc/common/config/arc/arc-common.c | 2 +-
gcc/config
ARCv2 ISA introduces special clz/ctz instructions. This patch is
adding support for them when available.
Corner case:
movr0,0x0 : (w0) r0 <= 0x *
ffsr1,r0 : (w0) r1 <= 0x001f *
flsr2,r0 : (w0) r2 <= 0x *
gcc/
2021-05-10 Claudiu Z
Add alternative register name r26 for gp register, and add
alternative register name r27 for fp register.
gcc/
2021-05-10 Claudiu Zissulescu
* config/arc/arc.h (ADDITIONAL_REGISTER_NAMES): Add r26 and r27.
---
gcc/config/arc/arc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a
The arguments of __builtin_arc_sr are swapped in documentation. Fix it.
gcc/
2021-05-10 Claudiu Zissulescu
* doc/extend.texi (__builtin_arc_sr): Swap arguments.
Signed-off-by: Claudiu Zissulescu
---
gcc/doc/extend.texi | 10 +-
1 file changed, 5 insertions(+), 5 deletions
Remove unused function.
gcc/
2021-03-09 Claudiu Zissulescu
* config/arc/arc.c (arc_attr_type): Remove function.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc
From: Claudiu Zissulescu
The compiler can match mpyd.eq r0,r1,r0 as a predicated instruction,
which is incorrect. The mpyd(u) instruction takes as input two 32-bit
registers, returning into a double 64-bit even-odd register pair. For
the predicated case, the ARC instruction decoder expects the
Back port for gcc10
The adc/sbc patterns were unecessary spliting, remove that and
associated functions.
gcc/
2020-12-11 Claudiu Zissulescu
* config/arc/arc-protos.h (arc_scheduling_not_expected): Remove
it.
(arc_sets_cc_p): Likewise.
(arc_need_delay): Likewise
gcc/
2021-01-05 Claudiu Zissulescu
* config/arc/arc.md (maddsidi4_split): Use ACC_REG_FIRST.
(umaddsidi4_split): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/arc
1 - 100 of 638 matches
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