This is a respin of an older series of three patches which I have
merged into one. The new (committed) patch is keeping the obsolete
options int .opt file marking them accrodingly for backwards
compatibility.
Remove the following obsolete options:
- munalign-prob-threshold
- malign-call
- mmixed-code
The ARC's options are marked as obsolete and ignored for backwards
compatibility.
gcc/
2021-06-03 Claudiu Zissulescu <claz...@synopsys.com>
* common/config/arc/arc-common.c (arc_option_optimization_table):
Remove malign-call.
* config/arc/arc.c (arc_unalign_branch_p): Remove unused function.
* config/arc/arc.h (TARGET_MIXED_CODE): Remove macro.
(INDEX_REG_CLASS): Only refer to GENERAL_REGS.
* config/arc/arc.md (abssi2_mixed): Remove pattern.
* config/arc/arc.opt (munalign-prob-threshold): Mark it obsolete.
(malign-call): Likewise.
(mmixed-code): Likewise.
* doc/invoke.texi (ARC): Update doc.
Signed-off-by: Claudiu Zissulescu <claz...@synopsys.com>
---
gcc/common/config/arc/arc-common.c | 1 -
gcc/config/arc/arc.c | 23 -----------------------
gcc/config/arc/arc.h | 4 +---
gcc/config/arc/arc.md | 8 --------
gcc/config/arc/arc.opt | 18 ++++++------------
gcc/doc/invoke.texi | 13 +++----------
6 files changed, 10 insertions(+), 57 deletions(-)
diff --git a/gcc/common/config/arc/arc-common.c
b/gcc/common/config/arc/arc-common.c
index 86674dd3de7..6a119029616 100644
--- a/gcc/common/config/arc/arc-common.c
+++ b/gcc/common/config/arc/arc-common.c
@@ -62,7 +62,6 @@ static const struct default_options
arc_option_optimization_table[] =
{ OPT_LEVELS_SIZE, OPT_fif_conversion, NULL, 0 },
{ OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
{ OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_msize_level_, NULL, 0 },
- { OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_malign_call, NULL, 1 },
{ OPT_LEVELS_NONE, 0, NULL, 0 }
};
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 9153f0529ab..b77d0566386 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -9868,29 +9868,6 @@ gen_acc2 (void)
return gen_rtx_REG (SImode, TARGET_BIG_ENDIAN ? 57: 56);
}
-/* FIXME: a parameter should be added, and code added to final.c,
- to reproduce this functionality in shorten_branches. */
-#if 0
-/* Return nonzero iff BRANCH should be unaligned if possible by upsizing
- a previous instruction. */
-int
-arc_unalign_branch_p (rtx branch)
-{
- rtx note;
-
- if (!TARGET_UNALIGN_BRANCH)
- return 0;
- /* Do not do this if we have a filled delay slot. */
- if (get_attr_delay_slot_filled (branch) == DELAY_SLOT_FILLED_YES
- && !NEXT_INSN (branch)->deleted ())
- return 0;
- note = find_reg_note (branch, REG_BR_PROB, 0);
- return (!note
- || (arc_unalign_prob_threshold && !br_prob_note_reliable_p (note))
- || INTVAL (XEXP (note, 0)) < arc_unalign_prob_threshold);
-}
-#endif
-
/* When estimating sizes during arc_reorg, when optimizing for speed, there
are three reasons why we need to consider branches to be length 6:
- annull-false delay slot insns are implemented using conditional execution,
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 252241a858c..0224ae65074 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -115,8 +115,6 @@ extern const char *arc_cpu_to_as (int argc, const char
**argv);
/* Run-time compilation parameters selecting different hardware subsets. */
-#define TARGET_MIXED_CODE (TARGET_MIXED_CODE_SET)
-
#define TARGET_SPFP (TARGET_SPFP_FAST_SET || TARGET_SPFP_COMPACT_SET)
#define TARGET_DPFP (TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET \
|| TARGET_FP_DP_AX)
@@ -571,7 +569,7 @@ extern enum reg_class arc_regno_reg_class[];
a scale factor or added to another register (as well as added to a
displacement). */
-#define INDEX_REG_CLASS (TARGET_MIXED_CODE ? ARCOMPACT16_REGS : GENERAL_REGS)
+#define INDEX_REG_CLASS GENERAL_REGS
/* The class value for valid base registers. A base register is one used in
an address which is the register value plus a displacement. */
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index a67bb581003..de61b2b790f 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -2011,14 +2011,6 @@ (define_expand "extendhisi2"
;; Absolute instructions
-(define_insn "*abssi2_mixed"
- [(set (match_operand:SI 0 "compact_register_operand" "=q")
- (abs:SI (match_operand:SI 1 "compact_register_operand" "q")))]
- "TARGET_MIXED_CODE"
- "abs%? %0,%1%&"
- [(set_attr "type" "two_cycle_core")
- (set_attr "iscompact" "true")])
-
(define_insn "abssi2"
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,w,w")
(abs:SI (match_operand:SI 1 "nonmemory_operand" "Rcq#q,cL,Cal")))]
diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt
index 85688d57574..a8935db2dd8 100644
--- a/gcc/config/arc/arc.opt
+++ b/gcc/config/arc/arc.opt
@@ -136,12 +136,8 @@ Target Mask(CODE_DENSITY)
Enable code density instructions for ARCv2.
mmixed-code
-Target Mask(MIXED_CODE_SET)
-Tweak register allocation to help 16-bit instruction generation.
-; originally this was:
-;Generate ARCompact 16-bit instructions intermixed with 32-bit instructions
-; but we do that without -mmixed-code, too, it's just a different instruction
-; count / size tradeoff.
+Target Ignore
+Does nothing. Preserved for backward compatibility.
; We use an explict definition for the negative form because that is the
; actually interesting option, and we want that to have its own comment.
@@ -292,11 +288,9 @@ mmul32x16
Target Mask(MULMAC_32BY16_SET)
Generate 32x16 multiply and mac instructions.
-; the initializer is supposed to be: Init(REG_BR_PROB_BASE/2) ,
-; alas, basic-block.h is not included in options.c .
munalign-prob-threshold=
-Target RejectNegative Joined UInteger Var(arc_unalign_prob_threshold)
Init(10000/2)
-Set probability threshold for unaligning branches.
+Target Ignore
+Does nothing. Preserved for backward compatibility.
mmedium-calls
Target Var(TARGET_MEDIUM_CALLS) Init(TARGET_MMEDIUM_CALLS_DEFAULT)
@@ -307,8 +301,8 @@ Target Var(TARGET_ANNOTATE_ALIGN)
Explain what alignment considerations lead to the decision to make an insn
short or long.
malign-call
-Target Var(TARGET_ALIGN_CALL)
-Do alignment optimizations for call instructions.
+Target Ignore
+Does nothing. Preserved for backward compatibility.
mRcq
Target Var(TARGET_Rcq)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 08c3206b719..eb8142f596d 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -19255,7 +19255,7 @@ The following options fine tune code generation:
@table @gcctabopt
@item -malign-call
@opindex malign-call
-Do alignment optimizations for call instructions.
+Does nothing. Preserved for backward compatibility.
@item -mauto-modify-reg
@opindex mauto-modify-reg
@@ -19350,9 +19350,7 @@ code-density feature.
@item -mmixed-code
@opindex mmixed-code
-Tweak register allocation to help 16-bit instruction generation.
-This generally has the effect of decreasing the average instruction size
-while increasing the instruction count.
+Does nothing. Preserved for backward compatibility.
@item -mq-class
@opindex mq-class
@@ -19428,12 +19426,7 @@ normal instruction.
@item -munalign-prob-threshold=@var{probability}
@opindex munalign-prob-threshold
-Set probability threshold for unaligning branches.
-When tuning for @samp{ARC700} and optimizing for speed, branches without
-filled delay slot are preferably emitted unaligned and long, unless
-profiling indicates that the probability for the branch to be taken
-is below @var{probability}. @xref{Cross-profiling}.
-The default is (REG_BR_PROB_BASE/2), i.e.@: 5000.
+Does nothing. Preserved for backward compatibility.
@end table
--
2.31.1
