Re: Re: [PATCH 2/2] [V3] [RISC-V] support cm.push cm.pop cm.popret in zcmp

[jiawei]

 Sorry for the late,  I will send the binutils patch within this week.


- Original Message -
From: "Kito Cheng"
To: "Fei Gao"
Cc: gcc-patches@gcc.gnu.org, pal...@dabbelt.com, jeffreya...@gmail.com, 
sinan@linux.alibaba.com, jia...@iscas.ac.cn
Sent: Mon, 5 Jun 2023 16:31:29 +0800
Subject: Re: [PATCH 2/2] [V3] [RISC-V] support cm.push cm.pop cm.popret in zcmp

Only a few minor comments, otherwise LGTM :)

But I guess we need to wait until binutils merge zc stuff.

> Zcmp can share the same logic as save-restore in stack allocation: 
> pre-allocation
> by cm.push, step 1 and step 2.
>
> please be noted cm.push pushes ra, s0-s11 in reverse order than what 
> save-restore does.
> So adaption has been done in .cfi directives in my patch.
>
> Signed-off-by: Fei Gao
>
> gcc/ChangeLog:
>
> * config/riscv/iterators.md (-8): slot offset in bytes
> (-16): likewise
> (-24): likewise
> (-32): likewise
> (-40): likewise
> (-48): likewise
> (-56): likewise
> (-64): likewise
> (-72): likewise
> (-80): likewise
> (-88): likewise
> (-96): likewise
> (-104): likewise

Use slot0_offset...slot12_offset.

> @@ -422,6 +430,16 @@ static const struct riscv_tune_info 
> riscv_tune_info_table[] = {
> #include "riscv-cores.def"
> };
>
> +typedef enum
> +{
> + PUSH_IDX = 0,
> + POP_IDX,
> + POPRET_IDX,
> + ZCMP_OP_NUM
> +} op_idx;

op_idx -> riscv_zcmp_op_t
> @@ -5388,6 +5487,42 @@ riscv_adjust_libcall_cfi_prologue ()
> return dwarf;
> }
>
> +static rtx
> +riscv_adjust_multi_push_cfi_prologue (int saved_size)
> +{
> + rtx dwarf = NULL_RTX;
> + rtx adjust_sp_rtx, reg, mem, insn;
> + unsigned int mask = cfun->machine->frame.mask;
> + int offset;
> + int saved_cnt = 0;
> +
> + if (mask & S10_MASK)
> + mask |= S11_MASK;
> +
> + for (int regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
> + if (BITSET_P (mask & MULTI_PUSH_GPR_MASK, regno - GP_REG_FIRST))
> + {
> + /* The save order is s11-s0, ra
> + from high to low addr. */
> + offset = saved_size - UNITS_PER_WORD * (++saved_cnt);
> +
> + reg = gen_rtx_REG (SImode, regno);

Should be Pmode rather than SImode, and seems
riscv_adjust_libcall_cfi_prologue has same issue...could you send a
separate patch to fix that?

> + mem = gen_frame_mem (SImode, plus_constant (Pmode,

Same here.

> + stack_pointer_rtx,
> + offset));
> +
> + insn = gen_rtx_SET (mem, reg);
> + dwarf = alloc_reg_note (REG_CFA_OFFSET, insn, dwarf);
> + }
> +
> + /* Debug info for adjust sp. */
> + adjust_sp_rtx = gen_rtx_SET (stack_pointer_rtx,
> + plus_constant(Pmode, stack_pointer_rtx, -saved_size));
> + dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
> + dwarf);
> + return dwarf;
> +}
> +
> static void
> riscv_emit_stack_tie (void)
> {


> @@ -5493,6 +5697,32 @@ riscv_expand_prologue (void)
> }
> }
>
> +static rtx
> +riscv_adjust_multi_pop_cfi_epilogue (int saved_size)
> +{
> + rtx dwarf = NULL_RTX;
> + rtx adjust_sp_rtx, reg;
> + unsigned int mask = cfun->machine->frame.mask;
> +
> + if (mask & S10_MASK)
> + mask |= S11_MASK;
> +
> + /* Debug info for adjust sp. */
> + adjust_sp_rtx = gen_rtx_SET (stack_pointer_rtx,
> + plus_constant(Pmode, stack_pointer_rtx, saved_size));
> + dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
> + dwarf);
> +
> + for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
> + if (BITSET_P (mask, regno - GP_REG_FIRST))
> + {
> + reg = gen_rtx_REG (SImode, regno);

Pmode

> + dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf);
> + }
> +
> + return dwarf;
> +}
> +
> static rtx
> riscv_adjust_libcall_cfi_epilogue ()
> {

> diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
> new file mode 100644
> index 000..f2f2198598c
> --- /dev/null
> +++ b/gcc/config/riscv/zc.md
> @@ -0,0 +1,1042 @@
> +;; Machine description for RISC-V Zc extention.
> +;; Copyright (C) 2011-2023 Free Software Foundation, Inc.

2023 rather than 2011-2023

Re: [PATCH 1/4][V4][RISC-V] support cm.push cm.pop cm.popret in zcmp

[jiawei]

Seems there are some indent format problems in the patch, could you fix them :)

```
patch:509: indent with spaces.
  x_save_size = riscv_stack_align (num_multi_push * UNITS_PER_WORD);
error: patch failed: gcc/config/riscv/riscv.cc:5652
error: gcc/config/riscv/riscv.cc: patch does not apply
```

> -原始邮件-
> 发件人: "Fei Gao" 
> 发送时间: 2023-06-07 13:52:12 (星期三)
> 收件人: gcc-patches@gcc.gnu.org
> 抄送: kito.ch...@gmail.com, pal...@dabbelt.com, jeffreya...@gmail.com, 
sinan@linux.alibaba.com, jia...@iscas.ac.cn, "Fei Gao" 

> 主题: [PATCH 1/4][V4][RISC-V] support cm.push cm.pop cm.popret in zcmp
> 
> Zcmp can share the same logic as save-restore in stack allocation: 
pre-allocation
> by cm.push, step 1 and step 2.
> 
> please be noted cm.push pushes ra, s0-s11 in reverse order than what 
save-restore does.
> So adaption has been done in .cfi directives in my patch.
> 
> Signed-off-by: Fei Gao 
> 
> gcc/ChangeLog:
> 
> * config/riscv/iterators.md
> slot0_offset: slot 0 offset in stack GPRs area in bytes
> slot1_offset: slot 1 offset in stack GPRs area in bytes
> slot2_offset: likewise
> slot3_offset: likewise
> slot4_offset: likewise
> slot5_offset: likewise
> slot6_offset: likewise
> slot7_offset: likewise
> slot8_offset: likewise
> slot9_offset: likewise
> slot10_offset: likewise
> slot11_offset: likewise
> slot12_offset: likewise
> * config/riscv/predicates.md
> (stack_push_up_to_ra_operand): predicates of stack adjust pushing 
ra
> (stack_push_up_to_s0_operand): predicates of stack adjust pushing 
ra, s0
> (stack_push_up_to_s1_operand): likewise
> (stack_push_up_to_s2_operand): likewise
> (stack_push_up_to_s3_operand): likewise
> (stack_push_up_to_s4_operand): likewise
> (stack_push_up_to_s5_operand): likewise
> (stack_push_up_to_s6_operand): likewise
> (stack_push_up_to_s7_operand): likewise
> (stack_push_up_to_s8_operand): likewise
> (stack_push_up_to_s9_operand): likewise
> (stack_push_up_to_s11_operand): likewise
> (stack_pop_up_to_ra_operand): predicates of stack adjust poping ra
> (stack_pop_up_to_s0_operand): predicates of stack adjust poping 
ra, s0
> (stack_pop_up_to_s1_operand): likewise
> (stack_pop_up_to_s2_operand): likewise
> (stack_pop_up_to_s3_operand): likewise
> (stack_pop_up_to_s4_operand): likewise
> (stack_pop_up_to_s5_operand): likewise
> (stack_pop_up_to_s6_operand): likewise
> (stack_pop_up_to_s7_operand): likewise
> (stack_pop_up_to_s8_operand): likewise
> (stack_pop_up_to_s9_operand): likewise
> (stack_pop_up_to_s11_operand): likewise
> * config/riscv/riscv-protos.h
> (riscv_zcmp_valid_stack_adj_bytes_p):declaration
> * config/riscv/riscv.cc (struct riscv_frame_info): comment change
> (riscv_avoid_multi_push): helper function of riscv_use_multi_push
> (riscv_use_multi_push): true if multi push is used
> (riscv_multi_push_sregs_count): num of sregs in multi-push
> (riscv_multi_push_regs_count): num of regs in multi-push
> (riscv_16bytes_align): align to 16 bytes
> (riscv_stack_align): moved to a better place
> (riscv_save_libcall_count): no functional change
> (riscv_compute_frame_info): add zcmp frame info
> (riscv_adjust_multi_push_cfi_prologue): adjust cfi for cm.push
> (riscv_gen_multi_push_pop_insn): gen function for multi push and 
pop
> (riscv_expand_prologue): allocate stack by cm.push
> (riscv_adjust_multi_pop_cfi_epilogue): adjust cfi for cm.pop[ret]
> (riscv_expand_epilogue): allocate stack by cm.pop[ret]
> (zcmp_base_adj): calculate stack adjustment base size
> (zcmp_additional_adj): calculate stack adjustment additional size
> (riscv_zcmp_valid_stack_adj_bytes_p): check if stack adjustment 
valid
> * config/riscv/riscv.h (RETURN_ADDR_MASK): mask of ra
> (S0_MASK): likewise
> (S1_MASK): likewise
> (S2_MASK): likewise
> (S3_MASK): likewise
> (S4_MASK): likewise
> (S5_MASK): likewise
> (S6_MASK): likewise
> (S7_MASK): likewise
> (S8_MASK): likewise
> (S9_MASK): likewise
> (S10_MASK): likewise
> (S11_MASK): likewise
> (MULTI_PUSH_GPR_MASK): GPR_MASK that cm.push can cover at most
> (ZCMP_MAX_SPIMM): max spimm value
> (ZCMP_SP_INC_STEP): zcmp sp increment step
> (ZCMP_INVALID_S0S10_SREGS_COUNTS): num of s0-s10
> (ZCMP_S0S11_SREGS_COUNTS): num of s0-s11
> (ZCMP_MAX_GRP_SLOTS): max slots of pushing and poping in zcmp
> * config/riscv/riscv.md: include zc.md
> * config/riscv/zc.md: New file. machine description for zcmp
> 
> gcc/testsuite/ChangeLog

[PATCH v2 1/3] RISC-V: Minimal support for ZC* extensions.

[Jiawei]

This patch is the minimal support for ZC* extensions, include the extension
name, mask and target defination. Also define the dependencies with Zca
and Zce extension. Notes that all ZC* extensions depend on the Zca extension.
Zce includes all relevant ZC* extensions for microcontrollers using. Zce
will imply zcf when 'f' extension enabled in rv32.

Co-Authored by: Charlie Keaney 
Co-Authored by: Mary Bennett 
Co-Authored by: Nandni Jamnadas 
Co-Authored by: Simon Cook 
Co-Authored by: Sinan Lin 
Co-Authored by: Shihua Liao 
Co-Authored by: Yulong Shi 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_subset_list::parse): New 
extensions.
* config/riscv/riscv-opts.h (MASK_ZCA): New mask.
(MASK_ZCB): Ditto.
(MASK_ZCE): Ditto.
(MASK_ZCF): Ditto.
(MASK_ZCD): Ditto.
(MASK_ZCMP): Ditto.
(MASK_ZCMT): Ditto.
(TARGET_ZCA): New target.
(TARGET_ZCB): Ditto.
(TARGET_ZCE): Ditto.
(TARGET_ZCF): Ditto.
(TARGET_ZCD): Ditto.
(TARGET_ZCMP): Ditto.
(TARGET_ZCMT): Ditto.
* config/riscv/riscv.opt: New target variable.

---
 gcc/common/config/riscv/riscv-common.cc | 38 +
 gcc/config/riscv/riscv-opts.h   | 16 +++
 gcc/config/riscv/riscv.opt  |  3 ++
 3 files changed, 57 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 3247d526c0a..89bdbef43a5 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -111,6 +111,16 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zhinx", "zhinxmin"},
   {"zhinxmin", "zfinx"},
 
+  {"zce",  "zca"},
+  {"zce",  "zcb"},
+  {"zce",  "zcmp"},
+  {"zce",  "zcmt"},
+  {"zcf",  "zca"},
+  {"zcd",  "zca"},
+  {"zcb",  "zca"},
+  {"zcmp", "zca"},
+  {"zcmt", "zca"},
+
   {NULL, NULL}
 };
 
@@ -224,6 +234,14 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zca",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcb",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zce",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcf",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcd",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1156,8 +1174,19 @@ riscv_subset_list::parse (const char *arch, location_t 
loc)
   subset_list->handle_implied_ext (itr);
 }
 
+  /* Zce only implies zcf when RV32 and 'f' extension exist.  */
+  if (subset_list->lookup ("zce") != NULL
+   && subset_list->m_xlen == 32
+   && subset_list->lookup ("f") != NULL
+   && subset_list->lookup ("zcf") == NULL)
+subset_list->add ("zcf", false);
+
   subset_list->handle_combine_ext ();
 
+  if (subset_list->lookup ("zcf") && subset_list->m_xlen == 64)
+error_at (loc, "%<-march=%s%>: zcf extension supports in rv32 only"
+ , arch);
+
   if (subset_list->lookup ("zfinx") && subset_list->lookup ("f"))
 error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point "
   "extensions", arch);
@@ -1271,6 +1300,15 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
 
+  /* Code-size reduction extensions.  */
+  {"zca", &gcc_options::x_riscv_zc_subext, MASK_ZCA},
+  {"zcb", &gcc_options::x_riscv_zc_subext, MASK_ZCB},
+  {"zce", &gcc_options::x_riscv_zc_subext, MASK_ZCE},
+  {"zcf", &gcc_options::x_riscv_zc_subext, MASK_ZCF},
+  {"zcd", &gcc_options::x_riscv_zc_subext, MASK_ZCD},
+  {"zcmp",&gcc_options::x_riscv_zc_subext, MASK_ZCMP},
+  {"zcmt",&gcc_options::x_riscv_zc_subext, MASK_ZCMT},
+
   {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
   {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 208a557b8ff..3429fc1218e 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -215,6 +215,22 @@ enum riscv_entity
 #define MASK_ZMMUL  (1 << 0)
 #define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
 
+#define MASK_ZCA  (1 << 0)
+#define MASK_ZCB  (1 << 1)
+#define MASK_ZCE  (1 << 2)
+#define MASK_ZCF  (1 << 3)
+#define MASK_ZCD  (1 << 4)
+#define MASK_ZCMP (1 << 5)
+#define MASK_ZCMT (1 << 6)
+
+#define TARGET_ZCA((riscv_zc_subext & MASK_ZCA) != 0)
+#define TARGET_ZCB((riscv_zc_subext & MASK_ZCB) != 0)
+#define TARGET_ZCE((riscv_zc_subext & MASK_ZCE) != 0)
+#define TARGET_ZCF((riscv_zc_subext & MASK_ZCF) != 0)
+#define TARGET_ZCD((riscv_zc_subext & MASK_ZCD) != 0)
+#define TARGET_ZCMP   ((riscv_zc_subext & MASK_ZCMP) != 0)
+#define TARGET_ZCMT   ((riscv_zc_subext & MASK_ZCMT) != 0)
+
 #define MASK_SVINVAL (1 << 0)
 #define MASK_SVNAPO

[PATCH v2 0/3] RISC-V: Support ZC* extensions.

[Jiawei]

RISC-V Code Size Reduction(ZC*) extensions is a group of extensions 
which define subsets of the existing C extension (Zca, Zcd, Zcf) and new
extensions(Zcb, Zcmp, Zcmt) which only contain 16-bit encodings.[1]

The implementation of the RISC-V Code Size Reduction extension in GCC is
an important step towards making the RISC-V architecture more efficient.

The cooperation with OpenHW group has played a crucial role in this effort,
with facilitating the implementation, testing and validation. Currently
works can also find in OpenHW group's github repo.[2]

Thanks to Tariq Kurd, Ibrahim Abu Kharmeh for help with explain the 
specification, and Jeremy Bennett's patient guidance throughout the whole 
development process.a

V2 changes:
Fix Kito's comments in first version, Eswin assisted in optimizing the 
implementation of Zcmp extension:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617440.html
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617442.html

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620869.html


[1] github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification

[2] github.com/openhwgroup/corev-gcc

Co-Authored by: Charlie Keaney 
Co-Authored by: Mary Bennett 
Co-Authored by: Nandni Jamnadas 
Co-Authored by: Sinan Lin 
Co-Authored by: Simon Cook 
Co-Authored by: Shihua Liao 
Co-Authored by: Yulong Shi 

  RISC-V: Minimal support for ZC extensions.
  RISC-V: Enable compressible features when use ZC* extensions.
  RISC-V: Add ZC* test for march args being passed.


Jiawei (3):
  RISC-V: Minimal support for ZC* extensions.
  RISC-V: Enable compressible features when use ZC* extensions.
  RISC-V: Add ZC* test for failed march args being passed.

 gcc/common/config/riscv/riscv-common.cc   | 38 +++
 gcc/config/riscv/riscv-c.cc   |  2 +-
 gcc/config/riscv/riscv-opts.h | 16 ++
 gcc/config/riscv/riscv-shorten-memrefs.cc |  3 +-
 gcc/config/riscv/riscv.cc | 11 ---
 gcc/config/riscv/riscv.h  |  2 +-
 gcc/config/riscv/riscv.opt|  3 ++
 gcc/testsuite/gcc.target/riscv/arch-22.c  |  5 +++
 gcc/testsuite/gcc.target/riscv/arch-23.c  |  5 +++
 9 files changed, 78 insertions(+), 7 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-23.c

-- 
2.25.1

[PATCH v2 2/3] RISC-V: Enable compressible features when use ZC* extensions.

[Jiawei]

This patch enables the compressible features with ZC* extensions.

Since all ZC* extension depends on the Zca extension, it's sufficient to only
add the target Zca to extend the target RVC.

Co-Authored by: Mary Bennett 
Co-Authored by: Nandni Jamnadas 
Co-Authored by: Simon Cook 

gcc/ChangeLog:

* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
Enable compressed builtins when ZC* extensions enabled.
* config/riscv/riscv-shorten-memrefs.cc:
Enable shorten_memrefs pass when ZC* extensions enabled.
* config/riscv/riscv.cc (riscv_compressed_reg_p):
Enable compressible registers when ZC* extensions enabled.
(riscv_rtx_costs): Allow adjusting rtx costs when ZC* extensions 
enabled.
(riscv_address_cost): Allow adjusting address cost when ZC* extensions 
enabled.
(riscv_first_stack_step): Allow compression of the register saves
without adding extra instructions.
* config/riscv/riscv.h (FUNCTION_BOUNDARY): Adjusts function boundary
 to 16 bits when ZC* extensions enabled.

---
 gcc/config/riscv/riscv-c.cc   |  2 +-
 gcc/config/riscv/riscv-shorten-memrefs.cc |  3 ++-
 gcc/config/riscv/riscv.cc | 11 +++
 gcc/config/riscv/riscv.h  |  2 +-
 4 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 6ad562dcb8b..2937c160071 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -47,7 +47,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
 {
   builtin_define ("__riscv");
 
-  if (TARGET_RVC)
+  if (TARGET_RVC || TARGET_ZCA)
 builtin_define ("__riscv_compressed");
 
   if (TARGET_RVE)
diff --git a/gcc/config/riscv/riscv-shorten-memrefs.cc 
b/gcc/config/riscv/riscv-shorten-memrefs.cc
index 8f10d24ec39..6f2b973278e 100644
--- a/gcc/config/riscv/riscv-shorten-memrefs.cc
+++ b/gcc/config/riscv/riscv-shorten-memrefs.cc
@@ -65,7 +65,8 @@ public:
   /* opt_pass methods: */
   virtual bool gate (function *)
 {
-  return TARGET_RVC && riscv_mshorten_memrefs && optimize > 0;
+  return (TARGET_RVC || TARGET_ZCA)
+   && riscv_mshorten_memrefs && optimize > 0;
 }
   virtual unsigned int execute (function *);
 
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 21e7d3b3caa..3a07122bf6a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1176,7 +1176,8 @@ static bool
 riscv_compressed_reg_p (int regno)
 {
   /* x8-x15/f8-f15 are compressible registers.  */
-  return (TARGET_RVC && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
+  return ((TARGET_RVC  || TARGET_ZCA)
+ && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
  || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15)));
 }
 
@@ -2416,7 +2417,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
  /* When optimizing for size, make uncompressible 32-bit addresses
 more expensive so that compressible 32-bit addresses are
 preferred.  */
- if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
+ if ((TARGET_RVC || TARGET_ZCA)
+ && !speed && riscv_mshorten_memrefs && mode == SImode
  && !riscv_compressed_lw_address_p (XEXP (x, 0)))
cost++;
 
@@ -2828,7 +2830,8 @@ riscv_address_cost (rtx addr, machine_mode mode,
 {
   /* When optimizing for size, make uncompressible 32-bit addresses more
* expensive so that compressible 32-bit addresses are preferred.  */
-  if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
+  if ((TARGET_RVC || TARGET_ZCA)
+  && !speed && riscv_mshorten_memrefs && mode == SImode
   && !riscv_compressed_lw_address_p (addr))
 return riscv_address_insns (addr, mode, false) + 1;
   return riscv_address_insns (addr, mode, false);
@@ -5331,7 +5334,7 @@ riscv_first_stack_step (struct riscv_frame_info *frame, 
poly_int64 remaining_siz
   && remaining_const_size % IMM_REACH >= min_first_step)
 return remaining_const_size % IMM_REACH;
 
-  if (TARGET_RVC)
+  if (TARGET_RVC || TARGET_ZCA)
 {
   /* If we need two subtracts, and one is small enough to allow compressed
 loads and stores, then put that one first.  */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 4541255a8ae..a507db61900 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -186,7 +186,7 @@ ASM_MISA_SPEC
 #define PARM_BOUNDARY BITS_PER_WORD
 
 /* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
+#define FUNCTION_BOUNDARY ((TARGET_RVC || TARGET_ZCA) ? 16 : 32)
 
 /* The smallest supported stack boundary the calling convention supports.  */
 #define STACK_BOUNDARY \
-- 
2.25.1

[PATCH v2 3/3] RISC-V: Add ZC* test for failed march args being passed.

[Jiawei]

Add ZC* extensions march args tests for error input cases.

Co-Authored by: Nandni Jamnadas 
Co-Authored by: Jiawei 
Co-Authored by: Mary Bennett 
Co-Authored by: Simon Cook 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-22.c: New test.
* gcc.target/riscv/arch-23.c: New test.

---
 gcc/testsuite/gcc.target/riscv/arch-22.c | 5 +
 gcc/testsuite/gcc.target/riscv/arch-23.c | 5 +
 2 files changed, 10 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-23.c

diff --git a/gcc/testsuite/gcc.target/riscv/arch-22.c 
b/gcc/testsuite/gcc.target/riscv/arch-22.c
new file mode 100644
index 000..3be4ade65a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-22.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zcf -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" { 
target *-*-* } 0 } */
+/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" "" 
{ target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-23.c 
b/gcc/testsuite/gcc.target/riscv/arch-23.c
new file mode 100644
index 000..cecce06e474
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-23.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64if_zce -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64if_zce': zcf extension supports in rv32 only" "" { 
target *-*-* } 0 } */
+/* { dg-error "'-march=rv64if_zca_zcb_zce_zcf_zcmp_zcmt': zcf extension 
supports in rv32 only" "" { target *-*-* } 0 } */
-- 
2.25.1

Re: [RFC] RISC-V: Add support for RV64E/lp64e

[jiawei]

> gcc/ChangeLog

> 
> * config.gcc (riscv): Accept rv64e and lp64e.
> * config/riscv/arch-canonicalize: Likewise.
> * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Likewise.
> * config/riscv/riscv-opts.h (riscv_abi_type): Likewise.
> * config/riscv/riscv.cc (riscv_option_override): Likewise
> * config/riscv/riscv.h (UNITS_PER_FP_ARG): Likewise.
> (STACK_BOUNDARY): Likewise.
> (ABI_STACK_BOUNDARY): Likewise.
> (MAX_ARGS_IN_REGISTERS): Likewise.
> (ABI_SPEC): Likewise.
> * config/riscv/riscv.opt (abi_type): Likewise.
> * doc/invoke.texi (RISC-V) <-mabi>: Likewise.
> ---
> This is all still in flight, but evidently RV64E exists.  I haven't
> tested this at all, but given that we don't even have the ABI docs lined
> up yet it's likely a bit away from being mergable.
> ---
>  gcc/config.gcc |  8 +---
>  gcc/config/riscv/arch-canonicalize |  2 +-
>  gcc/config/riscv/riscv-c.cc|  1 +
>  gcc/config/riscv/riscv-opts.h  |  1 +
>  gcc/config/riscv/riscv.cc  |  6 --
>  gcc/config/riscv/riscv.h   | 11 +++
>  gcc/config/riscv/riscv.opt |  3 +++
>  gcc/doc/invoke.texi|  5 +++--
>  8 files changed, 25 insertions(+), 12 deletions(-)
> 
> diff --git a/gcc/config.gcc b/gcc/config.gcc
> index 4e3b15bb5e9..4617ecb8d9b 100644
> --- a/gcc/config.gcc
> +++ b/gcc/config.gcc
> @@ -4637,7 +4637,7 @@ case "${target}" in
>  
>  # Infer arch from --with-arch, --target, and --with-abi.
>  case "${with_arch}" in
> -rv32e* | rv32i* | rv32g* | rv64i* | rv64g*)
> +rv32e* | rv32i* | rv32g* | rv64e* | rv64i* | rv64g*)
>  # OK.
>  ;;
>  "")
> @@ -4645,12 +4645,13 @@ case "${target}" in
>  case "${with_abi}" in
>  ilp32e) with_arch="rv32e" ;;
>  ilp32 | ilp32f | ilp32d) with_arch="rv32gc" ;;
> +lp64e) with_arch="rv64e" ;;
>  lp64 | lp64f | lp64d) with_arch="rv64gc" ;;
>  *) with_arch="rv${xlen}gc" ;;
>  esac
>  ;;
>  *)
> -echo "--with-arch=${with_arch} is not supported.  The argument must begin 
with rv32e, rv32i, rv32g, rv64i, or rv64g." 1>&2
> +echo "--with-arch=${with_arch} is not supported.  The argument must begin 
with rv32e, rv32i, rv32g, rv64e, rv64i, or rv64g." 1>&2
>  exit 1
>  ;;
>  esac
> @@ -4672,6 +4673,7 @@ case "${target}" in
>  rv32e*) with_abi=ilp32e ;;
>  rv32*) with_abi=ilp32 ;;
>  rv64*d* | rv64g*) with_abi=lp64d ;;
> +rv64e*) with_abi=lp64e ;;
>  rv64*) with_abi=lp64 ;;
>  esac
>  ;;
> @@ -4687,7 +4689,7 @@ case "${target}" in
>  ilp32,rv32* | ilp32e,rv32e* \
>  | ilp32f,rv32*f* | ilp32f,rv32g* \
>  | ilp32d,rv32*d* | ilp32d,rv32g* \
> -| lp64,rv64* \
> +| lp64,rv64* | lp64e,rv64e* \
>  | lp64f,rv64*f* | lp64f,rv64g* \
>  | lp64d,rv64*d* | lp64d,rv64g*)
>  ;;
> diff --git a/gcc/config/riscv/arch-canonicalize 
b/gcc/config/riscv/arch-canonicalize
> index fd7651ac491..8db3e88ddd7 100755
> --- a/gcc/config/riscv/arch-canonicalize
> +++ b/gcc/config/riscv/arch-canonicalize
> @@ -71,7 +71,7 @@ def arch_canonicalize(arch, isa_spec):
>new_arch = ""
>extra_long_ext = []
>std_exts = []
> -  if arch[:5] in ['rv32e', 'rv32i', 'rv32g', 'rv64i', 'rv64g']:
> +  if arch[:5] in ['rv32e', 'rv32i', 'rv32g', 'rv64e', 'rv64i', 'rv64g']:
>  new_arch = arch[:5].replace("g", "i")
>  if arch[:5] in ['rv32g', 'rv64g']:
>std_exts = ['m', 'a', 'f', 'd']
> diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
> index eb7ef09297e..4614dc6b6d9 100644
> --- a/gcc/config/riscv/riscv-c.cc
> +++ b/gcc/config/riscv/riscv-c.cc
> @@ -67,6 +67,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
>switch (riscv_abi)
>  {
>  case ABI_ILP32E:
> +case ABI_LP64E:
>builtin_define ("__riscv_abi_rve");
>gcc_fallthrough ();
>  
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 1e153b3a6e7..70fe708cbae 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -27,6 +27,7 @@ enum riscv_abi_type {
>ABI_ILP32F,
>ABI_ILP32D,
>ABI_LP64,
> +  ABI_LP64E,
>ABI_LP64F,
>ABI_LP64D
>  };
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 2e83ca07394..51b7195c17b 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -5047,8 +5047,10 @@ riscv_option_override (void)
>  error ("requested ABI requires %<-march%> to subsume the %qc 
extension",
> UNITS_PER_FP_ARG > 8 ? 'Q' : (UNITS_PER_FP_ARG > 4 ? 'D' : 'F'));
>  
> -  if (TARGET_RVE && riscv_abi != ABI_ILP32E)
> +  if (riscv_xlen == 32 && TARGET_RVE && riscv_abi != ABI_ILP32E)
>  error ("rv32e requires ilp32e ABI");
> +  if (riscv_xlen == 64 && TARGET_RVE && riscv_abi != ABI_LP64E)
> +error ("rv64e requires lp64e ABI");
>  


Hi Palmer, I just run this patch and report unresolve the symbol "riscv_xlen" 
here,


maybe we can use "!TARGET_64BIT" and "TARGET_64BIT" to instead of them, thanks.



>/* We do not yet support ILP32 on RV64.  */
>if (BITS_PER_WORD != POINTER_SIZE)
> @@ -5140,7 +5142,7 @@ riscv_conditio

[PATCH] testsuite: Add extra RISC-V options so that -fprefetch-loop-arrays works

[jiawei]

This patch adds the additional options on RISC-V target.
"-fprefetch-loop-arrays" option needs enable prefetch instruction,
for RISC-V that contained in "zicbop" extension.
Use "-march" with "zicbop" will enable this feature.

gcc/testsuite/ChangeLog:

* gcc.dg/pr106397.c: New dg-additional-options for RISC-V.

---
 gcc/testsuite/gcc.dg/pr106397.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/gcc/testsuite/gcc.dg/pr106397.c b/gcc/testsuite/gcc.dg/pr106397.c
index 2bc17f8cf80..19274fa8771 100644
--- a/gcc/testsuite/gcc.dg/pr106397.c
+++ b/gcc/testsuite/gcc.dg/pr106397.c
@@ -1,6 +1,8 @@
 /* { dg-do compile } */
 /* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 --param 
prefetch-latency=3 -fprefetch-loop-arrays" } */
 /* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-* 
x86_64-*-* } && ia32 } } } */
+/* { dg-additional-options "-march=rv64gc_zicbop" { target { riscv64-*-* } } */
+/* { dg-additional-options "-march=rv32gc_zicbop" { target { riscv32-*-* } } */
 
 int
 bar (void)
-- 
2.25.1

Re: Re: [PATCH] testsuite: Add extra RISC-V options so that -fprefetch-loop-arrays works

[jiawei]

> -原始邮件-
> 发件人: "Richard Biener" 
> 发送时间: 2022-07-28 15:45:27 (星期四)
> 收件人: jiawei 
> 抄送: gcc-patches@gcc.gnu.org, ja...@redhat.com, pal...@rivosinc.com, 
kito.ch...@gmail.com, jim.wilson@gmail.com, wuwei2...@iscas.ac.cn
> 主题: Re: [PATCH] testsuite: Add extra RISC-V options so that 
-fprefetch-loop-arrays works
> 
> On Thu, 28 Jul 2022, jiawei wrote:
> 
> > This patch adds the additional options on RISC-V target.
> > "-fprefetch-loop-arrays" option needs enable prefetch instruction,
> > for RISC-V that contained in "zicbop" extension.
> > Use "-march" with "zicbop" will enable this feature.
> 
> OK.
> 
> Note -fprefetch-loop-arrays is just required to trigger an ICE,
> do you see a diagnostic when prefetching is not supported?  Maybe
> simply adding -w is better then.

Yes, without -march support it report warning info:

cc1: warning: '-fprefetch-loop-arrays' not supported for this target (try 
'-march' switches)

after add -w the warning ignored.

> 
> > gcc/testsuite/ChangeLog:
> > 
> > * gcc.dg/pr106397.c: New dg-additional-options for RISC-V.
> > 
> > ---
> >  gcc/testsuite/gcc.dg/pr106397.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/gcc/testsuite/gcc.dg/pr106397.c 
b/gcc/testsuite/gcc.dg/pr106397.c
> > index 2bc17f8cf80..19274fa8771 100644
> > --- a/gcc/testsuite/gcc.dg/pr106397.c
> > +++ b/gcc/testsuite/gcc.dg/pr106397.c
> > @@ -1,6 +1,8 @@
> >  /* { dg-do compile } */
> >  /* { dg-options "-O3 -fprefetch-loop-arrays --param l2-cache-size=0 
--param prefetch-latency=3 -fprefetch-loop-arrays" } */
> >  /* { dg-additional-options "-march=i686 -msse" { target { { i?86-*-* 
x86_64-*-* } && ia32 } } } */
> > +/* { dg-additional-options "-march=rv64gc_zicbop" { target { 
riscv64-*-* } } */
> > +/* { dg-additional-options "-march=rv32gc_zicbop" { target { 
riscv32-*-* } } */
> >  
> >  int
> >  bar (void)
> > 
> 
> -- 
> Richard Biener 
> SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg,
> Germany; GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman;
> HRB 36809 (AG Nuernberg)

Re: [PATCH] RISC-V: Optimize the MASK opt generation

[jiawei]

v.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -203,36 +203,126 @@ long riscv_stack_protector_guard_offset = 0
 TargetVariable
 int riscv_zi_subext

+Mask(ZICSR) in TargetVariable(riscv_zi_subext)
+
+Mask(ZIFENCEI) in TargetVariable(riscv_zi_subext)
+
 TargetVariable
 int riscv_za_subext

+Mask(ZAWRS) in TargetVariable(riscv_za_subext)
+
 TargetVariable
 int riscv_zb_subext

+Mask(ZBA) in TargetVariable(riscv_zb_subext)
+
+Mask(ZBB) in TargetVariable(riscv_zb_subext)
+
+Mask(ZBC) in TargetVariable(riscv_zb_subext)
+
+Mask(ZBS) in TargetVariable(riscv_zb_subext)
+
 TargetVariable
 int riscv_zinx_subext

+Mask(ZFINX) in TargetVariable(riscv_zinx_subext)
+
+Mask(ZDINX) in TargetVariable(riscv_zinx_subext)
+
+Mask(ZHINX) in TargetVariable(riscv_zinx_subext)
+
+Mask(ZHINXMIN) in TargetVariable(riscv_zinx_subext)
+
 TargetVariable
 int riscv_zk_subext

+Mask(ZBKB) in TargetVariable(riscv_zk_subext)
+
+Mask(ZBKC) in TargetVariable(riscv_zk_subext)
+
+Mask(ZBKX) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKNE) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKND) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKNH) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKR) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKSED) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKSH) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKT) in TargetVariable(riscv_zk_subext)
+
 TargetVariable
 int riscv_vector_elen_flags

+Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_64) in TargetVariable(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_FP_32) in TargetVariable(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_FP_64) in TargetVariable(riscv_vector_elen_flags)
+
 TargetVariable
 int riscv_zvl_flags

+Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL64B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL128B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL256B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL512B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL1024B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL2048B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL4096B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL8192B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL16384B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL32768B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL65536B) in TargetVariable(riscv_zvl_flags)
+
 TargetVariable
 int riscv_zicmo_subext

+Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)
+
+Mask(ZICBOM) in TargetVariable(riscv_zicmo_subext)
+
+Mask(ZICBOP) in TargetVariable(riscv_zicmo_subext)
+
 TargetVariable
 int riscv_zf_subext

+Mask(ZFHMIN) in TargetVariable(riscv_zf_subext)
+
+Mask(ZFH) in TargetVariable(riscv_zf_subext)
+
 TargetVariable
 int riscv_zm_subext

+Mask(ZMMUL) in TargetVariable(riscv_zm_subext)
+
 TargetVariable
 int riscv_sv_subext

+Mask(SVINVAL) in TargetVariable(riscv_sv_subext)
+
+Mask(SVNAPOT) in TargetVariable(riscv_sv_subext)
+It looks like a good idea. However, there are still many modules that look 
very similar, can we further optimize these codes.BR,Jiawei

 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
index 2aee0b9f1c3..9d6080d64a8 100644
--- a/gcc/opt-functions.awk
+++ b/gcc/opt-functions.awk
@@ -387,3 +387,14 @@ function integer_range_info(range_option, init, option, 
uinteger_used)
 else
 return "-1, -1"
 }
+
+# Find the index of target variable from extra_target_vars
+function find_index(var, var_arry, n_var_arry)
+{
+for (var_index = 0; var_index < n_var_arry; var_index++)
+{
+if (var_arry[var_index] == var)
+break
+}
+return var_index
+}
\ No newline at end of file
diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
index ce3617c8d4a..ebe48db968b 100644
--- a/gcc/opt-read.awk
+++ b/gcc/opt-read.awk
@@ -22,6 +22,7 @@ BEGIN {
n_opts = 0
n_langs = 0
n_target_save = 0
+   n_target_vars = 0
n_extra_vars = 0
n_extra_target_vars = 0
n_extra_masks = 0
@@ -121,7 +122,20 @@ BEGIN {
n_opts++;
}
else {
-   extra_masks[n_extra_masks++] = name
+   if($0 ~ "in")
+   {
+   target_var = opt_args("TargetVariable", 
$1)
+   var_index = find_index(target_var, 
target_vars, n_target_vars)
+   if (var_index == n_target_vars)
+   {
+   target_vars[n_target_vars++] = 
target_var
+   }
+   
other_masks[var_index][n_other_mask[var_index]++] = name
+   }
+   else
+   

Re: [PATCH] RISC-V: Optimize the MASK opt generation

[jiawei]

_zvl_flags & MASK_ZVL4096B) != 0)> -#define 
> TARGET_ZVL8192B  ((riscv_zvl_flags & MASK_ZVL8192B) != 0)> -#define 
> TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)> -#define 
> TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)> -#define 
> TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)> -> -#define 
> MASK_ZICBOZ   (1 << 0)> -#define MASK_ZICBOM   (1 << 1)> -#define MASK_ZICBOP 
>   (1 << 2)> -> -#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 
> 0)> -#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)> 
> -#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)> -> -#define 
> MASK_ZFHMIN   (1 << 0)> -#define MASK_ZFH  (1 << 1)> -> -#define 
> TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)> -#define TARGET_ZFH
> ((riscv_zf_subext & MASK_ZFH) != 0)> -> -#define MASK_ZMMUL  (1 << 0)> 
> -#define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)> -> -#define 
> MASK_SVINVAL (1 << 0)> -#define MASK_SVNAPOT (1 << 1)> -> -#define 
> TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)> -#define 
> TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)> ->  /* Bit of 
> riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is> set, 
> e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use> popcount 
> to caclulate the minimal VLEN.  */> diff --git a/gcc/config/riscv/riscv.opt 
> b/gcc/config/riscv/riscv.opt> index 7c3ca48d1cc..77f553356b1 100644> --- 
> a/gcc/config/riscv/riscv.opt> +++ b/gcc/config/riscv/riscv.opt> @@ -203,36 
> +203,126 @@ long riscv_stack_protector_guard_offset = 0>  TargetVariable>  
> int riscv_zi_subext> > +Mask(ZICSR) in TargetVariable(riscv_zi_subext)> +> 
> +Mask(ZIFENCEI) in TargetVariable(riscv_zi_subext)> +>  TargetVariable>  int 
> riscv_za_subext> > +Mask(ZAWRS) in TargetVariable(riscv_za_subext)> +>  
> TargetVariable>  int riscv_zb_subext> > +Mask(ZBA) in 
> TargetVariable(riscv_zb_subext)> +> +Mask(ZBB) in 
> TargetVariable(riscv_zb_subext)> +> +Mask(ZBC) in 
> TargetVariable(riscv_zb_subext)> +> +Mask(ZBS) in 
> TargetVariable(riscv_zb_subext)> +>  TargetVariable>  int riscv_zinx_subext> 
> > +Mask(ZFINX) in TargetVariable(riscv_zinx_subext)> +> +Mask(ZDINX) in 
> TargetVariable(riscv_zinx_subext)> +> +Mask(ZHINX) in 
> TargetVariable(riscv_zinx_subext)> +> +Mask(ZHINXMIN) in 
> TargetVariable(riscv_zinx_subext)> +>  TargetVariable>  int riscv_zk_subext> 
> > +Mask(ZBKB) in TargetVariable(riscv_zk_subext)> +> +Mask(ZBKC) in 
> TargetVariable(riscv_zk_subext)> +> +Mask(ZBKX) in 
> TargetVariable(riscv_zk_subext)> +> +Mask(ZKNE) in 
> TargetVariable(riscv_zk_subext)> +> +Mask(ZKND) in 
> TargetVariable(riscv_zk_subext)> +> +Mask(ZKNH) in 
> TargetVariable(riscv_zk_subext)> +> +Mask(ZKR) in 
> TargetVariable(riscv_zk_subext)> +> +Mask(ZKSED) in 
> TargetVariable(riscv_zk_subext)> +> +Mask(ZKSH) in 
> TargetVariable(riscv_zk_subext)> +> +Mask(ZKT) in 
> TargetVariable(riscv_zk_subext)> +>  TargetVariable>  int 
> riscv_vector_elen_flags> > +Mask(VECTOR_ELEN_32) in 
> TargetVariable(riscv_vector_elen_flags)> +> +Mask(VECTOR_ELEN_64) in 
> TargetVariable(riscv_vector_elen_flags)> +> +Mask(VECTOR_ELEN_FP_32) in 
> TargetVariable(riscv_vector_elen_flags)> +> +Mask(VECTOR_ELEN_FP_64) in 
> TargetVariable(riscv_vector_elen_flags)> +>  TargetVariable>  int 
> riscv_zvl_flags> > +Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)> +> 
> +Mask(ZVL64B) in TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL128B) in 
> TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL256B) in 
> TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL512B) in 
> TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL1024B) in 
> TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL2048B) in 
> TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL4096B) in 
> TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL8192B) in 
> TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL16384B) in 
> TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL32768B) in 
> TargetVariable(riscv_zvl_flags)> +> +Mask(ZVL65536B) in 
> TargetVariable(riscv_zvl_flags)> +>  TargetVariable>  int riscv_zicmo_subext> 
> > +Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)> +> +Mask(ZICBOM) in 
> TargetVariable(riscv_zicmo_subext)> +> +Mask(ZICBOP) in 
> TargetVariable(riscv_zicmo_subext)> +>  Targe

Re: [PATCH] RISC-V: Don't try to vectorize tree-ssa/gen-vect-34.c

[jiawei]

LGTM, Maybe we can try is after RVV supported.> We don't yet support 
vectorization on RISC-V.
> > gcc/testsuite/ChangeLog> >  * gcc.dg/tree-ssa/gen-vect-34.c: Skip RISC-V 
> > targets.> --->  gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c | 2 +->  1 file 
> > changed, 1 insertion(+), 1 deletion(-)> > diff --git 
> > a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c 
> > b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c> index 
> > 8d2d36401fe..41877e05efd 100644> --- 
> > a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c> +++ 
> > b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-34.c> @@ -13,4 +13,4 @@ float 
> > summul(int n, float *arg1, float *arg2)>  return res1;  
> >  >  }>  > -/* { dg-final { scan-tree-dump-times 
> > "vectorized 1 loops" 1 "vect" { target { ! { avr-*-* pru-*-* } } } } } */> 
> > +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { 
> > target { ! { avr-*-* pru-*-* riscv*-*-* } } } } } */> -- > 2.34.1

[PATCH] testsuite: Skip target not support -pthread [pr104676].

[jiawei]

The "ftree-parallelize-loops=" imply -pthread option in gcc/gcc.cc,
some target are not support pthread like elf target use newlib,
and will get an error:

"*-*-elf-gcc: error: unrecognized command-line option '-pthread'"

so we add an additional condition "{target pthread}" to make sure the
dg-additional-options runs on support targets.

---
 gcc/testsuite/gcc.dg/torture/pr104676.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.dg/torture/pr104676.c 
b/gcc/testsuite/gcc.dg/torture/pr104676.c
index 50845bb9e15..0991b78f758 100644
--- a/gcc/testsuite/gcc.dg/torture/pr104676.c
+++ b/gcc/testsuite/gcc.dg/torture/pr104676.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-additional-options "-ftree-loop-distribution 
-ftree-parallelize-loops=2" } */
+/* { dg-additional-options "-ftree-loop-distribution 
-ftree-parallelize-loops=2" { target pthread } } */
 
 struct S {
   int f;
-- 
2.25.1

[v4 PATCH 1/4] RISC-V: Minimal support of z*inx extension.

[jiawei]

From: Jiawei 

Minimal support of z*inx extension, include 'zfinx'， 'zdinx' and 
'zhinx/zhinxmin'
corresponding to 'f', 'd' and 'zfh/zfhmin', the 'zdinx' will imply 'zfinx'
same as 'd' imply 'f', 'zhinx' will aslo imply 'zfinx', all zfinx extension 
imply 'zicsr'.

Co-Authored-By: Sinan Lin.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New extensions.
* config/riscv/arch-canonicalize: New imply relations.
* config/riscv/riscv-opts.h (MASK_ZFINX): New mask.
(MASK_ZDINX): Ditto.
(MASK_ZHINX): Ditto.
(MASK_ZHINXMIN): Ditto.
(TARGET_ZFINX): New target.
(TARGET_ZDINX): Ditto.
(TARGET_ZHINX): Ditto.
(TARGET_ZHINXMIN): Ditto.
* config/riscv/riscv.opt: New target variable.

---
 gcc/common/config/riscv/riscv-common.cc | 18 ++
 gcc/config/riscv/arch-canonicalize  |  5 +
 gcc/config/riscv/riscv-opts.h   | 10 ++
 gcc/config/riscv/riscv.opt  |  3 +++
 4 files changed, 36 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index c39ed2e2696..55f3328df7a 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -51,6 +51,11 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"d", "f"},
   {"f", "zicsr"},
   {"d", "zicsr"},
+
+  {"zdinx", "zfinx"},
+  {"zfinx", "zicsr"},
+  {"zdinx", "zicsr"},
+
   {"zk", "zkn"},
   {"zk", "zkr"},
   {"zk", "zkt"},
@@ -99,6 +104,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
 
   {"zfh", "zfhmin"},
   {"zfhmin", "f"},
+  
+  {"zhinx", "zhinxmin"},
+  {"zhinxmin", "zfinx"},
 
   {NULL, NULL}
 };
@@ -158,6 +166,11 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zhinx", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zhinxmin", ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zbkb",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbkc",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbkx",  ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1168,6 +1181,11 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zbc",&gcc_options::x_riscv_zb_subext, MASK_ZBC},
   {"zbs",&gcc_options::x_riscv_zb_subext, MASK_ZBS},
 
+  {"zfinx",&gcc_options::x_riscv_zinx_subext, MASK_ZFINX},
+  {"zdinx",&gcc_options::x_riscv_zinx_subext, MASK_ZDINX},
+  {"zhinx",&gcc_options::x_riscv_zinx_subext, MASK_ZHINX},
+  {"zhinxmin", &gcc_options::x_riscv_zinx_subext, MASK_ZHINXMIN},
+
   {"zbkb",   &gcc_options::x_riscv_zk_subext, MASK_ZBKB},
   {"zbkc",   &gcc_options::x_riscv_zk_subext, MASK_ZBKC},
   {"zbkx",   &gcc_options::x_riscv_zk_subext, MASK_ZBKX},
diff --git a/gcc/config/riscv/arch-canonicalize 
b/gcc/config/riscv/arch-canonicalize
index fd7651ac491..2498db506b7 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -41,6 +41,11 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 IMPLIED_EXT = {
   "d" : ["f", "zicsr"],
   "f" : ["zicsr"],
+  "zdinx" : ["zfinx", "zicsr"],
+  "zfinx" : ["zicsr"],
+  "zhinx" : ["zhinxmin", "zfinx", "zicsr"],
+  "zhinxmin" : ["zfinx", "zicsr"],
+
   "zk" : ["zkn", "zkr", "zkt"],
   "zkn" : ["zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"],
   "zks" : ["zbkb", "zbkc", "zbkx", "zksed", "zksh"],
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 55e0bc0a0e9..bb2322ad182 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -83,6 +83,16 @@ enum stack_protector_guard {
 #define TARGET_ZBC((riscv_zb_subext & MASK_ZBC) != 0)
 #define TARGET_ZBS((riscv_zb_subext & MASK_ZBS) != 0)
 
+#define MASK_ZFINX  (1 << 0)
+#define MASK_ZDINX  (1 << 1)
+#define MASK_ZHINX  (1 << 2)
+#define MASK_ZHINXMIN   (1 << 3)
+
+#define TARGET_ZFINX((riscv_zinx_subext & MASK_ZFINX) != 0)
+#define TARGET_ZDINX((riscv_zinx_subext & MASK_ZDINX) != 0)
+#define TARGET_ZHINX((riscv_zinx_subext & MASK_ZHINX) != 0)
+#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
+
 #define MASK_ZBKB (1 << 0)
 #define MASK_ZBKC (1 << 1)
 #define MASK_ZBKX (1 << 2)
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 8923a11a97d..7c1e0ed5f2d 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -206,6 +206,9 @@ int riscv_zi_subext
 TargetVariable
 int riscv_zb_subext
 
+TargetVariable
+int riscv_zinx_subext
+
 TargetVariable
 int riscv_zk_subext
 
-- 
2.25.1

[v4 PATCH 0/4] RISC-V: Support z*inx extensions.

[jiawei]

Zfinx extension[1] had already ratified. Here is the 
implementation patch set that reuse floating point pattern and ban
the use of fpr when use z*inx as a target.

Current works can be find in follow links, binutils and simulator 
works already supported on upstream.
  https://github.com/pz9115/riscv-gcc/tree/zfinx-rebase

Thanks for Tariq Kurd, Kito Cheng, Jim Willson, 
Jeremy Bennett helped us a lot with this work.

[1] https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf

Version log:

v2: As Kito Cheng's comment, add Changelog part in patches, update imply 
info in riscv-common.c, remove useless check and update annotation in 
riscv.c.

v3: Update with new isa-spec version 20191213, make zfinx imply zicsr as
default, fix the lack of fcsr use in zfinx.

v4: Rebase patch with upstream, add zhinx/zhinxmin extensions support.
Add additional zhinx/zhinxmin same like zfh/zfhmin.

Jiawei (4):
  RISC-V: Minimal support of z*inx extension.
  RISC-V: Target support for z*inx extension.
  RISC-V: Limit regs use for z*inx extension.
  RISC-V: Add zhinx/zhinxmin testcases.

 gcc/common/config/riscv/riscv-common.cc   | 18 +
 gcc/config/riscv/arch-canonicalize|  5 ++
 gcc/config/riscv/constraints.md   |  5 +-
 gcc/config/riscv/iterators.md |  6 +-
 gcc/config/riscv/riscv-builtins.cc|  4 +-
 gcc/config/riscv/riscv-c.cc   |  2 +-
 gcc/config/riscv/riscv-opts.h | 10 +++
 gcc/config/riscv/riscv.cc | 21 -
 gcc/config/riscv/riscv.md | 78 ++-
 gcc/config/riscv/riscv.opt|  3 +
 .../gcc.target/riscv/_Float16-zhinx-1.c   | 10 +++
 .../gcc.target/riscv/_Float16-zhinx-2.c   |  9 +++
 .../gcc.target/riscv/_Float16-zhinx-3.c   |  9 +++
 .../gcc.target/riscv/_Float16-zhinxmin-1.c| 10 +++
 .../gcc.target/riscv/_Float16-zhinxmin-2.c| 10 +++
 .../gcc.target/riscv/_Float16-zhinxmin-3.c| 10 +++
 16 files changed, 160 insertions(+), 50 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c

-- 
2.25.1

[v4 PATCH 2/4] RISC-V: Target support for z*inx extension.

[jiawei]

From: Jiawei 

Support 'TARGET_ZFINX' with float instruction pattern and builtin function.
Reuse 'TARGET_HADR_FLOAT',  'TARGET_DOUBLE_FLOAT' and 'TARGET_ZHINX' patterns.

gcc/ChangeLog:

* config/riscv/iterators.md (TARGET_ZFINX):New target.
(TARGET_ZDINX): Ditto.
(TARGET_ZHINX): Ditto.
* config/riscv/riscv-builtins.cc (AVAIL): Ditto.
(riscv_atomic_assign_expand_fenv): Ditto.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Ditto.
* config/riscv/riscv.md: Ditto.

---
 gcc/config/riscv/iterators.md  |  6 +--
 gcc/config/riscv/riscv-builtins.cc |  4 +-
 gcc/config/riscv/riscv-c.cc|  2 +-
 gcc/config/riscv/riscv.md  | 78 +++---
 4 files changed, 46 insertions(+), 44 deletions(-)

diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 39dffabc235..50380ecfac9 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -59,9 +59,9 @@
 (define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")])
 
 ;; Iterator for hardware-supported floating-point modes.
-(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
-   (DF "TARGET_DOUBLE_FLOAT")
-   (HF "TARGET_ZFH")])
+(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
+   (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")
+   (HF "TARGET_ZFH || TARGET_ZHINX")])
 
 ;; Iterator for floating-point modes that can be loaded into X registers.
 (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")])
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 14865d70955..1534cfd860b 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -87,7 +87,7 @@ struct riscv_builtin_description {
   unsigned int (*avail) (void);
 };
 
-AVAIL (hard_float, TARGET_HARD_FLOAT)
+AVAIL (hard_float, TARGET_HARD_FLOAT || TARGET_ZFINX)
 
 
 AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT)
@@ -322,7 +322,7 @@ riscv_expand_builtin (tree exp, rtx target, rtx subtarget 
ATTRIBUTE_UNUSED,
 void
 riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
 {
-  if (!TARGET_HARD_FLOAT)
+  if (!(TARGET_HARD_FLOAT || TARGET_ZFINX))
 return;
 
   tree frflags = GET_BUILTIN_DECL (CODE_FOR_riscv_frflags);
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 78f6eacb068..826ae0067bb 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -61,7 +61,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
   if (TARGET_HARD_FLOAT)
 builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
 
-  if (TARGET_HARD_FLOAT && TARGET_FDIV)
+  if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV)
 {
   builtin_define ("__riscv_fdiv");
   builtin_define ("__riscv_fsqrt");
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 2d1cda2b98f..09ca91fb2c3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -434,7 +434,7 @@
   [(set (match_operand:ANYF0 "register_operand" "=f")
(plus:ANYF (match_operand:ANYF 1 "register_operand" " f")
   (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fadd.\t%0,%1,%2"
   [(set_attr "type" "fadd")
(set_attr "mode" "")])
@@ -565,7 +565,7 @@
   [(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fsub.\t%0,%1,%2"
   [(set_attr "type" "fadd")
(set_attr "mode" "")])
@@ -735,7 +735,7 @@
   [(set (match_operand:ANYF   0 "register_operand" "=f")
(mult:ANYF (match_operand:ANYF1 "register_operand" " f")
  (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT  || TARGET_ZFINX"
   "fmul.\t%0,%1,%2"
   [(set_attr "type" "fmul")
(set_attr "mode" "")])
@@ -1042,7 +1042,7 @@
   [(set (match_operand:ANYF   0 "register_operand" "=f")
(div:ANYF (match_operand:ANYF 1 "register_operand" " f")
  

[v4 PATCH 4/4] RISC-V: Add zhinx/zhinxmin testcases.

[jiawei]

From: Jiawei 

Test zhinx/zhinxmin support, same like with zfh/zfhmin testcases
but use gprs and don't use fmv instruction.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/_Float16-zhinx-1.c: New test.
* gcc.target/riscv/_Float16-zhinx-2.c: New test.
* gcc.target/riscv/_Float16-zhinx-3.c: New test.
* gcc.target/riscv/_Float16-zhinxmin-1.c: New test.
* gcc.target/riscv/_Float16-zhinxmin-2.c: New test.
* gcc.target/riscv/_Float16-zhinxmin-3.c: New test.

---
 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c| 10 ++
 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c|  9 +
 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c|  9 +
 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c | 10 ++
 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c | 10 ++
 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c | 10 ++
 6 files changed, 58 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c 
b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
new file mode 100644
index 000..90172b57e05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinx -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+return b;
+}
+
+/* { dg-final { scan-assembler-not "fmv.h" } } */
+/* { dg-final { scan-assembler-times "mv" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c 
b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
new file mode 100644
index 000..26f01198c97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinx -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+/* { dg-final { scan-assembler-not "fadd.h fa" } } */
+/* { dg-final { scan-assembler-times "fadd.h   a" 1 } } */
+return a + b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c 
b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
new file mode 100644
index 000..573913568e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinx-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinx -mabi=lp64 -O" } */
+
+int foo1 (_Float16 a, _Float16 b)
+{
+/* { dg-final { scan-assembler-not "fgt.h  fa" } } */
+/* { dg-final { scan-assembler-times "fgt.ha" 1 } } */
+return a > b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c 
b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
new file mode 100644
index 000..0070ebf616c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinxmin -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+/* { dg-final { scan-assembler-not "fmv.h" } } */
+/* { dg-final { scan-assembler-not "fmv.s" } } */
+/* { dg-final { scan-assembler-times "mv" 1 } } */
+return b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c 
b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
new file mode 100644
index 000..17f45a938d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zhinxmin -mabi=lp64 -O" } */
+
+_Float16 foo1 (_Float16 a, _Float16 b)
+{
+/* { dg-final { scan-assembler-not "fadd.h" } } */
+/* { dg-final { scan-assembler-not "fadd.s fa" } } */
+/* { dg-final { scan-assembler-times "fadd.s   a" 1 } } */
+return a + b;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c 
b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c
new file mode 100644
index 000..7a43641a5a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/_Float16-zhinxmin-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64if_zfhmin -mabi=lp64f -O" } */
+
+int foo1 (_Float16 a, _Float16 b)
+{
+/* { dg-final { scan-assembler-not "fgt.h" } } */
+/* { dg-final { scan-assembler-not "fgt.s  fa" } } */
+/* { dg-final { scan-assembler-times "fgt.sa" 1 } } */
+return a > b;
+}
-- 
2.25.1

[v4 PATCH 3/4] RISC-V: Limit regs use for z*inx extension.

[jiawei]

From: Jiawei 

Limit z*inx abi support with 'ilp32','ilp32e','lp64' only.
Use GPR instead FPR when 'zfinx' enable, Only use even registers 
in RV32 when 'zdinx' enable.
Enable FLOAT16 when Zhinx/Zhinxmin enabled.

Co-Authored-By: Sinan Lin.

gcc/ChangeLog:

* config/riscv/constraints.md (TARGET_ZFINX ? GR_REGS): Set GPRS
  use while Zfinx is enable.
* config/riscv/riscv.cc (riscv_hard_regno_mode_ok): Limit odd
  registers use when Zdinx enable in RV32 cases.
(riscv_option_override): New target enable MASK_FDIV.
(riscv_libgcc_floating_mode_supported_p): New error info when
  use incompatible arch&abi.
(riscv_excess_precision): New target enable FLOAT16.

---
 gcc/config/riscv/constraints.md |  5 +++--
 gcc/config/riscv/riscv.cc   | 21 +
 2 files changed, 20 insertions(+), 6 deletions(-)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 8997284f32e..c53e0f38920 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -21,8 +21,9 @@
 
 ;; Register constraints
 
-(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
-  "A floating-point register (if available).")
+(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS :
+  (TARGET_ZFINX ? GR_REGS) : NO_REGS"
+  "A floating-point register (if available, reuse GPR as FPR when use zfinx).")
 
 (define_register_constraint "j" "SIBCALL_REGS"
   "@internal")
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ad57b995e7b..38631605b2c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5356,6 +5356,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, 
machine_mode mode)
!= call_used_or_fixed_reg_p (regno + i))
   return false;
 
+  /* Only use even registers in RV32 ZDINX */
+  if (!TARGET_64BIT && TARGET_ZDINX){
+if (GET_MODE_CLASS (mode) == MODE_FLOAT &&
+ GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode))
+return !(regno & 1);
+  }
+
   return true;
 }
 
@@ -5595,7 +5602,7 @@ riscv_option_override (void)
 error ("%<-mdiv%> requires %<-march%> to subsume the % extension");
 
   /* Likewise floating-point division and square root.  */
-  if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
+  if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & 
MASK_FDIV) == 0)
 target_flags |= MASK_FDIV;
 
   /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
@@ -5641,6 +5648,11 @@ riscv_option_override (void)
   if (TARGET_RVE && riscv_abi != ABI_ILP32E)
 error ("rv32e requires ilp32e ABI");
 
+  // Zfinx require abi ilp32,ilp32e or lp64.
+  if (TARGET_ZFINX && riscv_abi != ABI_ILP32
+  && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
+error ("z*inx requires ABI ilp32, ilp32e or lp64");
+
   /* We do not yet support ILP32 on RV64.  */
   if (BITS_PER_WORD != POINTER_SIZE)
 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
@@ -6273,7 +6285,7 @@ riscv_libgcc_floating_mode_supported_p (scalar_float_mode 
mode)
precision of the _FloatN type; evaluate all other operations and
constants to the range and precision of the semantic type;
 
-   If we have the zfh extensions then we support _Float16 in native
+   If we have the zfh/zhinx extensions then we support _Float16 in native
precision, so we should set this to 16.  */
 static enum flt_eval_method
 riscv_excess_precision (enum excess_precision_type type)
@@ -6282,8 +6294,9 @@ riscv_excess_precision (enum excess_precision_type type)
 {
 case EXCESS_PRECISION_TYPE_FAST:
 case EXCESS_PRECISION_TYPE_STANDARD:
-  return (TARGET_ZFH ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
-: FLT_EVAL_METHOD_PROMOTE_TO_FLOAT);
+  return ((TARGET_ZFH || TARGET_ZHINX || TARGET_ZHINXMIN) 
+   ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
+   : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT);
 case EXCESS_PRECISION_TYPE_IMPLICIT:
 case EXCESS_PRECISION_TYPE_FLOAT16:
   return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16;
-- 
2.25.1

[RFC] RISC-V: Add profile supports.

[jiawei]

Supports RISC-V profiles[1] in -march option, add minimal extension name 
supports.

Default input set the profile is before other formal extensions.

Test with -march=RV[I/M/A]2[0/2][U/M/S][64/32]+otherextensions.

[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc


jiawei (2):
  RISC-V: Add minimal supports for new extension in profile.
  RISC-V: Add profile supports.

 gcc/common/config/riscv/riscv-common.cc | 115 ++--
 gcc/config/riscv/riscv-opts.h   |  15 
 gcc/config/riscv/riscv-subset.h |   5 +-
 3 files changed, 129 insertions(+), 6 deletions(-)

-- 
2.25.1

[RFC] RISC-V: Minimal supports for new extensions in profile.

[jiawei]

This patch just add name support contain in profiles.
Set the extension version as 0.1.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New extensions.
* config/riscv/riscv-opts.h (MASK_ZICCAMOA): New mask.
(MASK_ZICCIF): Ditto.
(MASK_ZICCLSM): Ditto.
(MASK_ZICCRSE): Ditto.
(MASK_ZICNTR): Ditto.
(MASK_ZIHINTPAUSE): Ditto.
(MASK_ZIHPM): Ditto.
(TARGET_ZICCAMOA): New target.
(TARGET_ZICCIF): Ditto.
(TARGET_ZICCLSM): Ditto.
(TARGET_ZICCRSE): Ditto.
(TARGET_ZICNTR): Ditto.
(TARGET_ZIHINTPAUSE): Ditto.
(TARGET_ZIHPM): Ditto.
(MASK_SVPBMT): New mask.

---
 gcc/common/config/riscv/riscv-common.cc | 20 
 gcc/config/riscv/riscv-opts.h   | 15 +++
 2 files changed, 35 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index d6404a01205..602491c638d 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -163,6 +163,15 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
   {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
 
+  {"ziccamoa", ISA_SPEC_CLASS_NONE, 0, 1},
+  {"ziccif", ISA_SPEC_CLASS_NONE, 0, 1},
+  {"zicclsm", ISA_SPEC_CLASS_NONE, 0, 1},
+  {"ziccrse", ISA_SPEC_CLASS_NONE, 0, 1},
+  {"zicntr", ISA_SPEC_CLASS_NONE, 0, 1},
+
+  {"zihintpause", ISA_SPEC_CLASS_NONE, 0, 1},
+  {"zihpm", ISA_SPEC_CLASS_NONE, 0, 1},
+
   {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -219,6 +228,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"svpbmt", ISA_SPEC_CLASS_NONE, 0, 1},
 
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
@@ -1179,6 +1189,14 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"zicsr",&gcc_options::x_riscv_zi_subext, MASK_ZICSR},
   {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
+  {"ziccamoa", &gcc_options::x_riscv_zi_subext, MASK_ZICCAMOA},
+  {"ziccif", &gcc_options::x_riscv_zi_subext, MASK_ZICCIF},
+  {"zicclsm", &gcc_options::x_riscv_zi_subext, MASK_ZICCLSM},
+  {"ziccrse", &gcc_options::x_riscv_zi_subext, MASK_ZICCRSE},
+  {"zicntr", &gcc_options::x_riscv_zi_subext, MASK_ZICNTR},
+
+  {"zihintpause", &gcc_options::x_riscv_zi_subext, MASK_ZIHINTPAUSE},
+  {"zihpm", &gcc_options::x_riscv_zi_subext, MASK_ZIHPM},
 
   {"zba",&gcc_options::x_riscv_zb_subext, MASK_ZBA},
   {"zbb",&gcc_options::x_riscv_zb_subext, MASK_ZBB},
@@ -1230,6 +1248,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zvl1024b",  &gcc_options::x_riscv_zvl_flags, MASK_ZVL1024B},
   {"zvl2048b",  &gcc_options::x_riscv_zvl_flags, MASK_ZVL2048B},
   {"zvl4096b",  &gcc_options::x_riscv_zvl_flags, MASK_ZVL4096B},
+
   {"zvl8192b",  &gcc_options::x_riscv_zvl_flags, MASK_ZVL8192B},
   {"zvl16384b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL16384B},
   {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B},
@@ -1242,6 +1261,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
   {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
+  {"svpbmt", &gcc_options::x_riscv_sv_subext, MASK_SVPBMT},
 
   {NULL, NULL, 0}
 };
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1dfe8c89209..906b6280188 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -69,9 +69,23 @@ enum stack_protector_guard {
 
 #define MASK_ZICSR(1 << 0)
 #define MASK_ZIFENCEI (1 << 1)
+#define MASK_ZICCAMOA (1 << 2)
+#define MASK_ZICCIF   (1 << 3)
+#define MASK_ZICCLSM  (1 << 4)
+#define MASK_ZICCRSE  (1 << 5)
+#define MASK_ZICNTR   (1 << 6)
+#define MASK_ZIHINTPAUSE (1 << 7)
+#define MASK_ZIHPM(1 << 8)
 
 #define TARGET_ZICSR((riscv_zi_subext & MASK_ZICSR) != 0)
 #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
+#define TARGET_ZICCAMOA ((riscv_zi_subext & MASK_ZICCAMOA) != 0)
+#define TARGET_ZICCIF   ((riscv_zi_subext & MASK_ZICCIF) != 0)
+#define TARGET_ZICCLSM  ((riscv_zi_subext & MASK_ZICCLSM) != 0)
+#define TARGET_ZICCRSE  ((riscv_zi_subext & MASK_ZICCRSE) != 0)
+#define TARGET_ZICNTR   ((riscv_zi_subext & MASK_ZICNTR) != 0)
+#define TARGET_ZIHINTPAUSE ((riscv_zi_subext & MASK_ZIHINTPAUSE) != 0)
+#define TARGET_ZIHPM((riscv_zi_subext & MASK_ZIHPM) != 0)
 
 #define MASK_ZBA  (1 << 0)
 #define MASK_ZBB  (1 << 1)
@@ -174,6 +188,7 @@ enum stack_protector_guard {
 
 #define MASK_SVINVAL (1 << 0)
 #define MASK_SVNAPOT (1 << 1)
+#define MASK_SVPBMT   (1 << 2)
 
 #define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
 #define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
-- 
2

[RFC] RISC-V: Add profile supports.

[jiawei]

Add two new function to handle profile input,
"parse_profile" will check if a input into -march is
legal, if it is then "handle_profile" will check the
profile's type[I/M/A], year[20/22] and mode[U/S/M],
set different extensions combine, just deal mandatory
part currently.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc 
(riscv_subset_list::parse_profile): Check if profile name is valid or 
not.
(riscv_subset_list::parse_std_ext): If input of -march option is
a profile,skip first ISA check.
(riscv_subset_list::parse): Handle rofile input in -march.
(riscv_subset_list::handle_profile): Handle differen profiles
 expand to extensions.
* config/riscv/riscv-subset.h: New function prototypes.


---
 gcc/common/config/riscv/riscv-common.cc | 95 +++--
 gcc/config/riscv/riscv-subset.h |  5 +-
 2 files changed, 94 insertions(+), 6 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 602491c638d..da06bd89144 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -777,6 +777,35 @@ riscv_subset_list::parsing_subset_version (const char *ext,
   return p;
 }
 
+/* Parsing function for profile.
+
+   Return Value:
+ Points to the end of profile.
+
+   Arguments:
+ `p`: Current parsing position.  */
+
+const char *
+riscv_subset_list::parse_profile (const char *p)
+{
+  if(*p == 'I' || *p == 'M' || *p == 'A'){
+p++;
+if(startswith (p, "20") || startswith (p, "22"))
+  p += 2;
+if (*p == 'U' || *p == 'S' || *p == 'M')
+  p++;
+if(startswith (p, "64") || startswith (p, "32")){
+   p += 2;
+   riscv_subset_list::handle_profile(p-6, p-4, p-3);
+   return p;
+}
+  }
+  else
+error_at (m_loc, "%<-march=%s%>: Invalid profile.", m_arch);
+  return NULL;
+}
+
+
 /* Parsing function for standard extensions.
 
Return Value:
@@ -786,7 +815,7 @@ riscv_subset_list::parsing_subset_version (const char *ext,
  `p`: Current parsing position.  */
 
 const char *
-riscv_subset_list::parse_std_ext (const char *p)
+riscv_subset_list::parse_std_ext (const char *p, bool isprofile)
 {
   const char *all_std_exts = riscv_supported_std_ext ();
   const char *std_exts = all_std_exts;
@@ -795,8 +824,8 @@ riscv_subset_list::parse_std_ext (const char *p)
   unsigned minor_version = 0;
   char std_ext = '\0';
   bool explicit_version_p = false;
-
-  /* First letter must start with i, e or g.  */
+  if (!isprofile){
+/* First letter must start with i, e or g.  */
   switch (*p)
 {
 case 'i':
@@ -850,6 +879,7 @@ riscv_subset_list::parse_std_ext (const char *p)
"% or %", m_arch);
   return NULL;
 }
+}
 
   while (p != NULL && *p)
 {
@@ -1093,6 +1123,7 @@ riscv_subset_list::parse (const char *arch, location_t 
loc)
   riscv_subset_list *subset_list = new riscv_subset_list (arch, loc);
   riscv_subset_t *itr;
   const char *p = arch;
+  bool isprofile = false;
   if (startswith (p, "rv32"))
 {
   subset_list->m_xlen = 32;
@@ -1103,15 +1134,26 @@ riscv_subset_list::parse (const char *arch, location_t 
loc)
   subset_list->m_xlen = 64;
   p += 4;
 }
+  else if (startswith (p, "RV"))
+{
+  if (startswith (p+6, "64"))
+   subset_list->m_xlen = 64;
+  else
+   subset_list->m_xlen = 32;
+  p += 2;
+  /* Parsing profile name.  */
+  p = subset_list->parse_profile (p);
+  isprofile = true;
+}
   else
 {
-  error_at (loc, "%<-march=%s%>: ISA string must begin with rv32 or rv64",
+  error_at (loc, "%<-march=%s%>: ISA string must begin with rv32 , rv64 or 
a profile",
arch);
   goto fail;
 }
 
   /* Parsing standard extension.  */
-  p = subset_list->parse_std_ext (p);
+  p = subset_list->parse_std_ext (p,isprofile);
 
   if (p == NULL)
 goto fail;
@@ -1349,6 +1391,49 @@ riscv_handle_option (struct gcc_options *opts,
 }
 }
 
+/* Expand profile with defined mandatory extensions,
+   M-type/mode is emtpy and set as base right now.  */
+void riscv_subset_list::handle_profile(const char *profile_type,
+   const char *profile_year,
+   const char *profile_mode)
+{
+  add ("i", false);
+  if(*profile_type == 'A'){
+add ("m", false);
+add ("a", false);
+add ("f", false);
+add ("d", false);
+add ("c", false);
+add ("ziccamoa", false);
+add ("ziccif", false);
+add ("zicclsm", false);
+add ("ziccrse", false);
+add ("zicntr", false);
+add ("zicsr", false);
+
+if(*profile_mode == 'S')
+  add ("zifencei", false);
+  
+if(*profile_year == '2')
+{
+  add ("zihintpause", false);
+  add ("zihpm", false);
+  add ("zba", false);
+  add ("zbb", false);
+  add ("zbs", false);
+  add ("zicbom",

[PATCH] RISC-V:Add '-m[no]-csr-check' option in gcc.

[jiawei]

From: Jiawei 

Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option,
it will add csr-check in .option section and pass this to assembler.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_file_start): New .option.
* config/riscv/riscv.opt: New options.
* doc/invoke.texi: New definations.

---
 gcc/config/riscv/riscv.cc  | 5 +
 gcc/config/riscv/riscv.opt | 6 ++
 gcc/doc/invoke.texi| 6 ++
 3 files changed, 17 insertions(+)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 675d92c0961..e98e6b1f561 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5135,6 +5135,11 @@ riscv_file_start (void)
   if (! riscv_mrelax)
 fprintf (asm_out_file, "\t.option norelax\n");
 
+  /* If the user specifies "-mcsr-check" on the command line then enable csr
+ check in the assembler.  */
+  if (riscv_mcsr_check)
+fprintf (asm_out_file, "\t.option csr-check\n");
+
   if (riscv_emit_attribute_p)
 riscv_emit_attribute ();
 }
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index fbca91b956c..3a12dd47310 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -132,6 +132,12 @@ Target Bool Var(riscv_mrelax) Init(1)
 Take advantage of linker relaxations to reduce the number of instructions
 required to materialize symbol addresses.
 
+mcsr-check
+Target Bool Var(riscv_mcsr_check) Init(1)
+Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
+The ISA-dependent CSR are only valid when the specific ISA is set.  The
+read-only CSR can not be written by the CSR instructions.
+
 Mask(64BIT)
 
 Mask(MUL)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index dd3302fcd15..7caade26b94 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1224,6 +1224,7 @@ See RS/6000 and PowerPC Options.
 -mbig-endian  -mlittle-endian @gol
 -mstack-protector-guard=@var{guard}  -mstack-protector-guard-reg=@var{reg} @gol
 -mstack-protector-guard-offset=@var{offset}}
+-mcsr-check -mno-csr-check @gol
 
 @emph{RL78 Options}
 @gccoptlist{-msim  -mmul=none  -mmul=g13  -mmul=g14  -mallregs @gol
@@ -28551,6 +28552,11 @@ linker relaxations.
 Emit (do not emit) RISC-V attribute to record extra information into ELF
 objects.  This feature requires at least binutils 2.32.
 
+@item -mcsr-check
+@itemx -mno-csr-check
+@opindex mcsr-check
+Enables or disables the CSR checking.
+
 @item -malign-data=@var{type}
 @opindex malign-data
 Control how GCC aligns variables and constants of array, structure, or union
-- 
2.34.1

[V2 PATCH] RISC-V:Add '-m[no]-csr-check' option in gcc.

[jiawei]

From: Jiawei 

Add -m[no]-csr-check option in gcc part, when enable -mcsr-check option,
it will add csr-check in .option section and pass this to assembler.

V2: Add assembler support check info for -mcsr-check. Thanks for Kito's
suggestions.

gcc/ChangeLog:

* config.in: New def.
* config/riscv/riscv.cc (riscv_file_start): New .option.
* config/riscv/riscv.opt: New options.
* configure.ac: New check.
* doc/invoke.texi: New def.

---
 gcc/config.in  | 6 ++
 gcc/config/riscv/riscv.cc  | 5 +
 gcc/config/riscv/riscv.opt | 6 ++
 gcc/configure.ac   | 5 +
 gcc/doc/invoke.texi| 6 ++
 5 files changed, 28 insertions(+)

diff --git a/gcc/config.in b/gcc/config.in
index 9c53319b544..a4c39e1384d 100644
--- a/gcc/config.in
+++ b/gcc/config.in
@@ -616,6 +616,12 @@
 #endif
 
 
+/* Define if your assembler supports -mcsr-check. */
+#ifndef USED_FOR_TARGET
+#undef HAVE_AS_MCSR_CHECK
+#endif
+
+
 /* Define if your Mac OS X assembler supports -mllvm -x86-pad-for-align=false.
*/
 #ifndef USED_FOR_TARGET
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 675d92c0961..e98e6b1f561 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5135,6 +5135,11 @@ riscv_file_start (void)
   if (! riscv_mrelax)
 fprintf (asm_out_file, "\t.option norelax\n");
 
+  /* If the user specifies "-mcsr-check" on the command line then enable csr
+ check in the assembler.  */
+  if (riscv_mcsr_check)
+fprintf (asm_out_file, "\t.option csr-check\n");
+
   if (riscv_emit_attribute_p)
 riscv_emit_attribute ();
 }
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index fbca91b956c..3a12dd47310 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -132,6 +132,12 @@ Target Bool Var(riscv_mrelax) Init(1)
 Take advantage of linker relaxations to reduce the number of instructions
 required to materialize symbol addresses.
 
+mcsr-check
+Target Bool Var(riscv_mcsr_check) Init(1)
+Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
+The ISA-dependent CSR are only valid when the specific ISA is set.  The
+read-only CSR can not be written by the CSR instructions.
+
 Mask(64BIT)
 
 Mask(MUL)
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 50bb61c1b61..1a9288ee659 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -5269,6 +5269,11 @@ configured with --enable-newlib-nano-formatted-io.])
   [-march=rv32i_zifencei2p0],,,
   [AC_DEFINE(HAVE_AS_MARCH_ZIFENCEI, 1,
 [Define if the assembler understands -march=rv*_zifencei.])])
+gcc_GAS_CHECK_FEATURE([-mcsr-check],
+  gcc_cv_as_riscv_csr_check,
+  [-mcsr-check],,,
+  [AC_DEFINE(HAVE_AS_MCSR_CHECK, 1,
+[Define if the assembler understands -mcsr-check.])])
 ;;
 loongarch*-*-*)
 gcc_GAS_CHECK_FEATURE([.dtprelword support],
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index dd3302fcd15..7caade26b94 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1224,6 +1224,7 @@ See RS/6000 and PowerPC Options.
 -mbig-endian  -mlittle-endian @gol
 -mstack-protector-guard=@var{guard}  -mstack-protector-guard-reg=@var{reg} @gol
 -mstack-protector-guard-offset=@var{offset}}
+-mcsr-check -mno-csr-check @gol
 
 @emph{RL78 Options}
 @gccoptlist{-msim  -mmul=none  -mmul=g13  -mmul=g14  -mallregs @gol
@@ -28551,6 +28552,11 @@ linker relaxations.
 Emit (do not emit) RISC-V attribute to record extra information into ELF
 objects.  This feature requires at least binutils 2.32.
 
+@item -mcsr-check
+@itemx -mno-csr-check
+@opindex mcsr-check
+Enables or disables the CSR checking.
+
 @item -malign-data=@var{type}
 @opindex malign-data
 Control how GCC aligns variables and constants of array, structure, or union
-- 
2.34.1

[PATCH] testsuite: Update Wconversion testcase check type.

[jiawei]

Some compiler target like arm-linux\riscv\power\s390x\xtensa-gcc handle 
char as unsigned char, then there are no warnings occur and got FAIL cases.
Just change the type char into explicit signed char to keep the feature
consistency.

gcc/testsuite/ChangeLog:

* c-c++-common/Wconversion-1.c: Update type.

---
 gcc/testsuite/c-c++-common/Wconversion-1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/c-c++-common/Wconversion-1.c 
b/gcc/testsuite/c-c++-common/Wconversion-1.c
index ed65918c70f..7053f6b5dbb 100644
--- a/gcc/testsuite/c-c++-common/Wconversion-1.c
+++ b/gcc/testsuite/c-c++-common/Wconversion-1.c
@@ -10,5 +10,5 @@ void g()
   signed char sc = 300; /* { dg-warning "conversion from .int. to .signed 
char. changes value from .300. to .44." } */
   unsigned char uc = 300; /* { dg-warning "conversion from .int. to .unsigned 
char. changes value from .300. to .44." } */
   unsigned char uc2 = 300u; /* { dg-warning "conversion from .unsigned int. to 
.unsigned char. changes value from .300. to .44." } */
-  char c2 = (double)1.0 + 200; /* { dg-warning "overflow in conversion from 
.double. to .char. changes value from .2.01e\\+2. to .127." } */
+  signed char c2 = (double)1.0 + 200; /* { dg-warning "overflow in conversion 
from .double. to .signed char. changes value from .2.01e\\+2. to .127." } */
 }
-- 
2.25.1

[PATCH] testsuite: opt: Fix const7.C for RISC-V.

[jiawei]

Similar to patch 593993, RISC-V needs to limit symbols send in sdata.
Thanks for Palmer's help.

gcc/testsuite/ChangeLog:

* g++.dg/opt/const7.C: Don't use small data on RISC-V.

---
 gcc/testsuite/g++.dg/opt/const7.C | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/g++.dg/opt/const7.C 
b/gcc/testsuite/g++.dg/opt/const7.C
index 5bcf94897a8..50d902beae1 100644
--- a/gcc/testsuite/g++.dg/opt/const7.C
+++ b/gcc/testsuite/g++.dg/opt/const7.C
@@ -1,6 +1,7 @@
 // PR c++/104142
 // { dg-do compile { target c++11 } }
 // { dg-additional-options -Wunused-variable }
+// { dg-options "-msmall-data-limit=0" { target { riscv*-*-* } } }
 
 struct B { B()=default; };
 static const B b_var;  //  { dg-bogus "" }
-- 
2.25.1

[PATCH v3 0/3] RISC-V: Support z[f/d]inx extension

[jiawei]

From: Jia-Wei Chen 

Zfinx extension[1] had already finished public review. Here is the 
implementation patch set that reuse floating point pattern and ban
the use of fpr when use zfinx as a target.

Current works can be find in follow links, will keep update zhinx
and zhinxmin soon after zfh/zfhmin implemented in gcc.
  https://github.com/pz9115/riscv-gcc/tree/zfinx-rebase
  https://github.com/pz9115/riscv-binutils-gdb/tree/zfinx-rebase

For test you can use qemu or spike that support zfinx extension, the
qemu will go upstream soon and spike is still in review:
  https://github.com/plctlab/plct-qemu/tree/plct-zfinx-dev
  https://github.com/plctlab/plct-spike/tree/plct-upstream-zfinx

Thanks for Tariq Kurd, Kito Cheng, Jim Willson, 
Jeremy Bennett helped us a lot with this work.

[1] https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf

Version log:

v2: As Kito Cheng's comment, add Changelog part in patches, update imply 
info in riscv-common.c, remove useless check and update annotation in 
riscv.c.

v3: Update with new isa-spec version 20191213, make zfinx imply zicsr as
default, fix the lack of fcsr use in zfinx.

jiawei (3):
  RISC-V: Minimal support of zfinx extension.
  RISC-V: Target support for zfinx extension.
  RISC-V: Limit regs use  for zfinx extension.

 gcc/common/config/riscv/riscv-common.cc |  9 
 gcc/config/riscv/arch-canonicalize  |  3 ++
 gcc/config/riscv/constraints.md |  4 +-
 gcc/config/riscv/riscv-builtins.cc  |  4 +-
 gcc/config/riscv/riscv-c.cc |  2 +-
 gcc/config/riscv/riscv-opts.h   |  6 +++
 gcc/config/riscv/riscv.cc   | 14 -
 gcc/config/riscv/riscv.md   | 72 -
 gcc/config/riscv/riscv.opt  |  3 ++
 9 files changed, 75 insertions(+), 42 deletions(-)

-- 
2.25.1

[PATCH v3 1/3] RISC-V: Minimal support of z[f/d]inx extension.

[jiawei]

From: Jia-Wei Chen 

Minimal support of zfinx extension, include 'zfinx' and 'zdinx'
corresponding to 'f' and 'd', the 'zdinx' will imply 'zfinx'
same as 'd' imply 'f'.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: Add z[f/d]inx extension info.
* config/riscv/arch-canonicalize: Add imply info.
* config/riscv/riscv-opts.h (MASK_ZFINX): New.
(MASK_ZDINX): Ditto.
(TARGET_ZFINX): Ditto.
(TARGET_ZDINX): Ditto.
* config/riscv/riscv.opt: New.
  
Co-Authored-By: Sinan Lin
---
 gcc/common/config/riscv/riscv-common.cc | 9 +
 gcc/config/riscv/arch-canonicalize  | 3 +++
 gcc/config/riscv/riscv-opts.h   | 6 ++
 gcc/config/riscv/riscv.opt  | 3 +++
 4 files changed, 21 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 1501242e296..124bccb23ce 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -50,6 +50,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"d", "f"},
   {"f", "zicsr"},
   {"d", "zicsr"},
+  {"zdinx", "zfinx"},
+  {"zfinx", "zicsr"},
+
   {"zk", "zkn"},
   {"zk", "zkr"},
   {"zk", "zkt"},
@@ -154,6 +157,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zbkb",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbkc",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbkx",  ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1099,6 +1105,9 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zbc",&gcc_options::x_riscv_zb_subext, MASK_ZBC},
   {"zbs",&gcc_options::x_riscv_zb_subext, MASK_ZBS},
 
+  {"zfinx",&gcc_options::x_riscv_zf_subext, MASK_ZFINX},
+  {"zdinx",&gcc_options::x_riscv_zf_subext, MASK_ZDINX},
+
   {"zbkb",   &gcc_options::x_riscv_zk_subext, MASK_ZBKB},
   {"zbkc",   &gcc_options::x_riscv_zk_subext, MASK_ZBKC},
   {"zbkx",   &gcc_options::x_riscv_zk_subext, MASK_ZBKX},
diff --git a/gcc/config/riscv/arch-canonicalize 
b/gcc/config/riscv/arch-canonicalize
index 41bab69193c..e4cfae40b8a 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -41,6 +41,9 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 IMPLIED_EXT = {
   "d" : ["f", "zicsr"],
   "f" : ["zicsr"],
+  "zdinx" : ["zfinx", "zicsr"],
+  "zfinx" : ["zicsr"],
+
   "zk" : ["zkn", "zkr", "zkt"],
   "zkn" : ["zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"],
   "zks" : ["zbkb", "zbkc", "zbkx", "zksed", "zksh"],
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 15bb5e76854..4faf62616d3 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -83,6 +83,12 @@ enum stack_protector_guard {
 #define TARGET_ZBC((riscv_zb_subext & MASK_ZBC) != 0)
 #define TARGET_ZBS((riscv_zb_subext & MASK_ZBS) != 0)
 
+#define MASK_ZFINX  (1 << 0)
+#define MASK_ZDINX  (1 << 0)
+
+#define TARGET_ZFINX((riscv_zf_subext & MASK_ZFINX) != 0)
+#define TARGET_ZDINX((riscv_zf_subext & MASK_ZDINX) != 0)
+
 #define MASK_ZBKB (1 << 0)
 #define MASK_ZBKC (1 << 1)
 #define MASK_ZBKX (1 << 2)
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 84c8cf5a2de..18fd11e3a51 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -200,6 +200,9 @@ int riscv_zi_subext
 TargetVariable
 int riscv_zb_subext
 
+TargetVariable
+int riscv_zf_subext
+
 TargetVariable
 int riscv_zk_subext
 
-- 
2.25.1

[PATCH v3 3/3] RISC-V: Limit regs use for z[f/d]inx extension.

[jiawei]

From: Jia-Wei Chen 

Limit zfinx abi support with 'ilp32','ilp32e','lp64' only.

Use GPR instead FPR when 'zfinx' enable, Only use even registers in RV32 when 
'zdinx' enable.

gcc/ChangeLog:

* config/riscv/constraints.md (TARGET_HARD_FLOAT ? FP_REGS :
 ((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)):
  Use gpr when zfinx or zdinx enable.
* config/riscv/riscv.c (riscv_hard_regno_mode_ok): Add TARGET_ZFINX.
(riscv_option_override): Ditto.
(riscv_abi): Add ABI limit for zfinx with ilp32/lp64.

Co-Authored-By: Sinan Lin.
---
 gcc/config/riscv/constraints.md |  4 ++--
 gcc/config/riscv/riscv.cc   | 14 +-
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index bafa4188ccb..0b3d55fee19 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -21,8 +21,8 @@
 
 ;; Register constraints
 
-(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
-  "A floating-point register (if available).")
+(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX 
|| TARGET_ZDINX) ? GR_REGS : NO_REGS)"
+  "A floating-point register (if available, reuse GPR as FPR when use zfinx).")
 
 (define_register_constraint "j" "SIBCALL_REGS"
   "@internal")
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ee756aab694..01deef54480 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4789,6 +4789,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, 
machine_mode mode)
!= call_used_or_fixed_reg_p (regno + i))
   return false;
 
+  /* Only use even registers in RV32 ZDINX */
+  if (!TARGET_64BIT && TARGET_ZDINX){
+if (GET_MODE_CLASS (mode) == MODE_FLOAT &&
+ GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode))
+return !(regno & 1);
+  }
+
   return true;
 }
 
@@ -4980,7 +4987,7 @@ riscv_option_override (void)
 error ("%<-mdiv%> requires %<-march%> to subsume the % extension");
 
   /* Likewise floating-point division and square root.  */
-  if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
+  if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & 
MASK_FDIV) == 0)
 target_flags |= MASK_FDIV;
 
   /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
@@ -5026,6 +5033,11 @@ riscv_option_override (void)
   if (TARGET_RVE && riscv_abi != ABI_ILP32E)
 error ("rv32e requires ilp32e ABI");
 
+  // Zfinx require abi ilp32,ilp32e or lp64.
+  if (TARGET_ZFINX && riscv_abi != ABI_ILP32
+  && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
+error ("z*inx requires ABI ilp32, ilp32e or lp64");
+
   /* We do not yet support ILP32 on RV64.  */
   if (BITS_PER_WORD != POINTER_SIZE)
 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
-- 
2.25.1

[PATCH v3 2/3] RISC-V: Target support for z[f/d]inx extension.

[jiawei]

From: Jia-Wei Chen 

Support 'TARGET_ZFINX' with float instruction pattern and builtin function.
Reuse 'TARGET_HADR_FLOAT' and 'TARGET_DOUBLE_FLOAT' patterns.

gcc/ChangeLog:

* config/riscv/riscv-builtins.cc (AVAIL): Add TARGET_ZFINX.
(riscv_atomic_assign_expand_fenv): Ditto.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add TARGET_ZFINX.
* config/riscv/riscv.md (TARGET_HARD_FLOAT): Add TARGET_ZFINX.
(TARGET_HARD_FLOAT || TARGET_ZFINX): Add TARGET_ZFINX.
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX): Add TARGET_ZDINX.

Co-Authored-By: Sinan Lin.
---
 gcc/config/riscv/riscv-builtins.cc |  4 +-
 gcc/config/riscv/riscv-c.cc|  2 +-
 gcc/config/riscv/riscv.md  | 76 +++---
 3 files changed, 41 insertions(+), 41 deletions(-)

diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 0658f8d3047..21896d747f5 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -85,7 +85,7 @@ struct riscv_builtin_description {
   unsigned int (*avail) (void);
 };
 
-AVAIL (hard_float, TARGET_HARD_FLOAT)
+AVAIL (hard_float, TARGET_HARD_FLOAT || TARGET_ZFINX)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -279,7 +279,7 @@ riscv_expand_builtin (tree exp, rtx target, rtx subtarget 
ATTRIBUTE_UNUSED,
 void
 riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
 {
-  if (!TARGET_HARD_FLOAT)
+  if (!(TARGET_HARD_FLOAT || TARGET_ZFINX))
 return;
 
   tree frflags = GET_BUILTIN_DECL (CODE_FOR_riscv_frflags);
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index eb7ef09297e..a9c43a64fd4 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -58,7 +58,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
   if (TARGET_HARD_FLOAT)
 builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
 
-  if (TARGET_HARD_FLOAT && TARGET_FDIV)
+  if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV)
 {
   builtin_define ("__riscv_fdiv");
   builtin_define ("__riscv_fsqrt");
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index d9b451be0b4..f81e315666e 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -300,8 +300,8 @@
 (define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")])
 
 ;; Iterator for hardware-supported floating-point modes.
-(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
-   (DF "TARGET_DOUBLE_FLOAT")])
+(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
+   (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")])
 
 ;; Iterator for floating-point modes that can be loaded into X registers.
 (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT")])
@@ -448,7 +448,7 @@
   [(set (match_operand:ANYF0 "register_operand" "=f")
(plus:ANYF (match_operand:ANYF 1 "register_operand" " f")
   (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fadd.\t%0,%1,%2"
   [(set_attr "type" "fadd")
(set_attr "mode" "")])
@@ -579,7 +579,7 @@
   [(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fsub.\t%0,%1,%2"
   [(set_attr "type" "fadd")
(set_attr "mode" "")])
@@ -749,7 +749,7 @@
   [(set (match_operand:ANYF   0 "register_operand" "=f")
(mult:ANYF (match_operand:ANYF1 "register_operand" " f")
  (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fmul.\t%0,%1,%2"
   [(set_attr "type" "fmul")
(set_attr "mode" "")])
@@ -1056,7 +1056,7 @@
   [(set (match_operand:ANYF   0 "register_operand" "=f")
(div:ANYF (match_operand:ANYF 1 "register_operand" " f")
  (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT && TARGET_FDIV"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV"
   "fdiv.\t%0,%1,%2"
   [(set_attr "type" "fdiv")
(set_attr "mode" "")])
@@ -1071,7 +1071,7 @@
 (define_insn "sqrt2"
   [(set (match_operand:ANYF0 "register_operand" "=f")
(sqrt:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT && TARGET_FDIV"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV"
 {
 return "fsqrt.\t%0,%1";
 }
@@ -1086,7 +1086,7 @@
(fma:ANYF (match_operand:ANYF 1 "register_operand" " f")
  (match_operand:ANYF 2 "register_operand" " f")
  (match_operand:ANYF 3 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fmadd.\t%0,%1,%2,%3"
   [(set_attr "type" "fmadd")
(set_attr "mode" "")])
@@ -1097

[PATCH v3 0/3] RISC-V: Support z[f/d]inx extension

[jiawei]

From: Jia-Wei Chen 

Zfinx extension[1] had already finished public review. Here is the 
implementation patch set that reuse floating point pattern and ban
the use of fpr when use zfinx as a target.

Current works can be find in follow links, will keep update zhinx
and zhinxmin soon after zfh/zfhmin implemented in gcc.
  https://github.com/pz9115/riscv-gcc/tree/zfinx-rebase
  https://github.com/pz9115/riscv-binutils-gdb/tree/zfinx-rebase

For test you can use qemu or spike that support zfinx extension, the
qemu will go upstream soon and spike is still in review:
  https://github.com/plctlab/plct-qemu/tree/plct-zfinx-dev
  https://github.com/plctlab/plct-spike/tree/plct-upstream-zfinx

Thanks for Tariq Kurd, Kito Cheng, Jim Willson, 
Jeremy Bennett helped us a lot with this work.

[1] https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf

Version log:

v2: As Kito Cheng's comment, add Changelog part in patches, update imply 
info in riscv-common.c, remove useless check and update annotation in 
riscv.c.

v3: Update with new isa-spec version 20191213, make zfinx imply zicsr as
default, fix the lack of fcsr use in zfinx.

jiawei (3):
  RISC-V: Minimal support of zfinx extension.
  RISC-V: Target support for zfinx extension.
  RISC-V: Limit regs use  for zfinx extension.

 gcc/common/config/riscv/riscv-common.cc |  9 
 gcc/config/riscv/arch-canonicalize  |  3 ++
 gcc/config/riscv/constraints.md |  4 +-
 gcc/config/riscv/riscv-builtins.cc  |  4 +-
 gcc/config/riscv/riscv-c.cc |  2 +-
 gcc/config/riscv/riscv-opts.h   |  6 +++
 gcc/config/riscv/riscv.cc   | 14 -
 gcc/config/riscv/riscv.md   | 72 -
 gcc/config/riscv/riscv.opt  |  3 ++
 9 files changed, 75 insertions(+), 42 deletions(-)

-- 
2.25.1

[PATCH v2 0/3] RISC-V: Support zfinx extension

[jiawei]

Zfinx extension[1] had already finished public review. Here is the 
implementation patch set that reuse floating point pattern and ban the use of 
fpr when use zfinx as a target.

Current works can be find in follow links, we will keep update zhinx and 
zhinxmin after zfh extension goes upstream.
  https://github.com/pz9115/riscv-gcc/tree/zfinx-rebase
  https://github.com/pz9115/riscv-binutils-gdb/tree/zfinx-rebase

For test you can use qemu or spike that support zfinx extension, the
qemu will go upstream soon and spike is still in review:
  https://github.com/plctlab/plct-qemu/tree/plct-zfinx-dev
  https://github.com/plctlab/plct-spike/tree/plct-upstream-zfinx  

Thanks for Tariq Kurd, Kito Cheng, Jim Willson, Jeremy Bennett helped us a lot 
with this work.

[1] https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf

Version log:

v2: As Kito Cheng's comment, add Changelog part in patches, update imply info 
in riscv-common.c,
remove useless check and update annotation in riscv.c.

jiawei (3):
  RISC-V: Minimal support of zfinx extension
  RISC-V: Target support for zfinx extension
  RISC-V: Limit regs use  for zfinx extension

 gcc/common/config/riscv/riscv-common.c |  7 +++
 gcc/config/riscv/arch-canonicalize |  1 +
 gcc/config/riscv/constraints.md|  3 +-
 gcc/config/riscv/riscv-builtins.c  |  4 +-
 gcc/config/riscv/riscv-c.c |  2 +-
 gcc/config/riscv/riscv-opts.h  |  6 +++
 gcc/config/riscv/riscv.c   | 14 -
 gcc/config/riscv/riscv.md  | 72 +-
 gcc/config/riscv/riscv.opt |  3 ++
 9 files changed, 71 insertions(+), 41 deletions(-)

-- 
2.25.1

[PATCH v2 2/3] RISC-V: Target support for zfinx extension

[jiawei]

Support 'TARGET_ZFINX' with float instruction pattern and builtin function.

gcc/ChangeLog:

* config/riscv/riscv-builtins.c (AVAIL): Add TARGET_ZFINX.
(riscv_atomic_assign_expand_fenv): Ditto.
* config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Add TARGET_ZFINX.
* config/riscv/riscv.md 
(TARGET_HARD_FLOAT || TARGET_ZFINX): Add TARGET_ZFINX.
(TARGET_DOUBLE_FLOAT || TARGET_ZDINX): Add TARGET_ZDINX.

Co-Authored-By: sinan 
---
 gcc/config/riscv/riscv-builtins.c |  4 +-
 gcc/config/riscv/riscv-c.c|  2 +-
 gcc/config/riscv/riscv.md | 72 +++
 3 files changed, 39 insertions(+), 39 deletions(-)

diff --git a/gcc/config/riscv/riscv-builtins.c 
b/gcc/config/riscv/riscv-builtins.c
index 97b1480a15e..d892e6cdb26 100644
--- a/gcc/config/riscv/riscv-builtins.c
+++ b/gcc/config/riscv/riscv-builtins.c
@@ -85,7 +85,7 @@ struct riscv_builtin_description {
   unsigned int (*avail) (void);
 };
 
-AVAIL (hard_float, TARGET_HARD_FLOAT)
+AVAIL (hard_float, TARGET_HARD_FLOAT || TARGET_ZFINX)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -279,7 +279,7 @@ riscv_expand_builtin (tree exp, rtx target, rtx subtarget 
ATTRIBUTE_UNUSED,
 void
 riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
 {
-  if (!TARGET_HARD_FLOAT)
+  if (!(TARGET_HARD_FLOAT || TARGET_ZFINX))
 return;
 
   tree frflags = GET_BUILTIN_DECL (CODE_FOR_riscv_frflags);
diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c
index efd4a61ea29..d064a7fc2b3 100644
--- a/gcc/config/riscv/riscv-c.c
+++ b/gcc/config/riscv/riscv-c.c
@@ -58,7 +58,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
   if (TARGET_HARD_FLOAT)
 builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
 
-  if (TARGET_HARD_FLOAT && TARGET_FDIV)
+  if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV)
 {
   builtin_define ("__riscv_fdiv");
   builtin_define ("__riscv_fsqrt");
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 225e5b259c1..27c9c74c679 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -296,8 +296,8 @@
 (define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")])
 
 ;; Iterator for hardware-supported floating-point modes.
-(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
-   (DF "TARGET_DOUBLE_FLOAT")])
+(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
+   (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")])
 
 ;; Iterator for floating-point modes that can be loaded into X registers.
 (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT")])
@@ -444,7 +444,7 @@
   [(set (match_operand:ANYF0 "register_operand" "=f")
(plus:ANYF (match_operand:ANYF 1 "register_operand" " f")
   (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fadd.\t%0,%1,%2"
   [(set_attr "type" "fadd")
(set_attr "mode" "")])
@@ -575,7 +575,7 @@
   [(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fsub.\t%0,%1,%2"
   [(set_attr "type" "fadd")
(set_attr "mode" "")])
@@ -745,7 +745,7 @@
   [(set (match_operand:ANYF   0 "register_operand" "=f")
(mult:ANYF (match_operand:ANYF1 "register_operand" " f")
  (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fmul.\t%0,%1,%2"
   [(set_attr "type" "fmul")
(set_attr "mode" "")])
@@ -1052,7 +1052,7 @@
   [(set (match_operand:ANYF   0 "register_operand" "=f")
(div:ANYF (match_operand:ANYF 1 "register_operand" " f")
  (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT && TARGET_FDIV"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV"
   "fdiv.\t%0,%1,%2"
   [(set_attr "type" "fdiv")
(set_attr "mode" "")])
@@ -1067,7 +1067,7 @@
 (define_insn "sqrt2"
   [(set (match_operand:ANYF0 "register_operand" "=f")
(sqrt:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT && TARGET_FDIV"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV"
 {
 return "fsqrt.\t%0,%1";
 }
@@ -1082,7 +1082,7 @@
(fma:ANYF (match_operand:ANYF 1 "register_operand" " f")
  (match_operand:ANYF 2 "register_operand" " f")
  (match_operand:ANYF 3 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fmadd.\t%0,%1,%2,%3"
   [(set_attr "type" "fmadd")
(set_attr "mode" "")])
@@ -1093,7 +1093,7 @@
(fma:ANYF (match_operand:ANYF   1 "register_operand" " f")
  (match_operand:ANYF   

[PATCH v2 3/3] RISC-V: Limit regs use for zfinx extension

[jiawei]

Limit zfinx abi support with 'ilp32','ilp32e','lp64' only.

Use GPR instead FPR when 'zfinx' enable, Only use even registers in RV32 when 
'zdinx' enable.

gcc/ChangeLog:

* config/riscv/constraints.md
(TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX || TARGET_ZDINX) ? 
GR_REGS : NO_REGS)):
  Use gpr when zfinx or zdinx enable.
* config/riscv/riscv.c (riscv_hard_regno_mode_ok): Add TARGET_ZFINX.
(riscv_option_override): Ditto.
(riscv_abi): Add ABI limit for zfinx.

Co-Authored-By: sinan 
---
 gcc/config/riscv/constraints.md |  3 ++-
 gcc/config/riscv/riscv.c| 14 +-
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index c87d5b796a5..a99b8ce277e 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -20,8 +20,9 @@
 ;; .
 
 ;; Register constraints
+;; Zfinx support need refuse FPR and use GPR
 
-(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
+(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX 
|| TARGET_ZDINX) ? GR_REGS : NO_REGS)"
   "A floating-point register (if available).")
 
 (define_register_constraint "j" "SIBCALL_REGS"
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index a545dbf66f7..f4e0e46e1a7 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -4789,6 +4789,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, 
machine_mode mode)
!= call_used_or_fixed_reg_p (regno + i))
   return false;
 
+  /* Only use even registers in RV32 ZDINX */
+  if (!TARGET_64BIT && TARGET_ZDINX){
+if (GET_MODE_CLASS (mode) == MODE_FLOAT &&
+   GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode))
+  return !(regno & 1);
+  }
+
   return true;
 }
 
@@ -4980,7 +4987,7 @@ riscv_option_override (void)
 error ("%<-mdiv%> requires %<-march%> to subsume the % extension");
 
   /* Likewise floating-point division and square root.  */
-  if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
+  if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & 
MASK_FDIV) == 0)
 target_flags |= MASK_FDIV;
 
   /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
@@ -5026,6 +5033,11 @@ riscv_option_override (void)
   if (TARGET_RVE && riscv_abi != ABI_ILP32E)
 error ("rv32e requires ilp32e ABI");
 
+  // Zfinx require abi ilp32,ilp32e or lp64.
+  if (TARGET_ZFINX && riscv_abi != ABI_ILP32
+&& riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
+  error ("z*inx requires ABI ilp32, ilp32e or lp64");
+
   /* We do not yet support ILP32 on RV64.  */
   if (BITS_PER_WORD != POINTER_SIZE)
 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
-- 
2.25.1

[PATCH v2 1/3] RISC-V: Minimal support of zfinx extension

[jiawei]

Minimal support of zfinx extension, include 'zfinx' and 'zdinx' corresponding 
to 'f' and 'd', the 'zdinx' will imply 'zfinx' same as 'd' imply 'f'.

gcc/ChangeLog:

* common/config/riscv/riscv-common.c(riscv_implied_info_t): Add zdinx 
imply zfinx.
  (riscv_ext_version_table): Add zfinx, zdinx.
* config/riscv/arch-canonicalize(IMPLIED_EXT): Add zdinx imply zfinx.
* config/riscv/riscv-opts.h
  (MASK_ZFINX): New.
  (MASK_ZDINX): Ditto.
  (TARGET_ZFINX): Ditto.
  (TARGET_ZDINX): Ditto.
* config/riscv/riscv.opt(riscv_zf_subext): New.

Co-Authored-By: sinan 
---
 gcc/common/config/riscv/riscv-common.c | 7 +++
 gcc/config/riscv/arch-canonicalize | 1 +
 gcc/config/riscv/riscv-opts.h  | 6 ++
 gcc/config/riscv/riscv.opt | 3 +++
 4 files changed, 17 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.c 
b/gcc/common/config/riscv/riscv-common.c
index 37b6ea80086..6db5a434257 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -50,6 +50,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"d", "f"},
   {"f", "zicsr"},
   {"d", "zicsr"},
+  {"zdinx", "zfinx"},
   {NULL, NULL}
 };
 
@@ -106,6 +107,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -916,6 +920,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zbc",&gcc_options::x_riscv_zb_subext, MASK_ZBC},
   {"zbs",&gcc_options::x_riscv_zb_subext, MASK_ZBS},
 
+  {"zfinx",&gcc_options::x_riscv_zf_subext, MASK_ZFINX},
+  {"zdinx",&gcc_options::x_riscv_zf_subext, MASK_ZDINX},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/arch-canonicalize 
b/gcc/config/riscv/arch-canonicalize
index c7df3c8a313..9197163d1c3 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -36,6 +36,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 #
 IMPLIED_EXT = {
   "d" : ["f"],
+  "zdinx" : ["zfinx"],
 }
 
 def arch_canonicalize(arch):
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 2efc4b80f1f..5a790a028cf 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -83,4 +83,10 @@ enum stack_protector_guard {
 #define TARGET_ZBC((riscv_zb_subext & MASK_ZBC) != 0)
 #define TARGET_ZBS((riscv_zb_subext & MASK_ZBS) != 0)
 
+#define MASK_ZFINX  (1 << 0)
+#define MASK_ZDINX  (1 << 1)
+
+#define TARGET_ZFINX((riscv_zf_subext & MASK_ZFINX) != 0)
+#define TARGET_ZDINX((riscv_zf_subext & MASK_ZDINX) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 15bf89e17c2..54d27747eff 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -198,6 +198,9 @@ int riscv_zi_subext
 TargetVariable
 int riscv_zb_subext
 
+TargetVariable
+int riscv_zf_subext
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):
-- 
2.25.1

[PATCH 0/3] RISC-V: Zfinx extension support

[jiawei]

Zfinx extension[1] had already finished public review. Here is the 
implementation patch set that reuse floating point pattern and ban the use of 
fpr when use zfinx as a target.

Current works can be find in follow links, we will keep update zhinx and 
zhinxmin after zfh extension goes upstream.
  https://github.com/pz9115/riscv-gcc/tree/zfinx-rebase
  https://github.com/pz9115/riscv-binutils-gdb/tree/zfinx-rebase

For test you can use qemu or spike that support zfinx extension, the
qemu will go upstream soon and spike is still in review:
  https://github.com/plctlab/plct-qemu/tree/plct-zfinx-dev
  https://github.com/plctlab/plct-spike/tree/plct-upstream-zfinx  

Thanks for Tariq Kurd, Kito Cheng, Jim Willson, Jeremy Bennett helped us a lot 
with this work.

[1] https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf

jiawei sinan (3):
  RISC-V: Minimal support of zfinx extension
  RISC-V: Target support for zfinx extension
  RISC-V: Imply info and regs limit for zfinx extension

 gcc/common/config/riscv/riscv-common.c |  6 +++
 gcc/config/riscv/arch-canonicalize |  1 +
 gcc/config/riscv/constraints.md|  3 +-
 gcc/config/riscv/riscv-builtins.c  |  4 +-
 gcc/config/riscv/riscv-c.c |  2 +-
 gcc/config/riscv/riscv-opts.h  |  6 +++
 gcc/config/riscv/riscv.c   | 15 +-
 gcc/config/riscv/riscv.md  | 72 +-
 gcc/config/riscv/riscv.opt |  3 ++
 9 files changed, 70 insertions(+), 42 deletions(-)

[PATCH 1/3] RISC-V: Minimal support of zfinx extension

[jiawei]

Co-Authored-By: sinan 
---
 gcc/common/config/riscv/riscv-common.c | 6 ++
 gcc/config/riscv/riscv-opts.h  | 6 ++
 gcc/config/riscv/riscv.opt | 3 +++
 3 files changed, 15 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.c 
b/gcc/common/config/riscv/riscv-common.c
index 37b6ea80086..ab48909e338 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -106,6 +106,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -916,6 +919,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zbc",&gcc_options::x_riscv_zb_subext, MASK_ZBC},
   {"zbs",&gcc_options::x_riscv_zb_subext, MASK_ZBS},
 
+  {"zfinx",&gcc_options::x_riscv_zf_subext, MASK_ZFINX},
+  {"zdinx",&gcc_options::x_riscv_zf_subext, MASK_ZDINX},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 2efc4b80f1f..5a790a028cf 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -83,4 +83,10 @@ enum stack_protector_guard {
 #define TARGET_ZBC((riscv_zb_subext & MASK_ZBC) != 0)
 #define TARGET_ZBS((riscv_zb_subext & MASK_ZBS) != 0)
 
+#define MASK_ZFINX  (1 << 0)
+#define MASK_ZDINX  (1 << 1)
+
+#define TARGET_ZFINX((riscv_zf_subext & MASK_ZFINX) != 0)
+#define TARGET_ZDINX((riscv_zf_subext & MASK_ZDINX) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 15bf89e17c2..54d27747eff 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -198,6 +198,9 @@ int riscv_zi_subext
 TargetVariable
 int riscv_zb_subext
 
+TargetVariable
+int riscv_zf_subext
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):
-- 
2.25.1

[PATCH 2/3] RISC-V: Target support for zfinx extension

[jiawei]

Co-Authored-By: sinan 
---
 gcc/config/riscv/riscv-builtins.c |  4 +-
 gcc/config/riscv/riscv-c.c|  2 +-
 gcc/config/riscv/riscv.md | 72 +++
 3 files changed, 39 insertions(+), 39 deletions(-)

diff --git a/gcc/config/riscv/riscv-builtins.c 
b/gcc/config/riscv/riscv-builtins.c
index 97b1480a15e..d892e6cdb26 100644
--- a/gcc/config/riscv/riscv-builtins.c
+++ b/gcc/config/riscv/riscv-builtins.c
@@ -85,7 +85,7 @@ struct riscv_builtin_description {
   unsigned int (*avail) (void);
 };
 
-AVAIL (hard_float, TARGET_HARD_FLOAT)
+AVAIL (hard_float, TARGET_HARD_FLOAT || TARGET_ZFINX)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -279,7 +279,7 @@ riscv_expand_builtin (tree exp, rtx target, rtx subtarget 
ATTRIBUTE_UNUSED,
 void
 riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
 {
-  if (!TARGET_HARD_FLOAT)
+  if (!(TARGET_HARD_FLOAT || TARGET_ZFINX))
 return;
 
   tree frflags = GET_BUILTIN_DECL (CODE_FOR_riscv_frflags);
diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c
index efd4a61ea29..d064a7fc2b3 100644
--- a/gcc/config/riscv/riscv-c.c
+++ b/gcc/config/riscv/riscv-c.c
@@ -58,7 +58,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
   if (TARGET_HARD_FLOAT)
 builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
 
-  if (TARGET_HARD_FLOAT && TARGET_FDIV)
+  if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV)
 {
   builtin_define ("__riscv_fdiv");
   builtin_define ("__riscv_fsqrt");
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index dd4c24292f2..0fef80c8742 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -296,8 +296,8 @@
 (define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")])
 
 ;; Iterator for hardware-supported floating-point modes.
-(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
-   (DF "TARGET_DOUBLE_FLOAT")])
+(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX")
+   (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX")])
 
 ;; Iterator for floating-point modes that can be loaded into X registers.
 (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT")])
@@ -444,7 +444,7 @@
   [(set (match_operand:ANYF0 "register_operand" "=f")
(plus:ANYF (match_operand:ANYF 1 "register_operand" " f")
   (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fadd.\t%0,%1,%2"
   [(set_attr "type" "fadd")
(set_attr "mode" "")])
@@ -575,7 +575,7 @@
   [(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF (match_operand:ANYF 1 "register_operand" " f")
(match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fsub.\t%0,%1,%2"
   [(set_attr "type" "fadd")
(set_attr "mode" "")])
@@ -745,7 +745,7 @@
   [(set (match_operand:ANYF   0 "register_operand" "=f")
(mult:ANYF (match_operand:ANYF1 "register_operand" " f")
  (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fmul.\t%0,%1,%2"
   [(set_attr "type" "fmul")
(set_attr "mode" "")])
@@ -1052,7 +1052,7 @@
   [(set (match_operand:ANYF   0 "register_operand" "=f")
(div:ANYF (match_operand:ANYF 1 "register_operand" " f")
  (match_operand:ANYF 2 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT && TARGET_FDIV"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV"
   "fdiv.\t%0,%1,%2"
   [(set_attr "type" "fdiv")
(set_attr "mode" "")])
@@ -1067,7 +1067,7 @@
 (define_insn "sqrt2"
   [(set (match_operand:ANYF0 "register_operand" "=f")
(sqrt:ANYF (match_operand:ANYF 1 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT && TARGET_FDIV"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV"
 {
 return "fsqrt.\t%0,%1";
 }
@@ -1082,7 +1082,7 @@
(fma:ANYF (match_operand:ANYF 1 "register_operand" " f")
  (match_operand:ANYF 2 "register_operand" " f")
  (match_operand:ANYF 3 "register_operand" " f")))]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fmadd.\t%0,%1,%2,%3"
   [(set_attr "type" "fmadd")
(set_attr "mode" "")])
@@ -1093,7 +1093,7 @@
(fma:ANYF (match_operand:ANYF   1 "register_operand" " f")
  (match_operand:ANYF   2 "register_operand" " f")
  (neg:ANYF (match_operand:ANYF 3 "register_operand" " f"]
-  "TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT || TARGET_ZFINX"
   "fmsub.\t%0,%1,%2,%3"
   [(set_attr "type" "fmadd")
(set_attr "mode" "")])
@@ -1105,7 +1105,7 @@
(neg:ANYF (match_operand:ANYF 1 "register_operand" " f"))
(match_operand:ANYF   2 "register_operand" " f")
(neg:ANYF (match_operand:A

[PATCH 3/3] RISC-V: Imply info and regs limit for zfinx extension

[jiawei]

Co-Authored-By: sinan 
---
 gcc/config/riscv/arch-canonicalize |  1 +
 gcc/config/riscv/constraints.md|  3 ++-
 gcc/config/riscv/riscv.c   | 15 +--
 3 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/gcc/config/riscv/arch-canonicalize 
b/gcc/config/riscv/arch-canonicalize
index ea95a0693f3..3bb195416b4 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -36,6 +36,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 #
 IMPLIED_EXT = {
   "d" : ["f"],
+  "zdinx" : ["zfinx"],
 }
 
 def arch_canonicalize(arch):
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index c87d5b796a5..a99b8ce277e 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -20,8 +20,9 @@
 ;; .
 
 ;; Register constraints
+;; Zfinx support need refuse FPR and use GPR
 
-(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
+(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX 
|| TARGET_ZDINX) ? GR_REGS : NO_REGS)"
   "A floating-point register (if available).")
 
 (define_register_constraint "j" "SIBCALL_REGS"
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 6aef3d3a6cf..505435c3cee 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -4013,7 +4013,7 @@ riscv_compute_frame_info (void)
 
   /* Find out which FPRs we need to save.  This loop must iterate over
 the same space as its companion in riscv_for_each_saved_reg.  */
-  if (TARGET_HARD_FLOAT)
+  if (TARGET_HARD_FLOAT && !TARGET_ZFINX)
for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
  if (riscv_save_reg_p (regno))
frame->fmask |= 1 << (regno - FP_REG_FIRST), num_f_saved++;
@@ -4790,6 +4790,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, 
machine_mode mode)
!= call_used_or_fixed_reg_p (regno + i))
   return false;
 
+  /* Only use even registers in RV32 ZFINX */
+  if (!TARGET_64BIT && TARGET_ZDINX){
+if (GET_MODE_CLASS (mode) == MODE_FLOAT &&
+   GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode))
+  return !(regno & 1);
+  }
+
   return true;
 }
 
@@ -4981,7 +4988,7 @@ riscv_option_override (void)
 error ("%<-mdiv%> requires %<-march%> to subsume the % extension");
 
   /* Likewise floating-point division and square root.  */
-  if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
+  if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & 
MASK_FDIV) == 0)
 target_flags |= MASK_FDIV;
 
   /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
@@ -5027,6 +5034,10 @@ riscv_option_override (void)
   if (TARGET_RVE && riscv_abi != ABI_ILP32E)
 error ("rv32e requires ilp32e ABI");
 
+  // Zfinx require abi ilp32,ilp32e or lp64.
+  if (TARGET_ZFINX && riscv_abi != ABI_ILP32 && riscv_abi != ABI_LP64 && 
riscv_abi != ABI_ILP32E)
+  error ("z*inx requires ABI ilp32, ilp32e or lp64");
+
   /* We do not yet support ILP32 on RV64.  */
   if (BITS_PER_WORD != POINTER_SIZE)
 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
-- 
2.25.1

Re: Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.

[jiawei]

> -原始邮件-
> 发件人: "Jeff Law" 
> 发送时间: 2024-03-19 10:54:09 (星期二)
> 收件人: Jiawei , gcc-patches@gcc.gnu.org
> 抄送: kito.ch...@sifive.com, pal...@dabbelt.com, 
christoph.muell...@vrull.eu, wuwei2...@iscas.ac.cn, shi...@iscas.ac.cn, 
shiyul...@iscas.ac.cn, chenyix...@iscas.ac.cn
> 主题: Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.
> 
> 
> 
> On 2/27/24 1:52 AM, Jiawei wrote:
> > From: Chen Jiawei 
> > 
> > Co-Authored by: Lin Jiawei 
> > 
> > This patch add XiangShan Nanhu cpu microarchitecture,
> > Nanhu is a 6-issue, superscalar, out-of-order processor.
> > More details see: 
https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch
> > 
> > gcc/ChangeLog:
> > 
> >  * config/riscv/riscv-cores.def (RISCV_TUNE): New def.
> >  (RISCV_CORE): Ditto.
> >  * config/riscv/riscv-opts.h (enum
> >  * riscv_microarchitecture_type): New option.
> >  * config/riscv/riscv.cc: New def.
> >  * config/riscv/riscv.md: New include.
> >  * config/riscv/xiangshan.md: New file.
> > 
> > gcc/testsuite/ChangeLog:
> > 
> >  * gcc.target/riscv/mcpu-xiangshan-nanhu.c: New test.
> As was discussed last Tuesday, this should be safe, even at this late 
> stage in the gcc-14 cycle.
> 
> >   
> > +/* Costs to use when optimizing for xiangshan nanhu.  */
> > +static const struct riscv_tune_param xiangshan_nanhu_tune_info = {
> > +  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},/* fp_add */
> > +  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},/* fp_mul */
> > +  {COSTS_N_INSNS (10), COSTS_N_INSNS (20)},  /* fp_div */
> > +  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},/* int_mul */
> > +  {COSTS_N_INSNS (6), COSTS_N_INSNS (6)},/* int_div */
> > +  6, /* issue_rate */
> > +  3, /* branch_cost */
> > +  3, /* memory_cost */
> > +  3, /* fmv_cost */
> > +  true,  /* 
slow_unaligned_access */
> > +  false, /* use_divmod_expansion 
*/
> > +  RISCV_FUSE_ZEXTW | RISCV_FUSE_ZEXTH,  /* fusible_ops */
> > +  NULL,  /* vector cost 
*/
> Is your integer division really that fast?  The table above essentially 
> says that your cpu can do integer division in 6 cycles.
> 
> > +
> > +(define_insn_reservation "xiangshan_mul" 3
> > +  (and (eq_attr "tune" "xiangshan")
> > +   (eq_attr "type" "imul"))
> > +  "xs_mdu_rs")
> > +
> > +(define_insn_reservation "xiangshan_div" 21
> > +  (and (eq_attr "tune" "xiangshan")
> > +   (eq_attr "type" "idiv"))
> > +  "xs_mdu_rs")
> Whereas your pipeline description says it's 21c.
> 
> I strongly suspect you want to increase the cost of the int_div in the 
> tuning table.  And with a the higher cost you probably want to turn on 
> use_divmod_expansion.
> 
> I'll also note that your scheduler description also indicates your 
> division is fully pipelined.  Is that correct?  if not, you'll want to 
> adjust that reservation.
> 
> 
> 
> > +
> > +(define_insn_reservation "xiangshan_sfdiv" 11
> > +  (and (eq_attr "tune" "xiangshan")
> > +   (eq_attr "type" "fdiv")
> > +   (eq_attr "mode" "SF"))
> > +  "xs_fmisc_rs")
> > +
> > +(define_insn_reservation "xiangshan_sfsqrt" 17
> > +  (and (eq_attr "tune" "xiangshan")
> > +   (eq_attr "type" "fsqrt")
> > +   (eq_attr "mode" "SF"))
> > +  "xs_fmisc_rs")
> > +
> > +(define_insn_reservation "xiangshan_dfdiv" 21
> > +  (and (eq_attr "tune" "xiangshan")
> > +   (eq_attr "type" "fdiv")
> > +   (eq_attr "mode" "DF"))
> > +  "xs_fmisc_rs")
> > +
> > +(define_insn_reservation "xiangshan_dfsqrt" 37
> > +  (and (eq_attr "tune" "xiangshan")
> > +   (eq_attr "type" "fsqrt")
> > +   (eq_attr "mode" "DF"))
> > +  "xs_fmisc_rs")
> Similarly these say your fpdiv and fpsqrt are fully pipelined.  It's 
> certainly possible, but I suspect it's really just an oversight.  Given 
> these values you may also want to adjust the cost of an fp division in 
> the cost table.
> 
> 
> Finally with such high values for for the div/sqrt units, we find that 
> the DFA "blows up" causing genattrtab to run for a very long time. We'll 
> have to keep an eye on that.
> 
> And just to be clear, I think these can be done as a followup patch. I'm 
> going to push this patch as-is rather than make any adjustments -- you 
> almost certainly know the processor's capabilities better than myself or 
> anyone else on this list :-)
> 
> 
> Jeff

Thank you for the comment, some pipeline processing costs may still need to
 be confirmed, and I will correct them in next patch.

BR,
Jiawei

[PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.

[Jiawei]

From: Chen Jiawei 

Co-Authored by: Lin Jiawei 

This patch add XiangShan Nanhu cpu microarchitecture,
Nanhu is a 6-issue, superscalar, out-of-order processor.
More details see: https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch

gcc/ChangeLog:

* config/riscv/riscv-cores.def (RISCV_TUNE): New def.
(RISCV_CORE): Ditto.
* config/riscv/riscv-opts.h (enum
* riscv_microarchitecture_type): New option.
* config/riscv/riscv.cc: New def.
* config/riscv/riscv.md: New include.
* config/riscv/xiangshan.md: New file.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/mcpu-xiangshan-nanhu.c: New test.

---
 gcc/config/riscv/riscv-cores.def  |   6 +
 gcc/config/riscv/riscv-opts.h |   1 +
 gcc/config/riscv/riscv.cc |  17 ++
 gcc/config/riscv/riscv.md |   3 +-
 gcc/config/riscv/xiangshan.md | 148 ++
 .../gcc.target/riscv/mcpu-xiangshan-nanhu.c   |  34 
 6 files changed, 208 insertions(+), 1 deletion(-)
 create mode 100644 gcc/config/riscv/xiangshan.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-nanhu.c

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 57928bccdc8..ab23bb7a856 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -40,6 +40,7 @@ RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
 RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info)
 RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
 RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
+RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
 RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
 RISCV_TUNE("size", generic, optimize_size_tune_info)
 
@@ -90,4 +91,9 @@ RISCV_CORE("thead-c906",  
"rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
  "xtheadcondmov_xtheadfmemidx_xtheadmac_"
  "xtheadmemidx_xtheadmempair_xtheadsync",
  "thead-c906")
+
+RISCV_CORE("xiangshan-nanhu",  "rv64imafdc_zba_zbb_zbc_zbs_"
+ "zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_"
+ "svinval_zicbom_zicboz",
+ "xiangshan-nanhu")
 #undef RISCV_CORE
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 4edddbadc37..31f9bffa9b6 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -57,6 +57,7 @@ enum riscv_microarchitecture_type {
   sifive_7,
   sifive_p400,
   sifive_p600,
+  xiangshan,
   generic_ooo
 };
 extern enum riscv_microarchitecture_type riscv_microarchitecture;
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5e984ee2a55..aa53e25ae03 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -498,6 +498,23 @@ static const struct riscv_tune_param thead_c906_tune_info 
= {
   NULL,/* vector cost */
 };
 
+/* Costs to use when optimizing for xiangshan nanhu.  */
+static const struct riscv_tune_param xiangshan_nanhu_tune_info = {
+  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},  /* fp_add */
+  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},  /* fp_mul */
+  {COSTS_N_INSNS (10), COSTS_N_INSNS (20)},/* fp_div */
+  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},  /* int_mul */
+  {COSTS_N_INSNS (6), COSTS_N_INSNS (6)},  /* int_div */
+  6,   /* issue_rate */
+  3,   /* branch_cost */
+  3,   /* memory_cost */
+  3,   /* fmv_cost */
+  true,/* 
slow_unaligned_access */
+  false,   /* use_divmod_expansion */
+  RISCV_FUSE_ZEXTW | RISCV_FUSE_ZEXTH,  /* fusible_ops */
+  NULL,/* vector cost */
+};
+
 /* Costs to use when optimizing for a generic ooo profile.  */
 static const struct riscv_tune_param generic_ooo_tune_info = {
   {COSTS_N_INSNS (2), COSTS_N_INSNS (2)},  /* fp_add */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 1fec13092e2..8aafe19ab51 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -685,7 +685,7 @@
 ;; Microarchitectures we know how to tune for.
 ;; Keep this in sync with enum riscv_microarchitecture.
 (define_attr "tune"
-  "generic,sifive_7,sifive_p400,sifive_p600,generic_ooo"
+  "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo"
   (const (symbol_ref "((enum attr_tune) r

[PATCH v2] RISC-V: Supports RISC-V Profiles in '-march' option.

[Jiawei]

Supports RISC-V profiles[1] in -march option.

Default input set the profile is before other formal extensions.

V2: Fixes some format errors and adds code comments for parse function
Thanks for Jeff Law's review and comments.

[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (struct riscv_profiles):
  New struct.
(riscv_subset_list::parse_profiles): New function.
(riscv_subset_list::parse): New table.
* config/riscv/riscv-subset.h: New protype.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-31.c: New test.
* gcc.target/riscv/arch-32.c: New test.
* gcc.target/riscv/arch-33.c: New test.
* gcc.target/riscv/arch-34.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  | 83 +++-
 gcc/config/riscv/riscv-subset.h  |  2 +
 gcc/testsuite/gcc.target/riscv/arch-31.c |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-32.c |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-33.c |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-34.c |  7 ++
 6 files changed, 106 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-31.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-33.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-34.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 4d5a2f874a2..8b674a4a280 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -195,6 +195,12 @@ struct riscv_ext_version
   int minor_version;
 };
 
+struct riscv_profiles
+{
+  const char *profile_name;
+  const char *profile_string;
+};
+
 /* All standard extensions defined in all supported ISA spec.  */
 static const struct riscv_ext_version riscv_ext_version_table[] =
 {
@@ -379,6 +385,42 @@ static const struct riscv_ext_version riscv_combine_info[] 
=
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
 
+/* This table records the mapping form RISC-V Profiles into march string.  */
+static const riscv_profiles riscv_profiles_table[] =
+{
+  /* RVI20U only contains the base extesnion 'i' as mandatory extension.  */
+  {"RVI20U64", "rv64i"},
+  {"RVI20U32", "rv32i"},
+
+  /* RVA20U contains the 'i,m,a,f,d,c,zicsr' as mandatory extensions.
+ Currently we don't have zicntr,ziccif,ziccrse,ziccamoa,
+ zicclsm,za128rs yet.   */
+  {"RVA20U64", "rv64imafdc_zicsr"},
+
+  /* RVA20S64 mandatory include all the extensions in RVA20U64 and
+ additonal 'zifencei' as mandatory extensions.
+ Notes that ss1p11, svbare, sv39, svade, sscptr, ssvecd, sstvala should
+ control by binutils.  */
+  {"RVA20S64", "rv64imafdc_zicsr_zifencei"},
+
+  /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,
+ zicbom,zicbop,zicboz,zfhmin,zkt' as mandatory extensions.
+ Currently we don't have zicntr,zihpm,ziccif,ziccrse,ziccamoa,
+ zicclsm,zic64b,za64rs yet.  */
+  {"RVA22U64", "rv64imafdc_zicsr_zihintpause_zba_zbb_zbs"  
\
+   "_zicbom_zicbop_zicboz_zfhmin_zkt"},
+
+  /* RVA22S64 mandatory include all the extensions in RVA22U64 and
+ additonal 'zifencei,svpbmt,svinval' as mandatory extensions.
+ Notes that ss1p12, svbare, sv39, svade, sscptr, ssvecd, sstvala,
+ scounterenw extentions should control by binutils.  */
+  {"RVA22S64","rv64imafdc_zicsr_zifencei_zihintpause"  
\
+   "_zba_zbb_zbs_zicbom_zicbop_zicboz_zfhmin_zkt_svpbmt_svinval"},
+
+  /* Terminate the list.  */
+  {NULL, NULL}
+};
+
 static const riscv_cpu_info riscv_cpu_tables[] =
 {
 #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -958,6 +1000,42 @@ riscv_subset_list::parsing_subset_version (const char 
*ext,
   return p;
 }
 
+/* Parsing RISC-V Profiles in -march string.
+   Return string with mandatory extensions of Profiles.  */
+const char *
+riscv_subset_list::parse_profiles (const char * p){
+  /* Checking if input string contains a Profiles.
+ There are two cases use Proifles in -march option
+
+   1. Only use Proifles as -march input
+   2. Mixed Profiles with other extensions
+
+ use '+' to split Profiles and other extension.  */
+  for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i) {
+const char* match = strstr(p, riscv_profiles_table[i].profile_name);
+const char* plus_ext = strchr(p, '+');
+/* Find profile at the begin.  */
+if (match != NULL && match == p) {
+  /* If there's no '+' sign, return the profile_string directly.  */
+  if(!plus_ext)
+   return riscv_profiles_table[i].profile_string;
+  /* If there's a '+' sign, need to add profiles with other ext.  */
+  else {
+   size_t arch_len = strlen(riscv_profiles_table[i].profile_string)+
+ strlen(plus_ext);
+   /* Reset the input string with Profiles mandatory extensions,
+  end with '_' t

Re: Re: [RFC] RISC-V: Support RISC-V Profiles in -march option.

[jiawei]

> -原始邮件-
> 发件人: "Jeff Law" 
> 发送时间: 2023-12-12 00:15:44 (星期二)
> 收件人: Jiawei , gcc-patches@gcc.gnu.org
> 抄送: kito.ch...@sifive.com, pal...@dabbelt.com, christoph.muell...@vrull.eu
> 主题: Re: [RFC] RISC-V: Support RISC-V Profiles in -march option.
> 
> 
> 
> On 11/20/23 12:14, Jiawei wrote:
> > Supports RISC-V profiles[1] in -march option.
> > 
> > Default input set the profile is before other formal extensions.
> > 
> > [1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
> > 
> > gcc/ChangeLog:
> > 
> >  * common/config/riscv/riscv-common.cc (struct 
riscv_profiles):
> >New struct.
> >  (riscv_subset_list::parse_profiles): New function.
> >  (riscv_subset_list::parse): New table.
> >  * config/riscv/riscv-subset.h: New protype.
> > 
> > gcc/testsuite/ChangeLog:
> > 
> >  * gcc.target/riscv/arch-29.c: New test.
> >  * gcc.target/riscv/arch-30.c: New test.
> >  * gcc.target/riscv/arch-31.c: New test.
> > 
> > ---
> >   gcc/common/config/riscv/riscv-common.cc  | 58 
+++-
> >   gcc/config/riscv/riscv-subset.h  |  2 +
> >   gcc/testsuite/gcc.target/riscv/arch-29.c |  5 ++
> >   gcc/testsuite/gcc.target/riscv/arch-30.c |  5 ++
> >   gcc/testsuite/gcc.target/riscv/arch-31.c |  5 ++
> >   6 files changed, 81 insertions(+), 1 deletion(-)
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/arch-29.c
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/arch-30.c
> >   create mode 100644 gcc/testsuite/gcc.target/riscv/arch-31.c
> > 
> > diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
> > index 5111626157b..30617e619b1 100644
> > --- a/gcc/common/config/riscv/riscv-common.cc
> > +++ b/gcc/common/config/riscv/riscv-common.cc
> > @@ -165,6 +165,12 @@ struct riscv_ext_version
> > int minor_version;
> >   };
> >   
> > +struct riscv_profiles
> > +{
> > +  const char * profile_name;
> > +  const char * profile_string;
> > +};
> Just a formatting nit, no space between the '*' and the field name.

Fixed.

> 
> > @@ -348,6 +354,28 @@ static const struct riscv_ext_version 
riscv_combine_info[] =
> > {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
> >   };
> >   
> > +static const riscv_profiles riscv_profiles_table[] =
> > +{
> > +  {"RVI20U64", "rv64i"},
> > +  {"RVI20U32", "rv32i"},
> > +  /*Currently we don't have zicntr,ziccif,ziccrse,ziccamoa,
> > +zicclsm,za128rs yet.  */
> It is actually useful to note the extensions not included?  I don't 
> think the profiles are supposed to change once ratified.
> 
> > +  {"RVA22U64", "rv64imafdc_zicsr_zihintpause_zba_zbb_zbs_"   
\
> Note the trailing "_", was that intentional?  None of the other entries 
> have a trailing "_".

Here is a line break due to too long length of arch string,
Adjusted the format in the new patch.

> 
> 
> > @@ -927,6 +955,31 @@ riscv_subset_list::parsing_subset_version (const 
char *ext,
> > return p;
> >   }
> >   
> > +const char *
> > +riscv_subset_list::parse_profiles (const char * p){
> > +  for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i) 
{
> > +const char* match = strstr(p, 
riscv_profiles_table[i].profile_name);
> > +const char* plus_ext = strchr(p, '+');
> > +/* Find profile at the begin.  */
> > +if (match != NULL && match == p) {
> > +  /* If there's no '+' sign, return the profile_string directly. 
 */
> > +  if(!plus_ext)
> > + return riscv_profiles_table[i].profile_string;
> > +  /* If there's a '+' sign, concatenate profiles with other ext. 
 */
> > +  else {
> > + size_t arch_len = 
strlen(riscv_profiles_table[i].profile_string) +
> > + strlen(plus_ext);
> > + static char* result = new char[arch_len + 2];
> > + strcpy(result, riscv_profiles_table[i].profile_string);
> > + strcat(result, "_");
> > + strcat(result, plus_ext + 1); /* skip the '+'.  */
> > + return result;
> > +  }
> > +}
> > +  }
> > +  return p;
> > +}
> This needs a function comment.

Thanks, added the parse function descrption and some deal logical.

> 
> The open curly should always be on a line by itself which is going to 
> require reindenting all this code.  Comments go on separate lines rather 
> than appending them to an existing line.
> 
> 
> I think the consensus in the Tuesday patchwork meeting was that while 
> there are concerns about profiles, those concerns should prevent this 
> patch from going forward.  So if you could fix the formatting problem as 
> well as the trailing "_" issue noted above and repost, it would be 
> appreciated.
> 
> Thanks,
> 
> Jeff

Thanks for your review and comments, I had update them in the new patch:

https://gcc.gnu.org/pipermail/gcc-patches/2023-December/640324.html

BR,
Jiawei

[RFC] RISC-V: Support RISC-V Profiles in -march option.

[Jiawei]

Supports RISC-V profiles[1] in -march option.

Default input set the profile is before other formal extensions.

[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (struct riscv_profiles):
  New struct.
(riscv_subset_list::parse_profiles): New function.
(riscv_subset_list::parse): New table.
* config/riscv/riscv-subset.h: New protype.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-29.c: New test.
* gcc.target/riscv/arch-30.c: New test.
* gcc.target/riscv/arch-31.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  | 58 +++-
 gcc/config/riscv/riscv-subset.h  |  2 +
 gcc/testsuite/gcc.target/riscv/arch-29.c |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-30.c |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-31.c |  5 ++
 6 files changed, 81 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-29.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-30.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-31.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 5111626157b..30617e619b1 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -165,6 +165,12 @@ struct riscv_ext_version
   int minor_version;
 };
 
+struct riscv_profiles
+{
+  const char * profile_name;
+  const char * profile_string;
+};
+
 /* All standard extensions defined in all supported ISA spec.  */
 static const struct riscv_ext_version riscv_ext_version_table[] =
 {
@@ -348,6 +354,28 @@ static const struct riscv_ext_version riscv_combine_info[] 
=
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
 
+static const riscv_profiles riscv_profiles_table[] =
+{
+  {"RVI20U64", "rv64i"},
+  {"RVI20U32", "rv32i"},
+  /*Currently we don't have zicntr,ziccif,ziccrse,ziccamoa,
+zicclsm,za128rs yet.  */
+  {"RVA20U64", "rv64imafdc_zicsr"},
+  /*Ss1p11, svbare, sv39, svade, sscptr, ssvecd, sstvala should
+control by binutils.  */
+  {"RVA20S64", "rv64imafdc_zicsr_zifencei"},
+  /*Currently we don't have zicntr,zihpm,ziccif,ziccrse,ziccamoa,
+zicclsm,zic64b,za64rs yet.  */
+  {"RVA22U64", "rv64imafdc_zicsr_zihintpause_zba_zbb_zbs_" 
\
+   "zicbom_zicbop_zicboz_zfhmin_zkt"},
+  /*Ss1p12, svbare, sv39, svade, sscptr, ssvecd, sstvala,
+scounterenw should control by binutils.  */
+  {"RVA22S64","rv64imafdc_zicsr_zifencei_zihintpause"  
\
+   "_zba_zbb_zbs_zicbom_zicbop_zicboz_zfhmin_zkt_svpbmt_svinval"},
+  /* Terminate the list.  */
+  {NULL, NULL}
+};
+
 static const riscv_cpu_info riscv_cpu_tables[] =
 {
 #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -927,6 +955,31 @@ riscv_subset_list::parsing_subset_version (const char *ext,
   return p;
 }
 
+const char *
+riscv_subset_list::parse_profiles (const char * p){
+  for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i) {
+const char* match = strstr(p, riscv_profiles_table[i].profile_name);
+const char* plus_ext = strchr(p, '+');
+/* Find profile at the begin.  */
+if (match != NULL && match == p) {
+  /* If there's no '+' sign, return the profile_string directly.  */
+  if(!plus_ext)
+   return riscv_profiles_table[i].profile_string;
+  /* If there's a '+' sign, concatenate profiles with other ext.  */
+  else {
+   size_t arch_len = strlen(riscv_profiles_table[i].profile_string) +
+   strlen(plus_ext);
+   static char* result = new char[arch_len + 2];
+   strcpy(result, riscv_profiles_table[i].profile_string);
+   strcat(result, "_");
+   strcat(result, plus_ext + 1); /* skip the '+'.  */
+   return result;
+  }
+}
+  }
+  return p;
+}
+
 /* Parsing function for standard extensions.
 
Return Value:
@@ -1430,7 +1483,10 @@ riscv_subset_list::parse (const char *arch, location_t 
loc)
 
   riscv_subset_list *subset_list = new riscv_subset_list (arch, loc);
   riscv_subset_t *itr;
+
   const char *p = arch;
+  p = subset_list->parse_profiles(p);
+
   if (startswith (p, "rv32"))
 {
   subset_list->m_xlen = 32;
@@ -1443,7 +1499,7 @@ riscv_subset_list::parse (const char *arch, location_t 
loc)
 }
   else
 {
-  error_at (loc, "%<-march=%s%>: ISA string must begin with rv32 or rv64",
+  error_at (loc, "%<-march=%s%>: ISA string must begin with rv32, rv64 or 
a profile",
arch);
   goto fail;
 }
diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
index d2a4bd20530..c8b778330b4 100644
--- a/gcc/config/riscv/riscv-subset.h
+++ b/gcc/config/riscv/riscv-subset.h
@@ -76,6 +76,8 @@ private:
   const char *parse_single_multiletter_ext (const char *, const char *,
const char *);
 
+  const char *parse_profiles (const char*);
+
   void handle_implied_ext (co

[PATCH] Fix Wstringop-overflow-47.c warning in RISC-V target.

[Jiawei]

Update warning test info for RISC-V target, compared on godbolt:

https://godbolt.org/z/Mexd3dfcc

gcc/testsuite/ChangeLog:

* gcc.dg/Wstringop-overflow-47.c: Remove xfail target.

---
 gcc/testsuite/gcc.dg/Wstringop-overflow-47.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/Wstringop-overflow-47.c 
b/gcc/testsuite/gcc.dg/Wstringop-overflow-47.c
index 883921b097f..9fb78e55046 100644
--- a/gcc/testsuite/gcc.dg/Wstringop-overflow-47.c
+++ b/gcc/testsuite/gcc.dg/Wstringop-overflow-47.c
@@ -65,15 +65,15 @@ void warn_i16_64 (int16_t i)
like x86_64 it's a series of BIT_FIELD_REFs.  The overflow by
the former is detected but the latter is not yet.  */
 
- extern char warn_a64[64];   // { dg-message "at offset (1|128) into 
destination object 'warn_a64' of size (63|64)" "pr97027 note" { xfail { ! { 
aarch64-*-* riscv*-*-* } } } }
+ extern char warn_a64[64];   // { dg-message "at offset (1|128) into 
destination object 'warn_a64' of size (63|64)" "pr97027 note" { xfail { ! { 
aarch64-*-* } } } }
 
   void *p = warn_a64 + 1;
   I16_64 *q = (I16_64*)p;
-  *q = (I16_64){ i }; // { dg-warning "writing (1 byte|64 bytes) into 
a region of size (0|63)" "pr97027" { xfail { ! { aarch64-*-* riscv*-*-* } } } }
+  *q = (I16_64){ i }; // { dg-warning "writing (1 byte|64 bytes) into 
a region of size (0|63)" "pr97027" { xfail { ! { aarch64-*-* } } } }
 
   char a64[64];
   p = a64 + 1;
   q = (I16_64*)p;
-  *q = (I16_64){ i }; // { dg-warning "writing (1 byte|64 bytes) into 
a region of size (0|63)" "pr97027" { xfail { ! { aarch64-*-* riscv*-*-* } } } }
+  *q = (I16_64){ i }; // { dg-warning "writing (1 byte|64 bytes) into 
a region of size (0|63)" "pr97027" { xfail { ! { aarch64-*-* } } } }
   sink (p);
 }
-- 
2.25.1

Re: [PATCH] Fix Wstringop-overflow-47.c warning in RISC-V target.

[Jiawei]

在 2024/07/16 8:28, Jeff Law 写道:
IIRC these fails are dependent upon whether or not the statements turn 
into vector stores or not.


So to remove the xfail don't you have to know if vector is 
enabled/disabled? 


I am not sure, I tried to enable with RVV, but it still pass the test:

https://godbolt.org/z/bvWfffTe5

Any suggestions?

[PATCH] Update SLP reductions process.

[Jiawei]

This patch improves SLP reduction handling by ensuring proper processing 
even for a single reduction statement.Vectorization instances are now built 
only when there are multiple scalar statements to combine into an SLP
reduction.

An example see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110632,
this patch fix this problem,handling SLP reduction as expected.

gcc/ChangeLog:

* tree-vect-slp.cc (vect_analyze_slp): Improved handling of SLP 
reductions
for single reduction statements.

---
 gcc/tree-vect-slp.cc | 49 +---
 1 file changed, 23 insertions(+), 26 deletions(-)

diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index 55ae496cbb2..b6dfd9fd32f 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -4054,34 +4054,31 @@ vect_analyze_slp (vec_info *vinfo, unsigned 
max_tree_size)
}
}
  /* Save for re-processing on failure.  */
- vec saved_stmts = scalar_stmts.copy ();
- vec roots = vNULL;
- vec remain = vNULL;
- if (scalar_stmts.length () <= 1
- || !vect_build_slp_instance (loop_vinfo,
-  slp_inst_kind_reduc_group,
-  scalar_stmts, roots, remain,
-  max_tree_size, &limit, bst_map,
-  NULL))
-   {
- if (scalar_stmts.length () <= 1)
-   scalar_stmts.release ();
- /* Do SLP discovery for single-lane reductions.  */
- for (auto stmt_info : saved_stmts)
-   {
- vec stmts;
- vec roots = vNULL;
- vec remain = vNULL;
- stmts.create (1);
- stmts.quick_push (vect_stmt_to_vectorize (stmt_info));
- vect_build_slp_instance (vinfo,
-  slp_inst_kind_reduc_group,
-  stmts, roots, remain,
-  max_tree_size, &limit,
-  bst_map, NULL);
+ if (loop_vinfo->reductions.length() > 0) {
+   vec scalar_stmts;
+   scalar_stmts.create(loop_vinfo->reductions.length());
+
+   for (auto next_info : loop_vinfo->reductions) {
+ if (STMT_VINFO_DEF_TYPE(next_info) == vect_reduction_def) {
+   gassign *g = dyn_cast(STMT_VINFO_STMT(next_info));
+   if (!g || !lane_reducing_op_p(gimple_assign_rhs_code(g))) {
+ scalar_stmts.quick_push(next_info);
}
- saved_stmts.release ();
+ }
}
+
+ if (scalar_stmts.length() > 1) {
+   vec roots = vNULL;
+   vec remain = vNULL;
+   if (!vect_build_slp_instance(loop_vinfo, slp_inst_kind_reduc_group, 
scalar_stmts, roots, remain, max_tree_size, &limit, bst_map, NULL)) {
+   scalar_stmts.release();
+   }
+   }
+ else {
+   scalar_stmts.release();
+ }
+ }
+
}
 }
 
-- 
2.25.1

Re: [PATCH] Update SLP reductions process.

[Jiawei]

Thanks for your quick reply,sorry for the missing of information.

I meet this problem in risc-v test:

gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-8.c

I found that this SLP change will add additional instrutions in the 
test, please see this link:


https://godbolt.org/z/5Tfqs9zqj


在 2024/07/18 15:05, Richard Biener 写道:

On Thu, 18 Jul 2024, Jiawei wrote:


This patch improves SLP reduction handling by ensuring proper processing
even for a single reduction statement.Vectorization instances are now built
only when there are multiple scalar statements to combine into an SLP
reduction.

An example seehttps://gcc.gnu.org/bugzilla/show_bug.cgi?id=110632,
this patch fix this problem,handling SLP reduction as expected.

That PR is lacking any information so I'm not sure what kind of problem
you are fixing.

But the patch is clearly wrong - we want to use SLP even for single
reduction statements, the non-SLP path is going away.


I located the problem from the following modifications and made some 
attempts.


But it seems wrong, do you have any suggestions?

- if (scalar_stmts.length () > 1)
+ /* Save for re-processing on failure.  */
+ vec saved_stmts = scalar_stmts.copy ();
+ vec roots = vNULL;
+ vec remain = vNULL;
+ if (scalar_stmts.length () <= 1
+ || !vect_build_slp_instance (loop_vinfo,
+ slp_inst_kind_reduc_group,
+  scalar_stmts, roots, remain,
+  max_tree_size, &limit, bst_map,
+  NULL))
    {
- vec roots = vNULL;
- vec remain = vNULL;
- vect_build_slp_instance (loop_vinfo, 
slp_inst_kind_reduc_group,

-  scalar_stmts, roots, remain,

-  max_tree_size, &limit, bst_map, 
NULL);


BR,

Jiawei



Richard.


gcc/ChangeLog:

* tree-vect-slp.cc (vect_analyze_slp): Improved handling of SLP 
reductions
for single reduction statements.

---
  gcc/tree-vect-slp.cc | 49 +---
  1 file changed, 23 insertions(+), 26 deletions(-)

diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index 55ae496cbb2..b6dfd9fd32f 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -4054,34 +4054,31 @@ vect_analyze_slp (vec_info *vinfo, unsigned 
max_tree_size)
}
}
  /* Save for re-processing on failure.  */
- vec saved_stmts = scalar_stmts.copy ();
- vec roots = vNULL;
- vec remain = vNULL;
- if (scalar_stmts.length () <= 1
- || !vect_build_slp_instance (loop_vinfo,
-  slp_inst_kind_reduc_group,
-  scalar_stmts, roots, remain,
-  max_tree_size, &limit, bst_map,
-  NULL))
-   {
- if (scalar_stmts.length () <= 1)
-   scalar_stmts.release ();
- /* Do SLP discovery for single-lane reductions.  */
- for (auto stmt_info : saved_stmts)
-   {
- vec stmts;
- vec roots = vNULL;
- vec remain = vNULL;
- stmts.create (1);
- stmts.quick_push (vect_stmt_to_vectorize (stmt_info));
- vect_build_slp_instance (vinfo,
-  slp_inst_kind_reduc_group,
-  stmts, roots, remain,
-  max_tree_size, &limit,
-  bst_map, NULL);
+ if (loop_vinfo->reductions.length() > 0) {
+   vec scalar_stmts;
+   scalar_stmts.create(loop_vinfo->reductions.length());
+
+   for (auto next_info : loop_vinfo->reductions) {
+ if (STMT_VINFO_DEF_TYPE(next_info) == vect_reduction_def) {
+   gassign *g = dyn_cast(STMT_VINFO_STMT(next_info));
+   if (!g || !lane_reducing_op_p(gimple_assign_rhs_code(g))) {
+ scalar_stmts.quick_push(next_info);
}
- saved_stmts.release ();
+ }
}
+
+ if (scalar_stmts.length() > 1) {
+   vec roots = vNULL;
+   vec remain = vNULL;
+   if (!vect_build_slp_instance(loop_vinfo, slp_inst_kind_reduc_group, 
scalar_stmts, roots, remain, max_tree_size, &limit, bst_map, NULL)) {
+   scalar_stmts.release();
+   }
+   }
+ else {
+   scalar_stmts.release();
+ }
+ }
+
}
  }
  

[PATCH] tree-ssa-pre.c/1071140(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE if no equal.

[Jiawei]

An ICE bug reported in
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1071140.
https://godbolt.org/z/WE9aGYvoo

Return NULL_TREE when TREE_CODE(op) not equal to SSA_NAME.

gcc/ChangeLog:

* tree-ssa-pre.cc (find_or_generate_expression): Remove assert.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr1071140.c: New test.

---
 .../gcc.target/riscv/rvv/vsetvl/pr1071140.c   | 52 +++
 gcc/tree-ssa-pre.cc   |  4 +-
 2 files changed, 55 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
new file mode 100644
index 000..4f0815e099f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w" 
} */
+
+#include 
+
+static inline __attribute__(()) int vaddq_f32();
+static inline __attribute__(()) int vload_tillz_f32(int nlane) {
+  vint32m1_t __trans_tmp_9;
+  {
+int __trans_tmp_0 = nlane;
+{
+  vint64m1_t __trans_tmp_1;
+  vint64m1_t __trans_tmp_2;
+  vint64m1_t __trans_tmp_3;
+  vint64m1_t __trans_tmp_4;
+  if (__trans_tmp_0 == 1) {
+{
+  __trans_tmp_3 =
+  __riscv_vslideup_vx_i64m1(__trans_tmp_1, __trans_tmp_2, 1, 2);
+}
+__trans_tmp_4 = __trans_tmp_2;
+  }
+  __trans_tmp_4 = __trans_tmp_3;
+  __trans_tmp_9 = __riscv_vreinterpret_v_i64m1_i32m1(__trans_tmp_3);
+}
+  }
+  return vaddq_f32(__trans_tmp_9); /* { dg-error {RVV type 'vint32m1_t' cannot 
be passed to an unprototyped function} } */
+}
+
+char CFLOAT_add_args[3];
+const int *CFLOAT_add_steps;
+const int CFLOAT_steps;
+
+__attribute__(()) void CFLOAT_add() {
+  char *b_src0 = &CFLOAT_add_args[0], *b_src1 = &CFLOAT_add_args[1],
+   *b_dst = &CFLOAT_add_args[2];
+  const float *src1 = (float *)b_src1;
+  float *dst = (float *)b_dst;
+  const int ssrc1 = CFLOAT_add_steps[1] / sizeof(float);
+  const int sdst = CFLOAT_add_steps[2] / sizeof(float);
+  const int hstep = 4 / 2;
+  vfloat32m1x2_t a;
+  int len = 255;
+  for (; len > 0; len -= hstep, src1 += 4, dst += 4) {
+int b = vload_tillz_f32(len);
+int r = vaddq_f32(a.__val[0], b); /* { dg-error {RVV type 
'__rvv_float32m1_t' cannot be passed to an unprototyped function} } */
+  }
+  for (; len > 0; --len, b_src0 += CFLOAT_steps,
+  b_src1 += CFLOAT_add_steps[1], b_dst += CFLOAT_add_steps[2])
+;
+}
+
diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc
index 75217f5cde1..e3d9c47f96b 100644
--- a/gcc/tree-ssa-pre.cc
+++ b/gcc/tree-ssa-pre.cc
@@ -2777,7 +2777,9 @@ find_or_generate_expression (basic_block block, tree op, 
gimple_seq *stmts)
   if (is_gimple_min_invariant (op))
 return op;
 
-  gcc_assert (TREE_CODE (op) == SSA_NAME);
+  if (TREE_CODE (op) != SSA_NAME)
+return NULL_TREE;
+
   vn_ssa_aux_t info = VN_INFO (op);
   unsigned int lookfor = info->value_id;
   if (value_id_constant_p (lookfor))
-- 
2.25.1

Re: [PATCH] tree-ssa-pre.c/1071140(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE if no equal.

[Jiawei]

On 2024/5/24 20:33, Richard Biener wrote:

On Fri, May 24, 2024 at 1:49 PM Jiawei  wrote:

An ICE bug reported in
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1071140.
https://godbolt.org/z/WE9aGYvoo

Return NULL_TREE when TREE_CODE(op) not equal to SSA_NAME.

The assert is on purpose.  Can you open a GCC bug for this please?  It looks
like we have unfolded POLY_INT_CST [16, 16] /[ex] 16 here.

It seems that

 /* We can't always put a size in units of the element alignment
here as the element alignment may be not visible.  See
PR43783.  Simply drop the element size for constant
sizes.  */
 if (TREE_CODE (genop3) == INTEGER_CST
 && TREE_CODE (TYPE_SIZE_UNIT (elmt_type)) == INTEGER_CST
 && wi::eq_p (wi::to_offset (TYPE_SIZE_UNIT (elmt_type)),
  (wi::to_offset (genop3)
   * vn_ref_op_align_unit (currop
   genop3 = NULL_TREE;

fails to match the POLY_INT case - the unit alignment is 16 here.  One
possibility would be to match the EXACT_DIV_EXPR case and the
INTEGER_CST divisor to vn_ref_op_align_unit and the other half
separately.  But maybe this can be written in a "proper" way?

The EXACT_DIV_EXPR is built by copy_reference_ops_from_ref,
I suppose SVE could be similarly affected.

Richard.


Thanks for your quick reply, reported it on bugzilla——

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115214


BR，

Jiawei


gcc/ChangeLog:

 * tree-ssa-pre.cc (find_or_generate_expression): Remove assert.

gcc/testsuite/ChangeLog:

 * gcc.target/riscv/rvv/vsetvl/pr1071140.c: New test.

---
  .../gcc.target/riscv/rvv/vsetvl/pr1071140.c   | 52 +++
  gcc/tree-ssa-pre.cc   |  4 +-
  2 files changed, 55 insertions(+), 1 deletion(-)
  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
new file mode 100644
index 000..4f0815e099f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr1071140.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w" 
} */
+
+#include 
+
+static inline __attribute__(()) int vaddq_f32();
+static inline __attribute__(()) int vload_tillz_f32(int nlane) {
+  vint32m1_t __trans_tmp_9;
+  {
+int __trans_tmp_0 = nlane;
+{
+  vint64m1_t __trans_tmp_1;
+  vint64m1_t __trans_tmp_2;
+  vint64m1_t __trans_tmp_3;
+  vint64m1_t __trans_tmp_4;
+  if (__trans_tmp_0 == 1) {
+{
+  __trans_tmp_3 =
+  __riscv_vslideup_vx_i64m1(__trans_tmp_1, __trans_tmp_2, 1, 2);
+}
+__trans_tmp_4 = __trans_tmp_2;
+  }
+  __trans_tmp_4 = __trans_tmp_3;
+  __trans_tmp_9 = __riscv_vreinterpret_v_i64m1_i32m1(__trans_tmp_3);
+}
+  }
+  return vaddq_f32(__trans_tmp_9); /* { dg-error {RVV type 'vint32m1_t' cannot 
be passed to an unprototyped function} } */
+}
+
+char CFLOAT_add_args[3];
+const int *CFLOAT_add_steps;
+const int CFLOAT_steps;
+
+__attribute__(()) void CFLOAT_add() {
+  char *b_src0 = &CFLOAT_add_args[0], *b_src1 = &CFLOAT_add_args[1],
+   *b_dst = &CFLOAT_add_args[2];
+  const float *src1 = (float *)b_src1;
+  float *dst = (float *)b_dst;
+  const int ssrc1 = CFLOAT_add_steps[1] / sizeof(float);
+  const int sdst = CFLOAT_add_steps[2] / sizeof(float);
+  const int hstep = 4 / 2;
+  vfloat32m1x2_t a;
+  int len = 255;
+  for (; len > 0; len -= hstep, src1 += 4, dst += 4) {
+int b = vload_tillz_f32(len);
+int r = vaddq_f32(a.__val[0], b); /* { dg-error {RVV type 
'__rvv_float32m1_t' cannot be passed to an unprototyped function} } */
+  }
+  for (; len > 0; --len, b_src0 += CFLOAT_steps,
+  b_src1 += CFLOAT_add_steps[1], b_dst += CFLOAT_add_steps[2])
+;
+}
+
diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc
index 75217f5cde1..e3d9c47f96b 100644
--- a/gcc/tree-ssa-pre.cc
+++ b/gcc/tree-ssa-pre.cc
@@ -2777,7 +2777,9 @@ find_or_generate_expression (basic_block block, tree op, 
gimple_seq *stmts)
if (is_gimple_min_invariant (op))
  return op;

-  gcc_assert (TREE_CODE (op) == SSA_NAME);
+  if (TREE_CODE (op) != SSA_NAME)
+return NULL_TREE;
+
vn_ssa_aux_t info = VN_INFO (op);
unsigned int lookfor = info->value_id;
if (value_id_constant_p (lookfor))
--
2.25.1

[PATCH v2] tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE when deal special cases.

[Jiawei]

Return NULL_TREE when match the POLY_INT case.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652641.html

gcc/ChangeLog:

* tree-ssa-pre.cc (create_component_ref_by_pieces_1): New
* conditions.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr115214.c: New test.

---
 .../gcc.target/riscv/rvv/vsetvl/pr115214.c| 51 +++
 gcc/tree-ssa-pre.cc   | 13 +++--
 2 files changed, 61 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
new file mode 100644
index 000..9d19641196f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w" 
} */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+
+#include 
+
+static inline __attribute__(()) int vaddq_f32();
+static inline __attribute__(()) int vload_tillz_f32(int nlane) {
+  vint32m1_t __trans_tmp_9;
+  {
+int __trans_tmp_0 = nlane;
+{
+  vint64m1_t __trans_tmp_1;
+  vint64m1_t __trans_tmp_2;
+  vint64m1_t __trans_tmp_3;
+  vint64m1_t __trans_tmp_4;
+  if (__trans_tmp_0 == 1) {
+{
+  __trans_tmp_3 =
+  __riscv_vslideup_vx_i64m1(__trans_tmp_1, __trans_tmp_2, 1, 2);
+}
+__trans_tmp_4 = __trans_tmp_2;
+  }
+  __trans_tmp_4 = __trans_tmp_3;
+  __trans_tmp_9 = __riscv_vreinterpret_v_i64m1_i32m1(__trans_tmp_3);
+}
+  }
+  return vaddq_f32(__trans_tmp_9); /* { dg-error {RVV type 'vint32m1_t' cannot 
be passed to an unprototyped function} } */
+}
+
+char CFLOAT_add_args[3];
+const int *CFLOAT_add_steps;
+const int CFLOAT_steps;
+
+__attribute__(()) void CFLOAT_add() {
+  char *b_src0 = &CFLOAT_add_args[0], *b_src1 = &CFLOAT_add_args[1],
+   *b_dst = &CFLOAT_add_args[2];
+  const float *src1 = (float *)b_src1;
+  float *dst = (float *)b_dst;
+  const int ssrc1 = CFLOAT_add_steps[1] / sizeof(float);
+  const int sdst = CFLOAT_add_steps[2] / sizeof(float);
+  const int hstep = 4 / 2;
+  vfloat32m1x2_t a;
+  int len = 255;
+  for (; len > 0; len -= hstep, src1 += 4, dst += 4) {
+int b = vload_tillz_f32(len);
+int r = vaddq_f32(a.__val[0], b); /* { dg-error {RVV type 
'__rvv_float32m1_t' cannot be passed to an unprototyped function} } */
+  }
+  for (; len > 0; --len, b_src0 += CFLOAT_steps,
+  b_src1 += CFLOAT_add_steps[1], b_dst += CFLOAT_add_steps[2])
+;
+}
\ No newline at end of file
diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc
index 75217f5cde1..b185f858c7f 100644
--- a/gcc/tree-ssa-pre.cc
+++ b/gcc/tree-ssa-pre.cc
@@ -2685,11 +2685,18 @@ create_component_ref_by_pieces_1 (basic_block block, 
vn_reference_t ref,
   here as the element alignment may be not visible.  See
   PR43783.  Simply drop the element size for constant
   sizes.  */
-   if (TREE_CODE (genop3) == INTEGER_CST
+   if ((TREE_CODE (genop3) == INTEGER_CST
&& TREE_CODE (TYPE_SIZE_UNIT (elmt_type)) == INTEGER_CST
&& wi::eq_p (wi::to_offset (TYPE_SIZE_UNIT (elmt_type)),
-(wi::to_offset (genop3)
- * vn_ref_op_align_unit (currop
+ (wi::to_offset (genop3) * vn_ref_op_align_unit (currop
+   || (TREE_CODE (genop3) == POLY_INT_CST
+ && TREE_CODE (TYPE_SIZE_UNIT (elmt_type)) == POLY_INT_CST
+ && wi::eq_p (wi::to_offset (TYPE_SIZE_UNIT (elmt_type)),
+   (wi::to_offset (genop3) * vn_ref_op_align_unit (currop
+   || (TREE_CODE (genop3) == EXACT_DIV_EXPR
+ && TREE_CODE (TREE_OPERAND (genop3, 1)) == INTEGER_CST
+ && wi::eq_p (wi::to_offset (TREE_OPERAND (genop3, 1)),
+   vn_ref_op_align_unit (currop
  genop3 = NULL_TREE;
else
  {
-- 
2.25.1

[PATCH v3] tree-ssa-pre.c/115214(ICE in find_or_generate_expression, at tree-ssa-pre.c:2780): Return NULL_TREE when deal special cases.

[Jiawei]

Return NULL_TREE when genop3 equal EXACT_DIV_EXPR.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652641.html

version log v3: remove additional POLY_INT_CST check.
https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652795.html

gcc/ChangeLog:

* tree-ssa-pre.cc (create_component_ref_by_pieces_1): New conditions.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr115214.c: New test.

---
 .../gcc.target/riscv/rvv/vsetvl/pr115214.c| 52 +++
 gcc/tree-ssa-pre.cc   | 10 ++--
 2 files changed, 59 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
new file mode 100644
index 000..fce2e9da766
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr115214.c
@@ -0,0 +1,52 @@
+/* { dg-do compile } */
+/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gcv -mabi=lp64d -O3 -w" 
} */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+
+#include 
+
+static inline __attribute__(()) int vaddq_f32();
+static inline __attribute__(()) int vload_tillz_f32(int nlane) {
+  vint32m1_t __trans_tmp_9;
+  {
+int __trans_tmp_0 = nlane;
+{
+  vint64m1_t __trans_tmp_1;
+  vint64m1_t __trans_tmp_2;
+  vint64m1_t __trans_tmp_3;
+  vint64m1_t __trans_tmp_4;
+  if (__trans_tmp_0 == 1) {
+{
+  __trans_tmp_3 =
+  __riscv_vslideup_vx_i64m1(__trans_tmp_1, __trans_tmp_2, 1, 2);
+}
+__trans_tmp_4 = __trans_tmp_2;
+  }
+  __trans_tmp_4 = __trans_tmp_3;
+  __trans_tmp_9 = __riscv_vreinterpret_v_i64m1_i32m1(__trans_tmp_3);
+}
+  }
+  return vaddq_f32(__trans_tmp_9); /* { dg-error {RVV type 'vint32m1_t' cannot 
be passed to an unprototyped function} } */
+}
+
+char CFLOAT_add_args[3];
+const int *CFLOAT_add_steps;
+const int CFLOAT_steps;
+
+__attribute__(()) void CFLOAT_add() {
+  char *b_src0 = &CFLOAT_add_args[0], *b_src1 = &CFLOAT_add_args[1],
+   *b_dst = &CFLOAT_add_args[2];
+  const float *src1 = (float *)b_src1;
+  float *dst = (float *)b_dst;
+  const int ssrc1 = CFLOAT_add_steps[1] / sizeof(float);
+  const int sdst = CFLOAT_add_steps[2] / sizeof(float);
+  const int hstep = 4 / 2;
+  vfloat32m1x2_t a;
+  int len = 255;
+  for (; len > 0; len -= hstep, src1 += 4, dst += 4) {
+int b = vload_tillz_f32(len);
+int r = vaddq_f32(a.__val[0], b); /* { dg-error {RVV type 
'__rvv_float32m1_t' cannot be passed to an unprototyped function} } */
+  }
+  for (; len > 0; --len, b_src0 += CFLOAT_steps,
+  b_src1 += CFLOAT_add_steps[1], b_dst += CFLOAT_add_steps[2])
+;
+}
diff --git a/gcc/tree-ssa-pre.cc b/gcc/tree-ssa-pre.cc
index 75217f5cde1..5cf1968bc26 100644
--- a/gcc/tree-ssa-pre.cc
+++ b/gcc/tree-ssa-pre.cc
@@ -2685,11 +2685,15 @@ create_component_ref_by_pieces_1 (basic_block block, 
vn_reference_t ref,
   here as the element alignment may be not visible.  See
   PR43783.  Simply drop the element size for constant
   sizes.  */
-   if (TREE_CODE (genop3) == INTEGER_CST
+   if ((TREE_CODE (genop3) == INTEGER_CST
&& TREE_CODE (TYPE_SIZE_UNIT (elmt_type)) == INTEGER_CST
&& wi::eq_p (wi::to_offset (TYPE_SIZE_UNIT (elmt_type)),
-(wi::to_offset (genop3)
- * vn_ref_op_align_unit (currop
+(wi::to_offset (genop3) * vn_ref_op_align_unit 
(currop
+ || (TREE_CODE (genop3) == EXACT_DIV_EXPR
+   && TREE_CODE (TREE_OPERAND (genop3, 1)) == INTEGER_CST
+   && operand_equal_p (TREE_OPERAND (genop3, 0), TYPE_SIZE_UNIT 
(elmt_type))
+   && wi::eq_p (wi::to_offset (TREE_OPERAND (genop3, 1)),
+vn_ref_op_align_unit (currop
  genop3 = NULL_TREE;
else
  {
-- 
2.25.1

[PATCH] pro

[Jiawei]

---
 gcc/common/config/riscv/riscv-common.cc  | 75 +++-
 gcc/config/riscv/riscv-subset.h  |  2 +
 gcc/testsuite/gcc.target/riscv/arch-44.c |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-45.c | 12 
 gcc/testsuite/gcc.target/riscv/arch-46.c | 12 
 5 files changed, 105 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-44.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-46.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 62c6e1dab1f..ff23bdc4406 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -234,6 +234,12 @@ struct riscv_ext_version
   int minor_version;
 };
 
+struct riscv_profiles
+{
+  const char *profile_name;
+  const char *profile_string;
+};
+
 /* All standard extensions defined in all supported ISA spec.  */
 static const struct riscv_ext_version riscv_ext_version_table[] =
 {
@@ -449,6 +455,31 @@ static const struct riscv_ext_version riscv_combine_info[] 
=
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
 
+/* This table records the mapping form RISC-V Profiles into march string.  */
+static const riscv_profiles riscv_profiles_table[] =
+{
+  /* RVI20U only contains the base extension 'i' as mandatory extension.  */
+  {"RVI20U64", "rv64i"},
+  {"RVI20U32", "rv32i"},
+
+  /* RVA20U contains the 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,
+ zicclsm,za128rs' as mandatory extensions.  */
+  {"RVA20U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_za128rs"},
+
+  /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
+ zihpm,ziccif,ziccrse,ziccamoa, zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,
+ zfhmin,zkt' as mandatory extensions.  */
+  {"RVA22U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt"},
+
+  /* Currently we do not define S/M mode Profiles in gcc part.  */
+
+  /* Terminate the list.  */
+  {NULL, NULL}
+};
+
 static const riscv_cpu_info riscv_cpu_tables[] =
 {
 #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -1056,6 +1087,46 @@ riscv_subset_list::parsing_subset_version (const char 
*ext,
   return p;
 }
 
+/* Parsing RISC-V Profiles in -march string.
+   Return string with mandatory extensions of Profiles.  */
+const char *
+riscv_subset_list::parse_profiles (const char *p)
+{
+  /* Checking if input string contains a Profiles.
+ There are two cases use Profiles in -march option:
+
+ 1. Only use Profiles as -march input
+ 2. Mixed Profiles with other extensions
+
+ Use '+' to split Profiles and other extension.  */
+  for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i)
+{
+  const char *match = strstr (p, riscv_profiles_table[i].profile_name);
+  const char *plus_ext = strchr (p, '+');
+  /* Find profile at the begin.  */
+  if (match != NULL && match == p)
+   {
+ /* If there's no '+' sign, return the profile_string directly.  */
+ if (!plus_ext)
+   return riscv_profiles_table[i].profile_string;
+ /* If there's a '+' sign, need to add profiles with other ext.  */
+ else
+ {
+   size_t arch_len = strlen (riscv_profiles_table[i].profile_string)
+ + strlen (plus_ext);
+   /* Reset the input string with Profiles mandatory extensions,
+  end with '_' to connect other additional extensions.  */
+   char *result = new char[arch_len + 2];
+   strcpy (result, riscv_profiles_table[i].profile_string);
+   strcat (result, "_");
+   strcat (result, plus_ext + 1); /* skip the '+'.  */
+   return result;
+ }
+   }
+}
+  return p;
+}
+
 /* Parsing function for base extensions, rv[32|64][i|e|g]
 
Return Value:
@@ -1070,6 +1141,8 @@ riscv_subset_list::parse_base_ext (const char *p)
   unsigned minor_version = 0;
   bool explicit_version_p = false;
 
+  p = parse_profiles(p);
+
   if (startswith (p, "rv32"))
 {
   m_xlen = 32;
@@ -1082,7 +1155,7 @@ riscv_subset_list::parse_base_ext (const char *p)
 }
   else
 {
-  error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv32 or 
rv64",
+  error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv32, rv64 
or Profile",
m_arch);
   return NULL;
 }
diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
index dace4de6575..98fd9877f74 100644
--- a/gcc/config/riscv/riscv-subset.h
+++ b/gcc/config/riscv/riscv-subset.h
@@ -80,6 +80,8 @@ private:
   const char *parse_single_multiletter_ext (const char *, const char *,
const char *, bool);
 
+  const char *parse_profiles (const char*);
+
   void handle_implied_ext (const char *);
   bool check_implied_ext ()

[PATCH v4] RISC-V: Supports Profiles in '-march' option.

[Jiawei]

Supports RISC-V profiles[1] in -march option.

Default input set the profile before other formal extensions.

V2: Fixes some format errors and adds code comments for parse function
Thanks for Jeff Law's review and comments.

V3: Update testcases and profiles extensions support.Remove S/M mode Profiles. 
Thanks for Christoph Müllner,Palmer Dabbelt's  review and comments.

V4: Fix format issue, adjust test name.

[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (struct riscv_profiles):
* New struct.
(riscv_subset_list::parse_profiles): New function.
(riscv_subset_list::parse_base_ext): New process.
* config/riscv/riscv-subset.h: New protype.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-44.c: New test.
* gcc.target/riscv/arch-45.c: New test.
* gcc.target/riscv/arch-46.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  | 75 +++-
 gcc/config/riscv/riscv-subset.h  |  2 +
 gcc/testsuite/gcc.target/riscv/arch-44.c |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-45.c | 12 
 gcc/testsuite/gcc.target/riscv/arch-46.c | 12 
 5 files changed, 105 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-44.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-46.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 62c6e1dab1f..0bad4426971 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -234,6 +234,12 @@ struct riscv_ext_version
   int minor_version;
 };
 
+struct riscv_profiles
+{
+  const char *profile_name;
+  const char *profile_string;
+};
+
 /* All standard extensions defined in all supported ISA spec.  */
 static const struct riscv_ext_version riscv_ext_version_table[] =
 {
@@ -449,6 +455,31 @@ static const struct riscv_ext_version riscv_combine_info[] 
=
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
 
+/* This table records the mapping form RISC-V Profiles into march string.  */
+static const riscv_profiles riscv_profiles_table[] =
+{
+  /* RVI20U only contains the base extension 'i' as mandatory extension.  */
+  {"RVI20U64", "rv64i"},
+  {"RVI20U32", "rv32i"},
+
+  /* RVA20U contains the 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,
+ zicclsm,za128rs' as mandatory extensions.  */
+  {"RVA20U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_za128rs"},
+
+  /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
+ zihpm,ziccif,ziccrse,ziccamoa, zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,
+ zfhmin,zkt' as mandatory extensions.  */
+  {"RVA22U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt"},
+
+  /* Currently we do not define S/M mode Profiles in gcc part.  */
+
+  /* Terminate the list.  */
+  {NULL, NULL}
+};
+
 static const riscv_cpu_info riscv_cpu_tables[] =
 {
 #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -1056,6 +1087,46 @@ riscv_subset_list::parsing_subset_version (const char 
*ext,
   return p;
 }
 
+/* Parsing RISC-V Profiles in -march string.
+   Return string with mandatory extensions of Profiles.  */
+const char *
+riscv_subset_list::parse_profiles (const char *p)
+{
+  /* Checking if input string contains a Profiles.
+ There are two cases use Profiles in -march option:
+
+ 1. Only use Profiles as -march input
+ 2. Mixed Profiles with other extensions
+
+ Use '+' to split Profiles and other extension.  */
+  for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i)
+{
+  const char *match = strstr (p, riscv_profiles_table[i].profile_name);
+  const char *plus_ext = strchr (p, '+');
+  /* Find profile at the begin.  */
+  if (match != NULL && match == p)
+   {
+ /* If there's no '+' sign, return the profile_string directly.  */
+ if (!plus_ext)
+   return riscv_profiles_table[i].profile_string;
+ /* If there's a '+' sign, need to add profiles with other ext.  */
+ else
+ {
+   size_t arch_len = strlen (riscv_profiles_table[i].profile_string)
+ + strlen (plus_ext);
+   /* Reset the input string with Profiles mandatory extensions,
+  end with '_' to connect other additional extensions.  */
+   char *result = new char[arch_len + 2];
+   strcpy (result, riscv_profiles_table[i].profile_string);
+   strcat (result, "_");
+   strcat (result, plus_ext + 1); /* skip the '+'.  */
+   return result;
+ }
+   }
+}
+  return p;
+}
+
 /* Parsing function for base extensions, rv[32|64][i|e|g]
 
Return Value:
@@ -1070,6 +1141,8 @@ riscv_subset_list::parse_base_ext (const char *p)
   unsigned minor_ver

Re: [PATCH v4] RISC-V: Supports Profiles in '-march' option.

[Jiawei]

在 2024/8/21 3:23, Palmer Dabbelt 写道:

On Mon, 19 Aug 2024 21:53:54 PDT (-0700), jia...@iscas.ac.cn wrote:

Supports RISC-V profiles[1] in -march option.

Default input set the profile before other formal extensions.

V2: Fixes some format errors and adds code comments for parse function
Thanks for Jeff Law's review and comments.

V3: Update testcases and profiles extensions support.Remove S/M mode 
Profiles.

Thanks for Christoph Müllner,Palmer Dabbelt's  review and comments.

V4: Fix format issue, adjust test name.

[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (struct riscv_profiles):
* New struct.
(riscv_subset_list::parse_profiles): New function.
(riscv_subset_list::parse_base_ext): New process.
* config/riscv/riscv-subset.h: New protype.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-44.c: New test.
* gcc.target/riscv/arch-45.c: New test.
* gcc.target/riscv/arch-46.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  | 75 +++-
 gcc/config/riscv/riscv-subset.h  |  2 +
 gcc/testsuite/gcc.target/riscv/arch-44.c |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-45.c | 12 
 gcc/testsuite/gcc.target/riscv/arch-46.c | 12 
 5 files changed, 105 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-44.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-46.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc

index 62c6e1dab1f..0bad4426971 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -234,6 +234,12 @@ struct riscv_ext_version
   int minor_version;
 };

+struct riscv_profiles
+{
+  const char *profile_name;
+  const char *profile_string;
+};
+
 /* All standard extensions defined in all supported ISA spec. */
 static const struct riscv_ext_version riscv_ext_version_table[] =
 {
@@ -449,6 +455,31 @@ static const struct riscv_ext_version 
riscv_combine_info[] =

   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };

+/* This table records the mapping form RISC-V Profiles into march 
string.  */

+static const riscv_profiles riscv_profiles_table[] =
+{
+  /* RVI20U only contains the base extension 'i' as mandatory 
extension.  */

+  {"RVI20U64", "rv64i"},
+  {"RVI20U32", "rv32i"},
+
+  /* RVA20U contains the 
'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,

+ zicclsm,za128rs' as mandatory extensions.  */
+  {"RVA20U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_za128rs"},
+
+  /* RVA22U contains the 
'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
+ zihpm,ziccif,ziccrse,ziccamoa, 
zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,


Except at least the Spacemit stuff that claims RVA22 doesn't actually 
have Zicclsm, at least assuming the "supports" in there means "doesn't 
trap" (we could just say "supports" includes traps, and thus Zicclsm 
means nothing).


I'd argue we should just punt on the profiles until we figure out what 
they're actually going to be.  The pre-23 profiles were all minor 
releases anyway, so it's not like we should be losing much there (as 
they're not meant for software).  At least if we wait we don't end up 
committing to this whole "profiles don't mean anything" spot we're in, 
like we did for the other spec flavors.


Though now that I'm writing that it actually just sounds kind of silly 
to keep hoping that we're going to get any meaningful compatibility 
rules enforced by the RISC-V foundation.  There's really just no 
incentive for that to happen, as we keep bailing out vendors who ship 
broken systems and thus there's no pushback from their members.


So maybe the right answer here is to just break users and tell them to 
go complain to someone else?  At least that way everyone will be 
upset, maybe that'll be enough to get things to change?


Okay, let's continue to wait for the RVA/B23 forzen.




+ zfhmin,zkt' as mandatory extensions.  */
+  {"RVA22U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt"},
+
+  /* Currently we do not define S/M mode Profiles in gcc part. */
+
+  /* Terminate the list.  */
+  {NULL, NULL}
+};
+
 static const riscv_cpu_info riscv_cpu_tables[] =
 {
 #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -1056,6 +1087,46 @@ riscv_subset_list::parsing_subset_version 
(const char *ext,

   return p;
 }

+/* Parsing RISC-V Profiles in -march string.
+   Return string with mandatory extensions of Profiles.  */
+const char *
+riscv_subset_list::parse_profiles (const char *p)
+{
+  /* Checking if input string contains a Profiles.
+ There are two cases use Profiles in -march option:
+
+ 1. Only use Profiles as -march input
+ 2. Mixed Profiles with other extensions
+
+ Use '+' to split Profiles an

Re: [PATCH] RISC-V: Bugfix for Duplicate entries for -mtune in --target-help[Bug 116347]

[Jiawei]

在 2024/8/25 23:38, Jeff Law 写道:



On 8/19/24 2:14 AM, shiyul...@iscas.ac.cn wrote:

From: yulong 

This patch try to fix a bug[116347]. I change the name of the 
micro-arch,
because I think micro-arch and core have the same name that caused 
the error.


gcc/ChangeLog:

 * config/riscv/riscv-cores.def (RISCV_TUNE): Rename.
 (RISCV_CORE): Ditto.
Conceptually tuning means things like costs and scheduler model while 
core defines what instructions can be used.   So why are core entries 
showing up under known arguments for the -mtune option?


Jeff


In the current definition, different cores need to be configured with 
corresponding tuning in `riscv-cores.def`, so we can reuse the core name 
in '-mtune' option.



BR,

Jiawei

[PATCH v3] RISC-V: Supports Profiles in '-march' option.

[Jiawei]

Supports RISC-V profiles[1] in -march option.

Default input set the profile before other formal extensions.

V2: Fixes some format errors and adds code comments for parse function
Thanks for Jeff Law's review and comments.

V3: Update testcases and profiles extensions support.Remove S/M mode Profiles. 
Thanks for Christoph Müllner,Palmer Dabbelt's  review and comments.

[1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc

---
 gcc/common/config/riscv/riscv-common.cc  | 71 +++-
 gcc/config/riscv/riscv-subset.h  |  2 +
 gcc/testsuite/gcc.target/riscv/arch-41.c |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-42.c | 12 
 gcc/testsuite/gcc.target/riscv/arch-43.c | 12 
 5 files changed, 101 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-41.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-42.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-43.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 682826c0e34..e092026fe9b 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -231,6 +231,12 @@ struct riscv_ext_version
   int minor_version;
 };
 
+struct riscv_profiles
+{
+  const char *profile_name;
+  const char *profile_string;
+};
+
 /* All standard extensions defined in all supported ISA spec.  */
 static const struct riscv_ext_version riscv_ext_version_table[] =
 {
@@ -442,6 +448,31 @@ static const struct riscv_ext_version riscv_combine_info[] 
=
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
 
+/* This table records the mapping form RISC-V Profiles into march string.  */
+static const riscv_profiles riscv_profiles_table[] =
+{
+  /* RVI20U only contains the base extension 'i' as mandatory extension.  */
+  {"RVI20U64", "rv64i"},
+  {"RVI20U32", "rv32i"},
+
+  /* RVA20U contains the 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,
+ zicclsm,za128rs' as mandatory extensions.  */
+  {"RVA20U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_za128rs"},
+
+  /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
+ zihpm,ziccif,ziccrse,ziccamoa, zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,
+ zfhmin,zkt' as mandatory extensions.  */
+  {"RVA22U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt"},
+
+  /* Currently we do not define S/M mode Profiles in gcc part.  */
+
+  /* Terminate the list.  */
+  {NULL, NULL}
+};
+
 static const riscv_cpu_info riscv_cpu_tables[] =
 {
 #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -1047,6 +1078,42 @@ riscv_subset_list::parsing_subset_version (const char 
*ext,
   return p;
 }
 
+/* Parsing RISC-V Profiles in -march string.
+   Return string with mandatory extensions of Profiles.  */
+const char *
+riscv_subset_list::parse_profiles (const char * p){
+  /* Checking if input string contains a Profiles.
+ There are two cases use Profiles in -march option
+
+   1. Only use Profiles as -march input
+   2. Mixed Profiles with other extensions
+
+ use '+' to split Profiles and other extension.  */
+  for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i) {
+const char* match = strstr(p, riscv_profiles_table[i].profile_name);
+const char* plus_ext = strchr(p, '+');
+/* Find profile at the begin.  */
+if (match != NULL && match == p) {
+  /* If there's no '+' sign, return the profile_string directly.  */
+  if(!plus_ext)
+   return riscv_profiles_table[i].profile_string;
+  /* If there's a '+' sign, need to add profiles with other ext.  */
+  else {
+   size_t arch_len = strlen(riscv_profiles_table[i].profile_string)+
+ strlen(plus_ext);
+   /* Reset the input string with Profiles mandatory extensions,
+  end with '_' to connect other additional extensions.  */
+   char* result = new char[arch_len + 2];
+   strcpy(result, riscv_profiles_table[i].profile_string);
+   strcat(result, "_");
+   strcat(result, plus_ext + 1); /* skip the '+'.  */
+   return result;
+  }
+}
+  }
+  return p;
+}
+
 /* Parsing function for base extensions, rv[32|64][i|e|g]
 
Return Value:
@@ -1060,6 +1127,8 @@ riscv_subset_list::parse_base_ext (const char *p)
   unsigned major_version = 0;
   unsigned minor_version = 0;
   bool explicit_version_p = false;
+
+  p = parse_profiles(p);
 
   if (startswith (p, "rv32"))
 {
@@ -1073,7 +1142,7 @@ riscv_subset_list::parse_base_ext (const char *p)
 }
   else
 {
-  error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv32 or 
rv64",
+  error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv32, rv64 
or Profile",
m_arch);
   return NULL;
 }
diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
index dace4de6575..98fd9877f74 100644
--

[RFC] RISC-V: Add support for Profiles RVA/B23.

[Jiawei]

This patch adds support for RISC-V RVA23 and RVB23 Profiles[1], 
which depend on the base RISC-V Profiles support[2].

[1] 
https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review
[2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html


gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New Profiles.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/attribute-22.c: New test.
* gcc.target/riscv/attribute-23.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc   | 20 +++
 gcc/testsuite/gcc.target/riscv/attribute-22.c | 11 ++
 gcc/testsuite/gcc.target/riscv/attribute-23.c | 10 ++
 3 files changed, 41 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-22.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-23.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 23ae07fe2f3..e6e8adf5e1b 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -323,6 +323,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zicclsm",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"ziccrse",  ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zimop",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmop",  ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
   {"zihpm",  ISA_SPEC_CLASS_NONE, 2, 0},
 
@@ -467,6 +470,23 @@ static const riscv_profiles riscv_profiles_table[] =
"_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
"_zicboz_zfhmin_zkt"},
 
+  /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension
+ 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions.  */
+  {"RVA23U64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
+  
+  /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
+ 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions.  */
+  {"RVB23U64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
   /* Currently we do not define S/M mode Profiles in gcc part.  */
 
   /* Terminate the list.  */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-22.c 
b/gcc/testsuite/gcc.target/riscv/attribute-22.c
new file mode 100644
index 000..0bbb3242ddd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-22.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=RVA23U64 -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0"
+_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0"
+_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0"
+_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0"
+_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-23.c 
b/gcc/testsuite/gcc.target/riscv/attribute-23.c
new file mode 100644
index 000..459b5641ca3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-23.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=RVB23U64 -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0"
+"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0"
+"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0"
+"_zbb1p0_zbs1p0_zkt1p0\"" } } */
-- 
2.25.1

Re: [RFC] RISC-V: Add support for Profiles RVA/B23.

[Jiawei]

在 2024/7/31 4:48, Jeff Law 写道:



On 7/28/24 9:24 PM, Jiawei wrote:

This patch adds support for RISC-V RVA23 and RVB23 Profiles[1],
which depend on the base RISC-V Profiles support[2].

[1] 
https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review

[2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html


gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New Profiles.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/attribute-22.c: New test.
* gcc.target/riscv/attribute-23.c: New test.
So this was discussed in the patch review meeting earlier today. This 
really needs to wait until the profile is ratified.  So I've put the 
patch into the deferred state for now.


jeff


Appreciate it, I will await further updates on the ratification process.


BR,

jiawei

Re: [RFC] RISC-V: Add support for Profiles RVA/B23.

[Jiawei]

在 2024/8/1 21:54, Christoph Müllner 写道:

On Mon, Jul 29, 2024 at 5:26 AM Jiawei  wrote:

This patch adds support for RISC-V RVA23 and RVB23 Profiles[1],
which depend on the base RISC-V Profiles support[2].

[1] 
https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review
[2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html


gcc/ChangeLog:

 * common/config/riscv/riscv-common.cc: New Profiles.

gcc/testsuite/ChangeLog:

 * gcc.target/riscv/attribute-22.c: New test.
 * gcc.target/riscv/attribute-23.c: New test.

---
  gcc/common/config/riscv/riscv-common.cc   | 20 +++
  gcc/testsuite/gcc.target/riscv/attribute-22.c | 11 ++
  gcc/testsuite/gcc.target/riscv/attribute-23.c | 10 ++
  3 files changed, 41 insertions(+)
  create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-22.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-23.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 23ae07fe2f3..e6e8adf5e1b 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -323,6 +323,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
{"zicclsm",  ISA_SPEC_CLASS_NONE, 1, 0},
{"ziccrse",  ISA_SPEC_CLASS_NONE, 1, 0},

+  {"zimop",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmop",  ISA_SPEC_CLASS_NONE, 1, 0},
+

Independent of the fact that this will be delayed until ratification:
I would prefer to have this in a separate patch as Zimop and Zcmop are
dependencies.
Since Zimop and Zcmop are already ratified, this does not have a
dependency for the profiles ratification.


Ok, I will split it into another patch, thanks!

Jiawei





{"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
{"zihpm",  ISA_SPEC_CLASS_NONE, 2, 0},

@@ -467,6 +470,23 @@ static const riscv_profiles riscv_profiles_table[] =
 "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
 "_zicboz_zfhmin_zkt"},

+  /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension
+ 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions.  */
+  {"RVA23U64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
+
+  /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
+ 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions.  */
+  {"RVB23U64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
/* Currently we do not define S/M mode Profiles in gcc part.  */

/* Terminate the list.  */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-22.c 
b/gcc/testsuite/gcc.target/riscv/attribute-22.c
new file mode 100644
index 000..0bbb3242ddd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-22.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=RVA23U64 -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0"
+_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0"
+_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0"
+_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0"
+_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-23.c 
b/gcc/testsuite/gcc.target/riscv/attribute-23.c
new file mode 100644
index 000..459b5641ca3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-23.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=RVB23U64 -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0"
+"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0"
+"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0"
+"_zbb1p0_zbs1p0_zkt1p0\"" } } */
--
2.25.1

[PATCH] RISC-V: Minimal support for Zimop extension.

[Jiawei]

https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New extension.
* config/riscv/riscv.opt: New mask.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-42.c: New test.
* gcc.target/riscv/arch-43.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  | 8 
 gcc/config/riscv/riscv.opt   | 7 +++
 gcc/testsuite/gcc.target/riscv/arch-42.c | 5 +
 gcc/testsuite/gcc.target/riscv/arch-43.c | 5 +
 4 files changed, 25 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-42.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-43.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 1944c7785c4..62c6e1dab1f 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -97,6 +97,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zabha", "zaamo"},
   {"zacas", "zaamo"},
 
+  {"zcmop", "zca"},
+
   {"b", "zba"},
   {"b", "zbb"},
   {"b", "zbs"},
@@ -319,6 +321,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zicclsm",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"ziccrse",  ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zimop", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmop", ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
   {"zihpm",  ISA_SPEC_CLASS_NONE, 2, 0},
 
@@ -1629,6 +1634,9 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP},
   {"zic64b", &gcc_options::x_riscv_zicmo_subext, MASK_ZIC64B},
 
+  {"zimop",&gcc_options::x_riscv_mop_subext, MASK_ZIMOP},
+  {"zcmop",&gcc_options::x_riscv_mop_subext, MASK_ZCMOP},
+
   {"zve32x",   &gcc_options::x_target_flags, MASK_VECTOR},
   {"zve32f",   &gcc_options::x_target_flags, MASK_VECTOR},
   {"zve64x",   &gcc_options::x_target_flags, MASK_VECTOR},
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 2e340e5324f..a8758abc918 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -406,6 +406,13 @@ Mask(ZICBOP) Var(riscv_zicmo_subext)
 
 Mask(ZIC64B) Var(riscv_zicmo_subext)
 
+TargetVariable
+int riscv_mop_subext
+
+Mask(ZIMOP) Var(riscv_mop_subext)
+
+Mask(ZCMOP) Var(riscv_mop_subext)
+
 TargetVariable
 int riscv_zf_subext
 
diff --git a/gcc/testsuite/gcc.target/riscv/arch-42.c 
b/gcc/testsuite/gcc.target/riscv/arch-42.c
new file mode 100644
index 000..83f78d28dbe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-42.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zimop -mabi=lp64" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/riscv/arch-43.c 
b/gcc/testsuite/gcc.target/riscv/arch-43.c
new file mode 100644
index 000..4a300a165fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-43.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zcmop -mabi=lp64" } */
+int foo()
+{
+}
-- 
2.25.1

Re: [RFC] RISC-V: Add support for Profiles RVA/B23.

[Jiawei]

在 2024/8/1 21:54, Christoph Müllner 写道:

On Mon, Jul 29, 2024 at 5:26 AM Jiawei  wrote:

This patch adds support for RISC-V RVA23 and RVB23 Profiles[1],
which depend on the base RISC-V Profiles support[2].

[1] 
https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review
[2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html


gcc/ChangeLog:

 * common/config/riscv/riscv-common.cc: New Profiles.

gcc/testsuite/ChangeLog:

 * gcc.target/riscv/attribute-22.c: New test.
 * gcc.target/riscv/attribute-23.c: New test.

---
  gcc/common/config/riscv/riscv-common.cc   | 20 +++
  gcc/testsuite/gcc.target/riscv/attribute-22.c | 11 ++
  gcc/testsuite/gcc.target/riscv/attribute-23.c | 10 ++
  3 files changed, 41 insertions(+)
  create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-22.c
  create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-23.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 23ae07fe2f3..e6e8adf5e1b 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -323,6 +323,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
{"zicclsm",  ISA_SPEC_CLASS_NONE, 1, 0},
{"ziccrse",  ISA_SPEC_CLASS_NONE, 1, 0},

+  {"zimop",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmop",  ISA_SPEC_CLASS_NONE, 1, 0},
+

Independent of the fact that this will be delayed until ratification:
I would prefer to have this in a separate patch as Zimop and Zcmop are
dependencies.
Since Zimop and Zcmop are already ratified, this does not have a
dependency for the profiles ratification.


Thanks for your advice, implemented Zimop extension  in new patch

https://gcc.gnu.org/pipermail/gcc-patches/2024-August/659280.html





{"zicntr", ISA_SPEC_CLASS_NONE, 2, 0},
{"zihpm",  ISA_SPEC_CLASS_NONE, 2, 0},

@@ -467,6 +470,23 @@ static const riscv_profiles riscv_profiles_table[] =
 "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
 "_zicboz_zfhmin_zkt"},

+  /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension
+ 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions.  */
+  {"RVA23U64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
+
+  /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
+ 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions.  */
+  {"RVB23U64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
/* Currently we do not define S/M mode Profiles in gcc part.  */

/* Terminate the list.  */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-22.c 
b/gcc/testsuite/gcc.target/riscv/attribute-22.c
new file mode 100644
index 000..0bbb3242ddd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-22.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=RVA23U64 -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0"
+_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0"
+_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0"
+_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0"
+_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/attribute-23.c 
b/gcc/testsuite/gcc.target/riscv/attribute-23.c
new file mode 100644
index 000..459b5641ca3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/attribute-23.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=RVB23U64 -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0"
+"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0"
+"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0"
+"_zbb1p0_zbs1p0_zkt1p0\"" } } */
--
2.25.1

Re: [PATCH] RISC-V: Minimal support for Zimop extension.

[Jiawei]

在 2024/8/5 8:45, Jeff Law 写道:



On 8/2/24 9:32 AM, Jiawei wrote:

https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New extension.
* config/riscv/riscv.opt: New mask.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-42.c: New test.
* gcc.target/riscv/arch-43.c: New test.
Shouldn't the binutils bits go in first?  There's basic support for 
Zimop/Zcmop from Lyut on the binutils list in late 2023 or early 2024. 
I'm pretty sure it marked as DO NOT MERGE because we were waiting for 
the extension to get ratified.


Christoph informed me that Zimop has been ratified, so we may not need 
to worry about the spec lifecycle status:


https://jira.riscv.org/browse/RVS-1603?src=confmacro



I don't know if Lyut is doing any RISC-V work right now, so if you 
wanted to ping the patch on his behalf, it'd be appreciated and I can 
handle the review on the binutils side too.


I found that ESWIN's patch to support Zimop on the binutils mailing list 
last month:


https://sourceware.org/pipermail/binutils/2024-June/134592.html

I think the GCC bits are fine, but let's get the binutils bits 
installed first.

jeff


Okay, Thank you for your comments!

BR,

jiawei

[PATCH] testsuite: Add RISC-V to targets not xfailing gcc.dg/attr-alloc_size-11.c:50, 51.

[Jiawei]

The test has been observed to pass on most architectures including RISC-V:
https://godbolt.org/z/8nYEvW6n1

Origin issue see:
https://gcc.gnu.org/PR79356#c11

Update RISC-V target to to pass list.

gcc/testsuite/ChangeLog:

* gcc.dg/attr-alloc_size-11.c: Add RISC-V to the list
of targets excluding xfail on lines 50 and 51.

---
 gcc/testsuite/gcc.dg/attr-alloc_size-11.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c 
b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
index a2efe128915..6346d5e084b 100644
--- a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
+++ b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
@@ -47,8 +47,8 @@ typedef __SIZE_TYPE__size_t;
 
 /* The following tests fail because of missing range information.  The xfail
exclusions are PR79356.  */
-TEST (signed char, SCHAR_MIN + 2, ALLOC_MAX);   /* { dg-warning "argument 1 
range \\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info 
for signed char" { xfail { ! { aarch64*-*-* arm*-*-* avr-*-* alpha*-*-* 
cris-*-* ia64-*-* mips*-*-* or1k*-*-* pdp11*-*-* powerpc*-*-* sparc*-*-* 
s390*-*-* visium-*-* msp430-*-* nvptx*-*-*} } } } */
-TEST (short, SHRT_MIN + 2, ALLOC_MAX); /* { dg-warning "argument 1 range 
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info for 
short" { xfail { ! { aarch64*-*-* arm*-*-* alpha*-*-* avr-*-* cris-*-* ia64-*-* 
mips*-*-* or1k*-*-* pdp11*-*-* powerpc*-*-* sparc*-*-* s390x-*-* visium-*-* 
msp430-*-* nvptx*-*-* } } } } */
+TEST (signed char, SCHAR_MIN + 2, ALLOC_MAX);   /* { dg-warning "argument 1 
range \\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info 
for signed char" { xfail { ! { aarch64*-*-* arm*-*-* avr-*-* alpha*-*-* 
cris-*-* ia64-*-* mips*-*-* or1k*-*-* pdp11*-*-* powerpc*-*-* riscv*-*-* 
sparc*-*-* s390*-*-* visium-*-* msp430-*-* nvptx*-*-*} } } } */
+TEST (short, SHRT_MIN + 2, ALLOC_MAX); /* { dg-warning "argument 1 range 
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info for 
short" { xfail { ! { aarch64*-*-* arm*-*-* alpha*-*-* avr-*-* cris-*-* ia64-*-* 
mips*-*-* or1k*-*-* pdp11*-*-* powerpc*-*-* riscv*-*-* sparc*-*-* s390x-*-* 
visium-*-* msp430-*-* nvptx*-*-* } } } } */
 TEST (int, INT_MIN + 2, ALLOC_MAX);/* { dg-warning "argument 1 range 
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" } */
 TEST (int, -3, ALLOC_MAX); /* { dg-warning "argument 1 range 
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" } */
 TEST (int, -2, ALLOC_MAX); /* { dg-warning "argument 1 range 
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" } */
-- 
2.25.1

Re: [PATCH] RISC-V: Minimal support for Zimop extension.

[Jiawei]

在 2024/8/5 22:15, Jeff Law 写道:



On 8/4/24 8:20 PM, Jiawei wrote:


在 2024/8/5 8:45, Jeff Law 写道:



On 8/2/24 9:32 AM, Jiawei wrote:

https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New extension.
* config/riscv/riscv.opt: New mask.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-42.c: New test.
* gcc.target/riscv/arch-43.c: New test.
Shouldn't the binutils bits go in first?  There's basic support for 
Zimop/Zcmop from Lyut on the binutils list in late 2023 or early 
2024. I'm pretty sure it marked as DO NOT MERGE because we were 
waiting for the extension to get ratified.


Christoph informed me that Zimop has been ratified, so we may not 
need to worry about the spec lifecycle status:


https://jira.riscv.org/browse/RVS-1603?src=confmacro

Agreed.  No concerns about spec lifecycle at this point.





I don't know if Lyut is doing any RISC-V work right now, so if you 
wanted to ping the patch on his behalf, it'd be appreciated and I 
can handle the review on the binutils side too.


I found that ESWIN's patch to support Zimop on the binutils mailing 
list last month:


https://sourceware.org/pipermail/binutils/2024-June/134592.html

I don't watch binutils as closely as perhaps I should.

That patch looks marginally better than Lyut's version.  It has the 
updated version #s for the spec and handles the implied extensions. 
Let's go with Xiao's version.


Xiao, the Zimop/Zcmop patches are OK for binutils.

Jiawei, the GCC patches are OK once Xiao pushes his changes to the 
binutils repo.  Alternately if you have permissions in the binutils 
repo, you can push them for Xiao.


Jeff


Thanks Jeff! I think I do not have the permissions in the binutils repo, 
let me contact Nelson to ask him give  some help.



BR,

Jiawei

Re: [PATCH] testsuite: Add RISC-V to targets not xfailing gcc.dg/attr-alloc_size-11.c:50, 51.

[Jiawei]

在 2024/8/5 23:21, Jeff Law 写道:



On 8/5/24 6:26 AM, Jiawei wrote:
The test has been observed to pass on most architectures including 
RISC-V:

https://godbolt.org/z/8nYEvW6n1

Origin issue see:
https://gcc.gnu.org/PR79356#c11

Update RISC-V target to to pass list.

gcc/testsuite/ChangeLog:

* gcc.dg/attr-alloc_size-11.c: Add RISC-V to the list
of targets excluding xfail on lines 50 and 51.
Almost certainly behaving like the other targets in the list due to 
how promotions work.


OK for the trunk.  Thanks!

jeff


Okay, thanks for your review, committed.

BR,

jiawei

Re: [PATCH] Fix Wstringop-overflow-47.c warning in RISC-V target.

[Jiawei]

在 2024/8/5 23:16, Jeff Law 写道:



On 7/15/24 10:08 PM, Jiawei wrote:


在 2024/07/16 8:28, Jeff Law 写道:
IIRC these fails are dependent upon whether or not the statements 
turn into vector stores or not.


So to remove the xfail don't you have to know if vector is enabled/ 
disabled? 


I am not sure, I tried to enable with RVV, but it still pass the test:

https://godbolt.org/z/bvWfffTe5
Probably because it didn't vectorize ;-)  I don't remember all these 
tests, but I do remember some of them are highly sensitive to the 
changes in code generation from vectorization.


OK for the trunk.  Though I wouldn't be surprised if we have to come 
back to this at some point and adjust again.


jeff


Committed on trunk, I will keep an eye on this if it went wrong :)

BR,

jiawei

[PATCH] RISC-V: Optimal RVV epilogue logic.

[jiawei]

Skip add insn generate if the adjust size equal to zero.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_expand_epilogue): 
New if control segement.

---
 gcc/config/riscv/riscv.cc | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 02a01ca0b7c..af138db7545 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style)
}
 
   /* Get an rtx for STEP1 that we can add to BASE.  */
-  rtx adjust = GEN_INT (step1.to_constant ());
-  if (!SMALL_OPERAND (step1.to_constant ()))
+  if (step1.to_constant () != 0){
+rtx adjust = GEN_INT (step1.to_constant ());
+if (!SMALL_OPERAND (step1.to_constant ()))
{
  riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
  adjust = RISCV_PROLOGUE_TEMP (Pmode);
}
 
-  insn = emit_insn (
+insn = emit_insn (
   gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
 
-  rtx dwarf = NULL_RTX;
-  rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
+rtx dwarf = NULL_RTX;
+rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
 GEN_INT (step2));
 
-  dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
-  RTX_FRAME_RELATED_P (insn) = 1;
+dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
+RTX_FRAME_RELATED_P (insn) = 1;
 
-  REG_NOTES (insn) = dwarf;
+REG_NOTES (insn) = dwarf;
+  }
 }
   else if (frame_pointer_needed)
 {
-- 
2.25.1

Re: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.

[jiawei]

> -原始邮件-
> 发件人: "Kito Cheng" 
> 发送时间: 2022-11-15 09:48:26 (星期二)
> 收件人: jiawei 
> 抄送: gcc-patches@gcc.gnu.org, kito.ch...@sifive.com, pal...@rivosinc.com, 
juzhe.zh...@rivai.ai, christoph.muell...@vrull.eu, philipp.toms...@vrull.eu, 
wuwei2...@iscas.ac.cn
> 主题: Re: [PATCH] RISC-V: Optimal RVV epilogue logic.
> 
> Could you provide some testcase?

Sorry for not giving a clear description， 

You can use amost all testcases in gcc.target/riscv/rvv/base/spill-*.c

compile with -march=rv64gcv and check the assemble file spill-*.s,

before this patch, it will generate assemble code contain additional

`addi sp,sp,0`:

```
csrrt0,vlenb
sllit1,t0,1
add sp,sp,t1
addisp,sp,0
ld  s0,24(sp)
addisp,sp,32
jr  ra
```

after this patch it will removed:

```
csrrt0,vlenb
sllit1,t0,1
add sp,sp,t1
ld  s0,24(sp)
addisp,sp,32
jr  ra
```

> 
> On Tue, Nov 15, 2022 at 12:29 AM jiawei  wrote:
> >
> > Skip add insn generate if the adjust size equal to zero.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv.cc (riscv_expand_epilogue):
> > New if control segement.
> >
> > ---
> >  gcc/config/riscv/riscv.cc | 18 ++
> >  1 file changed, 10 insertions(+), 8 deletions(-)
> >
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 02a01ca0b7c..af138db7545 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style)
> > }
> >
> >/* Get an rtx for STEP1 that we can add to BASE.  */
> > -  rtx adjust = GEN_INT (step1.to_constant ());
> > -  if (!SMALL_OPERAND (step1.to_constant ()))
> > +  if (step1.to_constant () != 0){
> > +rtx adjust = GEN_INT (step1.to_constant ());
> > +if (!SMALL_OPERAND (step1.to_constant ()))
> > {
> >   riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
> >   adjust = RISCV_PROLOGUE_TEMP (Pmode);
> > }
> >
> > -  insn = emit_insn (
> > +insn = emit_insn (
> >gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, 
adjust));
> >
> > -  rtx dwarf = NULL_RTX;
> > -  rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
> > +rtx dwarf = NULL_RTX;
> > +rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
> >  GEN_INT (step2));
> >
> > -  dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, 
dwarf);
> > -  RTX_FRAME_RELATED_P (insn) = 1;
> > +dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, 
dwarf);
> > +RTX_FRAME_RELATED_P (insn) = 1;
> >
> > -  REG_NOTES (insn) = dwarf;
> > +REG_NOTES (insn) = dwarf;
> > +  }
> >  }
> >else if (frame_pointer_needed)
> >  {
> > --
> > 2.25.1
> >

[PATCH v2 2/2] RISC-V: Optimize RVV epilogue logic.

[jiawei]

Sometimes "step1 -= scalable_frame" will cause adjust equal to
zero. And it will generate additional redundant instruction 
"addi sp,sp,0". Add checking segement to skip that case.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_expand_epilogue): 
New check segement.

---
 gcc/config/riscv/riscv.cc | 35 +++
 1 file changed, 19 insertions(+), 16 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 02a01ca0b7c..433b9b13eb6 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5185,25 +5185,28 @@ riscv_expand_epilogue (int style)
  step1 -= scalable_frame;
}
 
-  /* Get an rtx for STEP1 that we can add to BASE.  */
-  rtx adjust = GEN_INT (step1.to_constant ());
-  if (!SMALL_OPERAND (step1.to_constant ()))
-   {
- riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
- adjust = RISCV_PROLOGUE_TEMP (Pmode);
-   }
-
-  insn = emit_insn (
-  gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
-
-  rtx dwarf = NULL_RTX;
-  rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
+  /* Get an rtx for STEP1 that we can add to BASE.  
+ Skip if adjust equal to zero.  */
+  if (step1.to_constant () != 0)
+  {
+rtx adjust = GEN_INT (step1.to_constant ());
+if (!SMALL_OPERAND (step1.to_constant ()))
+{
+  riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
+  adjust = RISCV_PROLOGUE_TEMP (Pmode);
+}
+
+insn = emit_insn (
+   gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
+rtx dwarf = NULL_RTX;
+rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
 GEN_INT (step2));
 
-  dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
-  RTX_FRAME_RELATED_P (insn) = 1;
+dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
+RTX_FRAME_RELATED_P (insn) = 1;
 
-  REG_NOTES (insn) = dwarf;
+REG_NOTES (insn) = dwarf;
+ }
 }
   else if (frame_pointer_needed)
 {
-- 
2.25.1

[PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic.

[jiawei]

Current epilogue will generate "addi sp,sp,0" redundant instruction.

```
csrrt0,vlenb
sllit1,t0,1
add sp,sp,t1
addisp,sp,0
ld  s0,24(sp)
addisp,sp,32
jr  ra
```

Optimize it by check if adjust equal to zero, remove redundant insn gen.

```
csrrt0,vlenb
sllit1,t0,1
add sp,sp,t1
ld  s0,24(sp)
addisp,sp,32
jr  ra
```

Thanks for Kito and Jeff's suggestion, add testcase and fix code format.

jiawei (2):
  RISC-V: Add spill sp adjust check testcase.
  RISC-V: Optimize RVV epilogue logic.

 gcc/config/riscv/riscv.cc | 35 ++-
 .../riscv/rvv/base/spill-sp-adjust.c  | 13 +++
 2 files changed, 32 insertions(+), 16 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c

-- 
2.25.1

[PATCH v2 1/2] RISC-V: Add spill sp adjust check testcase.

[jiawei]

This testcase mix exist spill-1.c and adding new fun to check if
there have redundant addi intructions. Idea provided by Jeff Law.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.

---
 .../gcc.target/riscv/rvv/base/spill-sp-adjust.c | 13 +
 1 file changed, 13 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
new file mode 100644
index 000..0226554abf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv" } */
+
+#include "spill-1.c"
+
+void
+spill_sp_adjust (int8_t *v)
+{
+  vint8mf8_t v1 = *(vint8mf8_t*)v; 
+}
+
+/* Make sure we do not have a useless SP adjustment.  */
+/* { dg-final { scan-assembler-not "addi\tsp,sp,0" } } */
-- 
2.25.1

RE: [wwwdocs] gcc-13: Add release note for RISC-V

[jiawei]

> ---
>  htdocs/gcc-13/changes.html | 31 ++-
>  1 file changed, 30 insertions(+), 1 deletion(-)
> 
> diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
> index f6941534..5427f805 100644
> --- a/htdocs/gcc-13/changes.html
> +++ b/htdocs/gcc-13/changes.html
> @@ -636,9 +636,32 @@ a work-in-progress.
>  
>  RISC-V
>  
> -New ISA extension support for zawrs.
> +Supports vector intrinsics as specified in  + href="https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/v0.11.x";>
> + version 0.11 of the RISC-V vector intrinsic specification,
> + thanks Ju-Zhe Zhong from https://rivai-ic.com.cn/";>RiVAI
> + for contributing most of implementation.
> +
>  Support for the following vendor extensions has been added:
>
> + Zawrs
> + Zicbom
> + Zicboz
> + Zicbop
> + Zfh
> + Zfhmin
> + Zmmul
> + Zdinx
> + Zfinx
> + Zhinx
> + Zhinxmin
> + Zksh
> + Zksed
> + Zknd
> + Zkne
> + Zbkb
> + Zbkc
> + Zbkx
>  XTheadBa
>  XTheadBb
>  XTheadBs
> @@ -657,8 +680,14 @@ a work-in-progress.
>option (GCC identifiers in parentheses).
>
>  T-Head's XuanTie C906 (thead-c906).
> +Ventana's VT1 (ventana-vt1).
>
>  
> +Improves the multi-lib selection mechanism for the bare-metal 
> toolchain
> + (riscv*-elf*). GCC will now automatically select the best-fit multi-lib
> + candidate instead of requiring all possible reuse rules to be listed at
> + build time.
> +
>  
>  
>  
> -- 
> 2.39.2LGTM, do we missed the timeline to merge code size reduction extensions 
> support in 
> gcc13?https://gcc.gnu.org/pipermail/gcc-patches/2023-April/615287.html

[PATCH] RISC-V/testsuite: Fix pr105666.c under rv32

[jiawei]

From: Jia-wei Chen 

In rv32 regression test, this cases will report an error:

"cc1: error: ABI requires '-march=rv32'"

Add '-mabi' option will fix this.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr105666.c: New options.

---
 gcc/testsuite/gcc.target/riscv/pr105666.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/riscv/pr105666.c 
b/gcc/testsuite/gcc.target/riscv/pr105666.c
index dd996eec8ef..752bbf1c017 100644
--- a/gcc/testsuite/gcc.target/riscv/pr105666.c
+++ b/gcc/testsuite/gcc.target/riscv/pr105666.c
@@ -7,7 +7,7 @@
 
 /* { dg-do compile } */
 /* { dg-require-effective-target hard_float } */
-/* { dg-options "-march=rv64g -ffast-math" } */
+/* { dg-options "-march=rv64g -mabi=lp64d -ffast-math" } */
 
 #define NITER 4
 #define NVARS 20
-- 
2.25.1

Re: Re: [PATCH] RISC-V: Add RVV registers register spilling

[jiawei]

> -原始邮件-
> 发件人: "Jeff Law" 
> 发送时间: 2022-11-21 23:26:37 (星期一)
> 收件人: "juzhe.zh...@rivai.ai" , schwab 

> 抄送: gcc-patches , "monk.chiang" 
, "kito.cheng" , jiawei 

> 主题: Re: [PATCH] RISC-V: Add RVV registers register spilling
> 
> 
> On 11/21/22 02:25, juzhe.zh...@rivai.ai wrote:
> > https://gcc.gnu.org/pipermail/gcc-patches/2022-November/606523.html
> > This patch obviously didn't include scalable size frame.
> > So it ICE in offset = 
cfun->machine->frame.gp_sp_offset.to_constant ();
> > We can't directly use to_constant if the frame is a scalable.
> > Please fix it or revert it. Thanks
> 
> We probably just need to reject everything in 
> riscv_get_setparate_components if the offset isn't constant. Something 
> like the attached patch (untested) might be enough to resolve the problem.
> 
> 
> Jeff
> 

I tested this patch and it fix that problem and works well, 
thanks for you works!

Jiawei

[PATCH] Testsuite: Add btf-dataset option for RISC-V.

[jiawei]

Add -msmall-data-limit option to put global and static data into right
section and generate 'btt_info' on RISC-V target.

BTF (BPF Type Format) is the metadata format which encodes the debug info 
related to BPF program/map, more details on:
https://www.kernel.org/doc/html/latest/bpf/index.html#bpf-type-format-btf

gcc/testsuite/ChangeLog:

* gcc.dg/debug/btf/btf-datasec-1.c: Add riscv target support.

---
 gcc/testsuite/gcc.dg/debug/btf/btf-datasec-1.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/testsuite/gcc.dg/debug/btf/btf-datasec-1.c 
b/gcc/testsuite/gcc.dg/debug/btf/btf-datasec-1.c
index dbb236bbda1..d54c8b1f63b 100644
--- a/gcc/testsuite/gcc.dg/debug/btf/btf-datasec-1.c
+++ b/gcc/testsuite/gcc.dg/debug/btf/btf-datasec-1.c
@@ -13,6 +13,7 @@
 /* { dg-options "-O0 -gbtf -dA" } */
 /* { dg-options "-O0 -gbtf -dA -msdata=none" { target { { powerpc*-*-* } && 
ilp32 } } } */
 /* { dg-options "-O0 -gbtf -dA -G0" { target { nios2-*-* } } } */
+/* { dg-options "-O0 -gbtf -dA -msmall-data-limit=2" { target { riscv*-*-* } } 
} */
 
 /* Check for two DATASEC entries with vlen 3, and one with vlen 1.  */
 /* { dg-final { scan-assembler-times "0xf03\[\t \]+\[^\n\]*btt_info" 2 } } 
*/
-- 
2.25.1

[PATCH] RISC-V: Change default ISA version into 20191213

[jiawei]

Bump default ISA spec to newer version 20191213, current default ISA spec
is 2.2, but it's already out of date for a long time, sync with binutils
ISA version, convention in toolchain use.

gcc/ChangeLog:

* config.gcc: Modify default isa_spec version.

---
 gcc/config.gcc | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f1b8d832c6f..47dc5a71917 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4641,12 +4641,12 @@ case "${target}" in
esac
 
case "${with_isa_spec}" in
-   ""|default|2.2)
-   tm_defines="${tm_defines} 
TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_2P2"
-   ;;
-   20191213 | 201912)
+   ""|default|20191213|201912)
tm_defines="${tm_defines} 
TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_20191213"
;;
+   2.2)
+   tm_defines="${tm_defines} 
TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_2P2"
+   ;;
20190608 | 201906)
tm_defines="${tm_defines} 
TARGET_DEFAULT_ISA_SPEC=ISA_SPEC_CLASS_20190608"
;;
-- 
2.25.1

[PATCH] RISC-V: Add Z*inx incompatible check in gcc.

[Jiawei]

Z*inx is conflict with float extensions, add incompatible check when
z*inx and hard_float both enabled.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_option_override): New check.

---
 gcc/config/riscv/riscv.cc | 4 
 1 file changed, 4 insertions(+)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 76eee4a55e9..162ba14d3c7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6285,6 +6285,10 @@ riscv_option_override (void)
   && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
 error ("z*inx requires ABI ilp32, ilp32e or lp64");
 
+  // Zfinx is conflict with float extensions.
+  if (TARGET_ZFINX && TARGET_HARD_FLOAT)
+error ("z*inx is conflict with float extensions");
+
   /* We do not yet support ILP32 on RV64.  */
   if (BITS_PER_WORD != POINTER_SIZE)
 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
-- 
2.25.1

[PATCH v2] RISC-V: Add Z*inx imcompatible check in gcc.

[Jiawei]

Z*inx is conflict with float extensions, add incompatible check when
z*inx and hard_float both enabled.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_option_override): New check.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-19.c: New test.

---
 gcc/config/riscv/riscv.cc| 4 
 gcc/testsuite/gcc.target/riscv/arch-19.c | 4 
 2 files changed, 8 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-19.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 76eee4a55e9..162ba14d3c7 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6285,6 +6285,10 @@ riscv_option_override (void)
   && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
 error ("z*inx requires ABI ilp32, ilp32e or lp64");
 
+  // Zfinx is conflict with float extensions.
+  if (TARGET_ZFINX && TARGET_HARD_FLOAT)
+error ("z*inx is conflict with float extensions");
+
   /* We do not yet support ILP32 on RV64.  */
   if (BITS_PER_WORD != POINTER_SIZE)
 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
diff --git a/gcc/testsuite/gcc.target/riscv/arch-19.c 
b/gcc/testsuite/gcc.target/riscv/arch-19.c
new file mode 100644
index 000..a6f72af3677
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-19.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64if_zfinx -mabi=lp64" } */
+int foo() {}
+/* { dg-error "z*inx is conflict with float extensions" "" { target *-*-* } 0 
} */
-- 
2.25.1

Re: Re: [PATCH v2] RISC-V: Add Z*inx imcompatible check in gcc.

[jiawei]

Hi Kito,

Thanks for your sugestions, I had added the new testcases in the new patch.
I feel it's hard to check long string name extension by use 
riscv_subset_list::parse,
Since it just check one char when the pointer moving, So I still keep the 
implement
by check the extenstison with target. Maybe we can add new check function in 
the new
version :)


> -原始邮件-
> 发件人: "Kito Cheng" 
> 发送时间: 2023-03-27 16:15:00 (星期一)
> 收件人: Jiawei 
> 抄送: gcc-patches@gcc.gnu.org, kito.ch...@sifive.com, pal...@dabbelt.com, 
christoph.muell...@vrull.eu, wuwei2...@iscas.ac.cn
> 主题: Re: [PATCH] RISC-V: Add Z*inx incompatible check in gcc.
> 
> HI Jiawei:
> 
> Thanks for the fix!
> 
> Two comments:
> - Could you add testcase like
> 
https://github.com/gcc-mirror/gcc/blob/master/gcc/testsuite/gcc.target/riscv/arch-12.c
> - And I would prefer those check happened in riscv_subset_list::parse
> @gcc/common/config/riscv/riscv-common.cc
> 
> On Sun, Mar 26, 2023 at 4:36 PM Jiawei  wrote:
> >
> > Z*inx is conflict with float extensions, add incompatible check when
> > z*inx and hard_float both enabled.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv.cc (riscv_option_override): New check.
> >
> > ---
> >  gcc/config/riscv/riscv.cc | 4 
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 76eee4a55e9..162ba14d3c7 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -6285,6 +6285,10 @@ riscv_option_override (void)
> >&& riscv_abi != ABI_LP64 && riscv_abi != 
ABI_ILP32E)
> >  error ("z*inx requires ABI ilp32, ilp32e or lp64");
> >
> > +  // Zfinx is conflict with float extensions.
> > +  if (TARGET_ZFINX && TARGET_HARD_FLOAT)
> > +error ("z*inx is conflict with float extensions");
> > +
> >/* We do not yet support ILP32 on RV64.  */
> >if (BITS_PER_WORD != POINTER_SIZE)
> >  error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);
> > --
> > 2.25.1
> >

[PATCH v3] RISC-V: Add Z*inx imcompatible check in gcc

[Jiawei]

Z*inx is conflict with float extensions, add incompatible check when
z*inx and f extension both enabled.

Since all float extension imply f extension and all z*inx extension 
imply zfinx extension, so we just need to check f with zfinx extension 
as the base case.

Co-Authored by: Kito Cheng 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
* New check.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-19.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  | 5 +
 gcc/testsuite/gcc.target/riscv/arch-19.c | 4 
 2 files changed, 9 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-19.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index ef221be1eb1..b3c6ec97e7a 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1153,6 +1153,11 @@ riscv_subset_list::parse (const char *arch, location_t 
loc)
 
   subset_list->handle_combine_ext ();
 
+  if (subset_list->lookup("zfinx") && subset_list->lookup("f"))
+   error_at (loc,
+   "%<-march=%s%>: z*inx is conflict with float extensions",
+   arch);
+
   return subset_list;
 
 fail:
diff --git a/gcc/testsuite/gcc.target/riscv/arch-19.c 
b/gcc/testsuite/gcc.target/riscv/arch-19.c
new file mode 100644
index 000..83c6e00a755
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-19.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64if_zfinx -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64if_zfinx': z\\*inx is conflict with float 
extensions" "" { target *-*-* } 0 } */
-- 
2.25.1

Re: Re: [PATCH v2] RISC-V: Add Z*inx imcompatible check in gcc.

[jiawei]

> -原始邮件-
> 发件人: "Jeff Law" 
> 发送时间: 2023-04-05 09:30:43 (星期三)
> 收件人: "Hans-Peter Nilsson" , Jiawei 
> 抄送: gcc-patches@gcc.gnu.org, kito.ch...@sifive.com, pal...@dabbelt.com, 
christoph.muell...@vrull.eu, wuwei2...@iscas.ac.cn
> 主题: Re: [PATCH v2] RISC-V: Add Z*inx imcompatible check in gcc.
> 
> 
> 
> On 4/3/23 19:46, Hans-Peter Nilsson wrote:
> > On Tue, 28 Mar 2023, Jiawei wrote:
> > 
> >> +  // Zfinx is conflict with float extensions.
> >> +  if (TARGET_ZFINX && TARGET_HARD_FLOAT)
> >> +error ("z*inx is conflict with float extensions");
> >> +
> > 
> > While I'm not a native English speaker, "is conflict with"
> > doesn't sound grammatically correct.  Perhaps "conflicts with"
> > or "is in conflict with"?
> "conflicts with" is better.
> 
> Jeff

Thanks for your reply, fixed in the trunk.

BR,
Jiawei

[PATCH 2/5] RISC-V: Enable compressible features when use ZC* extensions.

[Jiawei]

This patch enables the compressible features with ZC* extensions.

Since all ZC* extension depends on the Zca extension, it's sufficient to only
add the target Zca to extend the target RVC.

Co-Authored by: Mary Bennett 
Co-Authored by: Nandni Jamnadas 
Co-Authored by: Simon Cook 

gcc/ChangeLog:

* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
  Enable compressed builtins when ZC* extensions enabled.
* config/riscv/riscv-shorten-memrefs.cc:
  Enable shorten_memrefs pass when ZC* extensions enabled.
* config/riscv/riscv.cc (riscv_compressed_reg_p):
  Enable compressible registers when ZC* extensions enabled.
(riscv_rtx_costs):
  Allow adjusting rtx costs when ZC* extensions enabled.
(riscv_address_cost):
  Allow adjusting address cost when ZC* extensions enabled.
(riscv_first_stack_step):
  Allow compression of the register saves without
  adding extra instructions.
* config/riscv/riscv.h (FUNCTION_BOUNDARY):
  Adjusts function boundary to 16 bits when ZC* extensions enabled.
---
 gcc/config/riscv/riscv-c.cc   |  2 +-
 gcc/config/riscv/riscv-shorten-memrefs.cc |  3 ++-
 gcc/config/riscv/riscv.cc | 16 +---
 gcc/config/riscv/riscv.h  |  2 +-
 4 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 6ad562dcb8b..2937c160071 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -47,7 +47,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
 {
   builtin_define ("__riscv");
 
-  if (TARGET_RVC)
+  if (TARGET_RVC || TARGET_ZCA)
 builtin_define ("__riscv_compressed");
 
   if (TARGET_RVE)
diff --git a/gcc/config/riscv/riscv-shorten-memrefs.cc 
b/gcc/config/riscv/riscv-shorten-memrefs.cc
index 8f10d24ec39..27803e2c657 100644
--- a/gcc/config/riscv/riscv-shorten-memrefs.cc
+++ b/gcc/config/riscv/riscv-shorten-memrefs.cc
@@ -65,7 +65,8 @@ public:
   /* opt_pass methods: */
   virtual bool gate (function *)
 {
-  return TARGET_RVC && riscv_mshorten_memrefs && optimize > 0;
+  return (TARGET_RVC || TARGET_ZCA)
+ && riscv_mshorten_memrefs && optimize > 0;
 }
   virtual unsigned int execute (function *);
 
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5f542932d13..5f8cbfc15ed 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1118,8 +1118,9 @@ static bool
 riscv_compressed_reg_p (int regno)
 {
   /* x8-x15/f8-f15 are compressible registers.  */
-  return (TARGET_RVC && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
- || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15)));
+  return ((TARGET_RVC || TARGET_ZCA)
+ && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
+ || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15)));
 }
 
 /* Return true if x is an unsigned 5-bit immediate scaled by 4.  */
@@ -2323,8 +2324,9 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
  /* When optimizing for size, make uncompressible 32-bit addresses
 more expensive so that compressible 32-bit addresses are
 preferred.  */
- if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
- && !riscv_compressed_lw_address_p (XEXP (x, 0)))
+ if ((TARGET_RVC || TARGET_ZCA) && !speed && riscv_mshorten_memrefs
+ && mode == SImode
+ && !riscv_compressed_lw_address_p (XEXP (x, 0)))
cost++;
 
  *total = COSTS_N_INSNS (cost + tune_param->memory_cost);
@@ -2735,8 +2737,8 @@ riscv_address_cost (rtx addr, machine_mode mode,
 {
   /* When optimizing for size, make uncompressible 32-bit addresses more
* expensive so that compressible 32-bit addresses are preferred.  */
-  if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
-  && !riscv_compressed_lw_address_p (addr))
+  if ((TARGET_RVC || TARGET_ZCA) && !speed && riscv_mshorten_memrefs
+ && mode == SImode && !riscv_compressed_lw_address_p (addr))
 return riscv_address_insns (addr, mode, false) + 1;
   return riscv_address_insns (addr, mode, false);
 }
@@ -5202,7 +5204,7 @@ riscv_first_stack_step (struct riscv_frame_info *frame)
   && frame_total_constant_size % IMM_REACH >= min_first_step)
 return frame_total_constant_size % IMM_REACH;
 
-  if (TARGET_RVC)
+  if (TARGET_RVC || TARGET_ZCA)
 {
   /* If we need two subtracts, and one is small enough to allow compressed
 loads and stores, then put that one first.  */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 66fb07d6652..d05b1d59853 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -183,7 +183,7 @@ ASM_MISA_SPEC
 #define PARM_BOUNDARY BITS_PER_WORD
 
 /* Allocation bounda

[PATCH 3/5] RISC-V: Add ZC* test for march args being passed.

[Jiawei]

From: Charlie Keaney 

Add all ZC* extensions march args tests.

Co-Authored by: Nandni Jamnadas 
Co-Authored by: Jiawei 
Co-Authored by: Mary Bennett 
Co-Authored by: Simon Cook 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-20.c: New test.
* gcc.target/riscv/arch-21.c: New test.
* gcc.target/riscv/zc-zca-arch.c: New test.
* gcc.target/riscv/zc-zcb-arch.c: New test.
* gcc.target/riscv/zc-zcb-m-arch.c: New test.
* gcc.target/riscv/zc-zcb-zba-arch.c: New test.
* gcc.target/riscv/zc-zcb-zbb-arch.c: New test.
* gcc.target/riscv/zc-zcf-arch.c: New test.
* gcc.target/riscv/zc-zcmp-arch.c: New test.
* gcc.target/riscv/zc-zcmpe-arch.c: New test.
* gcc.target/riscv/zc-zcmt-arch.c: New test.
---
 gcc/testsuite/gcc.target/riscv/arch-20.c | 5 +
 gcc/testsuite/gcc.target/riscv/arch-21.c | 5 +
 gcc/testsuite/gcc.target/riscv/zc-zca-arch.c | 9 +
 gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c | 9 +
 gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c   | 9 +
 gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c | 9 +
 gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c | 9 +
 gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c | 9 +
 gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c| 9 +
 gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c   | 9 +
 gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c| 9 +
 11 files changed, 91 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-21.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c

diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c 
b/gcc/testsuite/gcc.target/riscv/arch-20.c
new file mode 100644
index 000..3be4ade65a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zcf -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" { 
target *-*-* } 0 } */
+/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" "" 
{ target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-21.c 
b/gcc/testsuite/gcc.target/riscv/arch-21.c
new file mode 100644
index 000..cecce06e474
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-21.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64if_zce -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64if_zce': zcf extension supports in rv32 only" "" { 
target *-*-* } 0 } */
+/* { dg-error "'-march=rv64if_zca_zcb_zce_zcf_zcmp_zcmt': zcf extension 
supports in rv32 only" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zca-arch.c 
b/gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
new file mode 100644
index 000..bcb8321e709
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zca -mabi=ilp32" } */
+
+int foo()
+{
+asm("c.sw x9, 32(x10)");
+}
+
+/* { dg-final { scan-assembler "c.sw x9, 32\\(x10\\)" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c 
b/gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
new file mode 100644
index 000..54d4dff63ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32i_zcb -mabi=ilp32" } */
+
+int foo()
+{
+asm("c.lbu x9,1(x8)");
+}
+
+/* { dg-final { scan-assembler "c.lbu x9,1\\(x8\\)" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c 
b/gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
new file mode 100644
index 000..f23fe304607
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32im_zcb -mabi=ilp32" } */
+
+int foo()
+{
+asm("c.lbu x9,1(x8)");
+}
+
+/* { dg-final { scan-assembler "c.lbu x9,1\\(x8\\)" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c 
b/gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c
new file mode 100644
index 000..6b4a8762078

[PATCH 0/5] RISC-V: Support ZC* extensions.

[Jiawei]

RISC-V Code Size Reduction(ZC*) extensions is a group of extensions 
which define subsets of the existing C extension (Zca, Zcd, Zcf) and new
extensions(Zcb, Zcmp, Zcmt) which only contain 16-bit encodings.[1]

The implementation of the RISC-V Code Size Reduction extension in GCC is
an important step towards making the RISC-V architecture more efficient.

The cooperation with OpenHW group has played a crucial role in this effort,
with facilitating the implementation, testing and validation. Currently
works can also find in OpenHW group's github repo.[2]

Thanks to Tariq Kurd, Ibrahim Abu Kharmeh for help with explain the 
specification, and Jeremy Bennett's patient guidance throughout the whole 
development process.

[1] github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification

[2] github.com/openhwgroup/corev-gcc

Co-Authored by: Charlie Keaney 
Co-Authored by: Mary Bennett 
Co-Authored by: Nandni Jamnadas 
Co-Authored by: Sinan Lin 
Co-Authored by: Simon Cook 
Co-Authored by: Shihua Liao 
Co-Authored by: Yulong Shi 

  RISC-V: Minimal support for ZC extensions.
  RISC-V: Enable compressible features when use ZC* extensions.
  RISC-V: Add ZC* test for march args being passed.
  RISC-V: Add Zcmp extension supports.
  RISC-V: Add ZCMP push/pop testcases.

 gcc/common/config/riscv/riscv-common.cc   |  39 ++
 gcc/config.gcc|   2 +-
 gcc/config/riscv/predicates.md|  16 +
 gcc/config/riscv/riscv-c.cc   |   2 +-
 gcc/config/riscv/riscv-opts.h |  16 +
 gcc/config/riscv/riscv-passes.def |   1 +
 gcc/config/riscv/riscv-protos.h   |   4 +
 gcc/config/riscv/riscv-shorten-memrefs.cc |   3 +-
 gcc/config/riscv/riscv-zcmp-popret.cc | 260 ++
 gcc/config/riscv/riscv.cc | 453 +-
 gcc/config/riscv/riscv.h  |   6 +-
 gcc/config/riscv/riscv.md |   3 +
 gcc/config/riscv/riscv.opt|   3 +
 gcc/config/riscv/t-riscv  |   4 +
 gcc/config/riscv/zc.md|  47 ++
 gcc/testsuite/gcc.target/riscv/arch-20.c  |   5 +
 gcc/testsuite/gcc.target/riscv/arch-21.c  |   5 +
 gcc/testsuite/gcc.target/riscv/zc-zca-arch.c  |   9 +
 gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c  |   9 +
 .../gcc.target/riscv/zc-zcb-m-arch.c  |   9 +
 .../gcc.target/riscv/zc-zcb-zba-arch.c|   9 +
 .../gcc.target/riscv/zc-zcb-zbb-arch.c|   9 +
 gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c  |   9 +
 gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c |   9 +
 .../gcc.target/riscv/zc-zcmp-push-pop-1.c |  15 +
 .../gcc.target/riscv/zc-zcmp-push-pop-2.c |  17 +
 .../gcc.target/riscv/zc-zcmp-push-pop-3.c |  17 +
 .../gcc.target/riscv/zc-zcmp-push-pop-4.c |  17 +
 .../gcc.target/riscv/zc-zcmp-push-pop-5.c |  17 +
 .../gcc.target/riscv/zc-zcmp-push-pop-6.c |  13 +
 .../gcc.target/riscv/zc-zcmp-push-pop-7.c |  16 +
 .../gcc.target/riscv/zc-zcmpe-arch.c  |   9 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-1.c|  15 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-2.c|  17 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-3.c|  17 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-4.c|  17 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-5.c|  17 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-6.c|  13 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-7.c|  16 +
 gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c |   9 +
 40 files changed, 1153 insertions(+), 21 deletions(-)
 create mode 100644 gcc/config/riscv/riscv-zcmp-popret.cc
 create mode 100644 gcc/config/riscv/zc.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-21.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-2.c
 create mode 10064

[PATCH 4/5] RISC-V: Add Zcmp extension supports.

[Jiawei]

Add Zcmp extension instructions support. Generate push/pop
with follow steps:

  1. preprocessing:
1.1. if there is no push rtx, then just return. e.g.
(note 5 1 22 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn/f 22 5 23 2 (set (reg/f:SI 2 sp)
  (plus:SI (reg/f:SI 2 sp)
(const_int -32 [0xffe0])))
(nil))
(note 23 22 2 2 NOTE_INSN_PROLOGUE_END)
1.2. if push rtx exists, then we compute the number of
pushed s-registers, n_sreg.

  push rtx should be find before NOTE_INSN_PROLOGUE_END tag

  [2 and 3 happend simultaneously]

  2. find valid move pattern, mv sN, aN, where N < n_sreg,
and aN is not used the move pattern, and sN is not
defined before the move pattern (from prologue to the
position of move pattern).

  3. analysis use and reach of every instruction from prologue
to the position of move pattern.
if any sN is used, then we mark the corresponding argument list
candidate as invalid.
e.g.
push  {ra,s0-s3}, {}, -32
sw  s0,44(sp) # s0 is used, then argument list is invalid
mv  a0,a5 # a0 is defined, then argument list is invalid
...
mv  s0,a0
mv  s1,a1
mv  s2,a2

  4. if there is a valid argument list, then replace the pop
push parallel insn, and delete mv pattern.
 if not, skip.

All "zcmpe" means Zcmp with RVE extension.
The push/pop instrunction implement is mostly finished by Sinan Lin.

Co-Authored by: Sinan Lin 
Co-Authored by: Simon Cook 
Co-Authored by: Shihua Liao 

gcc/ChangeLog:

* config.gcc: New object.
* config/riscv/predicates.md (riscv_stack_push_operation):
  New predicate.
(riscv_stack_pop_operation): Ditto.
(pop_return_value_constant): Ditto.
* config/riscv/riscv-passes.def (INSERT_PASS_AFTER): New pass.
* config/riscv/riscv-protos.h (riscv_output_popret_p):
  New routine.
(riscv_valid_stack_push_pop_p): Ditto.
(riscv_check_regno): Ditto.
(make_pass_zcmp_popret): New pass.
* config/riscv/riscv.cc (struct riscv_frame_info): New variable.
(riscv_output_popret_p): New function.
(riscv_print_pop_size): Ditto.
(riscv_print_reglist): Ditto.
(riscv_print_operand): New case symbols.
(riscv_save_push_pop_count): New function.
(riscv_push_pop_base_sp_adjust): Ditto.
(riscv_use_push_pop): Ditto.
(riscv_compute_frame_info): Adjust frame value.
(riscv_emit_pop_insn): New function.
(riscv_check_regno): Ditto.
(riscv_valid_stack_push_pop_p): Ditto.
(riscv_emit_push_insn): Ditto.
(riscv_expand_prologue): Modify frame pattern.
(riscv_expand_epilogue): Ditto.
* config/riscv/riscv.h (RETURN_VALUE_REGNUM):
(RISCV_ZCE_PUSH_POP_MASK): New mask.
(RISCV_ZCMPE_PUSH_POP_MASK): Ditto.
* config/riscv/riscv.md: Add new reg number and include info.
* config/riscv/t-riscv: New object rules.
* config/riscv/riscv-zcmp-popret.cc: New file.
* config/riscv/zc.md: New file.
---
 gcc/config.gcc|   2 +-
 gcc/config/riscv/predicates.md|  16 +
 gcc/config/riscv/riscv-passes.def |   1 +
 gcc/config/riscv/riscv-protos.h   |   4 +
 gcc/config/riscv/riscv-zcmp-popret.cc | 260 +++
 gcc/config/riscv/riscv.cc | 437 +-
 gcc/config/riscv/riscv.h  |   4 +
 gcc/config/riscv/riscv.md |   3 +
 gcc/config/riscv/t-riscv  |   4 +
 gcc/config/riscv/zc.md|  47 +++
 10 files changed, 767 insertions(+), 11 deletions(-)
 create mode 100644 gcc/config/riscv/riscv-zcmp-popret.cc
 create mode 100644 gcc/config/riscv/zc.md

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 629d324b5ef..a991c5273f9 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -529,7 +529,7 @@ pru-*-*)
;;
 riscv*)
cpu_type=riscv
-   extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o 
riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o"
+   extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o 
riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o 
riscv-zcmp-popret.o"
extra_objs="${extra_objs} riscv-vector-builtins.o 
riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
extra_objs="${extra_objs} thead.o"
d_target_objs="riscv-d.o"
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 0d9d7701c7e..6bff6cd047a 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -412,3 +412,19 @@
   (and (match_code "const_int")
(ior (match_operand 0 "not_uimm_extra_bit_operand")
(match_operand 0 "const_nottwobits_operand"
+
+(define_special_predicate "riscv_stack_push_operation"
+  (match_code "parallel")
+{
+  return riscv_valid_stack_push_pop_p (op, true);
+})
+
+(define_special_pr

[PATCH 1/5] RISC-V: Minimal support for ZC extensions.

[Jiawei]

This patch is the minimal support for ZC* extensions, include the extension
name, mask and target defination. Also define the dependencies with Zca
and Zce extension. Notes that all ZC* extensions depend on the Zca extension.
Zce includes all relevant ZC* extensions for microcontrollers using. Zce
will imply zcf when 'f' extension enabled in rv32.

Co-Authored by: Charlie Keaney 
Co-Authored by: Mary Bennett 
Co-Authored by: Nandni Jamnadas 
Co-Authored by: Simon Cook 
Co-Authored by: Sinan Lin 
Co-Authored by: Shihua Liao 
Co-Authored by: Yulong Shi 

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_subset_list::parse): New 
extensions.
* config/riscv/riscv-opts.h (MASK_ZCA): New mask.
(MASK_ZCB): Ditto.
(MASK_ZCE): Ditto.
(MASK_ZCF): Ditto.
(MASK_ZCD): Ditto.
(MASK_ZCMP): Ditto.
(MASK_ZCMT): Ditto.
(TARGET_ZCA): New target.
(TARGET_ZCB): Ditto.
(TARGET_ZCE): Ditto.
(TARGET_ZCF): Ditto.
(TARGET_ZCD): Ditto.
(TARGET_ZCMP): Ditto.
(TARGET_ZCMT): Ditto.
* config/riscv/riscv.opt: New target variable.
---
 gcc/common/config/riscv/riscv-common.cc | 39 +
 gcc/config/riscv/riscv-opts.h   | 16 ++
 gcc/config/riscv/riscv.opt  |  3 ++
 3 files changed, 58 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 2fc0f8bffc1..933c54edded 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -108,6 +108,16 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zhinx", "zhinxmin"},
   {"zhinxmin", "zfinx"},
 
+  {"zce",  "zca"},
+  {"zce",  "zcb"},
+  {"zce",  "zcmp"},
+  {"zce",  "zcmt"},
+  {"zcf",  "zca"},
+  {"zcd",  "zca"},
+  {"zcb",  "zca"},
+  {"zcmp", "zca"},
+  {"zcmt", "zca"},
+
   {NULL, NULL}
 };
 
@@ -219,6 +229,14 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zca",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcb",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zce",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcf",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcd",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1151,14 +1169,26 @@ riscv_subset_list::parse (const char *arch, location_t 
loc)
   subset_list->handle_implied_ext (itr);
 }
 
+  /* Zce only imply zcf when 'f' extension exist.  */
+  if (subset_list->lookup ("zce") != NULL
+   && subset_list->lookup ("f") != NULL
+   && subset_list->lookup ("zcf") == NULL)
+subset_list->add ("zcf", false);
+
   subset_list->handle_combine_ext ();
 
+  if (subset_list->lookup ("zcf") && subset_list->m_xlen == 64)
+error_at (loc, "%<-march=%s%>: zcf extension supports in rv32 only"
+ , arch);
+
   if (subset_list->lookup ("zfinx") && subset_list->lookup ("f"))
 error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point "
   "extensions", arch);
 
   return subset_list;
 
+
+
 fail:
   delete subset_list;
   return NULL;
@@ -1262,6 +1292,15 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
 
+  /* Code-size reduction extensions.  */
+  {"zca", &gcc_options::x_riscv_zc_subext, MASK_ZCA},
+  {"zcb", &gcc_options::x_riscv_zc_subext, MASK_ZCB},
+  {"zce", &gcc_options::x_riscv_zc_subext, MASK_ZCE},
+  {"zcf", &gcc_options::x_riscv_zc_subext, MASK_ZCF},
+  {"zcd", &gcc_options::x_riscv_zc_subext, MASK_ZCD},
+  {"zcmp",&gcc_options::x_riscv_zc_subext, MASK_ZCMP},
+  {"zcmt",&gcc_options::x_riscv_zc_subext, MASK_ZCMT},
+
   {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
   {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index cf0cd669be4..101d87d38b1 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -175,6 +175,22 @@ enum stack_protector_guard {
 #define MASK_ZMMUL  (1 << 0)
 #define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
 
+#define MASK_ZCA  (1 << 0)
+#define MASK_ZCB  (1 << 1)
+#define MASK_ZCE  (1 << 2)
+#define MASK_ZCF  (1 << 3)
+#define MASK_ZCD  (1 << 4)
+#define MASK_ZCMP (1 << 5)
+#define MASK_ZCMT (1 << 6)
+
+#define TARGET_ZCA((riscv_zc_subext & MASK_ZCA) != 0)
+#define TARGET_ZCB((riscv_zc_subext & MASK_ZCB) != 0)
+#define TARGET_ZCE((riscv_zc_subext & MASK_ZCE) != 0)
+#define TARGET_ZCF((riscv_zc_subext & MASK_ZCF) != 0)
+#define TARGET_ZCD((riscv_zc_subext & MASK_ZCD) != 0)
+#define TARGET_ZCMP   ((riscv_zc_subext & MASK_ZCMP) != 0)
+#define TARGET_ZCMT   ((riscv_zc_subext & MASK_ZCMT) != 0)
+
 #define MAS

[PATCH 5/5] RISC-V: Add ZCMP push/pop testcases.

[Jiawei]

Add Zcmp extension testcases, zcmpe means Zcmp with RVE extension.

Co-Authored by: Nandni Jamnadas 
Co-Authored by: Yulong Shi 
Co-Authored by: Shihua Liao 
Co-Authored by: Sinan Lin 

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zc-zcmp-push-pop-1.c: New test.
* gcc.target/riscv/zc-zcmp-push-pop-2.c: New test.
* gcc.target/riscv/zc-zcmp-push-pop-3.c: New test.
* gcc.target/riscv/zc-zcmp-push-pop-4.c: New test.
* gcc.target/riscv/zc-zcmp-push-pop-5.c: New test.
* gcc.target/riscv/zc-zcmp-push-pop-6.c: New test.
* gcc.target/riscv/zc-zcmp-push-pop-7.c: New test.
* gcc.target/riscv/zc-zcmpe-push-pop-1.c: New test.
* gcc.target/riscv/zc-zcmpe-push-pop-2.c: New test.
* gcc.target/riscv/zc-zcmpe-push-pop-3.c: New test.
* gcc.target/riscv/zc-zcmpe-push-pop-4.c: New test.
* gcc.target/riscv/zc-zcmpe-push-pop-5.c: New test.
* gcc.target/riscv/zc-zcmpe-push-pop-6.c: New test.
* gcc.target/riscv/zc-zcmpe-push-pop-7.c: New test.
---
 .../gcc.target/riscv/zc-zcmp-push-pop-1.c   | 15 +++
 .../gcc.target/riscv/zc-zcmp-push-pop-2.c   | 17 +
 .../gcc.target/riscv/zc-zcmp-push-pop-3.c   | 17 +
 .../gcc.target/riscv/zc-zcmp-push-pop-4.c   | 17 +
 .../gcc.target/riscv/zc-zcmp-push-pop-5.c   | 17 +
 .../gcc.target/riscv/zc-zcmp-push-pop-6.c   | 13 +
 .../gcc.target/riscv/zc-zcmp-push-pop-7.c   | 16 
 .../gcc.target/riscv/zc-zcmpe-push-pop-1.c  | 15 +++
 .../gcc.target/riscv/zc-zcmpe-push-pop-2.c  | 17 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-3.c  | 17 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-4.c  | 17 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-5.c  | 17 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-6.c  | 13 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-7.c  | 16 
 14 files changed, 224 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-7.c

diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-1.c 
b/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-1.c
new file mode 100644
index 000..58bb39438ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-1.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_zca_zcmp -mabi=lp64d -O0" } */
+
+int foo1(int a)
+{
+return a;
+}
+
+int foo2(int b)
+{
+return foo1(b);
+}
+
+/* { dg-final { scan-assembler "cm.push\t{ra,s0},-32" } } */
+/* { dg-final { scan-assembler "cm.popret\t{ra,s0},32" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-2.c 
b/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-2.c
new file mode 100644
index 000..2c692d80137
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32g_zca_zcmp -mabi=ilp32d -O2" } */
+
+void foo2 (int a, int b);
+
+int foo1(int a, int b)
+{ 
+if (b < a)
+{
+foo2(a, b);
+foo1(a, b);
+}
+return 0;
+}
+
+/* { dg-final { scan-assembler "cm.push\t{ra,s0-s1},-16" } } */
+/* { dg-final { scan-assembler "cm.popretz\t{ra,s0-s1},16" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-3.c 
b/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-3.c
new file mode 100644
index 000..ef22ce3d0f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-3.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32g_zca_zcmp -mabi=ilp32d -O2" } */
+
+void foo2 (int a, int b, int c, int d);
+
+int foo1(int a, int b, int c, int d)
+{ 
+if (b < a)
+{
+foo2(a, b, c, d);
+foo1(a, b, c, d);
+}
+return 0;
+}
+
+/* { dg-final { scan-assembler "cm.push\t{ra,s0-s3},-32" } } */
+/* { dg-final { scan-assembler "cm.popretz\t{ra,s0-s3},32" } } */
diff --git a/gcc/testsuite/gcc.target/

Re: [PATCH] hosthooks.h: Fix GCC_HOST_HOOKS_H typo

[Jiawei]

On Mon, Sep 23, 2024 at 10:12 AM Yangyu Chen
 wrote:
>//>/The comment of the final endif in hosthooks.h is wrong, it should be 
/>/GCC_HOST_HOOKS_H instead of GCC_LANG_HOOKS_H. /
This looks obvious to me. Do you have push access or do you need
someone to push this change for you?

Thanks,
Andrew

>//>/gcc/ChangeLog: />//>/* hosthooks.h (struct host_hooks): Fix GCC_HOST_HOOKS_H typo. />//>/Signed-off-by: Yangyu Chen 
 />/--- />/gcc/hosthooks.h | 2 +- />/1 file changed, 1 insertion(+), 1 deletion(-) />//>/diff --git 
a/gcc/hosthooks.h b/gcc/hosthooks.h />/index 53363801330..8178c9c692a 100644 />/--- a/gcc/hosthooks.h />/+++ b/gcc/hosthooks.h />/@@ -47,4 
+47,4 @@ struct host_hooks />//* Each host provides its own. */ />/extern const struct host_hooks host_hooks; />//>/-#endif /* 
GCC_LANG_HOOKS_H */ />/+#endif /* GCC_HOST_HOOKS_H */ />/-- />/2.45.2 />



Thanks, committed into trunk.

Jiawei

[PATCH 0/2] RISC-V: Support RISC-V Profiles.

[Jiawei]

This patch series introduces support for RISC-V Profiles RV20, RV22[1],
and RV23[2][3].The updates enhance compatibility and streamline the process
of leveraging RISC-V Profiles through the -march option. These additions
are in line with the RISC-V standard and facilitate the adoption of these
profiles in various development scenarios.

[1] https://github.com/riscv/riscv-profiles/releases/tag/v1.0
[2] 
https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-v0.7-ratification-vote
[3] 
https://riscv.org/announcements/2024/10/risc-v-announces-ratification-of-the-rva23-profile-standard/

Jiawei (2):
  RISC-V: Support RISC-V Profiles RV20/22.
  RISC-V: Support RISC-V Profiles RVA/B23.

 gcc/common/config/riscv/riscv-common.cc  | 91 +++-
 gcc/config/riscv/riscv-subset.h  |  2 +
 gcc/testsuite/gcc.target/riscv/arch-45.c |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-46.c | 12 
 gcc/testsuite/gcc.target/riscv/arch-47.c | 12 
 gcc/testsuite/gcc.target/riscv/arch-48.c | 11 +++
 gcc/testsuite/gcc.target/riscv/arch-49.c | 10 +++
 7 files changed, 142 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-46.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-47.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-48.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-49.c

-- 
2.43.0

[PATCH 1/2] RISC-V: Support RISC-V Profiles RV20/22.

[Jiawei]

This patch introduces support for RISC-V Profiles RV20 and RV22 [1],
enabling developers to utilize these profiles through the -march option.

[1] https://github.com/riscv/riscv-profiles/releases/tag/v1.0

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (struct riscv_profiles): New 
struct.
(riscv_subset_list::parse_profiles): New parser.
(riscv_subset_list::parse_base_ext): Ditto.
* config/riscv/riscv-subset.h: New def.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-45.c: New test.
* gcc.target/riscv/arch-46.c: New test.
* gcc.target/riscv/arch-47.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  | 75 +++-
 gcc/config/riscv/riscv-subset.h  |  2 +
 gcc/testsuite/gcc.target/riscv/arch-45.c |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-46.c | 12 
 gcc/testsuite/gcc.target/riscv/arch-47.c | 12 
 5 files changed, 105 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-46.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-47.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 4c9a72d1180..fe4c6d95c0d 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -238,6 +238,12 @@ struct riscv_ext_version
   int minor_version;
 };
 
+struct riscv_profiles
+{
+  const char *profile_name;
+  const char *profile_string;
+};
+
 /* All standard extensions defined in all supported ISA spec.  */
 static const struct riscv_ext_version riscv_ext_version_table[] =
 {
@@ -457,6 +463,31 @@ static const struct riscv_ext_version riscv_combine_info[] 
=
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
 
+/* This table records the mapping form RISC-V Profiles into march string.  */
+static const riscv_profiles riscv_profiles_table[] =
+{
+  /* RVI20U only contains the base extension 'i' as mandatory extension.  */
+  {"RVI20U64", "rv64i"},
+  {"RVI20U32", "rv32i"},
+
+  /* RVA20U contains the 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,
+ zicclsm,za128rs' as mandatory extensions.  */
+  {"RVA20U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_za128rs"},
+
+  /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
+ zihpm,ziccif,ziccrse,ziccamoa, zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,
+ zfhmin,zkt' as mandatory extensions.  */
+  {"RVA22U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt"},
+
+  /* Currently we do not define S/M mode Profiles in gcc part.  */
+
+  /* Terminate the list.  */
+  {NULL, NULL}
+};
+
 static const riscv_cpu_info riscv_cpu_tables[] =
 {
 #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -1064,6 +1095,46 @@ riscv_subset_list::parsing_subset_version (const char 
*ext,
   return p;
 }
 
+/* Parsing RISC-V Profiles in -march string.
+   Return string with mandatory extensions of Profiles.  */
+const char *
+riscv_subset_list::parse_profiles (const char *p)
+{
+  /* Checking if input string contains a Profiles.
+ There are two cases use Profiles in -march option:
+
+ 1. Only use Profiles as -march input
+ 2. Mixed Profiles with other extensions
+
+ Use '+' to split Profiles and other extension.  */
+  for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i)
+{
+  const char *match = strstr (p, riscv_profiles_table[i].profile_name);
+  const char *plus_ext = strchr (p, '+');
+  /* Find profile at the begin.  */
+  if (match != NULL && match == p)
+   {
+ /* If there's no '+' sign, return the profile_string directly.  */
+ if (!plus_ext)
+   return riscv_profiles_table[i].profile_string;
+ /* If there's a '+' sign, need to add profiles with other ext.  */
+ else
+ {
+   size_t arch_len = strlen (riscv_profiles_table[i].profile_string)
+ + strlen (plus_ext);
+   /* Reset the input string with Profiles mandatory extensions,
+  end with '_' to connect other additional extensions.  */
+   char *result = new char[arch_len + 2];
+   strcpy (result, riscv_profiles_table[i].profile_string);
+   strcat (result, "_");
+   strcat (result, plus_ext + 1); /* skip the '+'.  */
+   return result;
+ }
+   }
+}
+  return p;
+}
+
 /* Parsing function for base extensions, rv[32|64][i|e|g]
 
Return Value:
@@ -1078,6 +1149,8 @@ riscv_subset_list::parse_base_ext (const char *p)
   unsigned minor_version = 0;
   bool explicit_version_p = false;
 
+  p = parse_profiles(p);
+
   if (startswith (p, "rv32"))
 {
   m_xlen = 32;
@@ -1090,7 +1163,7 @@ riscv_subset_list::parse_base_ext (const char *p)
 }
   else
 {
-  error_at (m_loc, "%<-march=%s%>: ISA string must begin with rv3

[PATCH 2/2] RISC-V: Support RISC-V Profiles RVA/B23.

[Jiawei]

This patch introduces support for RISC-V Profiles RV23A and RV23B [1],
enabling developers to utilize these profiles through the -march option.

[1] 
https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-v0.7-ratification-vote

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New profile.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-48.c: New test.
* gcc.target/riscv/arch-49.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  | 16 
 gcc/testsuite/gcc.target/riscv/arch-48.c | 11 +++
 gcc/testsuite/gcc.target/riscv/arch-49.c | 10 ++
 3 files changed, 37 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-48.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-49.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index fe4c6d95c0d..92052adca54 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -482,6 +482,22 @@ static const riscv_profiles riscv_profiles_table[] =
"_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
"_zicboz_zfhmin_zkt"},
 
+  /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension
+ 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions.  */
+  {"RVA23U64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
+  /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
+ 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions.  */
+  {"RVB23U64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
   /* Currently we do not define S/M mode Profiles in gcc part.  */
 
   /* Terminate the list.  */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-48.c 
b/gcc/testsuite/gcc.target/riscv/arch-48.c
new file mode 100644
index 000..0bbb3242ddd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-48.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=RVA23U64 -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0"
+_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0"
+_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0"
+_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0"
+_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-49.c 
b/gcc/testsuite/gcc.target/riscv/arch-49.c
new file mode 100644
index 000..459b5641ca3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-49.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=RVB23U64 -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0"
+"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0"
+"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0"
+"_zbb1p0_zbs1p0_zkt1p0\"" } } */
-- 
2.43.0

Re: [PATCH 2/2] RISC-V: Support RISC-V Profiles RVA/B23.

[Jiawei]

在 2024/12/3 23:54, Palmer Dabbelt 写道:

On Tue, 03 Dec 2024 03:02:47 PST (-0800), jia...@iscas.ac.cn wrote:

This patch introduces support for RISC-V Profiles RV23A and RV23B [1],
enabling developers to utilize these profiles through the -march option.

[1] 
https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-v0.7-ratification-vote


gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New profile.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-48.c: New test.
* gcc.target/riscv/arch-49.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  | 16 
 gcc/testsuite/gcc.target/riscv/arch-48.c | 11 +++
 gcc/testsuite/gcc.target/riscv/arch-49.c | 10 ++
 3 files changed, 37 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-48.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-49.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc

index fe4c6d95c0d..92052adca54 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -482,6 +482,22 @@ static const riscv_profiles 
riscv_profiles_table[] =

"_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
    "_zicboz_zfhmin_zkt"},

+  /* RVA23 contains all mandatory base ISA for RVA22U64 and the new 
extension
+ 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as 
mandatory

+ extensions.  */
+  {"RVA23U64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+ 
"_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"

+   "_zfa_zawrs"},


We talked about this at the Cauldron, but I forget if we actually 
ended up saying anything on the mailing lists.  IIRC the general 
conclusion here was that we should take advantage of all the RVA22/23 
mandatory features, even if they're defacto not implemented in 
shipping systems -- in other words, just generate code that crashes 
now rather than trying to start working around vendors who ignore the 
requirements.


So specifically I'm thinking of the misaligned access stuff here.

I believe this discussion pertains to the Zicclsm extension. As you say, 
attempting to address misaligned access for non-compliant systems 
introduces significant maintenance burdens and risks diluting the 
clarity of the standard. Instead, allowing such issues to result in 
crashes might serve to emphasize the importance of compliance with 
RVA22/23 requirements.


Do you have any suggestions or thoughts on how we should handle this 
situation?



BR,

Jiawei



+
+  /* RVB23 contains all mandatory base ISA for RVA22U64 and the new 
extension

+ 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions.  */
+  {"RVB23U64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+ "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
   /* Currently we do not define S/M mode Profiles in gcc part. */

   /* Terminate the list.  */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-48.c 
b/gcc/testsuite/gcc.target/riscv/arch-48.c

new file mode 100644
index 000..0bbb3242ddd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-48.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=RVA23U64 -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0" 

+_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0" 

+_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0" 

+_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0" 


+_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-49.c 
b/gcc/testsuite/gcc.target/riscv/arch-49.c

new file mode 100644
index 000..459b5641ca3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-49.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=RVB23U64 -mabi=lp64" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0" 

+"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0" 

+"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0" 


+"_zbb1p0_zbs1p0_zkt1p0\"" } } */

Re: [PATCH 1/2] RISC-V: Support RISC-V Profiles RV20/22.

[Jiawei]

在 2024/12/15 23:50, Jeff Law 写道:



On 12/3/24 4:02 AM, Jiawei wrote:

This patch introduces support for RISC-V Profiles RV20 and RV22 [1],
enabling developers to utilize these profiles through the -march option.

[1] https://github.com/riscv/riscv-profiles/releases/tag/v1.0

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (struct riscv_profiles): 
New struct.

(riscv_subset_list::parse_profiles): New parser.
(riscv_subset_list::parse_base_ext): Ditto.
* config/riscv/riscv-subset.h: New def.


[ ... ]



+const char *
+riscv_subset_list::parse_profiles (const char *p)
+{
+  /* Checking if input string contains a Profiles.
+ There are two cases use Profiles in -march option:
+
+ 1. Only use Profiles as -march input
+ 2. Mixed Profiles with other extensions
+
+ Use '+' to split Profiles and other extension.  */
Does LLVM use this same convention (using '+' to split profiles from 
additional extensions)?  I don't see it in the spec so I think we 
really need to make sure LLVM and GCC are in sync on this.


I think we need some kind of documentation around the new option in 
invoke.texi.


I didn't check the precise set of options in the spec.  That should be 
double-checked in the expected update of this patchkit.



jeff


In fact, we do have a PR in 
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36 to 
discuss the format, but it was out of date, I will pick up it, and 
update the format doc first in


recent days.


BR,
Jiawei

[PATCH 1/2] RISC-V: Update Xsfvfnrclip implementation.

[Jiawei]

gcc/ChangeLog:

* config/riscv/genrvv-type-indexer.cc (expand_floattype): New func.
(main):
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_XFQF_OPS):
(vint8mf8_t):
(vint8mf4_t):
(vint8mf2_t):
(vint8m1_t):
(vint8m2_t):
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_XFQF_OPS):
(rvv_arg_type_info::get_xfqf_float_type):
* config/riscv/riscv-vector-builtins.def (xfqf_vector):
(xfqf_float):
* config/riscv/riscv-vector-builtins.h (struct rvv_arg_type_info):
* config/riscv/sifive-vector.md:
* config/riscv/vector-iterators.md:

---
 gcc/config/riscv/genrvv-type-indexer.cc   | 17 ++
 .../riscv/riscv-vector-builtins-types.def | 13 
 gcc/config/riscv/riscv-vector-builtins.cc | 33 +++
 gcc/config/riscv/riscv-vector-builtins.def|  4 ++-
 gcc/config/riscv/riscv-vector-builtins.h  |  1 +
 gcc/config/riscv/sifive-vector.md | 10 +++---
 gcc/config/riscv/vector-iterators.md  | 25 +++---
 7 files changed, 78 insertions(+), 25 deletions(-)

diff --git a/gcc/config/riscv/genrvv-type-indexer.cc 
b/gcc/config/riscv/genrvv-type-indexer.cc
index e1eee34237a..a2974269adc 100644
--- a/gcc/config/riscv/genrvv-type-indexer.cc
+++ b/gcc/config/riscv/genrvv-type-indexer.cc
@@ -164,6 +164,18 @@ floattype (unsigned sew, int lmul_log2)
   return mode.str ();
 }
 
+std::string
+expand_floattype (unsigned sew, int lmul_log2, unsigned nf)
+{
+  if (sew != 8 || nf!= 1
+  || (!valid_type (sew * 4, lmul_log2 + 2, /*float_t*/ true)))
+return "INVALID";
+
+  std::stringstream mode;
+  mode << "vfloat" << sew * 4 << to_lmul (lmul_log2 + 2) << "_t";
+  return mode.str ();
+}
+
 std::string
 floattype (unsigned sew, int lmul_log2, unsigned nf)
 {
@@ -276,6 +288,7 @@ main (int argc, const char **argv)
   fprintf (fp, "  /*QLMUL1*/ INVALID,\n");
   fprintf (fp, "  /*QLMUL1_SIGNED*/ INVALID,\n");
   fprintf (fp, "  /*QLMUL1_UNSIGNED*/ INVALID,\n");
+  fprintf (fp, "  /*XFQF*/ INVALID,\n");
   for (unsigned eew : {8, 16, 32, 64})
fprintf (fp, "  /*EEW%d_INTERPRET*/ INVALID,\n", eew);
 
@@ -384,6 +397,8 @@ main (int argc, const char **argv)
 inttype (8, /*lmul_log2*/ 0, false).c_str ());
fprintf (fp, "  /*QLMUL1_UNSIGNED*/ %s,\n",
 inttype (8, /*lmul_log2*/ 0, true).c_str ());
+   fprintf (fp, "  /*XFQF*/ %s,\n",
+expand_floattype (sew, lmul_log2, nf).c_str ());
for (unsigned eew : {8, 16, 32, 64})
  {
if (eew == sew)
@@ -473,6 +488,7 @@ main (int argc, const char **argv)
 bfloat16_wide_type (/*lmul_log2*/ 0).c_str ());
fprintf (fp, "  /*QLMUL1_SIGNED*/ INVALID,\n");
fprintf (fp, "  /*QLMUL1_UNSIGNED*/ INVALID,\n");
+   fprintf (fp, "  /*XFQF*/ INVALID,\n");
for (unsigned eew : {8, 16, 32, 64})
  fprintf (fp, "  /*EEW%d_INTERPRET*/ INVALID,\n", eew);
 
@@ -558,6 +574,7 @@ main (int argc, const char **argv)
   floattype (sew / 4, /*lmul_log2*/ 0).c_str ());
  fprintf (fp, "  /*QLMUL1_SIGNED*/ INVALID,\n");
  fprintf (fp, "  /*QLMUL1_UNSIGNED*/ INVALID,\n");
+ fprintf (fp, "  /*XFQF*/ INVALID,\n");
  for (unsigned eew : {8, 16, 32, 64})
fprintf (fp, "  /*EEW%d_INTERPRET*/ INVALID,\n", eew);
 
diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
b/gcc/config/riscv/riscv-vector-builtins-types.def
index 96412bfd1a5..df55b6a8823 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -363,6 +363,12 @@ along with GCC; see the file COPYING3. If not see
 #define DEF_RVV_QMACC_OPS(TYPE, REQUIRE)
 #endif
 
+/* Use "DEF_RVV_XFQF_OPS" macro include signed integer which will
+   be iterated and registered as intrinsic functions.  */
+#ifndef DEF_RVV_XFQF_OPS
+#define DEF_RVV_XFQF_OPS(TYPE, REQUIRE)
+#endif
+
 DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 DEF_RVV_I_OPS (vint8mf4_t, 0)
 DEF_RVV_I_OPS (vint8mf2_t, 0)
@@ -1451,6 +1457,12 @@ DEF_RVV_QMACC_OPS (vint32m2_t, 0)
 DEF_RVV_QMACC_OPS (vint32m4_t, 0)
 DEF_RVV_QMACC_OPS (vint32m8_t, 0)
 
+DEF_RVV_XFQF_OPS (vint8mf8_t, 0)
+DEF_RVV_XFQF_OPS (vint8mf4_t, 0)
+DEF_RVV_XFQF_OPS (vint8mf2_t, 0)
+DEF_RVV_XFQF_OPS (vint8m1_t, 0)
+DEF_RVV_XFQF_OPS (vint8m2_t, 0)
+
 #undef DEF_RVV_I_OPS
 #undef DEF_RVV_U_OPS
 #undef DEF_RVV_F_OPS
@@ -1506,3 +1518,4 @@ DEF_RVV_QMACC_OPS (vint32m8_t, 0)
 #undef DEF_RVV_CRYPTO_SEW64_OPS
 #undef DEF_RVV_F32_OPS
 #undef DEF_RVV_QMACC_OPS
+#undef DEF_RVV_XFQF_OPS
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc 
b/gcc/config/riscv/riscv-vector-builtins.cc
index b9b9d33adab..37c9f71fa85 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -551,6 +551,12 @@ static const rvv_type_info qmacc_ops[]

[PATCH 2/2] RISC-V: Update Xsfvqmacc and Xsfvfnrclip's testcases

[Jiawei]

From: Liao Shihua 

---
 gcc/config/riscv/vector.md|  7 ++-
 .../riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c  | 60 ++
 .../riscv/rvv/xsfvector/sf_vfnrclip_xu_f_qf.c | 63 ++-
 .../riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c | 16 +
 .../riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c | 16 +
 .../riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c   | 17 +
 .../riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c   | 17 +
 .../riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c| 16 +
 .../riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c| 17 +
 .../riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c   | 17 +
 .../riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c   | 17 +
 11 files changed, 259 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 58406f3d17c..d24916d2caf 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -56,7 +56,8 @@
  
vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,\
  
vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
  
vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\
- vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
+ vfncvtbf16,vfwcvtbf16,vfwmaccbf16,\
+ sf_vqmacc,sf_vfnrclip")
 (const_string "true")]
(const_string "false")))
 
@@ -893,7 +894,7 @@
  
vfredo,vfwredu,vfwredo,vslideup,vslidedown,vislide1up,\
  
vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
  
vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll,vclmul,vclmulh,\
- vfwmaccbf16")
+ vfwmaccbf16,sf_vqmacc,sf_vfnrclip")
   (symbol_ref "riscv_vector::get_ta(operands[6])")
 
 (eq_attr "type" "vimuladd,vfmuladd")
@@ -924,7 +925,7 @@
  vfwalu,vfwmul,vfsgnj,vfcmp,vslideup,vslidedown,\
  
vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,\
  
viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox,vandn,vrol,\
-  vror,vwsll,vclmul,vclmulh,vfwmaccbf16")
+ 
vror,vwsll,vclmul,vclmulh,vfwmaccbf16,sf_vqmacc,sf_vfnrclip")
   (symbol_ref "riscv_vector::get_ma(operands[7])")
 
 (eq_attr "type" "vimuladd,vfmuladd")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c
index 813f7860f64..a4193b5aea9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c
@@ -7,6 +7,7 @@
 /*
 ** test_sf_vfnrclip_x_f_qf_i8mf8_vint8mf8_t:
 ** ...
+** vsetivli\s+zero+,0+,e8+,mf8+,ta+,ma+
 ** sf\.vfnrclip\.x\.f\.qf\tv[0-9]+,v[0-9]+,fa[0-9]+
 ** ...
 */
@@ -17,6 +18,7 @@ vint8mf8_t 
test_sf_vfnrclip_x_f_qf_i8mf8_vint8mf8_t(vfloat32mf2_t vs2, float rs1
 /*
 ** test_sf_vfnrclip_x_f_qf_i8mf4_vint8mf4_t:
 ** ...
+** vsetivli\s+zero+,0+,e8+,mf4+,ta+,ma+
 ** sf\.vfnrclip\.x\.f\.qf\tv[0-9]+,v[0-9]+,fa[0-9]+
 ** ...
 */
@@ -27,6 +29,7 @@ vint8mf4_t 
test_sf_vfnrclip_x_f_qf_i8mf4_vint8mf4_t(vfloat32m1_t vs2, float rs1,
 /*
 ** test_sf_vfnrclip_x_f_qf_i8mf2_vint8mf2_t:
 ** ...
+** vsetivli\s+zero+,0+,e8+,mf2+,ta+,ma+
 ** sf\.vfnrclip\.x\.f\.qf\tv[0-9]+,v[0-9]+,fa[0-9]+
 ** ...
 */
@@ -37,6 +40,7 @@ vint8mf2_t 
test_sf_vfnrclip_x_f_qf_i8mf2_vint8mf2_t(vfloat32m2_t vs2, float rs1,
 /*
 ** test_sf_vfnrclip_x_f_qf_i8m1_vint8m1_t:
 ** ...
+** vsetivli\s+zero+,0+,e8+,m1+,ta+,ma+
 ** sf\.vfnrclip\.x\.f\.qf\tv[0-9]+,v[0-9]+,fa[0-9]+
 ** ...
 */
@@ -47,6 +51,7 @@ vint8m1_t test_sf_vfnrclip_x_f_qf_i8m1_vint8m1_t(vfloat32m4_t 
vs2, float rs1, si
 /*
 ** test_sf_vfnrclip_x_f_qf_i8m2_vint8m2_t:
 ** ...
+** vsetivli\s+zero+,0+,e8+,m2+,ta+,ma+
 ** sf\.vfnrclip\.x\.f\.qf\tv[0-9]+,v[0-9]+,fa[0-9]+
 ** ...
 */
@@ -57,6 +62,7 @@ vint8m2_t test_sf_vfnrclip_x_f_qf_i8m2_vint8m2_t(vfloat32m8_t 
vs2, float rs1, si
 /*
 ** test_sf_vfnrclip_x_f_qf_i8mf8_m_vint8mf8_t:
 ** ...
+** vsetivli\s+zero+,0+,e8+,mf8+,ta+,ma+
 ** sf\.vfnrclip\.x\.f\.qf\tv[0-9]+,v[0-9]+,fa[0-9]+,v0.t
 ** ...
 */
@@ -67,6 +73,7 @@ vint8mf8_t 
test_sf_vfnrclip_x_f_qf_i8mf8_m_vint8mf8_t(vbool64_t mask, vfloat32mf
 /*
 ** test_sf_vfnrclip_x_f_qf_i8mf4_m_vint8mf4_t:
 ** ...
+** vsetivli\s+zero+,0+,e8+,mf4+,ta+,ma+
 ** sf\.vfnrclip\.x\.f\.qf\tv[0-9]+,v[0-9]+,fa[0-9]+,v0.t
 ** ...
 */
@@ -77,6 +84,7 @@ vint8mf4_t 
test_sf_vfnrclip_x_f_qf_i8mf4_m_vint8mf4_t(vbool32_t mask, vfloat32m1
 /*
 ** test_sf_vfnrclip_x_f_qf_i8mf2_m_vint8mf2_t:
 ** ...
+** vsetivli\s+zero+,0+,e8+,mf2+,ta+,ma+
 ** sf\.vfnrclip\.x\.f\.qf\tv[0-9]+,v[0-9]+,fa[0-9]+,v0.t
 ** ...
 */
@@ -87,6 +95,7 @@ vint8mf2_t 
test_sf_vfnrclip_x_f_qf_i8mf2_m_vint8mf2_t(vbool16_t mask, vfloat32m2
 /*
 ** test_sf_vfnrclip_x_

[PATCH v3 2/2] RISC-V: Update Xsfvqmacc and Xsfvfnrclip's testcases

[Jiawei]

From: Liao Shihua 

Update Sifive Xsfvqmacc and Xsfvfnrclip extension's testcases.

version log:
Update synchronize LMUL settings with return type.

gcc/ChangeLog:

* config/riscv/vector.md: New attr set.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c: Add vsetivli 
checking.
* gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_xu_f_qf.c: Ditto.
* gcc.target/riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c: Ditto.
* gcc.target/riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c: Ditto.
* gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c: Ditto.
* gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c: Ditto.
* gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c: Ditto.
* gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c: Ditto.
* gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c: Ditto.
* gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c: Ditto.

---
 gcc/config/riscv/vector.md|  7 ++-
 .../riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c  | 60 ++
 .../riscv/rvv/xsfvector/sf_vfnrclip_xu_f_qf.c | 63 ++-
 .../riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c | 16 +
 .../riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c | 16 +
 .../riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c   | 17 +
 .../riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c   | 17 +
 .../riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c| 16 +
 .../riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c| 17 +
 .../riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c   | 17 +
 .../riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c   | 17 +
 11 files changed, 259 insertions(+), 4 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 58406f3d17c..d24916d2caf 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -56,7 +56,8 @@
  
vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,\
  
vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
  
vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\
- vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
+ vfncvtbf16,vfwcvtbf16,vfwmaccbf16,\
+ sf_vqmacc,sf_vfnrclip")
 (const_string "true")]
(const_string "false")))
 
@@ -893,7 +894,7 @@
  
vfredo,vfwredu,vfwredo,vslideup,vslidedown,vislide1up,\
  
vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
  
vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll,vclmul,vclmulh,\
- vfwmaccbf16")
+ vfwmaccbf16,sf_vqmacc,sf_vfnrclip")
   (symbol_ref "riscv_vector::get_ta(operands[6])")
 
 (eq_attr "type" "vimuladd,vfmuladd")
@@ -924,7 +925,7 @@
  vfwalu,vfwmul,vfsgnj,vfcmp,vslideup,vslidedown,\
  
vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,\
  
viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox,vandn,vrol,\
-  vror,vwsll,vclmul,vclmulh,vfwmaccbf16")
+ 
vror,vwsll,vclmul,vclmulh,vfwmaccbf16,sf_vqmacc,sf_vfnrclip")
   (symbol_ref "riscv_vector::get_ma(operands[7])")
 
 (eq_attr "type" "vimuladd,vfmuladd")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c 
b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c
index 813f7860f64..a4193b5aea9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c
@@ -7,6 +7,7 @@
 /*
 ** test_sf_vfnrclip_x_f_qf_i8mf8_vint8mf8_t:
 ** ...
+** vsetivli\s+zero+,0+,e8+,mf8+,ta+,ma+
 ** sf\.vfnrclip\.x\.f\.qf\tv[0-9]+,v[0-9]+,fa[0-9]+
 ** ...
 */
@@ -17,6 +18,7 @@ vint8mf8_t 
test_sf_vfnrclip_x_f_qf_i8mf8_vint8mf8_t(vfloat32mf2_t vs2, float rs1
 /*
 ** test_sf_vfnrclip_x_f_qf_i8mf4_vint8mf4_t:
 ** ...
+** vsetivli\s+zero+,0+,e8+,mf4+,ta+,ma+
 ** sf\.vfnrclip\.x\.f\.qf\tv[0-9]+,v[0-9]+,fa[0-9]+
 ** ...
 */
@@ -27,6 +29,7 @@ vint8mf4_t 
test_sf_vfnrclip_x_f_qf_i8mf4_vint8mf4_t(vfloat32m1_t vs2, float rs1,
 /*
 ** test_sf_vfnrclip_x_f_qf_i8mf2_vint8mf2_t:
 ** ...
+** vsetivli\s+zero+,0+,e8+,mf2+,ta+,ma+
 ** sf\.vfnrclip\.x\.f\.qf\tv[0-9]+,v[0-9]+,fa[0-9]+
 ** ...
 */
@@ -37,6 +40,7 @@ vint8mf2_t 
test_sf_vfnrclip_x_f_qf_i8mf2_vint8mf2_t(vfloat32m2_t vs2, float rs1,
 /*
 ** test_sf_vfnrclip_x_f_qf_i8m1_vint8m1_t:
 ** ...
+** vsetivli\s+zero+,0+,e8+,m1+,ta+,ma+
 ** sf\.vfnrclip\.x\.f\.qf\tv[0-9]+,v[0-9]+,fa[0-9]+
 ** ...
 */
@@ -47,6 +51,7 @@ vint8m1_t test_sf_vfnrclip_x_f_qf_i8m1_vint8m1_t(vfloat32m4_t 
vs2, float rs1, si
 /*
 ** test_sf_vfnrclip_x_f_qf_i8m2_vint8m2_t:
 ** ...
+** vsetivli\s+zero+,0+,e8+,m2+,ta+,ma+
 ** sf\.vfnrclip\.x\.f\.qf\tv[0-9]+,v[0-9]+,fa[0-9]+
 ** ...
 */
@@ -57,

[PATCH v3 1/2] RISC-V: Update Xsfvfnrclip implementation.

[Jiawei]

Update implementation of Xsfvfnrclip, using return type as iterator.

gcc/ChangeLog:

* config/riscv/genrvv-type-indexer.cc (expand_floattype): New func.
(main): New type.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_XFQF_OPS): New 
def.
(vint8mf8_t): Ditto.
(vint8mf4_t): Ditto.
(vint8mf2_t): Ditto.
(vint8m1_t): Ditto.
(vint8m2_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_XFQF_OPS): Ditto.
(rvv_arg_type_info::get_xfqf_float_type): Ditto.
* config/riscv/riscv-vector-builtins.def (xfqf_vector): Ditto.
(xfqf_float): Ditto.
* config/riscv/riscv-vector-builtins.h
*(struct rvv_arg_type_info): New function prototype.
* config/riscv/sifive-vector.md: Update iterator.
* config/riscv/vector-iterators.md: Ditto.

---
 gcc/config/riscv/genrvv-type-indexer.cc   | 17 ++
 .../riscv/riscv-vector-builtins-types.def | 13 
 gcc/config/riscv/riscv-vector-builtins.cc | 33 +++
 gcc/config/riscv/riscv-vector-builtins.def|  4 ++-
 gcc/config/riscv/riscv-vector-builtins.h  |  1 +
 gcc/config/riscv/sifive-vector.md | 10 +++---
 gcc/config/riscv/vector-iterators.md  | 25 +++---
 7 files changed, 78 insertions(+), 25 deletions(-)

diff --git a/gcc/config/riscv/genrvv-type-indexer.cc 
b/gcc/config/riscv/genrvv-type-indexer.cc
index e1eee34237a..a2974269adc 100644
--- a/gcc/config/riscv/genrvv-type-indexer.cc
+++ b/gcc/config/riscv/genrvv-type-indexer.cc
@@ -164,6 +164,18 @@ floattype (unsigned sew, int lmul_log2)
   return mode.str ();
 }
 
+std::string
+expand_floattype (unsigned sew, int lmul_log2, unsigned nf)
+{
+  if (sew != 8 || nf!= 1
+  || (!valid_type (sew * 4, lmul_log2 + 2, /*float_t*/ true)))
+return "INVALID";
+
+  std::stringstream mode;
+  mode << "vfloat" << sew * 4 << to_lmul (lmul_log2 + 2) << "_t";
+  return mode.str ();
+}
+
 std::string
 floattype (unsigned sew, int lmul_log2, unsigned nf)
 {
@@ -276,6 +288,7 @@ main (int argc, const char **argv)
   fprintf (fp, "  /*QLMUL1*/ INVALID,\n");
   fprintf (fp, "  /*QLMUL1_SIGNED*/ INVALID,\n");
   fprintf (fp, "  /*QLMUL1_UNSIGNED*/ INVALID,\n");
+  fprintf (fp, "  /*XFQF*/ INVALID,\n");
   for (unsigned eew : {8, 16, 32, 64})
fprintf (fp, "  /*EEW%d_INTERPRET*/ INVALID,\n", eew);
 
@@ -384,6 +397,8 @@ main (int argc, const char **argv)
 inttype (8, /*lmul_log2*/ 0, false).c_str ());
fprintf (fp, "  /*QLMUL1_UNSIGNED*/ %s,\n",
 inttype (8, /*lmul_log2*/ 0, true).c_str ());
+   fprintf (fp, "  /*XFQF*/ %s,\n",
+expand_floattype (sew, lmul_log2, nf).c_str ());
for (unsigned eew : {8, 16, 32, 64})
  {
if (eew == sew)
@@ -473,6 +488,7 @@ main (int argc, const char **argv)
 bfloat16_wide_type (/*lmul_log2*/ 0).c_str ());
fprintf (fp, "  /*QLMUL1_SIGNED*/ INVALID,\n");
fprintf (fp, "  /*QLMUL1_UNSIGNED*/ INVALID,\n");
+   fprintf (fp, "  /*XFQF*/ INVALID,\n");
for (unsigned eew : {8, 16, 32, 64})
  fprintf (fp, "  /*EEW%d_INTERPRET*/ INVALID,\n", eew);
 
@@ -558,6 +574,7 @@ main (int argc, const char **argv)
   floattype (sew / 4, /*lmul_log2*/ 0).c_str ());
  fprintf (fp, "  /*QLMUL1_SIGNED*/ INVALID,\n");
  fprintf (fp, "  /*QLMUL1_UNSIGNED*/ INVALID,\n");
+ fprintf (fp, "  /*XFQF*/ INVALID,\n");
  for (unsigned eew : {8, 16, 32, 64})
fprintf (fp, "  /*EEW%d_INTERPRET*/ INVALID,\n", eew);
 
diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
b/gcc/config/riscv/riscv-vector-builtins-types.def
index 96412bfd1a5..df55b6a8823 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -363,6 +363,12 @@ along with GCC; see the file COPYING3. If not see
 #define DEF_RVV_QMACC_OPS(TYPE, REQUIRE)
 #endif
 
+/* Use "DEF_RVV_XFQF_OPS" macro include signed integer which will
+   be iterated and registered as intrinsic functions.  */
+#ifndef DEF_RVV_XFQF_OPS
+#define DEF_RVV_XFQF_OPS(TYPE, REQUIRE)
+#endif
+
 DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 DEF_RVV_I_OPS (vint8mf4_t, 0)
 DEF_RVV_I_OPS (vint8mf2_t, 0)
@@ -1451,6 +1457,12 @@ DEF_RVV_QMACC_OPS (vint32m2_t, 0)
 DEF_RVV_QMACC_OPS (vint32m4_t, 0)
 DEF_RVV_QMACC_OPS (vint32m8_t, 0)
 
+DEF_RVV_XFQF_OPS (vint8mf8_t, 0)
+DEF_RVV_XFQF_OPS (vint8mf4_t, 0)
+DEF_RVV_XFQF_OPS (vint8mf2_t, 0)
+DEF_RVV_XFQF_OPS (vint8m1_t, 0)
+DEF_RVV_XFQF_OPS (vint8m2_t, 0)
+
 #undef DEF_RVV_I_OPS
 #undef DEF_RVV_U_OPS
 #undef DEF_RVV_F_OPS
@@ -1506,3 +1518,4 @@ DEF_RVV_QMACC_OPS (vint32m8_t, 0)
 #undef DEF_RVV_CRYPTO_SEW64_OPS
 #undef DEF_RVV_F32_OPS
 #undef DEF_RVV_QMACC_OPS
+#undef DEF_RVV_XFQF_OPS
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc 
b/gcc/config/riscv/riscv-ve

[v2 PATCH 1/2] RISC-V: Support RISC-V Profiles 20/22.

[Jiawei]

This patch introduces support for RISC-V Profiles RV20 and RV22 [1],
enabling developers to utilize these profiles through the -march option.

[1] https://github.com/riscv/riscv-profiles/releases/tag/v1.0

Version log:
Using lowercase letters to present Profiles.
Using '_' as divsor between Profiles and other RISC-V extension.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (struct riscv_profiles): New 
struct.
(riscv_subset_list::parse_profiles): New parser.
(riscv_subset_list::parse_base_ext): Ditto.
* config/riscv/riscv-subset.h: New def.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-45.c: New test.
* gcc.target/riscv/arch-46.c: New test.
* gcc.target/riscv/arch-47.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  | 75 +++-
 gcc/config/riscv/riscv-subset.h  |  2 +
 gcc/testsuite/gcc.target/riscv/arch-45.c |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-46.c | 12 
 gcc/testsuite/gcc.target/riscv/arch-47.c | 12 
 5 files changed, 105 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-46.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-47.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 5038f0eb959..da3829a5d43 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -242,6 +242,12 @@ struct riscv_ext_version
   int minor_version;
 };
 
+struct riscv_profiles
+{
+  const char *profile_name;
+  const char *profile_string;
+};
+
 /* All standard extensions defined in all supported ISA spec.  */
 static const struct riscv_ext_version riscv_ext_version_table[] =
 {
@@ -464,6 +470,31 @@ static const struct riscv_ext_version riscv_combine_info[] 
=
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
 
+/* This table records the mapping form RISC-V Profiles into march string.  */
+static const riscv_profiles riscv_profiles_table[] =
+{
+  /* RVI20U only contains the base extension 'i' as mandatory extension.  */
+  {"rvi20u64", "rv64i"},
+  {"rvi20u32", "rv32i"},
+
+  /* RVA20U contains the 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,
+ zicclsm,za128rs' as mandatory extensions.  */
+  {"rva20u64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_za128rs"},
+
+  /* RVA22U contains the 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
+ zihpm,ziccif,ziccrse,ziccamoa, zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,
+ zfhmin,zkt' as mandatory extensions.  */
+  {"rva22u64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt"},
+
+  /* Currently we do not define S/M mode Profiles in gcc part.  */
+
+  /* Terminate the list.  */
+  {NULL, NULL}
+};
+
 static const riscv_cpu_info riscv_cpu_tables[] =
 {
 #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -1071,6 +1102,46 @@ riscv_subset_list::parsing_subset_version (const char 
*ext,
   return p;
 }
 
+/* Parsing RISC-V Profiles in -march string.
+   Return string with mandatory extensions of Profiles.  */
+const char *
+riscv_subset_list::parse_profiles (const char *p)
+{
+  /* Checking if input string contains a Profiles.
+ There are two cases use Profiles in -march option:
+
+ 1. Only use Profiles in '-march' as input
+ 2. Mixed Profiles with other extensions
+
+ Use '_' to split Profiles and other extension.  */
+  for (int i = 0; riscv_profiles_table[i].profile_name != NULL; ++i)
+{
+  const char *match = strstr (p, riscv_profiles_table[i].profile_name);
+  const char *plus_ext = strchr (p, '_');
+  /* Find profile at the begin.  */
+  if (match != NULL && match == p)
+   {
+ /* If there's no '_' sign, return the profile_string directly.  */
+ if (!plus_ext)
+   return riscv_profiles_table[i].profile_string;
+ /* If there's a '_' sign, need to add profiles with other ext.  */
+ else
+ {
+   size_t arch_len = strlen (riscv_profiles_table[i].profile_string)
+ + strlen (plus_ext);
+   /* Reset the input string with Profiles mandatory extensions,
+  end with '_' to connect other additional extensions.  */
+   char *result = new char[arch_len + 2];
+   strcpy (result, riscv_profiles_table[i].profile_string);
+   strcat (result, "_");
+   strcat (result, plus_ext + 1); /* skip the '_'.  */
+   return result;
+ }
+   }
+}
+  return p;
+}
+
 /* Parsing function for base extensions, rv[32|64][i|e|g]
 
Return Value:
@@ -1085,6 +1156,8 @@ riscv_subset_list::parse_base_ext (const char *p)
   unsigned minor_version = 0;
   bool explicit_version_p = false;
 
+  p = parse_profiles(p);
+
   if (startswith (p, "rv32"))
 {
   m_xlen = 32;
@@ -1097,7 +1170,7 @@ riscv_subset_

[PATCH 2/2] RISC-V: Support RISC-V Profiles 23.

[Jiawei]

This patch introduces support for RISC-V Profiles RV23A and RV23B [1],
enabling developers to utilize these profiles through the -march option.

[1] 
https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-v0.7-ratification-vote

Version log:
Update the testcases, using lowercase letter.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc: New profile.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-48.c: New test.
* gcc.target/riscv/arch-49.c: New test.

---
 gcc/common/config/riscv/riscv-common.cc  | 16 
 gcc/testsuite/gcc.target/riscv/arch-48.c | 11 +++
 gcc/testsuite/gcc.target/riscv/arch-49.c | 10 ++
 3 files changed, 37 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-48.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-49.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index da3829a5d43..3e5da2f2d6d 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -489,6 +489,22 @@ static const riscv_profiles riscv_profiles_table[] =
"_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
"_zicboz_zfhmin_zkt"},
 
+  /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension
+ 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions.  */
+  {"rva23u64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
+  /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension
+ 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory
+ extensions.  */
+  {"rvb23u64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa"
+   "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop"
+   "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb"
+   "_zfa_zawrs"},
+
   /* Currently we do not define S/M mode Profiles in gcc part.  */
 
   /* Terminate the list.  */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-48.c 
b/gcc/testsuite/gcc.target/riscv/arch-48.c
new file mode 100644
index 000..8210978ee8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-48.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rva23u64 -mabi=lp64d" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0"
+_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0"
+_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0"
+_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0"
+_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-49.c 
b/gcc/testsuite/gcc.target/riscv/arch-49.c
new file mode 100644
index 000..6d242dfba50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-49.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rvb23u64 -mabi=lp64d" } */
+
+void foo(){}
+
+/* { dg-final { scan-assembler ".attribute arch, 
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
+"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0"
+"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0"
+"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0"
+"_zbb1p0_zbs1p0_zkt1p0\"" } } */
-- 
2.43.0

[v2 PATCH 0/2] RISC-V: Support RISC-V Profiles.

[Jiawei]

This patch series introduces support for RISC-V Profiles RV20, RV22, and
RV23[1][2].The updates enhance compatibility and streamline the process
of leveraging RISC-V Profiles through the -march option. These additions
are in line with the RISC-V standard and facilitate the adoption of these
profiles in various development scenarios.

[1] 
https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#Profiles
[2] 
https://riscv.org/announcements/2024/10/risc-v-announces-ratification-of-the-rva23-profile-standard/

Version log:
Update the Profiles format.

Jiawei (2):
  RISC-V: Support RISC-V Profiles 20/22.
  RISC-V: Support RISC-V Profiles 23.

 gcc/common/config/riscv/riscv-common.cc  | 91 +++-
 gcc/config/riscv/riscv-subset.h  |  2 +
 gcc/testsuite/gcc.target/riscv/arch-45.c |  5 ++
 gcc/testsuite/gcc.target/riscv/arch-46.c | 12 
 gcc/testsuite/gcc.target/riscv/arch-47.c | 12 
 gcc/testsuite/gcc.target/riscv/arch-48.c | 11 +++
 gcc/testsuite/gcc.target/riscv/arch-49.c | 10 +++
 7 files changed, 142 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-46.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-47.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-48.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-49.c

-- 
2.43.0