[PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic.

[jiawei]

Current epilogue will generate "addi sp,sp,0" redundant instruction.

```
        csrr    t0,vlenb
        slli    t1,t0,1
        add     sp,sp,t1
        addi    sp,sp,0
        ld      s0,24(sp)
        addi    sp,sp,32
        jr      ra
```

Optimize it by check if adjust equal to zero, remove redundant insn gen.

```
        csrr    t0,vlenb
        slli    t1,t0,1
        add     sp,sp,t1
        ld      s0,24(sp)
        addi    sp,sp,32
        jr      ra
```

Thanks for Kito and Jeff's suggestion, add testcase and fix code format.

jiawei (2):
  RISC-V: Add spill sp adjust check testcase.
  RISC-V: Optimize RVV epilogue logic.

 gcc/config/riscv/riscv.cc                     | 35 ++++++++++---------
 .../riscv/rvv/base/spill-sp-adjust.c          | 13 +++++++
 2 files changed, 32 insertions(+), 16 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c

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2.25.1