[PATCH v11 01/40] c++: Sort built-in identifiers alphabetically

[Ken Matsui via Gcc-patches]

This patch sorts built-in identifiers alphabetically for better code
readability.

gcc/cp/ChangeLog:

* constraint.cc (diagnose_trait_expr): Sort built-in identifiers
alphabetically.
* cp-trait.def: Likewise.
* semantics.cc (trait_expr_value): Likewise.
(finish_trait_expr): Likewise.
(finish_trait_type): Likewise.

gcc/testsuite/ChangeLog:

* g++.dg/ext/has-builtin-1.C: Sort built-in identifiers
alphabetically.

Signed-off-by: Ken Matsui 
---
 gcc/cp/constraint.cc | 68 +--
 gcc/cp/cp-trait.def  | 10 +--
 gcc/cp/semantics.cc  | 86 
 gcc/testsuite/g++.dg/ext/has-builtin-1.C | 70 +--
 4 files changed, 117 insertions(+), 117 deletions(-)

diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc
index c9e4e7043cd..722fc334e6f 100644
--- a/gcc/cp/constraint.cc
+++ b/gcc/cp/constraint.cc
@@ -3702,18 +3702,36 @@ diagnose_trait_expr (tree expr, tree args)
 case CPTK_HAS_TRIVIAL_DESTRUCTOR:
   inform (loc, "  %qT is not trivially destructible", t1);
   break;
+case CPTK_HAS_UNIQUE_OBJ_REPRESENTATIONS:
+  inform (loc, "  %qT does not have unique object representations", t1);
+  break;
 case CPTK_HAS_VIRTUAL_DESTRUCTOR:
   inform (loc, "  %qT does not have a virtual destructor", t1);
   break;
 case CPTK_IS_ABSTRACT:
   inform (loc, "  %qT is not an abstract class", t1);
   break;
+case CPTK_IS_AGGREGATE:
+  inform (loc, "  %qT is not an aggregate", t1);
+  break;
+case CPTK_IS_ASSIGNABLE:
+  inform (loc, "  %qT is not assignable from %qT", t1, t2);
+  break;
 case CPTK_IS_BASE_OF:
   inform (loc, "  %qT is not a base of %qT", t1, t2);
   break;
 case CPTK_IS_CLASS:
   inform (loc, "  %qT is not a class", t1);
   break;
+case CPTK_IS_CONSTRUCTIBLE:
+  if (!t2)
+inform (loc, "  %qT is not default constructible", t1);
+  else
+inform (loc, "  %qT is not constructible from %qE", t1, t2);
+  break;
+case CPTK_IS_CONVERTIBLE:
+  inform (loc, "  %qT is not convertible from %qE", t2, t1);
+  break;
 case CPTK_IS_EMPTY:
   inform (loc, "  %qT is not an empty class", t1);
   break;
@@ -3729,6 +3747,18 @@ diagnose_trait_expr (tree expr, tree args)
 case CPTK_IS_LITERAL_TYPE:
   inform (loc, "  %qT is not a literal type", t1);
   break;
+case CPTK_IS_NOTHROW_ASSIGNABLE:
+  inform (loc, "  %qT is not nothrow assignable from %qT", t1, t2);
+  break;
+case CPTK_IS_NOTHROW_CONSTRUCTIBLE:
+  if (!t2)
+   inform (loc, "  %qT is not nothrow default constructible", t1);
+  else
+   inform (loc, "  %qT is not nothrow constructible from %qE", t1, t2);
+  break;
+case CPTK_IS_NOTHROW_CONVERTIBLE:
+ inform (loc, "  %qT is not nothrow convertible from %qE", t2, t1);
+  break;
 case CPTK_IS_POINTER_INTERCONVERTIBLE_BASE_OF:
   inform (loc, "  %qT is not pointer-interconvertible base of %qT",
  t1, t2);
@@ -3748,50 +3778,20 @@ diagnose_trait_expr (tree expr, tree args)
 case CPTK_IS_TRIVIAL:
   inform (loc, "  %qT is not a trivial type", t1);
   break;
-case CPTK_IS_UNION:
-  inform (loc, "  %qT is not a union", t1);
-  break;
-case CPTK_IS_AGGREGATE:
-  inform (loc, "  %qT is not an aggregate", t1);
-  break;
-case CPTK_IS_TRIVIALLY_COPYABLE:
-  inform (loc, "  %qT is not trivially copyable", t1);
-  break;
-case CPTK_IS_ASSIGNABLE:
-  inform (loc, "  %qT is not assignable from %qT", t1, t2);
-  break;
 case CPTK_IS_TRIVIALLY_ASSIGNABLE:
   inform (loc, "  %qT is not trivially assignable from %qT", t1, t2);
   break;
-case CPTK_IS_NOTHROW_ASSIGNABLE:
-  inform (loc, "  %qT is not nothrow assignable from %qT", t1, t2);
-  break;
-case CPTK_IS_CONSTRUCTIBLE:
-  if (!t2)
-   inform (loc, "  %qT is not default constructible", t1);
-  else
-   inform (loc, "  %qT is not constructible from %qE", t1, t2);
-  break;
 case CPTK_IS_TRIVIALLY_CONSTRUCTIBLE:
   if (!t2)
inform (loc, "  %qT is not trivially default constructible", t1);
   else
inform (loc, "  %qT is not trivially constructible from %qE", t1, t2);
   break;
-case CPTK_IS_NOTHROW_CONSTRUCTIBLE:
-  if (!t2)
-   inform (loc, "  %qT is not nothrow default constructible", t1);
-  else
-   inform (loc, "  %qT is not nothrow constructible from %qE", t1, t2);
-  break;
-case CPTK_HAS_UNIQUE_OBJ_REPRESENTATIONS:
-  inform (loc, "  %qT does not have unique object representations", t1);
-  break;
-case CPTK_IS_CONVERTIBLE:
-  inform (loc, "  %qT is not convertible from %qE", t2, t1);
+case CPTK_IS_TRIVIALLY_COPYABLE:
+  inform (loc, "  %qT is not trivially copyable", t1);
   break;
-case CPTK_IS_NOTHROW_

[PATCH v11 09/40] libstdc++: Optimize is_unbounded_array trait performance

[Ken Matsui via Gcc-patches]

This patch optimizes the performance of the is_unbounded_array trait by
dispatching to the new __is_unbounded_array built-in trait.

libstdc++-v3/ChangeLog:

* include/std/type_traits (is_unbounded_array_v): Use
__is_unbounded_array built-in trait.

Signed-off-by: Ken Matsui 
---
 libstdc++-v3/include/std/type_traits | 5 +
 1 file changed, 5 insertions(+)

diff --git a/libstdc++-v3/include/std/type_traits 
b/libstdc++-v3/include/std/type_traits
index 4e8165e5af5..cb3d9e238fa 100644
--- a/libstdc++-v3/include/std/type_traits
+++ b/libstdc++-v3/include/std/type_traits
@@ -3541,11 +3541,16 @@ template
   /// True for a type that is an array of unknown bound.
   /// @ingroup variable_templates
   /// @since C++20
+# if _GLIBCXX_USE_BUILTIN_TRAIT(__is_unbounded_array)
+  template
+inline constexpr bool is_unbounded_array_v = __is_unbounded_array(_Tp);
+# else
   template
 inline constexpr bool is_unbounded_array_v = false;
 
   template
 inline constexpr bool is_unbounded_array_v<_Tp[]> = true;
+# endif
 
   /// True for a type that is an array of known bound.
   /// @since C++20
-- 
2.42.0

[PATCH v11 04/40] c++: Implement __is_volatile built-in trait

[Ken Matsui via Gcc-patches]

This patch implements built-in trait for std::is_volatile.

gcc/cp/ChangeLog:

* cp-trait.def: Define __is_volatile.
* constraint.cc (diagnose_trait_expr): Handle CPTK_IS_VOLATILE.
* semantics.cc (trait_expr_value): Likewise.
(finish_trait_expr): Likewise.

gcc/testsuite/ChangeLog:

* g++.dg/ext/has-builtin-1.C: Test existence of __is_volatile.
* g++.dg/ext/is_volatile.C: New test.

Signed-off-by: Ken Matsui 
---
 gcc/cp/constraint.cc |  3 +++
 gcc/cp/cp-trait.def  |  1 +
 gcc/cp/semantics.cc  |  4 
 gcc/testsuite/g++.dg/ext/has-builtin-1.C |  3 +++
 gcc/testsuite/g++.dg/ext/is_volatile.C   | 19 +++
 5 files changed, 30 insertions(+)
 create mode 100644 gcc/testsuite/g++.dg/ext/is_volatile.C

diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc
index 567dd35fe0a..f031e022541 100644
--- a/gcc/cp/constraint.cc
+++ b/gcc/cp/constraint.cc
@@ -3796,6 +3796,9 @@ diagnose_trait_expr (tree expr, tree args)
 case CPTK_IS_UNION:
   inform (loc, "  %qT is not a union", t1);
   break;
+case CPTK_IS_VOLATILE:
+  inform (loc, "  %qT is not a volatile type", t1);
+  break;
 case CPTK_REF_CONSTRUCTS_FROM_TEMPORARY:
   inform (loc, "  %qT is not a reference that binds to a temporary "
  "object of type %qT (direct-initialization)", t1, t2);
diff --git a/gcc/cp/cp-trait.def b/gcc/cp/cp-trait.def
index a4ebfd9f319..60462cd9874 100644
--- a/gcc/cp/cp-trait.def
+++ b/gcc/cp/cp-trait.def
@@ -83,6 +83,7 @@ DEFTRAIT_EXPR (IS_TRIVIALLY_ASSIGNABLE, 
"__is_trivially_assignable", 2)
 DEFTRAIT_EXPR (IS_TRIVIALLY_CONSTRUCTIBLE, "__is_trivially_constructible", -1)
 DEFTRAIT_EXPR (IS_TRIVIALLY_COPYABLE, "__is_trivially_copyable", 1)
 DEFTRAIT_EXPR (IS_UNION, "__is_union", 1)
+DEFTRAIT_EXPR (IS_VOLATILE, "__is_volatile", 1)
 DEFTRAIT_EXPR (REF_CONSTRUCTS_FROM_TEMPORARY, 
"__reference_constructs_from_temporary", 2)
 DEFTRAIT_EXPR (REF_CONVERTS_FROM_TEMPORARY, 
"__reference_converts_from_temporary", 2)
 DEFTRAIT_TYPE (REMOVE_CV, "__remove_cv", 1)
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index baeda9f03e9..18390f530ee 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -12202,6 +12202,9 @@ trait_expr_value (cp_trait_kind kind, tree type1, tree 
type2)
 case CPTK_IS_UNION:
   return type_code1 == UNION_TYPE;
 
+case CPTK_IS_VOLATILE:
+  return CP_TYPE_VOLATILE_P (type1);
+
 case CPTK_REF_CONSTRUCTS_FROM_TEMPORARY:
   return ref_xes_from_temporary (type1, type2, /*direct_init=*/true);
 
@@ -12363,6 +12366,7 @@ finish_trait_expr (location_t loc, cp_trait_kind kind, 
tree type1, tree type2)
 case CPTK_IS_ENUM:
 case CPTK_IS_SAME:
 case CPTK_IS_UNION:
+case CPTK_IS_VOLATILE:
   break;
 
 case CPTK_IS_LAYOUT_COMPATIBLE:
diff --git a/gcc/testsuite/g++.dg/ext/has-builtin-1.C 
b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
index e6e481b13c5..fb03dd20e84 100644
--- a/gcc/testsuite/g++.dg/ext/has-builtin-1.C
+++ b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
@@ -131,6 +131,9 @@
 #if !__has_builtin (__is_union)
 # error "__has_builtin (__is_union) failed"
 #endif
+#if !__has_builtin (__is_volatile)
+# error "__has_builtin (__is_volatile) failed"
+#endif
 #if !__has_builtin (__reference_constructs_from_temporary)
 # error "__has_builtin (__reference_constructs_from_temporary) failed"
 #endif
diff --git a/gcc/testsuite/g++.dg/ext/is_volatile.C 
b/gcc/testsuite/g++.dg/ext/is_volatile.C
new file mode 100644
index 000..004e397e5e7
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/is_volatile.C
@@ -0,0 +1,19 @@
+// { dg-do compile { target c++11 } }
+
+#include 
+
+using namespace __gnu_test;
+
+#define SA(X) static_assert((X),#X)
+
+// Positive tests.
+SA(__is_volatile(volatile int));
+SA(__is_volatile(const volatile int));
+SA(__is_volatile(vClassType));
+SA(__is_volatile(cvClassType));
+
+// Negative tests.
+SA(!__is_volatile(int));
+SA(!__is_volatile(const int));
+SA(!__is_volatile(ClassType));
+SA(!__is_volatile(cClassType));
-- 
2.42.0

[PATCH v11 11/40] libstdc++: Optimize is_bounded_array trait performance

[Ken Matsui via Gcc-patches]

This patch optimizes the performance of the is_bounded_array trait by
dispatching to the new __is_bounded_array built-in trait.

libstdc++-v3/ChangeLog:

* include/std/type_traits (is_bounded_array_v): Use __is_bounded_array
built-in trait.

Signed-off-by: Ken Matsui 
---
 libstdc++-v3/include/std/type_traits | 5 +
 1 file changed, 5 insertions(+)

diff --git a/libstdc++-v3/include/std/type_traits 
b/libstdc++-v3/include/std/type_traits
index cb3d9e238fa..d306073a797 100644
--- a/libstdc++-v3/include/std/type_traits
+++ b/libstdc++-v3/include/std/type_traits
@@ -3532,11 +3532,16 @@ template
   /// True for a type that is an array of known bound.
   /// @ingroup variable_templates
   /// @since C++20
+# if _GLIBCXX_USE_BUILTIN_TRAIT(__is_bounded_array)
+  template
+inline constexpr bool is_bounded_array_v = __is_bounded_array(_Tp);
+# else
   template
 inline constexpr bool is_bounded_array_v = false;
 
   template
 inline constexpr bool is_bounded_array_v<_Tp[_Size]> = true;
+# endif
 
   /// True for a type that is an array of unknown bound.
   /// @ingroup variable_templates
-- 
2.42.0

[PATCH v11 08/40] c++: Implement __is_unbounded_array built-in trait

[Ken Matsui via Gcc-patches]

This patch implements built-in trait for std::is_unbounded_array.

gcc/cp/ChangeLog:

* cp-trait.def: Define __is_unbounded_array.
* constraint.cc (diagnose_trait_expr): Handle CPTK_IS_UNBOUNDED_ARRAY.
* semantics.cc (trait_expr_value): Likewise.
(finish_trait_expr): Likewise.

gcc/testsuite/ChangeLog:

* g++.dg/ext/has-builtin-1.C: Test existence of __is_unbounded_array.
* g++.dg/ext/is_unbounded_array.C: New test.

Signed-off-by: Ken Matsui 
---
 gcc/cp/constraint.cc  |  3 ++
 gcc/cp/cp-trait.def   |  1 +
 gcc/cp/semantics.cc   |  4 ++
 gcc/testsuite/g++.dg/ext/has-builtin-1.C  |  3 ++
 gcc/testsuite/g++.dg/ext/is_unbounded_array.C | 37 +++
 5 files changed, 48 insertions(+)
 create mode 100644 gcc/testsuite/g++.dg/ext/is_unbounded_array.C

diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc
index 5e30a4a907a..751ac61b25a 100644
--- a/gcc/cp/constraint.cc
+++ b/gcc/cp/constraint.cc
@@ -3796,6 +3796,9 @@ diagnose_trait_expr (tree expr, tree args)
 case CPTK_IS_TRIVIALLY_COPYABLE:
   inform (loc, "  %qT is not trivially copyable", t1);
   break;
+case CPTK_IS_UNBOUNDED_ARRAY:
+  inform (loc, "  %qT is not an unbounded array", t1);
+  break;
 case CPTK_IS_UNION:
   inform (loc, "  %qT is not a union", t1);
   break;
diff --git a/gcc/cp/cp-trait.def b/gcc/cp/cp-trait.def
index c9106242bc8..1e67a3d2089 100644
--- a/gcc/cp/cp-trait.def
+++ b/gcc/cp/cp-trait.def
@@ -83,6 +83,7 @@ DEFTRAIT_EXPR (IS_TRIVIAL, "__is_trivial", 1)
 DEFTRAIT_EXPR (IS_TRIVIALLY_ASSIGNABLE, "__is_trivially_assignable", 2)
 DEFTRAIT_EXPR (IS_TRIVIALLY_CONSTRUCTIBLE, "__is_trivially_constructible", -1)
 DEFTRAIT_EXPR (IS_TRIVIALLY_COPYABLE, "__is_trivially_copyable", 1)
+DEFTRAIT_EXPR (IS_UNBOUNDED_ARRAY, "__is_unbounded_array", 1)
 DEFTRAIT_EXPR (IS_UNION, "__is_union", 1)
 DEFTRAIT_EXPR (IS_VOLATILE, "__is_volatile", 1)
 DEFTRAIT_EXPR (REF_CONSTRUCTS_FROM_TEMPORARY, 
"__reference_constructs_from_temporary", 2)
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index 562b0bb8438..4fdec0c30c1 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -12202,6 +12202,9 @@ trait_expr_value (cp_trait_kind kind, tree type1, tree 
type2)
 case CPTK_IS_TRIVIALLY_COPYABLE:
   return trivially_copyable_p (type1);
 
+case CPTK_IS_UNBOUNDED_ARRAY:
+  return array_of_unknown_bound_p (type1);
+
 case CPTK_IS_UNION:
   return type_code1 == UNION_TYPE;
 
@@ -12369,6 +12372,7 @@ finish_trait_expr (location_t loc, cp_trait_kind kind, 
tree type1, tree type2)
 case CPTK_IS_CONST:
 case CPTK_IS_ENUM:
 case CPTK_IS_SAME:
+case CPTK_IS_UNBOUNDED_ARRAY:
 case CPTK_IS_UNION:
 case CPTK_IS_VOLATILE:
   break;
diff --git a/gcc/testsuite/g++.dg/ext/has-builtin-1.C 
b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
index 645cabe088e..90997210c12 100644
--- a/gcc/testsuite/g++.dg/ext/has-builtin-1.C
+++ b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
@@ -131,6 +131,9 @@
 #if !__has_builtin (__is_trivially_copyable)
 # error "__has_builtin (__is_trivially_copyable) failed"
 #endif
+#if !__has_builtin (__is_unbounded_array)
+# error "__has_builtin (__is_unbounded_array) failed"
+#endif
 #if !__has_builtin (__is_union)
 # error "__has_builtin (__is_union) failed"
 #endif
diff --git a/gcc/testsuite/g++.dg/ext/is_unbounded_array.C 
b/gcc/testsuite/g++.dg/ext/is_unbounded_array.C
new file mode 100644
index 000..1307d24f5a5
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/is_unbounded_array.C
@@ -0,0 +1,37 @@
+// { dg-do compile { target c++11 } }
+
+#include 
+
+using namespace __gnu_test;
+
+#define SA(X) static_assert((X),#X)
+
+#define SA_TEST_CATEGORY(TRAIT, TYPE, EXPECT)  \
+  SA(TRAIT(TYPE) == EXPECT);   \
+  SA(TRAIT(const TYPE) == EXPECT); \
+  SA(TRAIT(volatile TYPE) == EXPECT);  \
+  SA(TRAIT(const volatile TYPE) == EXPECT)
+
+SA_TEST_CATEGORY(__is_unbounded_array, int[2], false);
+SA_TEST_CATEGORY(__is_unbounded_array, int[], true);
+SA_TEST_CATEGORY(__is_unbounded_array, int[2][3], false);
+SA_TEST_CATEGORY(__is_unbounded_array, int[][3], true);
+SA_TEST_CATEGORY(__is_unbounded_array, float*[2], false);
+SA_TEST_CATEGORY(__is_unbounded_array, float*[], true);
+SA_TEST_CATEGORY(__is_unbounded_array, float*[2][3], false);
+SA_TEST_CATEGORY(__is_unbounded_array, float*[][3], true);
+SA_TEST_CATEGORY(__is_unbounded_array, ClassType[2], false);
+SA_TEST_CATEGORY(__is_unbounded_array, ClassType[], true);
+SA_TEST_CATEGORY(__is_unbounded_array, ClassType[2][3], false);
+SA_TEST_CATEGORY(__is_unbounded_array, ClassType[][3], true);
+SA_TEST_CATEGORY(__is_unbounded_array, IncompleteClass[2][3], false);
+SA_TEST_CATEGORY(__is_unbounded_array, IncompleteClass[][3], true);
+SA_TEST_CATEGORY(__is_unbounded_array, int(*)[2], false);
+SA_TEST_CATEGORY(__is_unbounded_array

[PATCH v11 05/40] libstdc++: Optimize is_volatile trait performance

[Ken Matsui via Gcc-patches]

This patch optimizes the performance of the is_volatile trait by dispatching
to the new __is_volatile built-in trait.

libstdc++-v3/ChangeLog:

* include/std/type_traits (is_volatile): Use __is_volatile built-in
trait.
(is_volatile_v): Likewise.

Signed-off-by: Ken Matsui 
---
 libstdc++-v3/include/std/type_traits | 12 
 1 file changed, 12 insertions(+)

diff --git a/libstdc++-v3/include/std/type_traits 
b/libstdc++-v3/include/std/type_traits
index 686e38e47c3..c01f65df22b 100644
--- a/libstdc++-v3/include/std/type_traits
+++ b/libstdc++-v3/include/std/type_traits
@@ -800,6 +800,12 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 #endif
 
   /// is_volatile
+#if _GLIBCXX_USE_BUILTIN_TRAIT(__is_volatile)
+  template
+struct is_volatile
+: public __bool_constant<__is_volatile(_Tp)>
+{ };
+#else
   template
 struct is_volatile
 : public false_type { };
@@ -807,6 +813,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   template
 struct is_volatile<_Tp volatile>
 : public true_type { };
+#endif
 
   /// is_trivial
   template
@@ -3236,10 +3243,15 @@ template 
   inline constexpr bool is_const_v = true;
 #endif
 
+#if _GLIBCXX_USE_BUILTIN_TRAIT(__is_volatile)
+template 
+  inline constexpr bool is_volatile_v = __is_volatile(_Tp);
+#else
 template 
   inline constexpr bool is_volatile_v = false;
 template 
   inline constexpr bool is_volatile_v = true;
+#endif
 
 template 
   inline constexpr bool is_trivial_v = __is_trivial(_Tp);
-- 
2.42.0

[PATCH v11 27/40] c++: Implement __remove_pointer built-in trait

[Ken Matsui via Gcc-patches]

This patch implements built-in trait for std::remove_pointer.

gcc/cp/ChangeLog:

* cp-trait.def: Define __remove_pointer.
* semantics.cc (finish_trait_type): Handle CPTK_REMOVE_POINTER.

gcc/testsuite/ChangeLog:

* g++.dg/ext/has-builtin-1.C: Test existence of __remove_pointer.
* g++.dg/ext/remove_pointer.C: New test.

Signed-off-by: Ken Matsui 
---
 gcc/cp/cp-trait.def   |  1 +
 gcc/cp/semantics.cc   |  5 +++
 gcc/testsuite/g++.dg/ext/has-builtin-1.C  |  3 ++
 gcc/testsuite/g++.dg/ext/remove_pointer.C | 51 +++
 4 files changed, 60 insertions(+)
 create mode 100644 gcc/testsuite/g++.dg/ext/remove_pointer.C

diff --git a/gcc/cp/cp-trait.def b/gcc/cp/cp-trait.def
index 3bb33a3d5c0..07cd14b6e85 100644
--- a/gcc/cp/cp-trait.def
+++ b/gcc/cp/cp-trait.def
@@ -97,6 +97,7 @@ DEFTRAIT_EXPR (REF_CONSTRUCTS_FROM_TEMPORARY, 
"__reference_constructs_from_tempo
 DEFTRAIT_EXPR (REF_CONVERTS_FROM_TEMPORARY, 
"__reference_converts_from_temporary", 2)
 DEFTRAIT_TYPE (REMOVE_CV, "__remove_cv", 1)
 DEFTRAIT_TYPE (REMOVE_CVREF, "__remove_cvref", 1)
+DEFTRAIT_TYPE (REMOVE_POINTER, "__remove_pointer", 1)
 DEFTRAIT_TYPE (REMOVE_REFERENCE, "__remove_reference", 1)
 DEFTRAIT_TYPE (TYPE_PACK_ELEMENT, "__type_pack_element", -1)
 DEFTRAIT_TYPE (UNDERLYING_TYPE,  "__underlying_type", 1)
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index 7457475f646..4de2dbbf603 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -12473,6 +12473,11 @@ finish_trait_type (cp_trait_kind kind, tree type1, 
tree type2,
type1 = TREE_TYPE (type1);
   return cv_unqualified (type1);
 
+case CPTK_REMOVE_POINTER:
+  if (TYPE_PTR_P (type1))
+type1 = TREE_TYPE (type1);
+  return type1;
+
 case CPTK_REMOVE_REFERENCE:
   if (TYPE_REF_P (type1))
type1 = TREE_TYPE (type1);
diff --git a/gcc/testsuite/g++.dg/ext/has-builtin-1.C 
b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
index 4d3947572a4..bcab0599d1a 100644
--- a/gcc/testsuite/g++.dg/ext/has-builtin-1.C
+++ b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
@@ -173,6 +173,9 @@
 #if !__has_builtin (__remove_cvref)
 # error "__has_builtin (__remove_cvref) failed"
 #endif
+#if !__has_builtin (__remove_pointer)
+# error "__has_builtin (__remove_pointer) failed"
+#endif
 #if !__has_builtin (__remove_reference)
 # error "__has_builtin (__remove_reference) failed"
 #endif
diff --git a/gcc/testsuite/g++.dg/ext/remove_pointer.C 
b/gcc/testsuite/g++.dg/ext/remove_pointer.C
new file mode 100644
index 000..7b13db93950
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/remove_pointer.C
@@ -0,0 +1,51 @@
+// { dg-do compile { target c++11 } }
+
+#define SA(X) static_assert((X),#X)
+
+SA(__is_same(__remove_pointer(int), int));
+SA(__is_same(__remove_pointer(int*), int));
+SA(__is_same(__remove_pointer(int**), int*));
+
+SA(__is_same(__remove_pointer(const int*), const int));
+SA(__is_same(__remove_pointer(const int**), const int*));
+SA(__is_same(__remove_pointer(int* const), int));
+SA(__is_same(__remove_pointer(int** const), int*));
+SA(__is_same(__remove_pointer(int* const* const), int* const));
+
+SA(__is_same(__remove_pointer(volatile int*), volatile int));
+SA(__is_same(__remove_pointer(volatile int**), volatile int*));
+SA(__is_same(__remove_pointer(int* volatile), int));
+SA(__is_same(__remove_pointer(int** volatile), int*));
+SA(__is_same(__remove_pointer(int* volatile* volatile), int* volatile));
+
+SA(__is_same(__remove_pointer(const volatile int*), const volatile int));
+SA(__is_same(__remove_pointer(const volatile int**), const volatile int*));
+SA(__is_same(__remove_pointer(const int* volatile), const int));
+SA(__is_same(__remove_pointer(volatile int* const), volatile int));
+SA(__is_same(__remove_pointer(int* const volatile), int));
+SA(__is_same(__remove_pointer(const int** volatile), const int*));
+SA(__is_same(__remove_pointer(volatile int** const), volatile int*));
+SA(__is_same(__remove_pointer(int** const volatile), int*));
+SA(__is_same(__remove_pointer(int* const* const volatile), int* const));
+SA(__is_same(__remove_pointer(int* volatile* const volatile), int* volatile));
+SA(__is_same(__remove_pointer(int* const volatile* const volatile), int* const 
volatile));
+
+SA(__is_same(__remove_pointer(int&), int&));
+SA(__is_same(__remove_pointer(const int&), const int&));
+SA(__is_same(__remove_pointer(volatile int&), volatile int&));
+SA(__is_same(__remove_pointer(const volatile int&), const volatile int&));
+
+SA(__is_same(__remove_pointer(int&&), int&&));
+SA(__is_same(__remove_pointer(const int&&), const int&&));
+SA(__is_same(__remove_pointer(volatile int&&), volatile int&&));
+SA(__is_same(__remove_pointer(const volatile int&&), const volatile int&&));
+
+SA(__is_same(__remove_pointer(int[3]), int[3]));
+SA(__is_same(__remove_pointer(const int[3]), const int[3]));
+SA(__is_same(__remove_pointer(volatile int[3]), volatile int[3]));
+SA(__is_same(__remove_pointer(c

[PATCH v11 16/40] c, c++: Use 16 bits for all use of enum rid for more keyword space

[Ken Matsui via Gcc-patches]

Now that RID_MAX has reached 255, we need to update the bit sizes of every
use of the enum rid from 8 to 16 to support more keywords.

gcc/c-family/ChangeLog:

* c-indentation.h (struct token_indent_info): Make keyword 16 bits
and move this upward to minimize memory fragmentation.

gcc/c/ChangeLog:

* c-parser.cc (c_parse_init): Handle RID_MAX not to exceed the max
value of 16 bits.
* c-parser.h (struct c_token): Make keyword 16 bits and move this
upward to minimize memory fragmentation.

gcc/cp/ChangeLog:

* parser.h (struct cp_token): Make keyword 16 bits and move this
upward to minimize memory fragmentation.
(struct cp_lexer): Likewise, for saved_keyword.

libcpp/ChangeLog:

* include/cpplib.h (struct cpp_hashnode): Make rid_code 16 bits.

Signed-off-by: Ken Matsui 
---
 gcc/c-family/c-indentation.h | 2 +-
 gcc/c/c-parser.cc| 6 +++---
 gcc/c/c-parser.h | 6 +++---
 gcc/cp/parser.h  | 8 
 libcpp/include/cpplib.h  | 2 +-
 5 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/gcc/c-family/c-indentation.h b/gcc/c-family/c-indentation.h
index c0e07bf49f1..1ce8753813a 100644
--- a/gcc/c-family/c-indentation.h
+++ b/gcc/c-family/c-indentation.h
@@ -25,8 +25,8 @@ along with GCC; see the file COPYING3.  If not see
 struct token_indent_info
 {
   location_t location;
+  ENUM_BITFIELD (rid) keyword : 16;
   ENUM_BITFIELD (cpp_ttype) type : 8;
-  ENUM_BITFIELD (rid) keyword : 8;
 };
 
 /* Extract token information from TOKEN, which ought to either be a
diff --git a/gcc/c/c-parser.cc b/gcc/c/c-parser.cc
index b9a1b75ca43..2086f253923 100644
--- a/gcc/c/c-parser.cc
+++ b/gcc/c/c-parser.cc
@@ -115,9 +115,9 @@ c_parse_init (void)
   tree id;
   int mask = 0;
 
-  /* Make sure RID_MAX hasn't grown past the 8 bits used to hold the keyword in
- the c_token structure.  */
-  gcc_assert (RID_MAX <= 255);
+  /* Make sure RID_MAX hasn't grown past the 16 bits used to hold the keyword
+ in the c_token structure.  */
+  gcc_assert (RID_MAX <= 65535);
 
   mask |= D_CXXONLY;
   if (!flag_isoc99)
diff --git a/gcc/c/c-parser.h b/gcc/c/c-parser.h
index 545f0f4d9eb..eed6deaf0f8 100644
--- a/gcc/c/c-parser.h
+++ b/gcc/c/c-parser.h
@@ -51,14 +51,14 @@ enum c_id_kind {
 /* A single C token after string literal concatenation and conversion
of preprocessing tokens to tokens.  */
 struct GTY (()) c_token {
+  /* If this token is a keyword, this value indicates which keyword.
+ Otherwise, this value is RID_MAX.  */
+  ENUM_BITFIELD (rid) keyword : 16;
   /* The kind of token.  */
   ENUM_BITFIELD (cpp_ttype) type : 8;
   /* If this token is a CPP_NAME, this value indicates whether also
  declared as some kind of type.  Otherwise, it is C_ID_NONE.  */
   ENUM_BITFIELD (c_id_kind) id_kind : 8;
-  /* If this token is a keyword, this value indicates which keyword.
- Otherwise, this value is RID_MAX.  */
-  ENUM_BITFIELD (rid) keyword : 8;
   /* If this token is a CPP_PRAGMA, this indicates the pragma that
  was seen.  Otherwise it is PRAGMA_NONE.  */
   ENUM_BITFIELD (pragma_kind) pragma_kind : 8;
diff --git a/gcc/cp/parser.h b/gcc/cp/parser.h
index 6cbb9a8e031..3c3c482c6ce 100644
--- a/gcc/cp/parser.h
+++ b/gcc/cp/parser.h
@@ -40,11 +40,11 @@ struct GTY(()) tree_check {
 /* A C++ token.  */
 
 struct GTY (()) cp_token {
-  /* The kind of token.  */
-  enum cpp_ttype type : 8;
   /* If this token is a keyword, this value indicates which keyword.
  Otherwise, this value is RID_MAX.  */
-  enum rid keyword : 8;
+  enum rid keyword : 16;
+  /* The kind of token.  */
+  enum cpp_ttype type : 8;
   /* Token flags.  */
   unsigned char flags;
   /* True if this token is from a context where it is implicitly extern "C" */
@@ -101,8 +101,8 @@ struct GTY (()) cp_lexer {
   vec GTY ((skip)) saved_tokens;
 
   /* Saved pieces of end token we replaced with the eof token.  */
+  enum rid saved_keyword : 16;
   enum cpp_ttype saved_type : 8;
-  enum rid saved_keyword : 8;
 
   /* The next lexer in a linked list of lexers.  */
   struct cp_lexer *next;
diff --git a/libcpp/include/cpplib.h b/libcpp/include/cpplib.h
index fcdaf082b09..b93899cd364 100644
--- a/libcpp/include/cpplib.h
+++ b/libcpp/include/cpplib.h
@@ -988,7 +988,7 @@ struct GTY(()) cpp_hashnode {
   unsigned int directive_index : 7;/* If is_directive,
   then index into directive table.
   Otherwise, a NODE_OPERATOR.  */
-  unsigned int rid_code : 8;   /* Rid code - for front ends.  */
+  unsigned int rid_code : 16;  /* Rid code - for front ends.  */
   unsigned int flags : 9;  /* CPP flags.  */
   ENUM_BITFIELD(node_type) type : 2;   /* CPP node type.  */
 
-- 
2.42.0

[PATCH v11 07/40] libstdc++: Optimize is_array trait performance

[Ken Matsui via Gcc-patches]

This patch optimizes the performance of the is_array trait by dispatching to
the new __is_array built-in trait.

libstdc++-v3/ChangeLog:

* include/std/type_traits (is_array): Use __is_array built-in trait.
(is_array_v): Likewise.

Signed-off-by: Ken Matsui 
---
 libstdc++-v3/include/std/type_traits | 12 
 1 file changed, 12 insertions(+)

diff --git a/libstdc++-v3/include/std/type_traits 
b/libstdc++-v3/include/std/type_traits
index c01f65df22b..4e8165e5af5 100644
--- a/libstdc++-v3/include/std/type_traits
+++ b/libstdc++-v3/include/std/type_traits
@@ -523,6 +523,12 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 { };
 
   /// is_array
+#if _GLIBCXX_USE_BUILTIN_TRAIT(__is_array)
+  template
+struct is_array
+: public __bool_constant<__is_array(_Tp)>
+{ };
+#else
   template
 struct is_array
 : public false_type { };
@@ -534,6 +540,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   template
 struct is_array<_Tp[]>
 : public true_type { };
+#endif
 
   template
 struct __is_pointer_helper
@@ -3183,12 +3190,17 @@ template 
 template 
   inline constexpr bool is_floating_point_v = is_floating_point<_Tp>::value;
 
+#if _GLIBCXX_USE_BUILTIN_TRAIT(__is_array)
+template 
+  inline constexpr bool is_array_v = __is_array(_Tp);
+#else
 template 
   inline constexpr bool is_array_v = false;
 template 
   inline constexpr bool is_array_v<_Tp[]> = true;
 template 
   inline constexpr bool is_array_v<_Tp[_Num]> = true;
+#endif
 
 template 
   inline constexpr bool is_pointer_v = is_pointer<_Tp>::value;
-- 
2.42.0

[PATCH v11 28/40] libstdc++: Optimize remove_pointer trait performance

[Ken Matsui via Gcc-patches]

This patch optimizes the performance of the remove_pointer trait by
dispatching to the new remove_pointer built-in trait.

libstdc++-v3/ChangeLog:

* include/std/type_traits (remove_pointer): Use __remove_pointer
built-in trait.

Signed-off-by: Ken Matsui 
---
 libstdc++-v3/include/std/type_traits | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/libstdc++-v3/include/std/type_traits 
b/libstdc++-v3/include/std/type_traits
index 674d398c075..9c56d15c0b7 100644
--- a/libstdc++-v3/include/std/type_traits
+++ b/libstdc++-v3/include/std/type_traits
@@ -2105,6 +2105,12 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 
   // Pointer modifications.
 
+  /// remove_pointer
+#if _GLIBCXX_USE_BUILTIN_TRAIT(__remove_pointer)
+  template
+struct remove_pointer
+{ using type = __remove_pointer(_Tp); };
+#else
   template
 struct __remove_pointer_helper
 { using type = _Tp; };
@@ -2113,11 +2119,11 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 struct __remove_pointer_helper<_Tp, _Up*>
 { using type = _Up; };
 
-  /// remove_pointer
   template
 struct remove_pointer
 : public __remove_pointer_helper<_Tp, __remove_cv_t<_Tp>>
 { };
+#endif
 
   template
 struct __add_pointer_helper
-- 
2.42.0

[PATCH v11 06/40] c++: Implement __is_array built-in trait

[Ken Matsui via Gcc-patches]

This patch implements built-in trait for std::is_array.

gcc/cp/ChangeLog:

* cp-trait.def: Define __is_array.
* constraint.cc (diagnose_trait_expr): Handle CPTK_IS_ARRAY.
* semantics.cc (trait_expr_value): Likewise.
(finish_trait_expr): Likewise.

gcc/testsuite/ChangeLog:

* g++.dg/ext/has-builtin-1.C: Test existence of __is_array.
* g++.dg/ext/is_array.C: New test.

Signed-off-by: Ken Matsui 
---
 gcc/cp/constraint.cc |  3 +++
 gcc/cp/cp-trait.def  |  1 +
 gcc/cp/semantics.cc  |  4 
 gcc/testsuite/g++.dg/ext/has-builtin-1.C |  3 +++
 gcc/testsuite/g++.dg/ext/is_array.C  | 28 
 5 files changed, 39 insertions(+)
 create mode 100644 gcc/testsuite/g++.dg/ext/is_array.C

diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc
index f031e022541..5e30a4a907a 100644
--- a/gcc/cp/constraint.cc
+++ b/gcc/cp/constraint.cc
@@ -3714,6 +3714,9 @@ diagnose_trait_expr (tree expr, tree args)
 case CPTK_IS_AGGREGATE:
   inform (loc, "  %qT is not an aggregate", t1);
   break;
+case CPTK_IS_ARRAY:
+  inform (loc, "  %qT is not an array", t1);
+  break;
 case CPTK_IS_ASSIGNABLE:
   inform (loc, "  %qT is not assignable from %qT", t1, t2);
   break;
diff --git a/gcc/cp/cp-trait.def b/gcc/cp/cp-trait.def
index 60462cd9874..c9106242bc8 100644
--- a/gcc/cp/cp-trait.def
+++ b/gcc/cp/cp-trait.def
@@ -59,6 +59,7 @@ DEFTRAIT_EXPR (HAS_UNIQUE_OBJ_REPRESENTATIONS, 
"__has_unique_object_representati
 DEFTRAIT_EXPR (HAS_VIRTUAL_DESTRUCTOR, "__has_virtual_destructor", 1)
 DEFTRAIT_EXPR (IS_ABSTRACT, "__is_abstract", 1)
 DEFTRAIT_EXPR (IS_AGGREGATE, "__is_aggregate", 1)
+DEFTRAIT_EXPR (IS_ARRAY, "__is_array", 1)
 DEFTRAIT_EXPR (IS_ASSIGNABLE, "__is_assignable", 2)
 DEFTRAIT_EXPR (IS_BASE_OF, "__is_base_of", 2)
 DEFTRAIT_EXPR (IS_CLASS, "__is_class", 1)
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index 18390f530ee..562b0bb8438 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -12128,6 +12128,9 @@ trait_expr_value (cp_trait_kind kind, tree type1, tree 
type2)
 case CPTK_IS_AGGREGATE:
   return CP_AGGREGATE_TYPE_P (type1);
 
+case CPTK_IS_ARRAY:
+  return type_code1 == ARRAY_TYPE;
+
 case CPTK_IS_ASSIGNABLE:
   return is_xible (MODIFY_EXPR, type1, type2);
 
@@ -12361,6 +12364,7 @@ finish_trait_expr (location_t loc, cp_trait_kind kind, 
tree type1, tree type2)
return error_mark_node;
   break;
 
+case CPTK_IS_ARRAY:
 case CPTK_IS_CLASS:
 case CPTK_IS_CONST:
 case CPTK_IS_ENUM:
diff --git a/gcc/testsuite/g++.dg/ext/has-builtin-1.C 
b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
index fb03dd20e84..645cabe088e 100644
--- a/gcc/testsuite/g++.dg/ext/has-builtin-1.C
+++ b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
@@ -56,6 +56,9 @@
 #if !__has_builtin (__is_aggregate)
 # error "__has_builtin (__is_aggregate) failed"
 #endif
+#if !__has_builtin (__is_array)
+# error "__has_builtin (__is_array) failed"
+#endif
 #if !__has_builtin (__is_assignable)
 # error "__has_builtin (__is_assignable) failed"
 #endif
diff --git a/gcc/testsuite/g++.dg/ext/is_array.C 
b/gcc/testsuite/g++.dg/ext/is_array.C
new file mode 100644
index 000..facfed5c7cb
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/is_array.C
@@ -0,0 +1,28 @@
+// { dg-do compile { target c++11 } }
+
+#include 
+
+using namespace __gnu_test;
+
+#define SA(X) static_assert((X),#X)
+#define SA_TEST_CATEGORY(TRAIT, X, expect) \
+  SA(TRAIT(X) == expect);  \
+  SA(TRAIT(const X) == expect);\
+  SA(TRAIT(volatile X) == expect); \
+  SA(TRAIT(const volatile X) == expect)
+
+SA_TEST_CATEGORY(__is_array, int[2], true);
+SA_TEST_CATEGORY(__is_array, int[], true);
+SA_TEST_CATEGORY(__is_array, int[2][3], true);
+SA_TEST_CATEGORY(__is_array, int[][3], true);
+SA_TEST_CATEGORY(__is_array, float*[2], true);
+SA_TEST_CATEGORY(__is_array, float*[], true);
+SA_TEST_CATEGORY(__is_array, float*[2][3], true);
+SA_TEST_CATEGORY(__is_array, float*[][3], true);
+SA_TEST_CATEGORY(__is_array, ClassType[2], true);
+SA_TEST_CATEGORY(__is_array, ClassType[], true);
+SA_TEST_CATEGORY(__is_array, ClassType[2][3], true);
+SA_TEST_CATEGORY(__is_array, ClassType[][3], true);
+
+// Sanity check.
+SA_TEST_CATEGORY(__is_array, ClassType, false);
-- 
2.42.0

[PATCH v11 30/40] libstdc++: Optimize is_pointer trait performance

[Ken Matsui via Gcc-patches]

This patch optimizes the performance of the is_pointer trait by dispatching to
the new __is_pointer built-in trait.

libstdc++-v3/ChangeLog:

* include/bits/cpp_type_traits.h (__is_ptr): Use __is_pointer
built-in trait.
* include/std/type_traits (is_pointer): Likewise. Optimize its
implementation.
(is_pointer_v): Likewise.

Co-authored-by: Jonathan Wakely 
Signed-off-by: Ken Matsui 
---
 libstdc++-v3/include/bits/cpp_type_traits.h |  8 
 libstdc++-v3/include/std/type_traits| 44 +
 2 files changed, 44 insertions(+), 8 deletions(-)

diff --git a/libstdc++-v3/include/bits/cpp_type_traits.h 
b/libstdc++-v3/include/bits/cpp_type_traits.h
index 3711e4be526..4da1e7c407c 100644
--- a/libstdc++-v3/include/bits/cpp_type_traits.h
+++ b/libstdc++-v3/include/bits/cpp_type_traits.h
@@ -363,6 +363,13 @@ __INT_N(__GLIBCXX_TYPE_INT_N_3)
   //
   // Pointer types
   //
+#if __has_builtin(__is_pointer)
+  template
+struct __is_ptr : __truth_type<__is_pointer(_Tp)>
+{
+  enum { __value = __is_pointer(_Tp) };
+};
+#else
   template
 struct __is_ptr
 {
@@ -376,6 +383,7 @@ __INT_N(__GLIBCXX_TYPE_INT_N_3)
   enum { __value = 1 };
   typedef __true_type __type;
 };
+#endif
 
   //
   // An arithmetic type is an integer type or a floating point type
diff --git a/libstdc++-v3/include/std/type_traits 
b/libstdc++-v3/include/std/type_traits
index 9c56d15c0b7..3acd843f2f2 100644
--- a/libstdc++-v3/include/std/type_traits
+++ b/libstdc++-v3/include/std/type_traits
@@ -542,19 +542,33 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 : public true_type { };
 #endif
 
-  template
-struct __is_pointer_helper
+  /// is_pointer
+#if _GLIBCXX_USE_BUILTIN_TRAIT(__is_pointer)
+  template
+struct is_pointer
+: public __bool_constant<__is_pointer(_Tp)>
+{ };
+#else
+  template
+struct is_pointer
 : public false_type { };
 
   template
-struct __is_pointer_helper<_Tp*>
+struct is_pointer<_Tp*>
 : public true_type { };
 
-  /// is_pointer
   template
-struct is_pointer
-: public __is_pointer_helper<__remove_cv_t<_Tp>>::type
-{ };
+struct is_pointer<_Tp* const>
+: public true_type { };
+
+  template
+struct is_pointer<_Tp* volatile>
+: public true_type { };
+
+  template
+struct is_pointer<_Tp* const volatile>
+: public true_type { };
+#endif
 
   /// is_lvalue_reference
   template
@@ -3254,8 +3268,22 @@ template 
   inline constexpr bool is_array_v<_Tp[_Num]> = true;
 #endif
 
+#if _GLIBCXX_USE_BUILTIN_TRAIT(__is_pointer)
+template 
+  inline constexpr bool is_pointer_v = __is_pointer(_Tp);
+#else
 template 
-  inline constexpr bool is_pointer_v = is_pointer<_Tp>::value;
+  inline constexpr bool is_pointer_v = false;
+template 
+  inline constexpr bool is_pointer_v<_Tp*> = true;
+template 
+  inline constexpr bool is_pointer_v<_Tp* const> = true;
+template 
+  inline constexpr bool is_pointer_v<_Tp* volatile> = true;
+template 
+  inline constexpr bool is_pointer_v<_Tp* const volatile> = true;
+#endif
+
 template 
   inline constexpr bool is_lvalue_reference_v = false;
 template 
-- 
2.42.0

[PATCH v11 25/40] libstdc++: Optimize is_function trait performance

[Ken Matsui via Gcc-patches]

This patch optimizes the performance of the is_function trait by dispatching
to the new __is_function built-in trait.

libstdc++-v3/ChangeLog:

* include/std/type_traits (is_function): Use __is_function built-in
trait.
(is_function_v): Likewise. Optimize its implementation.

Signed-off-by: Ken Matsui 
---
 libstdc++-v3/include/std/type_traits | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/libstdc++-v3/include/std/type_traits 
b/libstdc++-v3/include/std/type_traits
index 36ad9814047..bd57488824b 100644
--- a/libstdc++-v3/include/std/type_traits
+++ b/libstdc++-v3/include/std/type_traits
@@ -637,6 +637,12 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 { };
 
   /// is_function
+#if _GLIBCXX_USE_BUILTIN_TRAIT(__is_function)
+  template
+struct is_function
+: public __bool_constant<__is_function(_Tp)>
+{ };
+#else
   template
 struct is_function
 : public __bool_constant::value> { };
@@ -648,6 +654,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   template
 struct is_function<_Tp&&>
 : public false_type { };
+#endif
 
 #ifdef __cpp_lib_is_null_pointer // C++ >= 11
   /// is_null_pointer (LWG 2247).
@@ -3269,8 +3276,18 @@ template 
   inline constexpr bool is_union_v = __is_union(_Tp);
 template 
   inline constexpr bool is_class_v = __is_class(_Tp);
+
+#if _GLIBCXX_USE_BUILTIN_TRAIT(__is_function)
 template 
-  inline constexpr bool is_function_v = is_function<_Tp>::value;
+  inline constexpr bool is_function_v = __is_function(_Tp);
+#else
+template 
+  inline constexpr bool is_function_v = !is_const_v;
+template 
+  inline constexpr bool is_function_v<_Tp&> = false;
+template 
+  inline constexpr bool is_function_v<_Tp&&> = false;
+#endif
 
 #if _GLIBCXX_USE_BUILTIN_TRAIT(__is_reference)
 template 
-- 
2.42.0

[PATCH v11 14/40] c++: Implement __is_member_pointer built-in trait

[Ken Matsui via Gcc-patches]

This patch implements built-in trait for std::is_member_pointer.

gcc/cp/ChangeLog:

* cp-trait.def: Define __is_member_pointer.
* constraint.cc (diagnose_trait_expr): Handle CPTK_IS_MEMBER_POINTER.
* semantics.cc (trait_expr_value): Likewise.
(finish_trait_expr): Likewise.

gcc/testsuite/ChangeLog:

* g++.dg/ext/has-builtin-1.C: Test existence of __is_member_pointer.
* g++.dg/ext/is_member_pointer.C: New test.

Signed-off-by: Ken Matsui 
---
 gcc/cp/constraint.cc |  3 ++
 gcc/cp/cp-trait.def  |  1 +
 gcc/cp/semantics.cc  |  4 +++
 gcc/testsuite/g++.dg/ext/has-builtin-1.C |  3 ++
 gcc/testsuite/g++.dg/ext/is_member_pointer.C | 30 
 5 files changed, 41 insertions(+)
 create mode 100644 gcc/testsuite/g++.dg/ext/is_member_pointer.C

diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc
index 1c0b2e0f178..f0d3f89464c 100644
--- a/gcc/cp/constraint.cc
+++ b/gcc/cp/constraint.cc
@@ -3756,6 +3756,9 @@ diagnose_trait_expr (tree expr, tree args)
 case CPTK_IS_LITERAL_TYPE:
   inform (loc, "  %qT is not a literal type", t1);
   break;
+case CPTK_IS_MEMBER_POINTER:
+  inform (loc, "  %qT is not a member pointer", t1);
+  break;
 case CPTK_IS_NOTHROW_ASSIGNABLE:
   inform (loc, "  %qT is not nothrow assignable from %qT", t1, t2);
   break;
diff --git a/gcc/cp/cp-trait.def b/gcc/cp/cp-trait.def
index 047307c95ce..7fed3483221 100644
--- a/gcc/cp/cp-trait.def
+++ b/gcc/cp/cp-trait.def
@@ -72,6 +72,7 @@ DEFTRAIT_EXPR (IS_ENUM, "__is_enum", 1)
 DEFTRAIT_EXPR (IS_FINAL, "__is_final", 1)
 DEFTRAIT_EXPR (IS_LAYOUT_COMPATIBLE, "__is_layout_compatible", 2)
 DEFTRAIT_EXPR (IS_LITERAL_TYPE, "__is_literal_type", 1)
+DEFTRAIT_EXPR (IS_MEMBER_POINTER, "__is_member_pointer", 1)
 DEFTRAIT_EXPR (IS_NOTHROW_ASSIGNABLE, "__is_nothrow_assignable", 2)
 DEFTRAIT_EXPR (IS_NOTHROW_CONSTRUCTIBLE, "__is_nothrow_constructible", -1)
 DEFTRAIT_EXPR (IS_NOTHROW_CONVERTIBLE, "__is_nothrow_convertible", 2)
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index 7f89616aa03..84291d660ce 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -12169,6 +12169,9 @@ trait_expr_value (cp_trait_kind kind, tree type1, tree 
type2)
 case CPTK_IS_LITERAL_TYPE:
   return literal_type_p (type1);
 
+case CPTK_IS_MEMBER_POINTER:
+  return TYPE_PTRMEM_P (type1);
+
 case CPTK_IS_NOTHROW_ASSIGNABLE:
   return is_nothrow_xible (MODIFY_EXPR, type1, type2);
 
@@ -12378,6 +12381,7 @@ finish_trait_expr (location_t loc, cp_trait_kind kind, 
tree type1, tree type2)
 case CPTK_IS_CLASS:
 case CPTK_IS_CONST:
 case CPTK_IS_ENUM:
+case CPTK_IS_MEMBER_POINTER:
 case CPTK_IS_SAME:
 case CPTK_IS_SCOPED_ENUM:
 case CPTK_IS_UNBOUNDED_ARRAY:
diff --git a/gcc/testsuite/g++.dg/ext/has-builtin-1.C 
b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
index ba97beea3c3..994873f14e9 100644
--- a/gcc/testsuite/g++.dg/ext/has-builtin-1.C
+++ b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
@@ -95,6 +95,9 @@
 #if !__has_builtin (__is_literal_type)
 # error "__has_builtin (__is_literal_type) failed"
 #endif
+#if !__has_builtin (__is_member_pointer)
+# error "__has_builtin (__is_member_pointer) failed"
+#endif
 #if !__has_builtin (__is_nothrow_assignable)
 # error "__has_builtin (__is_nothrow_assignable) failed"
 #endif
diff --git a/gcc/testsuite/g++.dg/ext/is_member_pointer.C 
b/gcc/testsuite/g++.dg/ext/is_member_pointer.C
new file mode 100644
index 000..7ee2e3ab90c
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/is_member_pointer.C
@@ -0,0 +1,30 @@
+// { dg-do compile { target c++11 } }
+
+#include 
+
+using namespace __gnu_test;
+
+#define SA(X) static_assert((X),#X)
+
+#define SA_TEST_NON_VOLATILE(TRAIT, TYPE, EXPECT)  \
+  SA(TRAIT(TYPE) == EXPECT);   \
+  SA(TRAIT(const TYPE) == EXPECT)
+
+#define SA_TEST_CATEGORY(TRAIT, TYPE, EXPECT)  \
+  SA(TRAIT(TYPE) == EXPECT);   \
+  SA(TRAIT(const TYPE) == EXPECT); \
+  SA(TRAIT(volatile TYPE) == EXPECT);  \
+  SA(TRAIT(const volatile TYPE) == EXPECT)
+
+SA_TEST_CATEGORY(__is_member_pointer, int (ClassType::*), true);
+SA_TEST_CATEGORY(__is_member_pointer, ClassType (ClassType::*), true);
+
+SA_TEST_NON_VOLATILE(__is_member_pointer, int (ClassType::*)(int), true);
+SA_TEST_NON_VOLATILE(__is_member_pointer, int (ClassType::*)(int) const, true);
+SA_TEST_NON_VOLATILE(__is_member_pointer, int (ClassType::*)(float, ...), 
true);
+SA_TEST_NON_VOLATILE(__is_member_pointer, ClassType (ClassType::*)(ClassType), 
true);
+SA_TEST_NON_VOLATILE(__is_member_pointer,
+float (ClassType::*)(int, float, int[], int&), true);
+
+// Sanity check.
+SA_TEST_CATEGORY(__is_member_pointer, ClassType, false);
-- 
2.42.0

[PATCH v11 40/40] libstdc++: Optimize is_scalar trait performance

[Ken Matsui via Gcc-patches]

This patch optimizes the performance of the is_scalar trait by dispatching to
the new __is_scalar built-in trait.

libstdc++-v3/ChangeLog:

* include/std/type_traits (is_scalar): Use __is_scalar built-in
trait.
(is_scalar_v): Likewise.

Signed-off-by: Ken Matsui 
---
 libstdc++-v3/include/std/type_traits | 13 +
 1 file changed, 13 insertions(+)

diff --git a/libstdc++-v3/include/std/type_traits 
b/libstdc++-v3/include/std/type_traits
index 7e93923f44b..eb16a642575 100644
--- a/libstdc++-v3/include/std/type_traits
+++ b/libstdc++-v3/include/std/type_traits
@@ -775,11 +775,18 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 struct is_member_pointer;
 
   /// is_scalar
+#if _GLIBCXX_USE_BUILTIN_TRAIT(__is_scalar)
+  template
+struct is_scalar
+: public __bool_constant<__is_scalar(_Tp)>
+{ };
+#else
   template
 struct is_scalar
 : public __or_, is_enum<_Tp>, is_pointer<_Tp>,
is_member_pointer<_Tp>, is_null_pointer<_Tp>>::type
 { };
+#endif
 
   /// is_compound
   template
@@ -3398,8 +3405,14 @@ template 
   inline constexpr bool is_object_v = is_object<_Tp>::value;
 #endif
 
+#if _GLIBCXX_USE_BUILTIN_TRAIT(__is_scalar)
+template 
+  inline constexpr bool is_scalar_v = __is_scalar(_Tp);
+#else
 template 
   inline constexpr bool is_scalar_v = is_scalar<_Tp>::value;
+#endif
+
 template 
   inline constexpr bool is_compound_v = !is_fundamental_v<_Tp>;
 
-- 
2.42.0

[PATCH v11 23/40] libstdc++: Optimize is_reference trait performance

[Ken Matsui via Gcc-patches]

This patch optimizes the performance of the is_reference trait by dispatching
to the new __is_reference built-in trait.

libstdc++-v3/ChangeLog:

* include/std/type_traits (is_reference): Use __is_reference built-in
trait.
(is_reference_v): Likewise.

Signed-off-by: Ken Matsui 
---
 libstdc++-v3/include/std/type_traits | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/libstdc++-v3/include/std/type_traits 
b/libstdc++-v3/include/std/type_traits
index 792213ebfe8..36ad9814047 100644
--- a/libstdc++-v3/include/std/type_traits
+++ b/libstdc++-v3/include/std/type_traits
@@ -682,6 +682,12 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   // Composite type categories.
 
   /// is_reference
+#if _GLIBCXX_USE_BUILTIN_TRAIT(__is_reference)
+  template
+struct is_reference
+: public __bool_constant<__is_reference(_Tp)>
+{ };
+#else
   template
 struct is_reference
 : public false_type
@@ -696,6 +702,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 struct is_reference<_Tp&&>
 : public true_type
 { };
+#endif
 
   /// is_arithmetic
   template
@@ -3264,12 +3271,19 @@ template 
   inline constexpr bool is_class_v = __is_class(_Tp);
 template 
   inline constexpr bool is_function_v = is_function<_Tp>::value;
+
+#if _GLIBCXX_USE_BUILTIN_TRAIT(__is_reference)
+template 
+  inline constexpr bool is_reference_v = __is_reference(_Tp);
+#else
 template 
   inline constexpr bool is_reference_v = false;
 template 
   inline constexpr bool is_reference_v<_Tp&> = true;
 template 
   inline constexpr bool is_reference_v<_Tp&&> = true;
+#endif
+
 template 
   inline constexpr bool is_arithmetic_v = is_arithmetic<_Tp>::value;
 template 
-- 
2.42.0

[PATCH v11 20/40] c++: Implement __is_member_object_pointer built-in trait

[Ken Matsui via Gcc-patches]

This patch implements built-in trait for std::is_member_object_pointer.

gcc/cp/ChangeLog:

* cp-trait.def: Define __is_member_object_pointer.
* constraint.cc (diagnose_trait_expr): Handle
CPTK_IS_MEMBER_OBJECT_POINTER.
* semantics.cc (trait_expr_value): Likewise.
(finish_trait_expr): Likewise.

gcc/testsuite/ChangeLog:

* g++.dg/ext/has-builtin-1.C: Test existence of
__is_member_object_pointer.
* g++.dg/ext/is_member_object_pointer.C: New test.

Signed-off-by: Ken Matsui 
---
 gcc/cp/constraint.cc  |  3 ++
 gcc/cp/cp-trait.def   |  1 +
 gcc/cp/semantics.cc   |  4 +++
 gcc/testsuite/g++.dg/ext/has-builtin-1.C  |  3 ++
 .../g++.dg/ext/is_member_object_pointer.C | 30 +++
 5 files changed, 41 insertions(+)
 create mode 100644 gcc/testsuite/g++.dg/ext/is_member_object_pointer.C

diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc
index d0464dd4f6a..98b1f004a68 100644
--- a/gcc/cp/constraint.cc
+++ b/gcc/cp/constraint.cc
@@ -3759,6 +3759,9 @@ diagnose_trait_expr (tree expr, tree args)
 case CPTK_IS_MEMBER_FUNCTION_POINTER:
   inform (loc, "  %qT is not a member function pointer", t1);
   break;
+case CPTK_IS_MEMBER_OBJECT_POINTER:
+  inform (loc, "  %qT is not a member object pointer", t1);
+  break;
 case CPTK_IS_MEMBER_POINTER:
   inform (loc, "  %qT is not a member pointer", t1);
   break;
diff --git a/gcc/cp/cp-trait.def b/gcc/cp/cp-trait.def
index 6ebe3984d17..47649150ab5 100644
--- a/gcc/cp/cp-trait.def
+++ b/gcc/cp/cp-trait.def
@@ -73,6 +73,7 @@ DEFTRAIT_EXPR (IS_FINAL, "__is_final", 1)
 DEFTRAIT_EXPR (IS_LAYOUT_COMPATIBLE, "__is_layout_compatible", 2)
 DEFTRAIT_EXPR (IS_LITERAL_TYPE, "__is_literal_type", 1)
 DEFTRAIT_EXPR (IS_MEMBER_FUNCTION_POINTER, "__is_member_function_pointer", 1)
+DEFTRAIT_EXPR (IS_MEMBER_OBJECT_POINTER, "__is_member_object_pointer", 1)
 DEFTRAIT_EXPR (IS_MEMBER_POINTER, "__is_member_pointer", 1)
 DEFTRAIT_EXPR (IS_NOTHROW_ASSIGNABLE, "__is_nothrow_assignable", 2)
 DEFTRAIT_EXPR (IS_NOTHROW_CONSTRUCTIBLE, "__is_nothrow_constructible", -1)
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index 294bcf3dcca..534f24a1f9c 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -12172,6 +12172,9 @@ trait_expr_value (cp_trait_kind kind, tree type1, tree 
type2)
 case CPTK_IS_MEMBER_FUNCTION_POINTER:
   return TYPE_PTRMEMFUNC_P (type1);
 
+case CPTK_IS_MEMBER_OBJECT_POINTER:
+  return TYPE_PTRMEM_P (type1) && !TYPE_PTRMEMFUNC_P (type1);
+
 case CPTK_IS_MEMBER_POINTER:
   return TYPE_PTRMEM_P (type1);
 
@@ -12385,6 +12388,7 @@ finish_trait_expr (location_t loc, cp_trait_kind kind, 
tree type1, tree type2)
 case CPTK_IS_CONST:
 case CPTK_IS_ENUM:
 case CPTK_IS_MEMBER_FUNCTION_POINTER:
+case CPTK_IS_MEMBER_OBJECT_POINTER:
 case CPTK_IS_MEMBER_POINTER:
 case CPTK_IS_SAME:
 case CPTK_IS_SCOPED_ENUM:
diff --git a/gcc/testsuite/g++.dg/ext/has-builtin-1.C 
b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
index 0dfe957474b..8d9cdc528cd 100644
--- a/gcc/testsuite/g++.dg/ext/has-builtin-1.C
+++ b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
@@ -98,6 +98,9 @@
 #if !__has_builtin (__is_member_function_pointer)
 # error "__has_builtin (__is_member_function_pointer) failed"
 #endif
+#if !__has_builtin (__is_member_object_pointer)
+# error "__has_builtin (__is_member_object_pointer) failed"
+#endif
 #if !__has_builtin (__is_member_pointer)
 # error "__has_builtin (__is_member_pointer) failed"
 #endif
diff --git a/gcc/testsuite/g++.dg/ext/is_member_object_pointer.C 
b/gcc/testsuite/g++.dg/ext/is_member_object_pointer.C
new file mode 100644
index 000..835e48c8f8e
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/is_member_object_pointer.C
@@ -0,0 +1,30 @@
+// { dg-do compile { target c++11 } }
+
+#include 
+
+using namespace __gnu_test;
+
+#define SA(X) static_assert((X),#X)
+
+#define SA_TEST_NON_VOLATILE(TRAIT, TYPE, EXPECT)  \
+  SA(TRAIT(TYPE) == EXPECT);   \
+  SA(TRAIT(const TYPE) == EXPECT)
+
+#define SA_TEST_CATEGORY(TRAIT, TYPE, EXPECT)  \
+  SA(TRAIT(TYPE) == EXPECT);   \
+  SA(TRAIT(const TYPE) == EXPECT); \
+  SA(TRAIT(volatile TYPE) == EXPECT);  \
+  SA(TRAIT(const volatile TYPE) == EXPECT)
+
+// Positive tests.
+SA_TEST_CATEGORY(__is_member_object_pointer, int (ClassType::*), true);
+SA_TEST_CATEGORY(__is_member_object_pointer, ClassType (ClassType::*), true);
+
+// Negative tests.
+SA_TEST_NON_VOLATILE(__is_member_object_pointer, int (ClassType::*) (int), 
false);
+SA_TEST_NON_VOLATILE(__is_member_object_pointer, int (ClassType::*) (float, 
...), false);
+SA_TEST_NON_VOLATILE(__is_member_object_pointer, ClassType (ClassType::*) 
(ClassType), false);
+SA_TEST_NON_VOLATILE(__is_member_object_pointer, float (ClassType::*) (i

[PATCH v11 12/40] c++: Implement __is_scoped_enum built-in trait

[Ken Matsui via Gcc-patches]

This patch implements built-in trait for std::is_scoped_enum.

gcc/cp/ChangeLog:

* cp-trait.def: Define __is_scoped_enum.
* constraint.cc (diagnose_trait_expr): Handle CPTK_IS_SCOPED_ENUM.
* semantics.cc (trait_expr_value): Likewise.
(finish_trait_expr): Likewise.

gcc/testsuite/ChangeLog:

* g++.dg/ext/has-builtin-1.C: Test existence of __is_scoped_enum.
* g++.dg/ext/is_scoped_enum.C: New test.

Signed-off-by: Ken Matsui 
---
 gcc/cp/constraint.cc  |  3 +
 gcc/cp/cp-trait.def   |  1 +
 gcc/cp/semantics.cc   |  4 ++
 gcc/testsuite/g++.dg/ext/has-builtin-1.C  |  3 +
 gcc/testsuite/g++.dg/ext/is_scoped_enum.C | 67 +++
 5 files changed, 78 insertions(+)
 create mode 100644 gcc/testsuite/g++.dg/ext/is_scoped_enum.C

diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc
index d09252a56b6..1c0b2e0f178 100644
--- a/gcc/cp/constraint.cc
+++ b/gcc/cp/constraint.cc
@@ -3781,6 +3781,9 @@ diagnose_trait_expr (tree expr, tree args)
 case CPTK_IS_SAME:
   inform (loc, "  %qT is not the same as %qT", t1, t2);
   break;
+case CPTK_IS_SCOPED_ENUM:
+  inform (loc, "  %qT is not a scoped enum", t1);
+  break;
 case CPTK_IS_STD_LAYOUT:
   inform (loc, "  %qT is not an standard layout type", t1);
   break;
diff --git a/gcc/cp/cp-trait.def b/gcc/cp/cp-trait.def
index b6146c010f6..047307c95ce 100644
--- a/gcc/cp/cp-trait.def
+++ b/gcc/cp/cp-trait.def
@@ -79,6 +79,7 @@ DEFTRAIT_EXPR (IS_POINTER_INTERCONVERTIBLE_BASE_OF, 
"__is_pointer_interconvertib
 DEFTRAIT_EXPR (IS_POD, "__is_pod", 1)
 DEFTRAIT_EXPR (IS_POLYMORPHIC, "__is_polymorphic", 1)
 DEFTRAIT_EXPR (IS_SAME, "__is_same", 2)
+DEFTRAIT_EXPR (IS_SCOPED_ENUM, "__is_scoped_enum", 1)
 DEFTRAIT_EXPR (IS_STD_LAYOUT, "__is_standard_layout", 1)
 DEFTRAIT_EXPR (IS_TRIVIAL, "__is_trivial", 1)
 DEFTRAIT_EXPR (IS_TRIVIALLY_ASSIGNABLE, "__is_trivially_assignable", 2)
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index bf6438fcfc5..7f89616aa03 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -12190,6 +12190,9 @@ trait_expr_value (cp_trait_kind kind, tree type1, tree 
type2)
 case CPTK_IS_SAME:
   return same_type_p (type1, type2);
 
+case CPTK_IS_SCOPED_ENUM:
+  return SCOPED_ENUM_P (type1);
+
 case CPTK_IS_STD_LAYOUT:
   return std_layout_type_p (type1);
 
@@ -12376,6 +12379,7 @@ finish_trait_expr (location_t loc, cp_trait_kind kind, 
tree type1, tree type2)
 case CPTK_IS_CONST:
 case CPTK_IS_ENUM:
 case CPTK_IS_SAME:
+case CPTK_IS_SCOPED_ENUM:
 case CPTK_IS_UNBOUNDED_ARRAY:
 case CPTK_IS_UNION:
 case CPTK_IS_VOLATILE:
diff --git a/gcc/testsuite/g++.dg/ext/has-builtin-1.C 
b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
index 4142da518b1..ba97beea3c3 100644
--- a/gcc/testsuite/g++.dg/ext/has-builtin-1.C
+++ b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
@@ -119,6 +119,9 @@
 #if !__has_builtin (__is_same_as)
 # error "__has_builtin (__is_same_as) failed"
 #endif
+#if !__has_builtin (__is_scoped_enum)
+# error "__has_builtin (__is_scoped_enum) failed"
+#endif
 #if !__has_builtin (__is_standard_layout)
 # error "__has_builtin (__is_standard_layout) failed"
 #endif
diff --git a/gcc/testsuite/g++.dg/ext/is_scoped_enum.C 
b/gcc/testsuite/g++.dg/ext/is_scoped_enum.C
new file mode 100644
index 000..a563b6ee67d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/is_scoped_enum.C
@@ -0,0 +1,67 @@
+// { dg-do compile { target c++11 } }
+
+#include 
+
+using namespace __gnu_test;
+
+#define SA(X) static_assert((X),#X)
+
+#define SA_TEST_FN(TRAIT, TYPE, EXPECT)\
+  SA(TRAIT(TYPE) == EXPECT);   \
+  SA(TRAIT(const TYPE) == EXPECT);
+
+#define SA_TEST_CATEGORY(TRAIT, TYPE, EXPECT)  \
+  SA(TRAIT(TYPE) == EXPECT);   \
+  SA(TRAIT(const TYPE) == EXPECT); \
+  SA(TRAIT(volatile TYPE) == EXPECT);  \
+  SA(TRAIT(const volatile TYPE) == EXPECT)
+
+enum class E { e1, e2 };
+SA_TEST_CATEGORY(__is_scoped_enum, E, true);
+enum class Ec : char { e1, e2 };
+SA_TEST_CATEGORY(__is_scoped_enum, Ec, true);
+
+// negative tests
+enum U { u1, u2 };
+SA_TEST_CATEGORY(__is_scoped_enum, U, false);
+enum F : int { f1, f2 };
+SA_TEST_CATEGORY(__is_scoped_enum, F, false);
+struct S;
+SA_TEST_CATEGORY(__is_scoped_enum, S, false);
+struct S { };
+SA_TEST_CATEGORY(__is_scoped_enum, S, false);
+
+SA_TEST_CATEGORY(__is_scoped_enum, int, false);
+SA_TEST_CATEGORY(__is_scoped_enum, int[], false);
+SA_TEST_CATEGORY(__is_scoped_enum, int[2], false);
+SA_TEST_CATEGORY(__is_scoped_enum, int[][2], false);
+SA_TEST_CATEGORY(__is_scoped_enum, int[2][3], false);
+SA_TEST_CATEGORY(__is_scoped_enum, int*, false);
+SA_TEST_CATEGORY(__is_scoped_enum, int&, false);
+SA_TEST_CATEGORY(__is_scoped_enum, int*&, false);
+SA_TEST_FN(__is_scoped_enum, int(), false);
+SA_TEST_FN(__is_scoped_enum, int(*)(), false);
+SA_TEST_F

Re: gcc-patches From rewriting mailman settings (Was: [Linaro-TCWG-CI] gcc patch #75674: FAIL: 68 regressions)

[Thomas Schwinge]

Hi Mark!

On 2023-09-13T17:02:05+0100, Iain Sandoe  wrote:
>> On 12 Sep 2023, at 16:00, Mark Wielaard  wrote:
>> Adding Jeff to CC who is the official gcc-patches mailinglist admin.
>>
>> On Tue, 2023-09-12 at 11:08 +0400, Maxim Kuvyrkov wrote:
>>> Normally, notifications from Linaro TCWG precommit CI are sent only to
>>> patch author and patch submitter.  In this case the sender was rewritten
>>> to "Benjamin Priour via Gcc-patches ",
>>> which was detected by Patchwork [1] as patch submitter.
>>
>> BTW. Really looking forward to your talk at Cauldron about this!

(Yes!)

>>> Is "From:" re-write on gcc-patches@ mailing list a side-effect of [2]?
>>> I see that some, but not all messages to gcc-patches@ have their
>>> "From:" re-written.
>>>
>>> Also, do you know if re-write of "From:" on gcc-patches@ is expected?
>>
>> Yes, it is expected for emails that come from domains with a dmarc
>> policy. That is because the current settings of the gcc-patches
>> mailinglist might slightly alter the message or headers in a way that
>> invalidates the DKIM signature. Without From rewriting those messages
>> would be bounced by recipients that check the dmarc policy/dkim
>> signature.
>>
>> As you noticed the glibc hackers have recently worked together with the
>> sourceware overseers to upgrade mailman and alter the postfix and the
>> libc-alpha mailinglist setting so it doesn't require From rewriting
>> anymore (the message and header aren't altered anymore to invalidate
>> the DKIM signatures).
>>
>> We (Jeff or anyone else with mailman admin privs) could use the same
>> settings for gcc-patches. The settings that need to be set are in that
>> bug:
>>
>> - subject_prefix (general): (empty)
>> - from_is_list (general): No
>> - anonymous_list (general): No
>> - first_strip_reply_to (general): No
>> - reply_goes_to_list (general): Poster
>> - reply_to_address (general): (empty)
>> - include_sender_header (general): No
>> - drop_cc (general): No
>> - msg_header (nondigest): (empty)
>> - msg_footer (nondigest): (empty)
>> - scrub_nondigest (nondigest): No
>> - dmarc_moderation_action (privacy): Accept
>> - filter_content (contentfilter): No
>>
>> The only visible change (apart from no more From rewriting) is that
>> HTML multi-parts aren't scrubbed anymore (that would be a message
>> altering issue). The html part is still scrubbed from the
>> inbox.sourceware.org archive, so b4 works just fine. But I don't know
>> what patchwork.sourceware.org does with HTML attachements. Of course
>> people really shouldn't sent HTML attachments to gcc-patches, so maybe
>> this is no real problem.
>>
>> Let me know if you want Jeff (or me or one of the other overseers) make
>> the above changes to the gcc-patches mailman settings.
>
> yes, please!

Yes, please!  For all mailing lists, globally.


Grüße
 Thomas
-
Siemens Electronic Design Automation GmbH; Anschrift: Arnulfstraße 201, 80634 
München; Gesellschaft mit beschränkter Haftung; Geschäftsführer: Thomas 
Heurung, Frank Thürauf; Sitz der Gesellschaft: München; Registergericht 
München, HRB 106955

Re: [pushed][PATCH] LoongArch: Change the value of branch_cost from 2 to 6.

[chenglulu]

Pushed to r14-3977.

在 2023/9/13 上午11:11, Lulu Cheng 写道:

gcc/ChangeLog:

* config/loongarch/loongarch-def.c: Modify the default value of
branch_cost.

gcc/testsuite/ChangeLog:

* gcc.target/loongarch/cmov_ii.c: New test.
---
  gcc/config/loongarch/loongarch-def.c |  4 ++--
  gcc/testsuite/gcc.target/loongarch/cmov_ii.c | 16 
  2 files changed, 18 insertions(+), 2 deletions(-)
  create mode 100644 gcc/testsuite/gcc.target/loongarch/cmov_ii.c

diff --git a/gcc/config/loongarch/loongarch-def.c 
b/gcc/config/loongarch/loongarch-def.c
index e744ee01d6d..430ef8b2d95 100644
--- a/gcc/config/loongarch/loongarch-def.c
+++ b/gcc/config/loongarch/loongarch-def.c
@@ -85,7 +85,7 @@ loongarch_cpu_align[N_TUNE_TYPES] = {
  .int_mult_di  = COSTS_N_INSNS (1),\
  .int_div_si   = COSTS_N_INSNS (4),\
  .int_div_di   = COSTS_N_INSNS (6),\
-.branch_cost   = 2,\
+.branch_cost   = 6,\
  .memory_latency   = 4
  
  /* The following properties cannot be looked up directly using "cpucfg".

@@ -118,7 +118,7 @@ loongarch_rtx_cost_optimize_size = {
  .int_mult_di  = 4,
  .int_div_si = 4,
  .int_div_di = 4,
-.branch_cost  = 2,
+.branch_cost  = 6,
  .memory_latency   = 4,
  };
  
diff --git a/gcc/testsuite/gcc.target/loongarch/cmov_ii.c b/gcc/testsuite/gcc.target/loongarch/cmov_ii.c

new file mode 100644
index 000..466a4c1c9af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/cmov_ii.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler "main:.*xor.*masknez.*maskeqz.*or.*" } }
+ */
+void printf (char *, ...);
+extern void foo_ii (int *, int *, int *, int *);
+
+int
+test (void)
+{
+  int a, b;
+  int c, d, out;
+  foo_ii (&a, &b, &c, &d);
+  out = a == b ? c : d;
+  printf ("%d\n", out);
+}

[PATCH V2] RISC-V: Fix ICE in get_avl_or_vl_reg

[Juzhe-Zhong]

update v1 -> v2: Add available fortran compiler check in rvv-fortran.exp.
This patch fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395 ICE

PR target/111395

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (avl_info::operator==): Fix ICE.
(vector_insn_info::global_merge): Ditto.
(vector_insn_info::get_avl_or_vl_reg): Ditto.
(pass_vsetvl::global_eliminate_vsetvl_insn): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/fortran/pr111395.f90: New test.
* gcc.target/riscv/rvv/rvv-fortran.exp: New test.

---
 gcc/config/riscv/riscv-vsetvl.cc  | 31 -
 .../gcc.target/riscv/rvv/fortran/pr111395.f90 | 41 +
 .../gcc.target/riscv/rvv/rvv-fortran.exp  | 45 +++
 3 files changed, 105 insertions(+), 12 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index f81361c4ccd..dc02246756d 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1652,6 +1652,8 @@ avl_info::operator== (const avl_info &other) const
   /* Handle VLMAX AVL.  */
   if (vlmax_avl_p (m_value))
 return vlmax_avl_p (other.get_value ());
+  if (vlmax_avl_p (other.get_value ()))
+return false;
 
   /* If any source is undef value, we think they are not equal.  */
   if (!m_source || !other.get_source ())
@@ -2258,6 +2260,18 @@ vector_insn_info::global_merge (const vector_insn_info 
&merge_info,
new_info.set_avl_source (first_set);
 }
 
+  /* Make sure VLMAX AVL always has a set_info the get VL.  */
+  if (vlmax_avl_p (new_info.get_avl ()))
+{
+  if (this->get_avl_source ())
+   new_info.set_avl_source (this->get_avl_source ());
+  else
+   {
+ gcc_assert (merge_info.get_avl_source ());
+ new_info.set_avl_source (merge_info.get_avl_source ());
+   }
+}
+
   new_info.fuse_sew_lmul (*this, merge_info);
   new_info.fuse_tail_policy (*this, merge_info);
   new_info.fuse_mask_policy (*this, merge_info);
@@ -2274,9 +2288,6 @@ vector_insn_info::get_avl_or_vl_reg (void) const
   if (!vlmax_avl_p (get_avl ()))
 return get_avl ();
 
-  if (get_avl_source ())
-return get_avl_reg_rtx ();
-
   rtx_insn *rinsn = get_insn ()->rtl ();
   if (has_vl_op (rinsn) || vsetvl_insn_p (rinsn))
 {
@@ -2288,14 +2299,9 @@ vector_insn_info::get_avl_or_vl_reg (void) const
return vl;
 }
 
-  /* A DIRTY (polluted EMPTY) block if:
-   - get_insn is scalar move (no AVL or VL operand).
-   - get_avl_source is null (no def in the current DIRTY block).
- Then we trace the previous insn which must be the insn
- already inserted in Phase 2 to get the VL operand for VLMAX.  */
-  rtx_insn *prev_rinsn = PREV_INSN (rinsn);
-  gcc_assert (prev_rinsn && vsetvl_insn_p (prev_rinsn));
-  return ::get_vl (prev_rinsn);
+  /* We always has avl_source if it is VLMAX AVL.  */
+  gcc_assert (get_avl_source ());
+  return get_avl_reg_rtx ();
 }
 
 bool
@@ -4054,7 +4060,8 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const bb_info 
*bb) const
 }
 
   /* Step1: Reshape the VL/VTYPE status to make sure everything compatible.  */
-  auto_vec pred_cfg_bbs = get_dominated_by (CDI_POST_DOMINATORS, 
cfg_bb);
+  auto_vec pred_cfg_bbs
+= get_dominated_by (CDI_POST_DOMINATORS, cfg_bb);
   FOR_EACH_EDGE (e, ei, cfg_bb->preds)
 {
   sbitmap avout = m_vector_manager->vector_avout[e->src->index];
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90 
b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
new file mode 100644
index 000..71253fe6bc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
@@ -0,0 +1,41 @@
+! { dg-do compile }
+! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -std=legacy" }
+
+MODULE a
+  REAL b
+CONTAINS
+  SUBROUTINE c(d,KTE)
+REAL,DIMENSION(KTE) :: d,e,f,g
+REAL,DIMENSION(KTE) :: h
+i : DO j=1,b
+   z=k
+   DO l=m,n
+  IF(o>=p)THEN
+ IF(laf)THEN
+   DO l=m,n
+  d=h
+   ENDDO
+ENDIF
+  END SUBROUTINE c
+END MODULE a
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp 
b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
new file mode 100644
index 000..88d82281d43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
@@ -0,0 +1,45 @@
+#   Copyright (C) 2023-2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABIL

Re: [PATCH] libstdc++: Remove some more unconditional uses of atomics

[Christophe Lyon via Gcc-patches]

Hi,


On Wed, 13 Sept 2023 at 14:32, Jonathan Wakely  wrote:

> Tested x86_64-linux and aarch64-linux. I intend to push this to trunk.
>
> -- >8 --
>
> These atomics cause linker errors on arm4t where __sync_synchronize is
> not defined. For single-threaded targets we don't need the atomics.
>
>
I ran the tests on arm-eabi default config (so, armv4t) with this patch,
and here is the list of remaining UNRESOLVED tests:
 29_atomics/atomic/compare_exchange_padding.cc
29_atomics/atomic/cons/value_init.cc
29_atomics/atomic_float/value_init.cc
29_atomics/atomic_integral/cons/value_init.cc
29_atomics/atomic_ref/compare_exchange_padding.cc
29_atomics/atomic_ref/generic.cc
29_atomics/atomic_ref/integral.cc
29_atomics/atomic_ref/pointer.cc
experimental/polymorphic_allocator/construct_pair.cc

all of them are due to undefined reference to __sync_synchronize
(some also reference __atomic_compare_exchange_4, etc...)


IIUC, this should not be the case for
experimental/polymorphic_allocator/construct_pair.cc ?
The reference for __sync_synchronize is near the beginning of test0[123]
from a call to __atomic_load_n line 835 of atomic_base.h
not sure where it comes from, the .loc directive indicates line 28 of the
testcase which is the opening brace

HTH

Christophe


libstdc++-v3/ChangeLog:
>
> * include/experimental/io_context (io_context)
> [!_GLIBCXX_HAS_GTHREADS]:
> Use a plain integer for _M_work_count for single-threaded
> targets.
> * src/c++17/memory_resource.cc [!_GLIBCXX_HAS_GTHREADS]
> (atomic_mem_res): Use unsynchronized type for single-threaded
> targets.
> ---
>  libstdc++-v3/include/experimental/io_context |  4 ++
>  libstdc++-v3/src/c++17/memory_resource.cc| 49 ++--
>  2 files changed, 29 insertions(+), 24 deletions(-)
>
> diff --git a/libstdc++-v3/include/experimental/io_context
> b/libstdc++-v3/include/experimental/io_context
> index c59f8c8e73b..c878d5a7025 100644
> --- a/libstdc++-v3/include/experimental/io_context
> +++ b/libstdc++-v3/include/experimental/io_context
> @@ -562,7 +562,11 @@ inline namespace v1
> }
>};
>
> +#ifdef _GLIBCXX_HAS_GTHREADS
>  atomic _M_work_count;
> +#else
> +count_type _M_work_count;
> +#endif
>  mutable execution_context::mutex_type  _M_mtx;
>  queue>_M_op;
>  bool   _M_stopped = false;
> diff --git a/libstdc++-v3/src/c++17/memory_resource.cc
> b/libstdc++-v3/src/c++17/memory_resource.cc
> index c0c7cf0cf83..63856eadaf5 100644
> --- a/libstdc++-v3/src/c++17/memory_resource.cc
> +++ b/libstdc++-v3/src/c++17/memory_resource.cc
> @@ -27,9 +27,9 @@
>  #include 
>  #include  // has_single_bit, bit_ceil,
> bit_width
>  #include 
> +#include  // std::__exchange
>  #if ATOMIC_POINTER_LOCK_FREE != 2
>  # include// std::mutex, std::lock_guard
> -# include // std::__exchange
>  #endif
>
>  #if __has_cpp_attribute(clang::require_constant_initialization)
> @@ -94,10 +94,31 @@ namespace pmr
>
>  __constinit constant_init newdel_res{};
>  __constinit constant_init null_res{};
> -#if ATOMIC_POINTER_LOCK_FREE == 2
> +
> +#ifndef _GLIBCXX_HAS_GTHREADS
> +# define _GLIBCXX_ATOMIC_MEM_RES_CAN_BE_CONSTANT_INITIALIZED
> +// Single-threaded, no need for synchronization
> +struct atomic_mem_res
> +{
> +  constexpr
> +  atomic_mem_res(memory_resource* r) : val(r) { }
> +
> +  memory_resource* val;
> +
> +  memory_resource* load(std::memory_order) const
> +  {
> +   return val;
> +  }
> +
> +  memory_resource* exchange(memory_resource* r, std::memory_order)
> +  {
> +   return std::__exchange(val, r);
> +  }
> +};
> +#elif ATOMIC_POINTER_LOCK_FREE == 2
>  using atomic_mem_res = atomic;
>  # define _GLIBCXX_ATOMIC_MEM_RES_CAN_BE_CONSTANT_INITIALIZED
> -#elif defined(_GLIBCXX_HAS_GTHREADS)
> +#else
>  // Can't use pointer-width atomics, define a type using a mutex
> instead:
>  struct atomic_mem_res
>  {
> @@ -123,27 +144,7 @@ namespace pmr
> return std::__exchange(val, r);
>}
>  };
> -#else
> -# define _GLIBCXX_ATOMIC_MEM_RES_CAN_BE_CONSTANT_INITIALIZED
> -// Single-threaded, no need for synchronization
> -struct atomic_mem_res
> -{
> -  constexpr
> -  atomic_mem_res(memory_resource* r) : val(r) { }
> -
> -  memory_resource* val;
> -
> -  memory_resource* load(std::memory_order) const
> -  {
> -   return val;
> -  }
> -
> -  memory_resource* exchange(memory_resource* r, std::memory_order)
> -  {
> -   return std::__exchange(val, r);
> -  }
> -};
> -#endif // ATOMIC_POINTER_LOCK_FREE == 2
> +#endif
>
>  #ifdef _GLIBCXX_ATOMIC_MEM_RES_CAN_BE_CONSTANT_INITIALIZED
>  __constinit constant_init
> default_res{&newdel_res.obj};
> --
> 2.41.0
>
>

Re: [PATCH V2] RISC-V: Fix ICE in get_avl_or_vl_reg

[Kito Cheng via Gcc-patches]

LGTM with a minor comment.

> @@ -4054,7 +4060,8 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const 
> bb_info *bb) const
>  }
>
>/* Step1: Reshape the VL/VTYPE status to make sure everything compatible.  
> */
> -  auto_vec pred_cfg_bbs = get_dominated_by 
> (CDI_POST_DOMINATORS, cfg_bb);
> +  auto_vec pred_cfg_bbs
> += get_dominated_by (CDI_POST_DOMINATORS, cfg_bb);

This change seems like a format fixing? If so plz split it into a
separate patch and apply clang-format to riscv-vsetvl.cc?
pre-approved for that reformat patch

>FOR_EACH_EDGE (e, ei, cfg_bb->preds)
>  {
>sbitmap avout = m_vector_manager->vector_avout[e->src->index];

[PATCH V3] RISC-V: Fix ICE in get_avl_or_vl_reg

[Juzhe-Zhong]

update v1 -> v2: Add available fortran compiler check in rvv-fortran.exp.

This patch fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395 ICE

update v2 -> v3: Remove redundant format.

PR target/111395

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (avl_info::operator==): Fix ICE.
(vector_insn_info::global_merge): Ditto.
(vector_insn_info::get_avl_or_vl_reg): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/fortran/pr111395.f90: New test.
* gcc.target/riscv/rvv/rvv-fortran.exp: New test.

---
 gcc/config/riscv/riscv-vsetvl.cc  | 28 +++-
 .../gcc.target/riscv/rvv/fortran/pr111395.f90 | 41 +
 .../gcc.target/riscv/rvv/rvv-fortran.exp  | 45 +++
 3 files changed, 103 insertions(+), 11 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index f81361c4ccd..8ec54092a48 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1652,6 +1652,8 @@ avl_info::operator== (const avl_info &other) const
   /* Handle VLMAX AVL.  */
   if (vlmax_avl_p (m_value))
 return vlmax_avl_p (other.get_value ());
+  if (vlmax_avl_p (other.get_value ()))
+return false;
 
   /* If any source is undef value, we think they are not equal.  */
   if (!m_source || !other.get_source ())
@@ -2258,6 +2260,18 @@ vector_insn_info::global_merge (const vector_insn_info 
&merge_info,
new_info.set_avl_source (first_set);
 }
 
+  /* Make sure VLMAX AVL always has a set_info the get VL.  */
+  if (vlmax_avl_p (new_info.get_avl ()))
+{
+  if (this->get_avl_source ())
+   new_info.set_avl_source (this->get_avl_source ());
+  else
+   {
+ gcc_assert (merge_info.get_avl_source ());
+ new_info.set_avl_source (merge_info.get_avl_source ());
+   }
+}
+
   new_info.fuse_sew_lmul (*this, merge_info);
   new_info.fuse_tail_policy (*this, merge_info);
   new_info.fuse_mask_policy (*this, merge_info);
@@ -2274,9 +2288,6 @@ vector_insn_info::get_avl_or_vl_reg (void) const
   if (!vlmax_avl_p (get_avl ()))
 return get_avl ();
 
-  if (get_avl_source ())
-return get_avl_reg_rtx ();
-
   rtx_insn *rinsn = get_insn ()->rtl ();
   if (has_vl_op (rinsn) || vsetvl_insn_p (rinsn))
 {
@@ -2288,14 +2299,9 @@ vector_insn_info::get_avl_or_vl_reg (void) const
return vl;
 }
 
-  /* A DIRTY (polluted EMPTY) block if:
-   - get_insn is scalar move (no AVL or VL operand).
-   - get_avl_source is null (no def in the current DIRTY block).
- Then we trace the previous insn which must be the insn
- already inserted in Phase 2 to get the VL operand for VLMAX.  */
-  rtx_insn *prev_rinsn = PREV_INSN (rinsn);
-  gcc_assert (prev_rinsn && vsetvl_insn_p (prev_rinsn));
-  return ::get_vl (prev_rinsn);
+  /* We always has avl_source if it is VLMAX AVL.  */
+  gcc_assert (get_avl_source ());
+  return get_avl_reg_rtx ();
 }
 
 bool
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90 
b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
new file mode 100644
index 000..71253fe6bc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
@@ -0,0 +1,41 @@
+! { dg-do compile }
+! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -std=legacy" }
+
+MODULE a
+  REAL b
+CONTAINS
+  SUBROUTINE c(d,KTE)
+REAL,DIMENSION(KTE) :: d,e,f,g
+REAL,DIMENSION(KTE) :: h
+i : DO j=1,b
+   z=k
+   DO l=m,n
+  IF(o>=p)THEN
+ IF(laf)THEN
+   DO l=m,n
+  d=h
+   ENDDO
+ENDIF
+  END SUBROUTINE c
+END MODULE a
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp 
b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
new file mode 100644
index 000..88d82281d43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
@@ -0,0 +1,45 @@
+#   Copyright (C) 2023-2023 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# .
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a RISC-V target.
+if { ![istarget riscv*-*-*] } then {
+  return
+}
+
+# Make sure there is a fortran compiler to test.
+if {

[Committed] RISC-V: Format VSETVL PASS code

[Juzhe-Zhong]

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc 
(pass_vsetvl::global_eliminate_vsetvl_insn): Format it.

---
 gcc/config/riscv/riscv-vsetvl.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 8ec54092a48..dc02246756d 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -4060,7 +4060,8 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const bb_info 
*bb) const
 }
 
   /* Step1: Reshape the VL/VTYPE status to make sure everything compatible.  */
-  auto_vec pred_cfg_bbs = get_dominated_by (CDI_POST_DOMINATORS, 
cfg_bb);
+  auto_vec pred_cfg_bbs
+= get_dominated_by (CDI_POST_DOMINATORS, cfg_bb);
   FOR_EACH_EDGE (e, ei, cfg_bb->preds)
 {
   sbitmap avout = m_vector_manager->vector_avout[e->src->index];
-- 
2.36.3

Re: [PATCH V3] RISC-V: Fix ICE in get_avl_or_vl_reg

[Kito Cheng via Gcc-patches]

lgtm

On Thu, Sep 14, 2023 at 3:52 PM Juzhe-Zhong  wrote:
>
> update v1 -> v2: Add available fortran compiler check in rvv-fortran.exp.
>
> This patch fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395 ICE
>
> update v2 -> v3: Remove redundant format.
>
> PR target/111395
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (avl_info::operator==): Fix ICE.
> (vector_insn_info::global_merge): Ditto.
> (vector_insn_info::get_avl_or_vl_reg): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/fortran/pr111395.f90: New test.
> * gcc.target/riscv/rvv/rvv-fortran.exp: New test.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc  | 28 +++-
>  .../gcc.target/riscv/rvv/fortran/pr111395.f90 | 41 +
>  .../gcc.target/riscv/rvv/rvv-fortran.exp  | 45 +++
>  3 files changed, 103 insertions(+), 11 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index f81361c4ccd..8ec54092a48 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -1652,6 +1652,8 @@ avl_info::operator== (const avl_info &other) const
>/* Handle VLMAX AVL.  */
>if (vlmax_avl_p (m_value))
>  return vlmax_avl_p (other.get_value ());
> +  if (vlmax_avl_p (other.get_value ()))
> +return false;
>
>/* If any source is undef value, we think they are not equal.  */
>if (!m_source || !other.get_source ())
> @@ -2258,6 +2260,18 @@ vector_insn_info::global_merge (const vector_insn_info 
> &merge_info,
> new_info.set_avl_source (first_set);
>  }
>
> +  /* Make sure VLMAX AVL always has a set_info the get VL.  */
> +  if (vlmax_avl_p (new_info.get_avl ()))
> +{
> +  if (this->get_avl_source ())
> +   new_info.set_avl_source (this->get_avl_source ());
> +  else
> +   {
> + gcc_assert (merge_info.get_avl_source ());
> + new_info.set_avl_source (merge_info.get_avl_source ());
> +   }
> +}
> +
>new_info.fuse_sew_lmul (*this, merge_info);
>new_info.fuse_tail_policy (*this, merge_info);
>new_info.fuse_mask_policy (*this, merge_info);
> @@ -2274,9 +2288,6 @@ vector_insn_info::get_avl_or_vl_reg (void) const
>if (!vlmax_avl_p (get_avl ()))
>  return get_avl ();
>
> -  if (get_avl_source ())
> -return get_avl_reg_rtx ();
> -
>rtx_insn *rinsn = get_insn ()->rtl ();
>if (has_vl_op (rinsn) || vsetvl_insn_p (rinsn))
>  {
> @@ -2288,14 +2299,9 @@ vector_insn_info::get_avl_or_vl_reg (void) const
> return vl;
>  }
>
> -  /* A DIRTY (polluted EMPTY) block if:
> -   - get_insn is scalar move (no AVL or VL operand).
> -   - get_avl_source is null (no def in the current DIRTY block).
> - Then we trace the previous insn which must be the insn
> - already inserted in Phase 2 to get the VL operand for VLMAX.  */
> -  rtx_insn *prev_rinsn = PREV_INSN (rinsn);
> -  gcc_assert (prev_rinsn && vsetvl_insn_p (prev_rinsn));
> -  return ::get_vl (prev_rinsn);
> +  /* We always has avl_source if it is VLMAX AVL.  */
> +  gcc_assert (get_avl_source ());
> +  return get_avl_reg_rtx ();
>  }
>
>  bool
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90 
> b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
> new file mode 100644
> index 000..71253fe6bc5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
> @@ -0,0 +1,41 @@
> +! { dg-do compile }
> +! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -std=legacy" }
> +
> +MODULE a
> +  REAL b
> +CONTAINS
> +  SUBROUTINE c(d,KTE)
> +REAL,DIMENSION(KTE) :: d,e,f,g
> +REAL,DIMENSION(KTE) :: h
> +i : DO j=1,b
> +   z=k
> +   DO l=m,n
> +  IF(o>=p)THEN
> + IF(l +q=z/0
> + ENDIF
> + e=q
> + f=EXP(r)
> +  ENDIF
> +   ENDDO
> +   s : DO t=1,2
> +  DO l=m,u
> + v=v+l
> +  ENDDO
> +  IF(w<=x)THEN
> + DO l=w,x
> +g=y
> + ENDDO
> +  ENDIF
> +   ENDDO  s
> +   aa=v
> +   ab=ac/aa
> +   k=ad/ab
> +ENDDO  i
> +IF(ae>af)THEN
> +   DO l=m,n
> +  d=h
> +   ENDDO
> +ENDIF
> +  END SUBROUTINE c
> +END MODULE a
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp 
> b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
> new file mode 100644
> index 000..88d82281d43
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
> @@ -0,0 +1,45 @@
> +#   Copyright (C) 2023-2023 Free Software Foundation, Inc.
> +
> +# This program is free software; you can redistribute it and/or modify
> +# it under the terms of the GNU General Public License as published

RE: [PATCH V3] RISC-V: Fix ICE in get_avl_or_vl_reg

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Thursday, September 14, 2023 3:56 PM
To: Juzhe-Zhong 
Cc: gcc-patches@gcc.gnu.org; kito.ch...@gmail.com; jeffreya...@gmail.com; 
rdapp@gmail.com
Subject: Re: [PATCH V3] RISC-V: Fix ICE in get_avl_or_vl_reg

lgtm

On Thu, Sep 14, 2023 at 3:52 PM Juzhe-Zhong  wrote:
>
> update v1 -> v2: Add available fortran compiler check in rvv-fortran.exp.
>
> This patch fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395 ICE
>
> update v2 -> v3: Remove redundant format.
>
> PR target/111395
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (avl_info::operator==): Fix ICE.
> (vector_insn_info::global_merge): Ditto.
> (vector_insn_info::get_avl_or_vl_reg): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/fortran/pr111395.f90: New test.
> * gcc.target/riscv/rvv/rvv-fortran.exp: New test.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc  | 28 +++-
>  .../gcc.target/riscv/rvv/fortran/pr111395.f90 | 41 +
>  .../gcc.target/riscv/rvv/rvv-fortran.exp  | 45 +++
>  3 files changed, 103 insertions(+), 11 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index f81361c4ccd..8ec54092a48 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -1652,6 +1652,8 @@ avl_info::operator== (const avl_info &other) const
>/* Handle VLMAX AVL.  */
>if (vlmax_avl_p (m_value))
>  return vlmax_avl_p (other.get_value ());
> +  if (vlmax_avl_p (other.get_value ()))
> +return false;
>
>/* If any source is undef value, we think they are not equal.  */
>if (!m_source || !other.get_source ())
> @@ -2258,6 +2260,18 @@ vector_insn_info::global_merge (const vector_insn_info 
> &merge_info,
> new_info.set_avl_source (first_set);
>  }
>
> +  /* Make sure VLMAX AVL always has a set_info the get VL.  */
> +  if (vlmax_avl_p (new_info.get_avl ()))
> +{
> +  if (this->get_avl_source ())
> +   new_info.set_avl_source (this->get_avl_source ());
> +  else
> +   {
> + gcc_assert (merge_info.get_avl_source ());
> + new_info.set_avl_source (merge_info.get_avl_source ());
> +   }
> +}
> +
>new_info.fuse_sew_lmul (*this, merge_info);
>new_info.fuse_tail_policy (*this, merge_info);
>new_info.fuse_mask_policy (*this, merge_info);
> @@ -2274,9 +2288,6 @@ vector_insn_info::get_avl_or_vl_reg (void) const
>if (!vlmax_avl_p (get_avl ()))
>  return get_avl ();
>
> -  if (get_avl_source ())
> -return get_avl_reg_rtx ();
> -
>rtx_insn *rinsn = get_insn ()->rtl ();
>if (has_vl_op (rinsn) || vsetvl_insn_p (rinsn))
>  {
> @@ -2288,14 +2299,9 @@ vector_insn_info::get_avl_or_vl_reg (void) const
> return vl;
>  }
>
> -  /* A DIRTY (polluted EMPTY) block if:
> -   - get_insn is scalar move (no AVL or VL operand).
> -   - get_avl_source is null (no def in the current DIRTY block).
> - Then we trace the previous insn which must be the insn
> - already inserted in Phase 2 to get the VL operand for VLMAX.  */
> -  rtx_insn *prev_rinsn = PREV_INSN (rinsn);
> -  gcc_assert (prev_rinsn && vsetvl_insn_p (prev_rinsn));
> -  return ::get_vl (prev_rinsn);
> +  /* We always has avl_source if it is VLMAX AVL.  */
> +  gcc_assert (get_avl_source ());
> +  return get_avl_reg_rtx ();
>  }
>
>  bool
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90 
> b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
> new file mode 100644
> index 000..71253fe6bc5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111395.f90
> @@ -0,0 +1,41 @@
> +! { dg-do compile }
> +! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -std=legacy" }
> +
> +MODULE a
> +  REAL b
> +CONTAINS
> +  SUBROUTINE c(d,KTE)
> +REAL,DIMENSION(KTE) :: d,e,f,g
> +REAL,DIMENSION(KTE) :: h
> +i : DO j=1,b
> +   z=k
> +   DO l=m,n
> +  IF(o>=p)THEN
> + IF(l +q=z/0
> + ENDIF
> + e=q
> + f=EXP(r)
> +  ENDIF
> +   ENDDO
> +   s : DO t=1,2
> +  DO l=m,u
> + v=v+l
> +  ENDDO
> +  IF(w<=x)THEN
> + DO l=w,x
> +g=y
> + ENDDO
> +  ENDIF
> +   ENDDO  s
> +   aa=v
> +   ab=ac/aa
> +   k=ad/ab
> +ENDDO  i
> +IF(ae>af)THEN
> +   DO l=m,n
> +  d=h
> +   ENDDO
> +ENDIF
> +  END SUBROUTINE c
> +END MODULE a
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp 
> b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
> new file mode 100644
> i

[PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[Juzhe-Zhong]

This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391

I notice that previous patch (V2 patch) cause additional execution fail of 
pr69719.c
This FAIL is because of the latent BUG of VSETVL PASS.

So this patch includes VSETVL PASS fix even though it's not related to the 
PR111391.

I have confirm the whole regression no additional FAILs are introduced.

PR target/111391

gcc/ChangeLog:

* config/riscv/autovec.md (@vec_extract): Remove @.
(vec_extract): Ditto.
* config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
(pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
* config/riscv/riscv.cc (riscv_legitimize_move): Expand move.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
* gcc.target/riscv/rvv/autovec/pr111391.c: New test.

---
 gcc/config/riscv/autovec.md   |  2 +-
 gcc/config/riscv/riscv-vsetvl.cc  |  4 ++-
 gcc/config/riscv/riscv.cc | 32 +++
 .../riscv/rvv/autovec/partial/slp-9.c |  1 -
 .../gcc.target/riscv/rvv/autovec/pr111391.c   | 28 
 5 files changed, 64 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index e74a1695709..7121bab1716 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1442,7 +1442,7 @@
 ;; -
 ;;  [INT,FP] Extract a vector element.
 ;; -
-(define_expand "@vec_extract"
+(define_expand "vec_extract"
   [(set (match_operand: 0 "register_operand")
  (vec_select:
(match_operand:V_VLS  1 "register_operand")
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index f81361c4ccd..7731e2a5f20 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -649,6 +649,8 @@ emit_vsetvl_insn (enum vsetvl_type insn_type, enum 
emit_type emit_type,
 {
   fprintf (dump_file, "\nInsert vsetvl insn PATTERN:\n");
   print_rtl_single (dump_file, pat);
+  fprintf (dump_file, "\nfor insn:\n");
+  print_rtl_single (dump_file, rinsn);
 }
 
   if (emit_type == EMIT_DIRECT)
@@ -3861,7 +3863,7 @@ pass_vsetvl::local_eliminate_vsetvl_insn (const bb_info 
*bb) const
  skip_one = true;
}
 
- curr_avl = get_avl (rinsn);
+ curr_avl = curr_dem.get_avl ();
 
  /* Some instrucion like pred_extract_first don't reqruie avl, so
 the avl is null, use vl_placeholder for unify the handling
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 762937b0e37..3ba6379028f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2513,6 +2513,38 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx 
src)
}
   return true;
 }
+  /* Expand
+   (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
+ Expand this data movement instead of simply forbid it since
+ we can improve the code generation for this following scenario
+ by RVV auto-vectorization:
+   (set (reg:V8QI 149) (vec_duplicate:V8QI (reg:QI))
+   (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
+ Since RVV mode and scalar mode are in different REG_CLASS,
+ we need to explicitly move data from V_REGS to GR_REGS by scalar move.  */
+  if (SUBREG_P (src) && riscv_v_ext_mode_p (GET_MODE (SUBREG_REG (src
+{
+  machine_mode vmode = GET_MODE (SUBREG_REG (src));
+  unsigned int mode_size = GET_MODE_SIZE (mode).to_constant ();
+  unsigned int vmode_size = GET_MODE_SIZE (vmode).to_constant ();
+  unsigned int nunits = vmode_size / mode_size;
+  scalar_mode smode = as_a (mode);
+  vmode = riscv_vector::get_vector_mode (smode, nunits).require ();
+  enum insn_code icode
+   = convert_optab_handler (vec_extract_optab, vmode, mode);
+  gcc_assert (icode != CODE_FOR_nothing);
+  class expand_operand ops[3];
+  create_output_operand (&ops[0], dest, mode);
+  ops[0].target = 1;
+  create_input_operand (&ops[1], gen_lowpart (vmode, SUBREG_REG (src)),
+   vmode);
+  unsigned int index = SUBREG_BYTE (src).to_constant () / mode_size;
+  create_integer_operand (&ops[2], index);
+  expand_insn (icode, 3, ops);
+  if (ops[0].value != dest)
+   emit_move_insn (dest, ops[0].value);
+  return true;
+}
   /* Expand
(set (reg:QI target) (mem:QI (address)))
  to
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c
index 5fba27c7a35..7c42438c9d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/slp-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/a

Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[Kito Cheng via Gcc-patches]

On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong  wrote:
>
> This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
>
> I notice that previous patch (V2 patch) cause additional execution fail of 
> pr69719.c
> This FAIL is because of the latent BUG of VSETVL PASS.
>
> So this patch includes VSETVL PASS fix even though it's not related to the 
> PR111391.
>
> I have confirm the whole regression no additional FAILs are introduced.
>
> PR target/111391
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (@vec_extract): Remove @.
> (vec_extract): Ditto.
> * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
> (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
> * config/riscv/riscv.cc (riscv_legitimize_move): Expand move.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
> * gcc.target/riscv/rvv/autovec/pr111391.c: New test.
>
> ---
>  gcc/config/riscv/autovec.md   |  2 +-
>  gcc/config/riscv/riscv-vsetvl.cc  |  4 ++-
>  gcc/config/riscv/riscv.cc | 32 +++
>  .../riscv/rvv/autovec/partial/slp-9.c |  1 -
>  .../gcc.target/riscv/rvv/autovec/pr111391.c   | 28 
>  5 files changed, 64 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index e74a1695709..7121bab1716 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1442,7 +1442,7 @@
>  ;; -
>  ;;  [INT,FP] Extract a vector element.
>  ;; -
> -(define_expand "@vec_extract"
> +(define_expand "vec_extract"

Why remove this? I saw this change was introduced in v3?


>[(set (match_operand: 0 "register_operand")
>   (vec_select:
> (match_operand:V_VLS  1 "register_operand")

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[juzhe.zh...@rivai.ai]

>> Why remove this? I saw this change was introduced in v3?

The "@" was introduced by this patch: 
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630184.html 
At the first time, I thought I need to explicitly call emit_insn 
(gen_vec_extract (mode, mode, )
That's why I added in the last patch.

However, I found I don't need to call gen_vec_extract, so I remove "@" in this 
patch:
+  enum insn_code icode
+   = convert_optab_handler (vec_extract_optab, vmode, mode);
+  gcc_assert (icode != CODE_FOR_nothing);
+  class expand_operand ops[3];
+  create_output_operand (&ops[0], dest, mode);
+  ops[0].target = 1;
+  create_input_operand (&ops[1], gen_lowpart (vmode, SUBREG_REG (src)),
+   vmode);
+  unsigned int index = SUBREG_BYTE (src).to_constant () / mode_size;
+  create_integer_operand (&ops[2], index);
+  expand_insn (icode, 3, ops);
This code is copied from optabs-query.cc



juzhe.zh...@rivai.ai
 
From: Kito Cheng
Date: 2023-09-14 16:11
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]
On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong  wrote:
>
> This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
>
> I notice that previous patch (V2 patch) cause additional execution fail of 
> pr69719.c
> This FAIL is because of the latent BUG of VSETVL PASS.
>
> So this patch includes VSETVL PASS fix even though it's not related to the 
> PR111391.
>
> I have confirm the whole regression no additional FAILs are introduced.
>
> PR target/111391
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (@vec_extract): Remove @.
> (vec_extract): Ditto.
> * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
> (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
> * config/riscv/riscv.cc (riscv_legitimize_move): Expand move.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
> * gcc.target/riscv/rvv/autovec/pr111391.c: New test.
>
> ---
>  gcc/config/riscv/autovec.md   |  2 +-
>  gcc/config/riscv/riscv-vsetvl.cc  |  4 ++-
>  gcc/config/riscv/riscv.cc | 32 +++
>  .../riscv/rvv/autovec/partial/slp-9.c |  1 -
>  .../gcc.target/riscv/rvv/autovec/pr111391.c   | 28 
>  5 files changed, 64 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index e74a1695709..7121bab1716 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1442,7 +1442,7 @@
>  ;; -
>  ;;  [INT,FP] Extract a vector element.
>  ;; -
> -(define_expand "@vec_extract"
> +(define_expand "vec_extract"
 
Why remove this? I saw this change was introduced in v3?
 
 
>[(set (match_operand: 0 "register_operand")
>   (vec_select:
> (match_operand:V_VLS  1 "register_operand")
 

Re: [PATCH] libstdc++: Remove some more unconditional uses of atomics

[Jonathan Wakely via Gcc-patches]

On Thu, 14 Sept 2023 at 08:44, Christophe Lyon
 wrote:
>
> Hi,
>
>
> On Wed, 13 Sept 2023 at 14:32, Jonathan Wakely  wrote:
>>
>> Tested x86_64-linux and aarch64-linux. I intend to push this to trunk.
>>
>> -- >8 --
>>
>> These atomics cause linker errors on arm4t where __sync_synchronize is
>> not defined. For single-threaded targets we don't need the atomics.
>>
>
> I ran the tests on arm-eabi default config (so, armv4t) with this patch, and 
> here is the list of remaining UNRESOLVED tests:
>  29_atomics/atomic/compare_exchange_padding.cc
> 29_atomics/atomic/cons/value_init.cc
> 29_atomics/atomic_float/value_init.cc
> 29_atomics/atomic_integral/cons/value_init.cc
> 29_atomics/atomic_ref/compare_exchange_padding.cc
> 29_atomics/atomic_ref/generic.cc
> 29_atomics/atomic_ref/integral.cc
> 29_atomics/atomic_ref/pointer.cc
> experimental/polymorphic_allocator/construct_pair.cc
>
> all of them are due to undefined reference to __sync_synchronize
> (some also reference __atomic_compare_exchange_4, etc...)
>
>
> IIUC, this should not be the case for 
> experimental/polymorphic_allocator/construct_pair.cc ?
> The reference for __sync_synchronize is near the beginning of test0[123]
> from a call to __atomic_load_n line 835 of atomic_base.h
> not sure where it comes from, the .loc directive indicates line 28 of the 
> testcase which is the opening brace

Doh, I removed the atomics from  but this is
, which has a separate implementation.

I'll make a change to  as well, thanks
for catching my silly mistake.

RE: [PATCH v4] libgfortran: Replace mutex with rwlock

[Zhu, Lipeng via Gcc-patches]

> Hi Thomas,
> 
> >
> > Hi Lipeng,
> >
> > > May I know any comment or concern on this patch, thanks for your
> > > time
> > > 😄
> >
> > Thanks for your patience in getting this reviewed.
> >
> > A few remarks / questions.
> >
> > Which strategy is used in this implementation, read-preferring or
> > write- preferring?  And if read-preferring is used, is there a danger
> > of deadlock if people do unreasonable things?
> > Maybe you could explain that, also in a comment in the code.
> >
> 
> Yes, the implementation use the read-preferring strategy, and comments in
> code.
> When adding the test cases, I didn’t meet the situation which may cause the
> deadlock.
> Maybe you can give more guidance about that.
> 
> > Can you add some sort of torture test case(s) which does a lot of
> > opening/closing/reading/writing, possibly with asynchronous I/O and/or
> > pthreads, to catch possible problems?  If there is a system dependency
> > or some race condition, chances are that regression testers will catch this.
> >
> 
> Sure, as your comments, in the patch V6, I added 3 test cases with OpenMP to
> test different cases in concurrency respectively:
> 1. find and create unit very frequently to stress read lock and write lock.
> 2. only access the unit which exist in cache to stress read lock.
> 3. access the same unit in concurrency.
> For the third test case, it also help to find a bug:  When unit can't be 
> found in
> cache nor unit list in read phase, then threads will try to acquire write 
> lock to
> insert the same unit, this will cause duplicate key error.
> To fix this bug, I get the unit from unit list once again before insert in 
> write lock.
> More details you can refer the patch v6.
> 

Could you help to review this update? I really appreciate your assistance.

> > With this, the libgfortran parts are OK, unless somebody else has more
> > comments, so give this a couple of days.  I cannot approve the libgcc
> > parts, that would be somebody else (Jakub?)
> >
> > Best regards
> >
> > Thomas
> >
> 
> Best Regards,
> Lipeng Zhu

Best Regards,
Lipeng Zhu

Re: [PATCH-1v2, rs6000] Enable SImode in FP registers on P7 [PR88558]

[HAO CHEN GUI via Gcc-patches]

Hi Kewen,

在 2023/9/12 17:33, Kewen.Lin 写道:
> Ok, at least regression testing doesn't expose any needs to do disparaging
> for this.  Could you also test this patch with SPEC2017 for P7 and P8
> separately at options like -O2 or -O3, to see if there is any assembly
> change, and if yes filtering out some typical to check it's expected or
> not?  I think it can help us to better evaluate the impact.  Thanks!

Just compared the object files of SPEC2017 for P7 and P8. There is no
difference between P7s'. For P8, some different object files are found.
All differences are the same. Patched object files replace xxlor with fmr.
It's expected as the fmr is added to ahead of xxlor in "*movsi_internal1".

Thanks
Gui Haochen

Re: [PATCH] Improve error message for if with an else part while in switch

[Richard Biener via Gcc-patches]

On Thu, Sep 14, 2023 at 12:30 AM Andrew Pinski via Gcc-patches
 wrote:
>
> While writing some match.pd code, I was trying to figure
> out why I was getting an `expected ), got (` error message
> while writing an if statement with an else clause. For switch
> statements, the if statements cannot have an else clause so
> it would be better to have a decent error message saying that
> explictly.
>
> OK? Bootstrapped and tested on x86_64-linux-gnu.

OK.

Richard.

> gcc/ChangeLog:
>
> * genmatch.cc (parser::parse_result): For an else clause
> of an if statement inside a switch, error out explictly.
> ---
>  gcc/genmatch.cc | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/gcc/genmatch.cc b/gcc/genmatch.cc
> index a1925a747a7..03d325efdf6 100644
> --- a/gcc/genmatch.cc
> +++ b/gcc/genmatch.cc
> @@ -4891,6 +4891,8 @@ parser::parse_result (operand *result, predicate_id 
> *matcher)
> ife->trueexpr = parse_result (result, matcher);
>   else
> ife->trueexpr = parse_op ();
> + if (peek ()->type == CPP_OPEN_PAREN)
> +   fatal_at (peek(), "if inside switch cannot have an else");
>   eat_token (CPP_CLOSE_PAREN);
> }
>   else
> --
> 2.31.1
>

Re: [PATCH] libstdc++: Remove some more unconditional uses of atomics

[Christophe Lyon via Gcc-patches]

On Thu, 14 Sept 2023 at 10:17, Jonathan Wakely  wrote:

> On Thu, 14 Sept 2023 at 08:44, Christophe Lyon
>  wrote:
> >
> > Hi,
> >
> >
> > On Wed, 13 Sept 2023 at 14:32, Jonathan Wakely 
> wrote:
> >>
> >> Tested x86_64-linux and aarch64-linux. I intend to push this to trunk.
> >>
> >> -- >8 --
> >>
> >> These atomics cause linker errors on arm4t where __sync_synchronize is
> >> not defined. For single-threaded targets we don't need the atomics.
> >>
> >
> > I ran the tests on arm-eabi default config (so, armv4t) with this patch,
> and here is the list of remaining UNRESOLVED tests:
> >  29_atomics/atomic/compare_exchange_padding.cc
> > 29_atomics/atomic/cons/value_init.cc
> > 29_atomics/atomic_float/value_init.cc
> > 29_atomics/atomic_integral/cons/value_init.cc
> > 29_atomics/atomic_ref/compare_exchange_padding.cc
> > 29_atomics/atomic_ref/generic.cc
> > 29_atomics/atomic_ref/integral.cc
> > 29_atomics/atomic_ref/pointer.cc
> > experimental/polymorphic_allocator/construct_pair.cc
> >
> > all of them are due to undefined reference to __sync_synchronize
> > (some also reference __atomic_compare_exchange_4, etc...)
> >
> >
> > IIUC, this should not be the case for
> experimental/polymorphic_allocator/construct_pair.cc ?
> > The reference for __sync_synchronize is near the beginning of test0[123]
> > from a call to __atomic_load_n line 835 of atomic_base.h
> > not sure where it comes from, the .loc directive indicates line 28 of
> the testcase which is the opening brace
>
> Doh, I removed the atomics from  but this is
> , which has a separate implementation.
>
> I'll make a change to  as well, thanks
> for catching my silly mistake.
>
>
You're welcome.
So I'll shrink my patch and add dg-require-thread-fence only to the few
29_atomics tests listed above.

Christophe

Re: [PATCH] MATCH: Support `(a != (CST+1)) & (a > CST)` optimizations

[Richard Biener via Gcc-patches]

On Thu, Sep 14, 2023 at 7:34 AM Andrew Pinski via Gcc-patches
 wrote:
>
> Even though this is done via reassocation, match can support
> these with a simple change to detect that the difference is just
> one. This allows to optimize these earlier and even during phiopt
> for an example.
>
> This patch adds the following cases:
> (a != (CST+1)) & (a > CST) -> a > (CST+1)
> (a != (CST-1)) & (a < CST) -> a < (CST-1)
> (a == (CST-1)) | (a >= CST) -> a >= (CST-1)
> (a == (CST+1)) | (a <= CST) -> a <= (CST+1)
>
> Canonicalizations of comparisons causes this case to show up more.
>
> OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.

OK.

> PR tree-optimization/106164
>
> gcc/ChangeLog:
>
> * match.pd (`(X CMP1 CST1) AND/IOR (X CMP2 CST2)`):
> Expand to support constants that are off by one.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.dg/pr21643.c: Update test now that match does
> the combing of the comparisons.
> * gcc.dg/tree-ssa/cmpbit-5.c: New test.
> * gcc.dg/tree-ssa/phi-opt-35.c: New test.
> ---
>  gcc/match.pd   | 44 ++-
>  gcc/testsuite/gcc.dg/pr21643.c |  6 ++-
>  gcc/testsuite/gcc.dg/tree-ssa/cmpbit-5.c   | 51 ++
>  gcc/testsuite/gcc.dg/tree-ssa/phi-opt-35.c | 13 ++
>  4 files changed, 111 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/cmpbit-5.c
>  create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/phi-opt-35.c
>
> diff --git a/gcc/match.pd b/gcc/match.pd
> index 7ecf5568599..07ffd831132 100644
> --- a/gcc/match.pd
> +++ b/gcc/match.pd
> @@ -2970,10 +2970,20 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
> && operand_equal_p (@1, @2)))
>  (with
>   {
> +  bool one_before = false;
> +  bool one_after = false;
>int cmp = 0;
>if (TREE_CODE (@1) == INTEGER_CST
>   && TREE_CODE (@2) == INTEGER_CST)
> -   cmp = tree_int_cst_compare (@1, @2);
> +   {
> + cmp = tree_int_cst_compare (@1, @2);
> + if (cmp < 0
> + && wi::to_wide (@1) == wi::to_wide (@2) - 1)
> +   one_before = true;
> + if (cmp > 0
> + && wi::to_wide (@1) == wi::to_wide (@2) + 1)
> +   one_after = true;
> +   }
>bool val;
>switch (code2)
>  {
> @@ -2998,6 +3008,16 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
> && code2 == LE_EXPR
>&& cmp == 0)
> (lt @0 @1))
> +  /* (a != (b+1)) & (a > b) -> a > (b+1) */
> +  (if (code1 == NE_EXPR
> +   && code2 == GT_EXPR
> +  && one_after)
> +   (gt @0 @1))
> +  /* (a != (b-1)) & (a < b) -> a < (b-1) */
> +  (if (code1 == NE_EXPR
> +   && code2 == LT_EXPR
> +  && one_before)
> +   (lt @0 @1))
>   )
>  )
> )
> @@ -3069,10 +3089,20 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
> && operand_equal_p (@1, @2)))
>  (with
>   {
> +  bool one_before = false;
> +  bool one_after = false;
>int cmp = 0;
>if (TREE_CODE (@1) == INTEGER_CST
>   && TREE_CODE (@2) == INTEGER_CST)
> -   cmp = tree_int_cst_compare (@1, @2);
> +   {
> + cmp = tree_int_cst_compare (@1, @2);
> + if (cmp < 0
> + && wi::to_wide (@1) == wi::to_wide (@2) - 1)
> +   one_before = true;
> + if (cmp > 0
> + && wi::to_wide (@1) == wi::to_wide (@2) + 1)
> +   one_after = true;
> +   }
>bool val;
>switch (code2)
> {
> @@ -3097,6 +3127,16 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
> && code2 == LT_EXPR
>&& cmp == 0)
> (le @0 @1))
> +  /* (a == (b-1)) | (a >= b) -> a >= (b-1) */
> +  (if (code1 == EQ_EXPR
> +   && code2 == GE_EXPR
> +  && one_before)
> +   (ge @0 @1))
> +  /* (a == (b+1)) | (a <= b) -> a <= (b-1) */
> +  (if (code1 == EQ_EXPR
> +   && code2 == LE_EXPR
> +  && one_after)
> +   (le @0 @1))
>   )
>  )
> )
> diff --git a/gcc/testsuite/gcc.dg/pr21643.c b/gcc/testsuite/gcc.dg/pr21643.c
> index 4e7f93d351a..42517b5af1e 100644
> --- a/gcc/testsuite/gcc.dg/pr21643.c
> +++ b/gcc/testsuite/gcc.dg/pr21643.c
> @@ -86,4 +86,8 @@ f9 (unsigned char c)
>return 1;
>  }
>
> -/* { dg-final { scan-tree-dump-times "Optimizing range tests c_\[0-9\]*.D. 
> -.0, 31. and -.32, 32.\[\n\r\]* into" 6 "reassoc1" } }  */
> +/* Note with match being able to simplify this, optimizing range tests is no 
> longer needed here. */
> +/* Equivalence: _7 | _2 -> c_5(D) <= 32 */
> +/* old test: dg-final  scan-tree-dump-times "Optimizing range tests 
> c_\[0-9\]*.D. -.0, 31. and -.32, 32.\[\n\r\]* into" 6 "reassoc1"   */
> +/* { dg-final { scan-tree-dump-times "Equivalence: _\[0-9\]+ \\\| _\[0-9\]+ 
> -> c_\[0-9\]+.D. <= 32" 5 "reassoc1" } }  */
> +/* { dg-final { scan-tree-dump-times "Equivalence: _\[0-9\]+ \& _\[0-9\]+ -> 
>

Re: [PATCH] libstdc++: Remove some more unconditional uses of atomics

[Jonathan Wakely via Gcc-patches]

On Thu, 14 Sept 2023 at 09:41, Christophe Lyon
 wrote:
>
>
>
> On Thu, 14 Sept 2023 at 10:17, Jonathan Wakely  wrote:
>>
>> On Thu, 14 Sept 2023 at 08:44, Christophe Lyon
>>  wrote:
>> >
>> > Hi,
>> >
>> >
>> > On Wed, 13 Sept 2023 at 14:32, Jonathan Wakely  wrote:
>> >>
>> >> Tested x86_64-linux and aarch64-linux. I intend to push this to trunk.
>> >>
>> >> -- >8 --
>> >>
>> >> These atomics cause linker errors on arm4t where __sync_synchronize is
>> >> not defined. For single-threaded targets we don't need the atomics.
>> >>
>> >
>> > I ran the tests on arm-eabi default config (so, armv4t) with this patch, 
>> > and here is the list of remaining UNRESOLVED tests:
>> >  29_atomics/atomic/compare_exchange_padding.cc
>> > 29_atomics/atomic/cons/value_init.cc
>> > 29_atomics/atomic_float/value_init.cc
>> > 29_atomics/atomic_integral/cons/value_init.cc
>> > 29_atomics/atomic_ref/compare_exchange_padding.cc
>> > 29_atomics/atomic_ref/generic.cc
>> > 29_atomics/atomic_ref/integral.cc
>> > 29_atomics/atomic_ref/pointer.cc
>> > experimental/polymorphic_allocator/construct_pair.cc
>> >
>> > all of them are due to undefined reference to __sync_synchronize
>> > (some also reference __atomic_compare_exchange_4, etc...)
>> >
>> >
>> > IIUC, this should not be the case for 
>> > experimental/polymorphic_allocator/construct_pair.cc ?
>> > The reference for __sync_synchronize is near the beginning of test0[123]
>> > from a call to __atomic_load_n line 835 of atomic_base.h
>> > not sure where it comes from, the .loc directive indicates line 28 of the 
>> > testcase which is the opening brace
>>
>> Doh, I removed the atomics from  but this is
>> , which has a separate implementation.
>>
>> I'll make a change to  as well, thanks
>> for catching my silly mistake.
>>
>
> You're welcome.
> So I'll shrink my patch and add dg-require-thread-fence only to the few 
> 29_atomics tests listed above.

Great, thanks. That's approved for trunk then.

N.B. if you'd prefer to add { dg-require-effective-target thread_fence
} instead of { dg-require-thread-fence "" } then that's fine, just
note that the effective target uses an underscore not a hyphen. The
dg-require-thread-fence proc just uses the proc that checks the
thread_fence effective target, so both forms do the same thing.

Re: gcc-patches From rewriting mailman settings (Was: [Linaro-TCWG-CI] gcc patch #75674: FAIL: 68 regressions)

[Richard Biener via Gcc-patches]

On Tue, Sep 12, 2023 at 5:00 PM Mark Wielaard  wrote:
>
> Hi Maxim,
>
> Adding Jeff to CC who is the official gcc-patches mailinglist admin.
>
> On Tue, 2023-09-12 at 11:08 +0400, Maxim Kuvyrkov wrote:
> > Normally, notifications from Linaro TCWG precommit CI are sent only to
> > patch author and patch submitter.  In this case the sender was rewritten
> > to "Benjamin Priour via Gcc-patches ",
> > which was detected by Patchwork [1] as patch submitter.
>
> BTW. Really looking forward to your talk at Cauldron about this!
>
> > Is "From:" re-write on gcc-patches@ mailing list a side-effect of [2]?
> > I see that some, but not all messages to gcc-patches@ have their
> > "From:" re-written.
> >
> > Also, do you know if re-write of "From:" on gcc-patches@ is expected?
>
> Yes, it is expected for emails that come from domains with a dmarc
> policy. That is because the current settings of the gcc-patches
> mailinglist might slightly alter the message or headers in a way that
> invalidates the DKIM signature. Without From rewriting those messages
> would be bounced by recipients that check the dmarc policy/dkim
> signature.
>
> As you noticed the glibc hackers have recently worked together with the
> sourceware overseers to upgrade mailman and alter the postfix and the
> libc-alpha mailinglist setting so it doesn't require From rewriting
> anymore (the message and header aren't altered anymore to invalidate
> the DKIM signatures).
>
> We (Jeff or anyone else with mailman admin privs) could use the same
> settings for gcc-patches. The settings that need to be set are in that
> bug:
>
> - subject_prefix (general): (empty)
> - from_is_list (general): No
> - anonymous_list (general): No
> - first_strip_reply_to (general): No
> - reply_goes_to_list (general): Poster
> - reply_to_address (general): (empty)
> - include_sender_header (general): No
> - drop_cc (general): No
> - msg_header (nondigest): (empty)
> - msg_footer (nondigest): (empty)
> - scrub_nondigest (nondigest): No
> - dmarc_moderation_action (privacy): Accept
> - filter_content (contentfilter): No
>
> The only visible change (apart from no more From rewriting) is that
> HTML multi-parts aren't scrubbed anymore (that would be a message
> altering issue). The html part is still scrubbed from the
> inbox.sourceware.org archive, so b4 works just fine. But I don't know
> what patchwork.sourceware.org does with HTML attachements. Of course
> people really shouldn't sent HTML attachments to gcc-patches, so maybe
> this is no real problem.

Ick (to the HTML part).  I wonder if we can use From rewriting for those,
still stripping the HTML part?  Maybe we can also go back to rejecting
mails that are not text/plain ...

> Let me know if you want Jeff (or me or one of the other overseers) make
> the above changes to the gcc-patches mailman settings.
>
> Cheers,
>
> Mark
>
> > [1] https://patchwork.sourceware.org/project/gcc/list/
> > [2] https://sourceware.org/bugzilla/show_bug.cgi?id=29713
>

[PATCH v2 2/2] libstdc++: Add dg-require-thread-fence in several tests

[Christophe Lyon via Gcc-patches]

Some targets like arm-eabi with newlib and default settings rely on
__sync_synchronize() to ensure synchronization.  Newlib does not
implement it by default, to make users aware they have to take special
care.

This makes a few tests fail to link.

This patch requires the missing thread-fence effective target in the
tests that need it, making them UNSUPPORTED instead of FAIL and
UNRESOLVED.

2023-09-10  Christophe Lyon  

libstdc++-v3/
* testsuite/29_atomics/atomic/compare_exchange_padding.cc: Likewise.
* testsuite/29_atomics/atomic/cons/value_init.cc: Likewise.
* testsuite/29_atomics/atomic_float/value_init.cc: Likewise.
* testsuite/29_atomics/atomic_integral/cons/value_init.cc: Likewise.
* testsuite/29_atomics/atomic_ref/compare_exchange_padding.cc: Likewise.
* testsuite/29_atomics/atomic_ref/generic.cc: Likewise.
* testsuite/29_atomics/atomic_ref/integral.cc: Likewise.
* testsuite/29_atomics/atomic_ref/pointer.cc: Likewise.
---
 .../testsuite/29_atomics/atomic/compare_exchange_padding.cc  | 1 +
 libstdc++-v3/testsuite/29_atomics/atomic/cons/value_init.cc  | 1 +
 libstdc++-v3/testsuite/29_atomics/atomic_float/value_init.cc | 1 +
 .../testsuite/29_atomics/atomic_integral/cons/value_init.cc  | 1 +
 .../testsuite/29_atomics/atomic_ref/compare_exchange_padding.cc  | 1 +
 libstdc++-v3/testsuite/29_atomics/atomic_ref/generic.cc  | 1 +
 libstdc++-v3/testsuite/29_atomics/atomic_ref/integral.cc | 1 +
 libstdc++-v3/testsuite/29_atomics/atomic_ref/pointer.cc  | 1 +
 8 files changed, 8 insertions(+)

diff --git 
a/libstdc++-v3/testsuite/29_atomics/atomic/compare_exchange_padding.cc 
b/libstdc++-v3/testsuite/29_atomics/atomic/compare_exchange_padding.cc
index c4ab876db2a..2e7ff0307bc 100644
--- a/libstdc++-v3/testsuite/29_atomics/atomic/compare_exchange_padding.cc
+++ b/libstdc++-v3/testsuite/29_atomics/atomic/compare_exchange_padding.cc
@@ -1,5 +1,6 @@
 // { dg-options "-std=gnu++20" }
 // { dg-do run { target c++20 } }
+// { dg-require-thread-fence "" }
 // { dg-add-options libatomic }
 
 #include 
diff --git a/libstdc++-v3/testsuite/29_atomics/atomic/cons/value_init.cc 
b/libstdc++-v3/testsuite/29_atomics/atomic/cons/value_init.cc
index 47d5a5d5b28..b8019486ccf 100644
--- a/libstdc++-v3/testsuite/29_atomics/atomic/cons/value_init.cc
+++ b/libstdc++-v3/testsuite/29_atomics/atomic/cons/value_init.cc
@@ -17,6 +17,7 @@
 
 // { dg-options "-std=gnu++2a" }
 // { dg-do run { target c++2a } }
+// { dg-require-thread-fence "" }
 
 #include 
 
diff --git a/libstdc++-v3/testsuite/29_atomics/atomic_float/value_init.cc 
b/libstdc++-v3/testsuite/29_atomics/atomic_float/value_init.cc
index 1cd1efb5422..6e89f2fc2a8 100644
--- a/libstdc++-v3/testsuite/29_atomics/atomic_float/value_init.cc
+++ b/libstdc++-v3/testsuite/29_atomics/atomic_float/value_init.cc
@@ -17,6 +17,7 @@
 
 // { dg-options "-std=gnu++2a" }
 // { dg-do run { target c++2a } }
+// { dg-require-thread-fence "" }
 // { dg-add-options libatomic }
 
 #include 
diff --git 
a/libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/value_init.cc 
b/libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/value_init.cc
index 96615a7d09f..2f6a48d36d8 100644
--- a/libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/value_init.cc
+++ b/libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/value_init.cc
@@ -17,6 +17,7 @@
 
 // { dg-options "-std=gnu++2a" }
 // { dg-do run { target c++2a } }
+// { dg-require-thread-fence "" }
 
 #include 
 #include 
diff --git 
a/libstdc++-v3/testsuite/29_atomics/atomic_ref/compare_exchange_padding.cc 
b/libstdc++-v3/testsuite/29_atomics/atomic_ref/compare_exchange_padding.cc
index 0dab8a23e10..8469ebf8a14 100644
--- a/libstdc++-v3/testsuite/29_atomics/atomic_ref/compare_exchange_padding.cc
+++ b/libstdc++-v3/testsuite/29_atomics/atomic_ref/compare_exchange_padding.cc
@@ -1,5 +1,6 @@
 // { dg-options "-std=gnu++20" }
 // { dg-do run { target c++20 } }
+// { dg-require-thread-fence "" }
 // { dg-add-options libatomic }
 
 #include 
diff --git a/libstdc++-v3/testsuite/29_atomics/atomic_ref/generic.cc 
b/libstdc++-v3/testsuite/29_atomics/atomic_ref/generic.cc
index 14f417d1739..adae07f8754 100644
--- a/libstdc++-v3/testsuite/29_atomics/atomic_ref/generic.cc
+++ b/libstdc++-v3/testsuite/29_atomics/atomic_ref/generic.cc
@@ -17,6 +17,7 @@
 
 // { dg-options "-std=gnu++2a" }
 // { dg-do run { target c++2a } }
+// { dg-require-thread-fence "" }
 // { dg-add-options libatomic }
 
 #include 
diff --git a/libstdc++-v3/testsuite/29_atomics/atomic_ref/integral.cc 
b/libstdc++-v3/testsuite/29_atomics/atomic_ref/integral.cc
index e03ca921eb9..a98adb7fbba 100644
--- a/libstdc++-v3/testsuite/29_atomics/atomic_ref/integral.cc
+++ b/libstdc++-v3/testsuite/29_atomics/atomic_ref/integral.cc
@@ -17,6 +17,7 @@
 
 // { dg-options "-std=gnu++2a" }
 // { dg-do run { target c++2a } }
+// { dg-require-thread-fence "" }
 // { dg-add-options libatomic }
 
 #includ

Re: [PATCH] libstdc++: Remove some more unconditional uses of atomics

[Christophe Lyon via Gcc-patches]

On Thu, 14 Sept 2023 at 11:06, Jonathan Wakely  wrote:

> On Thu, 14 Sept 2023 at 09:41, Christophe Lyon
>  wrote:
> >
> >
> >
> > On Thu, 14 Sept 2023 at 10:17, Jonathan Wakely 
> wrote:
> >>
> >> On Thu, 14 Sept 2023 at 08:44, Christophe Lyon
> >>  wrote:
> >> >
> >> > Hi,
> >> >
> >> >
> >> > On Wed, 13 Sept 2023 at 14:32, Jonathan Wakely 
> wrote:
> >> >>
> >> >> Tested x86_64-linux and aarch64-linux. I intend to push this to
> trunk.
> >> >>
> >> >> -- >8 --
> >> >>
> >> >> These atomics cause linker errors on arm4t where __sync_synchronize
> is
> >> >> not defined. For single-threaded targets we don't need the atomics.
> >> >>
> >> >
> >> > I ran the tests on arm-eabi default config (so, armv4t) with this
> patch, and here is the list of remaining UNRESOLVED tests:
> >> >  29_atomics/atomic/compare_exchange_padding.cc
> >> > 29_atomics/atomic/cons/value_init.cc
> >> > 29_atomics/atomic_float/value_init.cc
> >> > 29_atomics/atomic_integral/cons/value_init.cc
> >> > 29_atomics/atomic_ref/compare_exchange_padding.cc
> >> > 29_atomics/atomic_ref/generic.cc
> >> > 29_atomics/atomic_ref/integral.cc
> >> > 29_atomics/atomic_ref/pointer.cc
> >> > experimental/polymorphic_allocator/construct_pair.cc
> >> >
> >> > all of them are due to undefined reference to __sync_synchronize
> >> > (some also reference __atomic_compare_exchange_4, etc...)
> >> >
> >> >
> >> > IIUC, this should not be the case for
> experimental/polymorphic_allocator/construct_pair.cc ?
> >> > The reference for __sync_synchronize is near the beginning of
> test0[123]
> >> > from a call to __atomic_load_n line 835 of atomic_base.h
> >> > not sure where it comes from, the .loc directive indicates line 28 of
> the testcase which is the opening brace
> >>
> >> Doh, I removed the atomics from  but this is
> >> , which has a separate implementation.
> >>
> >> I'll make a change to  as well, thanks
> >> for catching my silly mistake.
> >>
> >
> > You're welcome.
> > So I'll shrink my patch and add dg-require-thread-fence only to the few
> 29_atomics tests listed above.
>
> Great, thanks. That's approved for trunk then.
>
> N.B. if you'd prefer to add { dg-require-effective-target thread_fence
> } instead of { dg-require-thread-fence "" } then that's fine, just
> note that the effective target uses an underscore not a hyphen. The
> dg-require-thread-fence proc just uses the proc that checks the
> thread_fence effective target, so both forms do the same thing.
>
> Ha! Just sent v2, I kept  dg-require-thread-fence, because it was used
elsewhere in the libstsdc++ testsuite.

Thanks,

Christophe

Re: [PATCH] testsuite: Fix gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c

[Christophe Lyon via Gcc-patches]

ping?

On Fri, 8 Sept 2023 at 10:43, Christophe Lyon 
wrote:

> The test was declaring 'int *carry;' and wrote to '*carry' without
> initializing 'carry' first, leading to an attempt to write at address
> zero, and a crash.
>
> Fix by declaring 'int carry;' and passing '&carrry' instead of 'carry'
> as parameter.
>
> 2023-09-08  Christophe Lyon  
>
> gcc/testsuite/
> * gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c: Fix.
> ---
>  .../arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c | 34 +--
>  1 file changed, 17 insertions(+), 17 deletions(-)
>
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c
> b/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c
> index a8c6cce67c8..931c9d2f30b 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/mve_vadcq_vsbcq_fpscr_overwrite.c
> @@ -7,7 +7,7 @@
>
>  volatile int32x4_t c1;
>  volatile uint32x4_t c2;
> -int *carry;
> +int carry;
>
>  int
>  main ()
> @@ -21,45 +21,45 @@ main ()
>uint32x4_t inactive2 = vcreateq_u32 (0, 0);
>
>mve_pred16_t p = 0x;
> -  (*carry) = 0x;
> +  carry = 0x;
>
>__builtin_arm_set_fpscr_nzcvqc (0);
> -  c1 = vadcq (a1, b1, carry);
> +  c1 = vadcq (a1, b1, &carry);
>if (__builtin_arm_get_fpscr_nzcvqc () & !0x2000)
>  __builtin_abort ();
> -  (*carry) = 0x;
> +  carry = 0x;
>__builtin_arm_set_fpscr_nzcvqc (0);
> -  c2 = vadcq (a2, b2, carry);
> +  c2 = vadcq (a2, b2, &carry);
>if (__builtin_arm_get_fpscr_nzcvqc () & !0x2000)
>  __builtin_abort ();
> -  (*carry) = 0x;
> +  carry = 0x;
>__builtin_arm_set_fpscr_nzcvqc (0);
> -  c1 = vsbcq (a1, b1, carry);
> +  c1 = vsbcq (a1, b1, &carry);
>if (__builtin_arm_get_fpscr_nzcvqc () & !0x2000)
>  __builtin_abort ();
> -  (*carry) = 0x;
> +  carry = 0x;
>__builtin_arm_set_fpscr_nzcvqc (0);
> -  c2 = vsbcq (a2, b2, carry);
> +  c2 = vsbcq (a2, b2, &carry);
>if (__builtin_arm_get_fpscr_nzcvqc () & !0x2000)
>  __builtin_abort ();
> -  (*carry) = 0x;
> +  carry = 0x;
>__builtin_arm_set_fpscr_nzcvqc (0);
> -  c1 = vadcq_m (inactive1, a1, b1, carry, p);
> +  c1 = vadcq_m (inactive1, a1, b1, &carry, p);
>if (__builtin_arm_get_fpscr_nzcvqc () & !0x2000)
>  __builtin_abort ();
> -  (*carry) = 0x;
> +  carry = 0x;
>__builtin_arm_set_fpscr_nzcvqc (0);
> -  c2 = vadcq_m (inactive2, a2, b2, carry, p);
> +  c2 = vadcq_m (inactive2, a2, b2, &carry, p);
>if (__builtin_arm_get_fpscr_nzcvqc () & !0x2000)
>  __builtin_abort ();
> -  (*carry) = 0x;
> +  carry = 0x;
>__builtin_arm_set_fpscr_nzcvqc (0);
> -  c1 = vsbcq_m (inactive1, a1, b1, carry, p);
> +  c1 = vsbcq_m (inactive1, a1, b1, &carry, p);
>if (__builtin_arm_get_fpscr_nzcvqc () & !0x2000)
>  __builtin_abort ();
> -  (*carry) = 0x;
> +  carry = 0x;
>__builtin_arm_set_fpscr_nzcvqc (0);
> -  c2 = vsbcq_m (inactive2, a2, b2, carry, p);
> +  c2 = vsbcq_m (inactive2, a2, b2, &carry, p);
>if (__builtin_arm_get_fpscr_nzcvqc () & !0x2000)
>  __builtin_abort ();
>
> --
> 2.34.1
>
>

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[juzhe.zh...@rivai.ai]

Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in 
vec_extract optab ?



juzhe.zh...@rivai.ai
 
From: Kito Cheng
Date: 2023-09-14 16:11
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]
On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong  wrote:
>
> This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
>
> I notice that previous patch (V2 patch) cause additional execution fail of 
> pr69719.c
> This FAIL is because of the latent BUG of VSETVL PASS.
>
> So this patch includes VSETVL PASS fix even though it's not related to the 
> PR111391.
>
> I have confirm the whole regression no additional FAILs are introduced.
>
> PR target/111391
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (@vec_extract): Remove @.
> (vec_extract): Ditto.
> * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
> (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
> * config/riscv/riscv.cc (riscv_legitimize_move): Expand move.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
> * gcc.target/riscv/rvv/autovec/pr111391.c: New test.
>
> ---
>  gcc/config/riscv/autovec.md   |  2 +-
>  gcc/config/riscv/riscv-vsetvl.cc  |  4 ++-
>  gcc/config/riscv/riscv.cc | 32 +++
>  .../riscv/rvv/autovec/partial/slp-9.c |  1 -
>  .../gcc.target/riscv/rvv/autovec/pr111391.c   | 28 
>  5 files changed, 64 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391.c
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index e74a1695709..7121bab1716 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1442,7 +1442,7 @@
>  ;; -
>  ;;  [INT,FP] Extract a vector element.
>  ;; -
> -(define_expand "@vec_extract"
> +(define_expand "vec_extract"
 
Why remove this? I saw this change was introduced in v3?
 
 
>[(set (match_operand: 0 "register_operand")
>   (vec_select:
> (match_operand:V_VLS  1 "register_operand")
 

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[Kito Cheng via Gcc-patches]

Could you check if it work correctly for rv64gcv_zve32x? add testcase
no matter if it works or not :)

On Thu, Sep 14, 2023 at 5:19 PM juzhe.zh...@rivai.ai
 wrote:
>
> Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in 
> vec_extract optab ?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-09-14 16:11
> To: Juzhe-Zhong
> CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]
> On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong  wrote:
> >
> > This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
> >
> > I notice that previous patch (V2 patch) cause additional execution fail of 
> > pr69719.c
> > This FAIL is because of the latent BUG of VSETVL PASS.
> >
> > So this patch includes VSETVL PASS fix even though it's not related to the 
> > PR111391.
> >
> > I have confirm the whole regression no additional FAILs are introduced.
> >
> > PR target/111391
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/autovec.md (@vec_extract): Remove @.
> > (vec_extract): Ditto.
> > * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
> > (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
> > * config/riscv/riscv.cc (riscv_legitimize_move): Expand move.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
> > * gcc.target/riscv/rvv/autovec/pr111391.c: New test.
> >
> > ---
> >  gcc/config/riscv/autovec.md   |  2 +-
> >  gcc/config/riscv/riscv-vsetvl.cc  |  4 ++-
> >  gcc/config/riscv/riscv.cc | 32 +++
> >  .../riscv/rvv/autovec/partial/slp-9.c |  1 -
> >  .../gcc.target/riscv/rvv/autovec/pr111391.c   | 28 
> >  5 files changed, 64 insertions(+), 3 deletions(-)
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391.c
> >
> > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> > index e74a1695709..7121bab1716 100644
> > --- a/gcc/config/riscv/autovec.md
> > +++ b/gcc/config/riscv/autovec.md
> > @@ -1442,7 +1442,7 @@
> >  ;; 
> > -
> >  ;;  [INT,FP] Extract a vector element.
> >  ;; 
> > -
> > -(define_expand "@vec_extract"
> > +(define_expand "vec_extract"
>
> Why remove this? I saw this change was introduced in v3?
>
>
> >[(set (match_operand: 0 "register_operand")
> >   (vec_select:
> > (match_operand:V_VLS  1 "register_operand")
>

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[juzhe.zh...@rivai.ai]

You mean try pr111391.c 
that I added with rv64gcv_zve32x ?



juzhe.zh...@rivai.ai
 
From: Kito Cheng
Date: 2023-09-14 17:20
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode 
move[PR111391]
Could you check if it work correctly for rv64gcv_zve32x? add testcase
no matter if it works or not :)
 
On Thu, Sep 14, 2023 at 5:19 PM juzhe.zh...@rivai.ai
 wrote:
>
> Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in 
> vec_extract optab ?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-09-14 16:11
> To: Juzhe-Zhong
> CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]
> On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong  wrote:
> >
> > This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
> >
> > I notice that previous patch (V2 patch) cause additional execution fail of 
> > pr69719.c
> > This FAIL is because of the latent BUG of VSETVL PASS.
> >
> > So this patch includes VSETVL PASS fix even though it's not related to the 
> > PR111391.
> >
> > I have confirm the whole regression no additional FAILs are introduced.
> >
> > PR target/111391
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/autovec.md (@vec_extract): Remove @.
> > (vec_extract): Ditto.
> > * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
> > (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
> > * config/riscv/riscv.cc (riscv_legitimize_move): Expand move.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
> > * gcc.target/riscv/rvv/autovec/pr111391.c: New test.
> >
> > ---
> >  gcc/config/riscv/autovec.md   |  2 +-
> >  gcc/config/riscv/riscv-vsetvl.cc  |  4 ++-
> >  gcc/config/riscv/riscv.cc | 32 +++
> >  .../riscv/rvv/autovec/partial/slp-9.c |  1 -
> >  .../gcc.target/riscv/rvv/autovec/pr111391.c   | 28 
> >  5 files changed, 64 insertions(+), 3 deletions(-)
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391.c
> >
> > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> > index e74a1695709..7121bab1716 100644
> > --- a/gcc/config/riscv/autovec.md
> > +++ b/gcc/config/riscv/autovec.md
> > @@ -1442,7 +1442,7 @@
> >  ;; 
> > -
> >  ;;  [INT,FP] Extract a vector element.
> >  ;; 
> > -
> > -(define_expand "@vec_extract"
> > +(define_expand "vec_extract"
>
> Why remove this? I saw this change was introduced in v3?
>
>
> >[(set (match_operand: 0 "register_operand")
> >   (vec_select:
> > (match_operand:V_VLS  1 "register_operand")
>
 

Re: [PATCH v2 2/2] libstdc++: Add dg-require-thread-fence in several tests

[Jonathan Wakely via Gcc-patches]

On Thu, 14 Sept 2023 at 10:10, Christophe Lyon
 wrote:
>
> Some targets like arm-eabi with newlib and default settings rely on
> __sync_synchronize() to ensure synchronization.  Newlib does not
> implement it by default, to make users aware they have to take special
> care.
>
> This makes a few tests fail to link.
>
> This patch requires the missing thread-fence effective target in the
> tests that need it, making them UNSUPPORTED instead of FAIL and
> UNRESOLVED.

OK for trunk, thanks.


>
> 2023-09-10  Christophe Lyon  
>
> libstdc++-v3/
> * testsuite/29_atomics/atomic/compare_exchange_padding.cc: Likewise.
> * testsuite/29_atomics/atomic/cons/value_init.cc: Likewise.
> * testsuite/29_atomics/atomic_float/value_init.cc: Likewise.
> * testsuite/29_atomics/atomic_integral/cons/value_init.cc: Likewise.
> * testsuite/29_atomics/atomic_ref/compare_exchange_padding.cc: 
> Likewise.
> * testsuite/29_atomics/atomic_ref/generic.cc: Likewise.
> * testsuite/29_atomics/atomic_ref/integral.cc: Likewise.
> * testsuite/29_atomics/atomic_ref/pointer.cc: Likewise.
> ---
>  .../testsuite/29_atomics/atomic/compare_exchange_padding.cc  | 1 +
>  libstdc++-v3/testsuite/29_atomics/atomic/cons/value_init.cc  | 1 +
>  libstdc++-v3/testsuite/29_atomics/atomic_float/value_init.cc | 1 +
>  .../testsuite/29_atomics/atomic_integral/cons/value_init.cc  | 1 +
>  .../testsuite/29_atomics/atomic_ref/compare_exchange_padding.cc  | 1 +
>  libstdc++-v3/testsuite/29_atomics/atomic_ref/generic.cc  | 1 +
>  libstdc++-v3/testsuite/29_atomics/atomic_ref/integral.cc | 1 +
>  libstdc++-v3/testsuite/29_atomics/atomic_ref/pointer.cc  | 1 +
>  8 files changed, 8 insertions(+)
>
> diff --git 
> a/libstdc++-v3/testsuite/29_atomics/atomic/compare_exchange_padding.cc 
> b/libstdc++-v3/testsuite/29_atomics/atomic/compare_exchange_padding.cc
> index c4ab876db2a..2e7ff0307bc 100644
> --- a/libstdc++-v3/testsuite/29_atomics/atomic/compare_exchange_padding.cc
> +++ b/libstdc++-v3/testsuite/29_atomics/atomic/compare_exchange_padding.cc
> @@ -1,5 +1,6 @@
>  // { dg-options "-std=gnu++20" }
>  // { dg-do run { target c++20 } }
> +// { dg-require-thread-fence "" }
>  // { dg-add-options libatomic }
>
>  #include 
> diff --git a/libstdc++-v3/testsuite/29_atomics/atomic/cons/value_init.cc 
> b/libstdc++-v3/testsuite/29_atomics/atomic/cons/value_init.cc
> index 47d5a5d5b28..b8019486ccf 100644
> --- a/libstdc++-v3/testsuite/29_atomics/atomic/cons/value_init.cc
> +++ b/libstdc++-v3/testsuite/29_atomics/atomic/cons/value_init.cc
> @@ -17,6 +17,7 @@
>
>  // { dg-options "-std=gnu++2a" }
>  // { dg-do run { target c++2a } }
> +// { dg-require-thread-fence "" }
>
>  #include 
>
> diff --git a/libstdc++-v3/testsuite/29_atomics/atomic_float/value_init.cc 
> b/libstdc++-v3/testsuite/29_atomics/atomic_float/value_init.cc
> index 1cd1efb5422..6e89f2fc2a8 100644
> --- a/libstdc++-v3/testsuite/29_atomics/atomic_float/value_init.cc
> +++ b/libstdc++-v3/testsuite/29_atomics/atomic_float/value_init.cc
> @@ -17,6 +17,7 @@
>
>  // { dg-options "-std=gnu++2a" }
>  // { dg-do run { target c++2a } }
> +// { dg-require-thread-fence "" }
>  // { dg-add-options libatomic }
>
>  #include 
> diff --git 
> a/libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/value_init.cc 
> b/libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/value_init.cc
> index 96615a7d09f..2f6a48d36d8 100644
> --- a/libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/value_init.cc
> +++ b/libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/value_init.cc
> @@ -17,6 +17,7 @@
>
>  // { dg-options "-std=gnu++2a" }
>  // { dg-do run { target c++2a } }
> +// { dg-require-thread-fence "" }
>
>  #include 
>  #include 
> diff --git 
> a/libstdc++-v3/testsuite/29_atomics/atomic_ref/compare_exchange_padding.cc 
> b/libstdc++-v3/testsuite/29_atomics/atomic_ref/compare_exchange_padding.cc
> index 0dab8a23e10..8469ebf8a14 100644
> --- a/libstdc++-v3/testsuite/29_atomics/atomic_ref/compare_exchange_padding.cc
> +++ b/libstdc++-v3/testsuite/29_atomics/atomic_ref/compare_exchange_padding.cc
> @@ -1,5 +1,6 @@
>  // { dg-options "-std=gnu++20" }
>  // { dg-do run { target c++20 } }
> +// { dg-require-thread-fence "" }
>  // { dg-add-options libatomic }
>
>  #include 
> diff --git a/libstdc++-v3/testsuite/29_atomics/atomic_ref/generic.cc 
> b/libstdc++-v3/testsuite/29_atomics/atomic_ref/generic.cc
> index 14f417d1739..adae07f8754 100644
> --- a/libstdc++-v3/testsuite/29_atomics/atomic_ref/generic.cc
> +++ b/libstdc++-v3/testsuite/29_atomics/atomic_ref/generic.cc
> @@ -17,6 +17,7 @@
>
>  // { dg-options "-std=gnu++2a" }
>  // { dg-do run { target c++2a } }
> +// { dg-require-thread-fence "" }
>  // { dg-add-options libatomic }
>
>  #include 
> diff --git a/libstdc++-v3/testsuite/29_atomics/atomic_ref/integral.cc 
> b/libstdc++-v3/testsuite/29_atomics/atomic_ref/integral.cc
> index e03ca921eb9..a98adb7fbba 100644
> ---

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[juzhe.zh...@rivai.ai]

Oh I see.
It ICE:

during RTL pass: expand
bug.c:26:9: internal compiler error: in require, at machmode.h:313
   26 | i (a);
  | ^
0x1032253 opt_mode::require() const
../../../../gcc/gcc/machmode.h:313
0x1c47877 riscv_legitimize_move(machine_mode, rtx_def*, rtx_def*)
../../../../gcc/gcc/config/riscv/riscv.cc:2532
0x274bbe0 gen_movdi(rtx_def*, rtx_def*)
../../../../gcc/gcc/config/riscv/riscv.md:2024
0x102cb1c rtx_insn* insn_gen_fn::operator()(rtx_def*, 
rtx_def*) const
../../../../gcc/gcc/recog.h:411
0x11fbc8e emit_move_insn_1(rtx_def*, rtx_def*)
../../../../gcc/gcc/expr.cc:4164
0x11fc809 emit_move_insn(rtx_def*, rtx_def*)
../../../../gcc/gcc/expr.cc:4334
0x1039a0b load_register_parameters
../../../../gcc/gcc/calls.cc:2155
0x103d865 expand_call(tree_node*, rtx_def*, int)
../../../../gcc/gcc/calls.cc:3626
0x121e78c expand_expr_real_1(tree_node*, rtx_def*, machine_mode, 
expand_modifier, rtx_def**, bool)
../../../../gcc/gcc/expr.cc:11921
0x120ffb8 expand_expr_real(tree_node*, rtx_def*, machine_mode, expand_modifier, 
rtx_def**, bool)
../../../../gcc/gcc/expr.cc:9010
0x102c694 expand_expr(tree_node*, rtx_def*, machine_mode, expand_modifier)
../../../../gcc/gcc/expr.h:310
0x105ccc9 expand_call_stmt
../../../../gcc/gcc/cfgexpand.cc:2831
0x10608af expand_gimple_stmt_1
../../../../gcc/gcc/cfgexpand.cc:3880
0x1060f4d expand_gimple_stmt
../../../../gcc/gcc/cfgexpand.cc:4044
0x10699f3 expand_gimple_basic_block


Thanks for catching this.



juzhe.zh...@rivai.ai
 
From: Kito Cheng
Date: 2023-09-14 17:20
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode 
move[PR111391]
Could you check if it work correctly for rv64gcv_zve32x? add testcase
no matter if it works or not :)
 
On Thu, Sep 14, 2023 at 5:19 PM juzhe.zh...@rivai.ai
 wrote:
>
> Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in 
> vec_extract optab ?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-09-14 16:11
> To: Juzhe-Zhong
> CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]
> On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong  wrote:
> >
> > This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
> >
> > I notice that previous patch (V2 patch) cause additional execution fail of 
> > pr69719.c
> > This FAIL is because of the latent BUG of VSETVL PASS.
> >
> > So this patch includes VSETVL PASS fix even though it's not related to the 
> > PR111391.
> >
> > I have confirm the whole regression no additional FAILs are introduced.
> >
> > PR target/111391
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/autovec.md (@vec_extract): Remove @.
> > (vec_extract): Ditto.
> > * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
> > (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
> > * config/riscv/riscv.cc (riscv_legitimize_move): Expand move.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
> > * gcc.target/riscv/rvv/autovec/pr111391.c: New test.
> >
> > ---
> >  gcc/config/riscv/autovec.md   |  2 +-
> >  gcc/config/riscv/riscv-vsetvl.cc  |  4 ++-
> >  gcc/config/riscv/riscv.cc | 32 +++
> >  .../riscv/rvv/autovec/partial/slp-9.c |  1 -
> >  .../gcc.target/riscv/rvv/autovec/pr111391.c   | 28 
> >  5 files changed, 64 insertions(+), 3 deletions(-)
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391.c
> >
> > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> > index e74a1695709..7121bab1716 100644
> > --- a/gcc/config/riscv/autovec.md
> > +++ b/gcc/config/riscv/autovec.md
> > @@ -1442,7 +1442,7 @@
> >  ;; 
> > -
> >  ;;  [INT,FP] Extract a vector element.
> >  ;; 
> > -
> > -(define_expand "@vec_extract"
> > +(define_expand "vec_extract"
>
> Why remove this? I saw this change was introduced in v3?
>
>
> >[(set (match_operand: 0 "register_operand")
> >   (vec_select:
> > (match_operand:V_VLS  1 "register_operand")
>
 

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[Kito Cheng via Gcc-patches]

Yeah, try pr111391.c with rv64gc_zve32x (NO v, my mistake in last mail
:P), maybe add a testcase pr111391-zve32x.c that just include
pr111391.c and set dg option to rv64gc_zve32x


On Thu, Sep 14, 2023 at 5:24 PM juzhe.zh...@rivai.ai
 wrote:
>
> You mean try pr111391.c
> that I added with rv64gcv_zve32x ?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-09-14 17:20
> To: juzhe.zh...@rivai.ai
> CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
> Subject: Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode 
> move[PR111391]
> Could you check if it work correctly for rv64gcv_zve32x? add testcase
> no matter if it works or not :)
>
> On Thu, Sep 14, 2023 at 5:19 PM juzhe.zh...@rivai.ai
>  wrote:
> >
> > Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in 
> > vec_extract optab ?
> >
> >
> >
> > juzhe.zh...@rivai.ai
> >
> > From: Kito Cheng
> > Date: 2023-09-14 16:11
> > To: Juzhe-Zhong
> > CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> > Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode 
> > move[PR111391]
> > On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong  wrote:
> > >
> > > This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
> > >
> > > I notice that previous patch (V2 patch) cause additional execution fail 
> > > of pr69719.c
> > > This FAIL is because of the latent BUG of VSETVL PASS.
> > >
> > > So this patch includes VSETVL PASS fix even though it's not related to 
> > > the PR111391.
> > >
> > > I have confirm the whole regression no additional FAILs are introduced.
> > >
> > > PR target/111391
> > >
> > > gcc/ChangeLog:
> > >
> > > * config/riscv/autovec.md (@vec_extract): Remove @.
> > > (vec_extract): Ditto.
> > > * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
> > > (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
> > > * config/riscv/riscv.cc (riscv_legitimize_move): Expand move.
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > > * gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
> > > * gcc.target/riscv/rvv/autovec/pr111391.c: New test.
> > >
> > > ---
> > >  gcc/config/riscv/autovec.md   |  2 +-
> > >  gcc/config/riscv/riscv-vsetvl.cc  |  4 ++-
> > >  gcc/config/riscv/riscv.cc | 32 +++
> > >  .../riscv/rvv/autovec/partial/slp-9.c |  1 -
> > >  .../gcc.target/riscv/rvv/autovec/pr111391.c   | 28 
> > >  5 files changed, 64 insertions(+), 3 deletions(-)
> > >  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391.c
> > >
> > > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> > > index e74a1695709..7121bab1716 100644
> > > --- a/gcc/config/riscv/autovec.md
> > > +++ b/gcc/config/riscv/autovec.md
> > > @@ -1442,7 +1442,7 @@
> > >  ;; 
> > > -
> > >  ;;  [INT,FP] Extract a vector element.
> > >  ;; 
> > > -
> > > -(define_expand "@vec_extract"
> > > +(define_expand "vec_extract"
> >
> > Why remove this? I saw this change was introduced in v3?
> >
> >
> > >[(set (match_operand: 0 "register_operand")
> > >   (vec_select:
> > > (match_operand:V_VLS  1 "register_operand")
> >
>

Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[juzhe.zh...@rivai.ai]

Hi. Kito.

Could you review this code ? Regression is running
  /* Expand
   (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
 Expand this data movement instead of simply forbid it since
 we can improve the code generation for this following scenario
 by RVV auto-vectorization:
   (set (reg:V8QI 149) (vec_duplicate:V8QI (reg:QI))
   (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
 Since RVV mode and scalar mode are in different REG_CLASS,
 we need to explicitly move data from V_REGS to GR_REGS by scalar move.  */
  if (SUBREG_P (src) && riscv_v_ext_mode_p (GET_MODE (SUBREG_REG (src
{
  machine_mode vmode = GET_MODE (SUBREG_REG (src));
  unsigned int mode_size = GET_MODE_SIZE (mode).to_constant ();
  unsigned int vmode_size = GET_MODE_SIZE (vmode).to_constant ();
  unsigned int nunits = vmode_size / mode_size;
  scalar_mode smode = as_a (mode);
  unsigned int index = SUBREG_BYTE (src).to_constant () / mode_size;
  unsigned int num = smode == DImode && !TARGET_VECTOR_ELEN_64 ? 2 : 1;

  if (num == 2)
{
  /* If we want to extract 64bit value but ELEN < 64,
 we use RVV vector mode with EEW = 32 to extract
 the highpart and lowpart.  */
  smode = SImode;
  nunits = nunits * 2;
}
  vmode = riscv_vector::get_vector_mode (smode, nunits).require ();
  enum insn_code icode
= convert_optab_handler (vec_extract_optab, vmode, smode);
  gcc_assert (icode != CODE_FOR_nothing);
  rtx v = gen_lowpart (vmode, SUBREG_REG (src));

  for (unsigned int i = 0; i < num; i++)
{
  class expand_operand ops[3];
  rtx result;
  if (num == 1)
result = dest;
  else if (i == 0)
result = gen_lowpart (smode, dest);
  else
result = gen_reg_rtx (smode);
  create_output_operand (&ops[0], result, smode);
  ops[0].target = 1;
  create_input_operand (&ops[1], v, vmode);
  create_integer_operand (&ops[2], index + i);
  expand_insn (icode, 3, ops);
  if (ops[0].value != result)
emit_move_insn (result, ops[0].value);

  if (i == 1)
{
  rtx tmp
= expand_binop (Pmode, ashl_optab, gen_lowpart (Pmode, result),
gen_int_mode (32, Pmode), NULL_RTX, 0,
OPTAB_DIRECT);
  rtx tmp2 = expand_binop (Pmode, ior_optab, tmp, dest, NULL_RTX, 0,
   OPTAB_DIRECT);
  emit_move_insn (dest, tmp2);
}
}
  return true;
}


ASM:
vsetivli zero,2,e32,mf2,ta,ma
vslidedown.vi v2,v1,1
vmv.x.s a5,v2
slli a5,a5,32
vmv.x.s a0,v1
or a0,a5,a0



juzhe.zh...@rivai.ai
 
From: Kito Cheng
Date: 2023-09-14 17:26
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode 
move[PR111391]
Yeah, try pr111391.c with rv64gc_zve32x (NO v, my mistake in last mail
:P), maybe add a testcase pr111391-zve32x.c that just include
pr111391.c and set dg option to rv64gc_zve32x
 
 
On Thu, Sep 14, 2023 at 5:24 PM juzhe.zh...@rivai.ai
 wrote:
>
> You mean try pr111391.c
> that I added with rv64gcv_zve32x ?
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Kito Cheng
> Date: 2023-09-14 17:20
> To: juzhe.zh...@rivai.ai
> CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
> Subject: Re: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode 
> move[PR111391]
> Could you check if it work correctly for rv64gcv_zve32x? add testcase
> no matter if it works or not :)
>
> On Thu, Sep 14, 2023 at 5:19 PM juzhe.zh...@rivai.ai
>  wrote:
> >
> > Is it Ok for trunk ? Or you want me send a separate patch to remove "@" in 
> > vec_extract optab ?
> >
> >
> >
> > juzhe.zh...@rivai.ai
> >
> > From: Kito Cheng
> > Date: 2023-09-14 16:11
> > To: Juzhe-Zhong
> > CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> > Subject: Re: [PATCH V3] RISC-V: Expand VLS mode to scalar mode 
> > move[PR111391]
> > On Thu, Sep 14, 2023 at 4:04 PM Juzhe-Zhong  wrote:
> > >
> > > This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391
> > >
> > > I notice that previous patch (V2 patch) cause additional execution fail 
> > > of pr69719.c
> > > This FAIL is because of the latent BUG of VSETVL PASS.
> > >
> > > So this patch includes VSETVL PASS fix even though it's not related to 
> > > the PR111391.
> > >
> > > I have confirm the whole regression no additional FAILs are introduced.
> > >
> > > PR target/111391
> > >
> > > gcc/ChangeLog:
> > >
> > > * config/riscv/autovec.md (@vec_extract): Remove @.
> > > (vec_extract): Ditto.
> > > * config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
> > > (pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
> > > * config/riscv/riscv.cc (riscv_legitimize_move): 

Re: [PATCHSET] Reintroduce targetrustm hooks

[Richard Biener via Gcc-patches]

On Wed, Sep 13, 2023 at 10:14 PM Iain Buclaw via Gcc-patches
 wrote:
>
> Excerpts from Arthur Cohen's message of September 7, 2023 3:41 pm:
> > Alright, was not expecting to mess up this patchset so bad so here we go:
> >
> > This patchset reintroduces proper targetrustm hooks without the old
> > problematic mess of macros we had, which had been removed for the first
> > merge of gccrs upstream.
> >
> > Tested on x86-64 GNU Linux, and has also been present in our development
> > repository for a long time - added by this pull-request from Iain [1]
> > which was merged in October 2022.
> >
> > Ok for trunk?
> >
> > [PATCH 01/14] rust: Add skeleton support and documentation for
> > [PATCH 02/14] rust: Reintroduce TARGET_RUST_CPU_INFO hook
> > [PATCH 03/14] rust: Reintroduce TARGET_RUST_OS_INFO hook
> > [PATCH 04/14] rust: Implement TARGET_RUST_CPU_INFO for i[34567]86-*-*
> > [PATCH 05/14] rust: Implement TARGET_RUST_OS_INFO for *-*-darwin*
> > [PATCH 06/14] rust: Implement TARGET_RUST_OS_INFO for *-*-freebsd*
> > [PATCH 07/14] rust: Implement TARGET_RUST_OS_INFO for *-*-netbsd*
> > [PATCH 08/14] rust: Implement TARGET_RUST_OS_INFO for *-*-openbsd*
> > [PATCH 09/14] rust: Implement TARGET_RUST_OS_INFO for *-*-solaris2*.
> > [PATCH 10/14] rust: Implement TARGET_RUST_OS_INFO for *-*-dragonfly*
> > [PATCH 11/14] rust: Implement TARGET_RUST_OS_INFO for *-*-vxworks*
> > [PATCH 12/14] rust: Implement TARGET_RUST_OS_INFO for *-*-fuchsia*.
> > [PATCH 13/14] rust: Implement TARGET_RUST_OS_INFO for
> > [PATCH 14/14] rust: Implement TARGET_RUST_OS_INFO for *-*-*linux*.
> >
>
> Thanks for eventually getting round to this.
>
> As the co-author of this patch series, I'm not going to look at it.
>
> FWIW, these being Rust-specific target changes isolated to just
> Rust-specific files, you should have the automony to commit without
> needing any request for review - at least this is my understanding when
> have made D-specific target changes in the past that have not touched
> common back-end headers.
>
> I'll let someone else confirm and check over the shared parts touched by
> the patch however.

I confirm.  I briefly went over the shared parts and they look OK.

Thanks,
Richard.

> For reviewers, this is pretty much a mirror of the D front-end's CPU and
> OS-specific target hooks (D has built-in version identifiers, not
> built-in attributes, but both Rust and D are otherwise the same in the
> kind of information exposed by them).
>
> > [1]: https://github.com/Rust-GCC/gccrs/pull/1543
> >
>
> The other GitHub pull request that added these is here.
>
> https://github.com/Rust-GCC/gccrs/pull/1596
>
> Regards,
> Iain.

Re: [PATCH] core: Support heap-based trampolines

[Richard Biener via Gcc-patches]

On Wed, Sep 6, 2023 at 5:44 PM FX Coudert  wrote:
>
> Hi,
>
> ping**2 on the revised patch, for Richard or another global reviewer. So far 
> all review feedback is that it’s a step forward, and it’s been widely used 
> for both aarch64-darwin and x86_64-darwin distributions for almost three 
> years now.
>
> OK to commit?

I just noticed that ftrampoline-impl isn't Optimize, thus it's not
streamed with LTO.  How does mixing
different -ftrampoline-impl for different LTO TUs behave?  How does
mis-specifying -ftrampoline-impl
at LTO link time compared to compile-time behave?  Is the state fully
reflected during pre-IPA compilation
and the flag not needed after that?  It appears so, but did you check?

OK if that's a non-issue.

Thanks,
Richard.

> FX
>
>
>
> > Le 5 août 2023 à 16:20, FX Coudert  a écrit :
> >
> > Hi Richard,
> >
> > Thanks for your feedback. Here is an amended version of the patch, taking 
> > into consideration your requests and the following discussion. There is no 
> > configure option for the libgcc part, and the documentation is amended. The 
> > patch is split into three commits for core, target and libgcc.
> >
> > Currently regtesting on x86_64 linux and darwin (it was fine before I split 
> > up into three commits, so I’m re-testing to make sure I didn’t screw 
> > anything up).
> >
> > OK to commit?
> > FX
>

[PATCH] aarch64: Coerce addresses to be suitable for LD1RQ

[Richard Sandiford via Gcc-patches]

In the following test:

  svuint8_t ld(uint8_t *ptr) { return svld1rq(svptrue_b8(), ptr + 2); }

ptr + 2 is a valid address for an Advanced SIMD load, but not for
an SVE load.  We therefore ended up generating:

ldr q0, [x0, 2]
dup z0.q, z0.q[0]

This patch makes us generate LD1RQ for that case too.  It takes the
slightly old-school approach of making the predicate broader than
the constraint.  That is: any valid memory address is accepted as
an operand before RA.  If the instruction remains during RA, LRA will
coerce the address to match the constraint.  If the instruction gets
split before RA, the splitter will load invalid addresses into a
scratch register.

Tested on aarch64-linux-gnu & pushed.

Richard

gcc/
* config/aarch64/aarch64-sve.md (@aarch64_vec_duplicate_vq_le):
Accept all nonimmediate_operands, but keep the existing constraints.
If the instruction is split before RA, load invalid addresses into
a temporary register.
* config/aarch64/predicates.md (aarch64_sve_dup_ld1rq_operand): Delete.

gcc/testsuite/
* gcc.target/aarch64/sve/acle/general/ld1rq_1.c: New test.
---
 gcc/config/aarch64/aarch64-sve.md | 15 -
 gcc/config/aarch64/predicates.md  |  4 ---
 .../aarch64/sve/acle/general/ld1rq_1.c| 33 +++
 3 files changed, 47 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/ld1rq_1.c

diff --git a/gcc/config/aarch64/aarch64-sve.md 
b/gcc/config/aarch64/aarch64-sve.md
index da5534c3e32..b223e7d3c9d 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -2611,11 +2611,18 @@ (define_insn_and_split "*vec_duplicate_reg"
 )
 
 ;; Duplicate an Advanced SIMD vector to fill an SVE vector (LE version).
+;;
+;; The addressing mode range of LD1RQ does not match the addressing mode
+;; range of LDR Qn.  If the predicate enforced the LD1RQ range, we would
+;; not be able to combine LDR Qns outside that range.  The predicate
+;; therefore accepts all memory operands, with only the constraints
+;; enforcing the actual restrictions.  If the instruction is split
+;; before RA, we need to load invalid addresses into a temporary.
 
 (define_insn_and_split "@aarch64_vec_duplicate_vq_le"
   [(set (match_operand:SVE_FULL 0 "register_operand" "=w, w")
(vec_duplicate:SVE_FULL
- (match_operand: 1 "aarch64_sve_dup_ld1rq_operand" "w, UtQ")))
+ (match_operand: 1 "nonimmediate_operand" "w, UtQ")))
(clobber (match_scratch:VNx16BI 2 "=X, Upl"))]
   "TARGET_SVE && !BYTES_BIG_ENDIAN"
   {
@@ -2633,6 +2640,12 @@ (define_insn_and_split 
"@aarch64_vec_duplicate_vq_le"
   "&& MEM_P (operands[1])"
   [(const_int 0)]
   {
+if (can_create_pseudo_p ()
+&& !aarch64_sve_ld1rq_operand (operands[1], mode))
+  {
+   rtx addr = force_reg (Pmode, XEXP (operands[1], 0));
+   operands[1] = replace_equiv_address (operands[1], addr);
+  }
 if (GET_CODE (operands[2]) == SCRATCH)
   operands[2] = gen_reg_rtx (VNx16BImode);
 emit_move_insn (operands[2], CONSTM1_RTX (VNx16BImode));
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 2d8d1fe25c1..01de4743974 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -732,10 +732,6 @@ (define_predicate "aarch64_sve_dup_operand"
   (ior (match_operand 0 "register_operand")
(match_operand 0 "aarch64_sve_ld1r_operand")))
 
-(define_predicate "aarch64_sve_dup_ld1rq_operand"
-  (ior (match_operand 0 "register_operand")
-   (match_operand 0 "aarch64_sve_ld1rq_operand")))
-
 (define_predicate "aarch64_sve_ptrue_svpattern_immediate"
   (and (match_code "const")
(match_test "aarch64_sve_ptrue_svpattern_p (op, NULL)")))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/ld1rq_1.c 
b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/ld1rq_1.c
new file mode 100644
index 000..9242c639731
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/ld1rq_1.c
@@ -0,0 +1,33 @@
+/* { dg-options "-O2" } */
+
+#include 
+
+#define TEST_OFFSET(TYPE, SUFFIX, OFFSET) \
+  sv##TYPE##_t \
+  test_##TYPE##_##SUFFIX (TYPE##_t *ptr) \
+  { \
+return svld1rq(svptrue_b8(), ptr + OFFSET); \
+  }
+
+#define TEST(TYPE) \
+  TEST_OFFSET (TYPE, 0, 0) \
+  TEST_OFFSET (TYPE, 1, 1) \
+  TEST_OFFSET (TYPE, 2, 2) \
+  TEST_OFFSET (TYPE, 16, 16) \
+  TEST_OFFSET (TYPE, 0x1, 0x1) \
+  TEST_OFFSET (TYPE, 0x10001, 0x10001) \
+  TEST_OFFSET (TYPE, m1, -1) \
+  TEST_OFFSET (TYPE, m2, -2) \
+  TEST_OFFSET (TYPE, m16, -16) \
+  TEST_OFFSET (TYPE, m0x1, -0x1) \
+  TEST_OFFSET (TYPE, m0x10001, -0x10001)
+
+TEST (int8)
+TEST (int16)
+TEST (uint32)
+TEST (uint64)
+
+/* { dg-final { scan-assembler-times {\tld1rqb\t} 11 { target 
aarch64_little_endian } } } */
+/* { dg-final { scan-assembler-times {\tld1rqh\t} 11 { target 
aarch64_little_endian } } } */

[PATCH] ira: Consider save/restore costs of callee-save registers [PR110071]

[Surya Kumari Jangala via Gcc-patches]

ira: Consider save/restore costs of callee-save registers [PR110071]

In improve_allocation() routine, IRA checks for each allocno if spilling
any conflicting allocnos can improve the allocation of this allocno.
This routine computes the cost improvement for usage of each profitable
hard register for a given allocno. The existing code in
improve_allocation() does not consider the save/restore costs of callee
save registers while computing the cost improvement.

This can result in a callee save register being assigned to a pseudo
that is live in the entire function and across a call, overriding a
non-callee save register assigned to the pseudo by graph coloring. So
the entry basic block requires a prolog, thereby causing shrink wrap to
fail.

2023-09-14  Surya Kumari Jangala  

gcc/
PR rtl-optimization/110071
* ira-color.cc (improve_allocation): Consider cost of callee
save registers.

gcc/testsuite/
PR rtl-optimization/110071
* gcc.target/powerpc/pr110071.c: New test.
---

diff --git a/gcc/ira-color.cc b/gcc/ira-color.cc
index 5807d6d26f6..f2e8ea34152 100644
--- a/gcc/ira-color.cc
+++ b/gcc/ira-color.cc
@@ -3150,13 +3150,15 @@ improve_allocation (void)
   int j, k, n, hregno, conflict_hregno, base_cost, class_size, word, nwords;
   int check, spill_cost, min_cost, nregs, conflict_nregs, r, best;
   bool try_p;
-  enum reg_class aclass;
+  enum reg_class aclass, rclass;
   machine_mode mode;
   int *allocno_costs;
   int costs[FIRST_PSEUDO_REGISTER];
   HARD_REG_SET conflicting_regs[2], profitable_hard_regs;
   ira_allocno_t a;
   bitmap_iterator bi;
+  int saved_nregs;
+  int add_cost;
 
   /* Don't bother to optimize the code with static chain pointer and
  non-local goto in order not to spill the chain pointer
@@ -3194,6 +3196,7 @@ improve_allocation (void)
  conflicting_regs,
  &profitable_hard_regs);
   class_size = ira_class_hard_regs_num[aclass];
+  mode = ALLOCNO_MODE (a);
   /* Set up cost improvement for usage of each profitable hard
 register for allocno A.  */
   for (j = 0; j < class_size; j++)
@@ -3207,6 +3210,22 @@ improve_allocation (void)
  costs[hregno] = (allocno_costs == NULL
   ? ALLOCNO_UPDATED_CLASS_COST (a) : allocno_costs[k]);
  costs[hregno] -= allocno_copy_cost_saving (a, hregno);
+
+ if ((saved_nregs = calculate_saved_nregs (hregno, mode)) != 0)
+ {
+   /* We need to save/restore the hard register in
+  epilogue/prologue.  Therefore we increase the cost.
+  Since the prolog is placed in the entry BB, the frequency
+  of the entry BB is considered while computing the cost.  */
+   rclass = REGNO_REG_CLASS (hregno);
+   add_cost = ((ira_memory_move_cost[mode][rclass][0]
++ ira_memory_move_cost[mode][rclass][1])
+   * saved_nregs / hard_regno_nregs (hregno,
+ mode) - 1)
+  * REG_FREQ_FROM_BB (ENTRY_BLOCK_PTR_FOR_FN (cfun));
+   costs[hregno] += add_cost;
+ }
+
  costs[hregno] -= base_cost;
  if (costs[hregno] < 0)
try_p = true;
diff --git a/gcc/testsuite/gcc.target/powerpc/pr110071.c 
b/gcc/testsuite/gcc.target/powerpc/pr110071.c
new file mode 100644
index 000..ec03fecfb15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110071.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -fdump-rtl-pro_and_epilogue" } */
+
+/* Verify there is an early return without the prolog and shrink-wrap
+   the function. */
+void bar ();
+long
+foo (long i, long cond)
+{
+  if (cond)
+bar ();
+  return i+1;
+}
+
+/* { dg-final { scan-rtl-dump-times "Performing shrink-wrapping" 1 
"pro_and_epilogue" } } */

[PATCH V4] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[Juzhe-Zhong]

This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391

PR target/111391

gcc/ChangeLog:

* config/riscv/autovec.md (@vec_extract): Remove @.
(vec_extract): Ditto.
* config/riscv/riscv-vsetvl.cc (emit_vsetvl_insn): Fix bug.
(pass_vsetvl::local_eliminate_vsetvl_insn): Fix bug.
* config/riscv/riscv.cc (riscv_legitimize_move): Expand VLS mode to 
scalar mode move.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/partial/slp-9.c: Adapt test.
* gcc.target/riscv/rvv/autovec/pr111391-1.c: New test.
* gcc.target/riscv/rvv/autovec/pr111391-2.c: New test.

---
 gcc/config/riscv/autovec.md   |  2 +-
 gcc/config/riscv/riscv-vsetvl.cc  |  4 +-
 gcc/config/riscv/riscv.cc | 64 +++
 .../riscv/rvv/autovec/partial/slp-9.c |  1 -
 .../gcc.target/riscv/rvv/autovec/pr111391-1.c | 28 
 .../gcc.target/riscv/rvv/autovec/pr111391-2.c | 10 +++
 6 files changed, 106 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111391-2.c

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index e74a1695709..7121bab1716 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1442,7 +1442,7 @@
 ;; -
 ;;  [INT,FP] Extract a vector element.
 ;; -
-(define_expand "@vec_extract"
+(define_expand "vec_extract"
   [(set (match_operand: 0 "register_operand")
  (vec_select:
(match_operand:V_VLS  1 "register_operand")
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index dc02246756d..5f031c18df5 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -649,6 +649,8 @@ emit_vsetvl_insn (enum vsetvl_type insn_type, enum 
emit_type emit_type,
 {
   fprintf (dump_file, "\nInsert vsetvl insn PATTERN:\n");
   print_rtl_single (dump_file, pat);
+  fprintf (dump_file, "\nfor insn:\n");
+  print_rtl_single (dump_file, rinsn);
 }
 
   if (emit_type == EMIT_DIRECT)
@@ -3867,7 +3869,7 @@ pass_vsetvl::local_eliminate_vsetvl_insn (const bb_info 
*bb) const
  skip_one = true;
}
 
- curr_avl = get_avl (rinsn);
+ curr_avl = curr_dem.get_avl ();
 
  /* Some instrucion like pred_extract_first don't reqruie avl, so
 the avl is null, use vl_placeholder for unify the handling
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 762937b0e37..8c766e2e2be 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2513,6 +2513,70 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx 
src)
}
   return true;
 }
+  /* Expand
+   (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
+ Expand this data movement instead of simply forbid it since
+ we can improve the code generation for this following scenario
+ by RVV auto-vectorization:
+   (set (reg:V8QI 149) (vec_duplicate:V8QI (reg:QI))
+   (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
+ Since RVV mode and scalar mode are in different REG_CLASS,
+ we need to explicitly move data from V_REGS to GR_REGS by scalar move.  */
+  if (SUBREG_P (src) && riscv_v_ext_mode_p (GET_MODE (SUBREG_REG (src
+{
+  machine_mode vmode = GET_MODE (SUBREG_REG (src));
+  unsigned int mode_size = GET_MODE_SIZE (mode).to_constant ();
+  unsigned int vmode_size = GET_MODE_SIZE (vmode).to_constant ();
+  unsigned int nunits = vmode_size / mode_size;
+  scalar_mode smode = as_a (mode);
+  unsigned int index = SUBREG_BYTE (src).to_constant () / mode_size;
+  unsigned int num = smode == DImode && !TARGET_VECTOR_ELEN_64 ? 2 : 1;
+
+  if (num == 2)
+   {
+ /* If we want to extract 64bit value but ELEN < 64,
+we use RVV vector mode with EEW = 32 to extract
+the highpart and lowpart.  */
+ smode = SImode;
+ nunits = nunits * 2;
+   }
+  vmode = riscv_vector::get_vector_mode (smode, nunits).require ();
+  enum insn_code icode
+   = convert_optab_handler (vec_extract_optab, vmode, smode);
+  gcc_assert (icode != CODE_FOR_nothing);
+  rtx v = gen_lowpart (vmode, SUBREG_REG (src));
+
+  for (unsigned int i = 0; i < num; i++)
+   {
+ class expand_operand ops[3];
+ rtx result;
+ if (num == 1)
+   result = dest;
+ else if (i == 0)
+   result = gen_lowpart (smode, dest);
+ else
+   result = gen_reg_rtx (smode);
+ create_output_operand (&ops[0], result, smode);
+ ops[0].target = 1;
+ create_input_operand (&ops[1], v, vmode);
+ c

[PATCH] tree-optimization/111294 - better DCE after forwprop

[Richard Biener via Gcc-patches]

The following adds more aggressive DCE to forwprop to clean up dead
stmts when folding a stmt leaves some operands unused.  The patch
uses simple_dce_from_worklist for this purpose, queueing original
operands before substitution and folding, but only if we folded the
stmt.

This removes one dead stmt biasing threading costs in a later pass
but it doesn't resolve the optimization issue in the PR yet.

Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed.

PR tree-optimization/111294
* tree-ssa-forwprop.cc (pass_forwprop::execute): Track
operands that eventually become dead and use simple_dce_from_worklist
to remove their definitions if they did so.

* gcc.dg/tree-ssa/evrp10.c: Adjust.
* gcc.dg/tree-ssa/evrp6.c: Likewise.
* gcc.dg/tree-ssa/forwprop-31.c: Likewise.
* gcc.dg/tree-ssa/neg-cast-3.c: Likewise.
---
 gcc/testsuite/gcc.dg/tree-ssa/evrp10.c  |  2 +-
 gcc/testsuite/gcc.dg/tree-ssa/evrp6.c   |  5 ++--
 gcc/testsuite/gcc.dg/tree-ssa/forwprop-31.c |  3 +--
 gcc/testsuite/gcc.dg/tree-ssa/neg-cast-3.c  |  4 +--
 gcc/tree-ssa-forwprop.cc| 27 +
 5 files changed, 28 insertions(+), 13 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/evrp10.c 
b/gcc/testsuite/gcc.dg/tree-ssa/evrp10.c
index 6ca00e4adaa..776c80c684f 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/evrp10.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/evrp10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fdump-tree-evrp" }*/
+/* { dg-options "-O2 -fdump-tree-evrp -fno-tree-forwprop" }*/
 
 typedef __INT32_TYPE__ int32_t;
 
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/evrp6.c 
b/gcc/testsuite/gcc.dg/tree-ssa/evrp6.c
index aaeec68866e..0f9561b6a72 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/evrp6.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/evrp6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -fdump-tree-evrp-details" } */
+/* { dg-options "-O2 -fdump-tree-evrp-details -fdump-tree-mergephi1" } */
 
 extern void abort (void);
 
@@ -18,4 +18,5 @@ foo (int k, int j)
 
   return j;
 }
-/* { dg-final { scan-tree-dump "\\\[12, \\+INF" "evrp" } } */
+/* { dg-final { scan-tree-dump "\\\[11, \\+INF" "evrp" } } */
+/* { dg-final { scan-tree-dump-not "abort" "mergephi1" } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/forwprop-31.c 
b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-31.c
index edf80264884..40cc86383fa 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/forwprop-31.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-31.c
@@ -9,6 +9,5 @@ int foo (int x)
   return w - z; /* becomes 0 */
 }
 
-/* Only z = x + 1 is retained.  */
-/* { dg-final { scan-tree-dump-times " = " 1 "forwprop1" } } */
+/* { dg-final { scan-tree-dump-times " = " 0 "forwprop1" } } */
 /* { dg-final { scan-tree-dump "return 0;" "forwprop1" } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/neg-cast-3.c 
b/gcc/testsuite/gcc.dg/tree-ssa/neg-cast-3.c
index 7b23ca85d1f..61b89403a93 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/neg-cast-3.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/neg-cast-3.c
@@ -10,6 +10,4 @@ unsigned f(_Bool a)
 }
 
 /* There should be no cast to int at all. */
-/* Forwprop1 does not remove all of the statements. */
-/* { dg-final { scan-tree-dump-not "\\\(int\\\)" "forwprop1" { xfail *-*-* } } 
} */
-/* { dg-final { scan-tree-dump-not "\\\(int\\\)" "optimized" } } */
+/* { dg-final { scan-tree-dump-not "\\\(int\\\)" "forwprop1" } } */
diff --git a/gcc/tree-ssa-forwprop.cc b/gcc/tree-ssa-forwprop.cc
index 94ca47a9726..d4e9202a2d4 100644
--- a/gcc/tree-ssa-forwprop.cc
+++ b/gcc/tree-ssa-forwprop.cc
@@ -53,6 +53,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "cgraph.h"
 #include "tree-ssa.h"
 #include "gimple-range.h"
+#include "tree-ssa-dce.h"
 
 /* This pass propagates the RHS of assignment statements into use
sites of the LHS of the assignment.  It's basically a specialized
@@ -3502,8 +3503,9 @@ pass_forwprop::execute (function *fun)
 |= EDGE_EXECUTABLE;
   auto_vec to_fixup;
   auto_vec to_remove;
+  auto_bitmap simple_dce_worklist;
+  auto_bitmap need_ab_cleanup;
   to_purge = BITMAP_ALLOC (NULL);
-  bitmap need_ab_cleanup = BITMAP_ALLOC (NULL);
   for (int i = 0; i < postorder_num; ++i)
 {
   gimple_stmt_iterator gsi;
@@ -3902,10 +3904,14 @@ pass_forwprop::execute (function *fun)
{
  tree use = USE_FROM_PTR (usep);
  tree val = fwprop_ssa_val (use);
- if (val && val != use && may_propagate_copy (use, val))
+ if (val && val != use)
{
- propagate_value (usep, val);
- substituted_p = true;
+ bitmap_set_bit (simple_dce_worklist, SSA_NAME_VERSION (use));
+ if (may_propagate_copy (use, val))
+   {
+ propagate_value (usep, val);
+ substituted_p = true;
+   }
}
}
  if (substituted_p

[PATCH] LoongArch: gcc: Modify gas uleb128 support test.

[Lulu Cheng]

From: mengqinggang 

Add "ld conftest.o -o conftest" process, then the "objdump -dr" contents
is right. Because gas write zero to objdec file and generate
R_LARCH_ADD_ULEB128/R_LARCH_SUB_ULEB128 reloc pair to calcualte uleb128
format symbol subtraction after ld relaxation.

gcc/ChangeLog:

* configure: Regenerate.
* configure.ac: Add "ld conftest.o -o conftest" process.
---
 gcc/configure| 13 +
 gcc/configure.ac | 13 +
 2 files changed, 26 insertions(+)

diff --git a/gcc/configure b/gcc/configure
index c7b26d1927d..d4763e6fd18 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -24638,6 +24638,19 @@ L2:
   test $ac_status = 0; }; }
 then
 
+case "$target" in
+  loongarch*-*-*)
+if test "x$gcc_cv_ld" != x; then
+  ac_try='$gcc_cv_ld conftest.o -o conftest -e 0x0 >&5'
+  { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0
+  mv conftest conftest.o
+fi
+esac
+
 if test "x$gcc_cv_objdump" != x; then
   if $gcc_cv_objdump -s conftest.o 2>/dev/null \
  | grep '04800a8e 78808080 80808080 808001' >/dev/null; then
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 09082e8ccae..072fe1d2b48 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -3226,6 +3226,19 @@ L2:
.uleb128 0x8000
 ],
 [[
+case "$target" in
+  loongarch*-*-*)
+if test "x$gcc_cv_ld" != x; then
+  ac_try='$gcc_cv_ld conftest.o -o conftest -e 0x0 >&5'
+  { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0
+  mv conftest conftest.o
+fi
+esac
+
 if test "x$gcc_cv_objdump" != x; then
   if $gcc_cv_objdump -s conftest.o 2>/dev/null \
  | grep '04800a8e 78808080 80808080 808001' >/dev/null; then
-- 
2.31.1

Re: [PATCH] LoongArch: gcc: Modify gas uleb128 support test.

[Xi Ruoyao via Gcc-patches]

On Thu, 2023-09-14 at 19:21 +0800, Lulu Cheng wrote:
> diff --git a/gcc/configure.ac b/gcc/configure.ac
> index 09082e8ccae..072fe1d2b48 100644
> --- a/gcc/configure.ac
> +++ b/gcc/configure.ac
> @@ -3226,6 +3226,19 @@ L2:
> .uleb128 0x8000
>  ],
>  [[
> +case "$target" in
> +  loongarch*-*-*)
> +    if test "x$gcc_cv_ld" != x; then
> +  ac_try='$gcc_cv_ld conftest.o -o conftest -e 0x0 >&5'
> +  { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
> +  (eval $ac_try) 2>&5
> +  ac_status=$?
> +  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
> +  test $ac_status = 0
> +  mv conftest conftest.o
> +    fi
> +esac

Phew.  Randomly modifying configure and paste the modification into
configure.ac is not the correct way to modify configure.ac.

ac_* are autoconf internal names so we cannot use them.

-- 
Xi Ruoyao 
School of Aerospace Science and Technology, Xidian University

Re: [PATCH] LoongArch: gcc: Modify gas uleb128 support test.

[chenglulu]

Sorry, it's my problem. We will modify it as soon as possible.

Thanks!

在 2023/9/14 下午7:45, Xi Ruoyao 写道:

On Thu, 2023-09-14 at 19:21 +0800, Lulu Cheng wrote:

diff --git a/gcc/configure.ac b/gcc/configure.ac
index 09082e8ccae..072fe1d2b48 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -3226,6 +3226,19 @@ L2:
 .uleb128 0x8000
  ],
  [[
+case "$target" in
+  loongarch*-*-*)
+    if test "x$gcc_cv_ld" != x; then
+  ac_try='$gcc_cv_ld conftest.o -o conftest -e 0x0 >&5'
+  { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0
+  mv conftest conftest.o
+    fi
+esac

Phew.  Randomly modifying configure and paste the modification into
configure.ac is not the correct way to modify configure.ac.

ac_* are autoconf internal names so we cannot use them.

RE: [PING][PATCH 1/2] arm: Add define_attr to to create a mapping between MVE predicated and unpredicated insns

[Kyrylo Tkachov via Gcc-patches]

Hi Stam,

> -Original Message-
> From: Stam Markianos-Wright 
> Sent: Wednesday, September 6, 2023 6:19 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> 
> Subject: [PING][PATCH 1/2] arm: Add define_attr to to create a mapping
> between MVE predicated and unpredicated insns
> 
> 
> Hi all,
> 
> I'd like to submit two patches that add support for Arm's MVE
> Tail Predicated Low Overhead Loop feature.
> 
> --- Introduction ---
> 
> The M-class Arm-ARM:
> https://developer.arm.com/documentation/ddi0553/bu/?lang=en
> Section B5.5.1 "Loop tail predication" describes the feature
> we are adding support for with this patch (although
> we only add codegen for DLSTP/LETP instruction loops).
> 
> Previously with commit d2ed233cb94 we'd added support for
> non-MVE DLS/LE loops through the loop-doloop pass, which, given
> a standard MVE loop like:
> 
> ```
> void  __attribute__ ((noinline)) test (int16_t *a, int16_t *b, int16_t
> *c, int n)
> {
>    while (n > 0)
>      {
>    mve_pred16_t p = vctp16q (n);
>    int16x8_t va = vldrhq_z_s16 (a, p);
>    int16x8_t vb = vldrhq_z_s16 (b, p);
>    int16x8_t vc = vaddq_x_s16 (va, vb, p);
>    vstrhq_p_s16 (c, vc, p);
>    c+=8;
>    a+=8;
>    b+=8;
>    n-=8;
>      }
> }
> ```
> .. would output:
> 
> ```
>      
>      dls lr, lr
> .L3:
>      vctp.16 r3
>      vmrs    ip, P0  @ movhi
>      sxth    ip, ip
>      vmsr P0, ip @ movhi
>      mov r4, r0
>      vpst
>      vldrht.16   q2, [r4]
>      mov r4, r1
>      vmov    q3, q0
>      vpst
>      vldrht.16   q1, [r4]
>      mov r4, r2
>      vpst
>      vaddt.i16   q3, q2, q1
>      subs    r3, r3, #8
>      vpst
>      vstrht.16   q3, [r4]
>      adds    r0, r0, #16
>      adds    r1, r1, #16
>      adds    r2, r2, #16
>      le  lr, .L3
> ```
> 
> where the LE instruction will decrement LR by 1, compare and
> branch if needed.
> 
> (there are also other inefficiencies with the above code, like the
> pointless vmrs/sxth/vmsr on the VPR and the adds not being merged
> into the vldrht/vstrht as a #16 offsets and some random movs!
> But that's different problems...)
> 
> The MVE version is similar, except that:
> * Instead of DLS/LE the instructions are DLSTP/LETP.
> * Instead of pre-calculating the number of iterations of the
>    loop, we place the number of elements to be processed by the
>    loop into LR.
> * Instead of decrementing the LR by one, LETP will decrement it
>    by FPSCR.LTPSIZE, which is the number of elements being
>    processed in each iteration: 16 for 8-bit elements, 5 for 16-bit
>    elements, etc.
> * On the final iteration, automatic Loop Tail Predication is
>    performed, as if the instructions within the loop had been VPT
>    predicated with a VCTP generating the VPR predicate in every
>    loop iteration.
> 
> The dlstp/letp loop now looks like:
> 
> ```
>      
>      dlstp.16    lr, r3
> .L14:
>      mov r3, r0
>      vldrh.16    q3, [r3]
>      mov r3, r1
>      vldrh.16    q2, [r3]
>      mov r3, r2
>      vadd.i16  q3, q3, q2
>      adds    r0, r0, #16
>      vstrh.16    q3, [r3]
>      adds    r1, r1, #16
>      adds    r2, r2, #16
>      letp    lr, .L14
> 
> ```
> 
> Since the loop tail predication is automatic, we have eliminated
> the VCTP that had been specified by the user in the intrinsic
> and converted the VPT-predicated instructions into their
> unpredicated equivalents (which also saves us from VPST insns).
> 
> The LE instruction here decrements LR by 8 in each iteration.
> 
> --- This 1/2 patch ---
> 
> This first patch lays some groundwork by adding an attribute to
> md patterns, and then the second patch contains the functional
> changes.
> 
> One major difficulty in implementing MVE Tail-Predicated Low
> Overhead Loops was the need to transform VPT-predicated insns
> in the insn chain into their unpredicated equivalents, like:
> `mve_vldrbq_z_ -> mve_vldrbq_`.
> 
> This requires us to have a deterministic link between two
> different patterns in mve.md -- this _could_ be done by
> re-ordering the entirety of mve.md such that the patterns are
> at some constant icode proximity (e.g. having the _z immediately
> after the unpredicated version would mean that to map from the
> former to the latter you could use icode-1), but that is a very
> messy solution that would lead to complex unknown dependencies
> between the ordering of patterns.
> 
> This patch proves an alternative way of doing that: using an insn
> attribute to encode the icode of the unpredicated instruction.
> 
> No regressions on arm-none-eabi with an MVE target.

This patch is okay once the second one is approved (we'd want them committed 
together)
Thanks,
Kyrill

> 
> Thank you,
> Stam Markianos-Wright
> 
> gcc/ChangeLog:
> 
>    

Re: [PATCH] LoongArch: gcc: Modify gas uleb128 support test.

[Xi Ruoyao via Gcc-patches]

On Thu, 2023-09-14 at 19:54 +0800, chenglulu wrote:
> Sorry, it's my problem. We will modify it as soon as possible.

Try this:

diff --git a/gcc/configure.ac b/gcc/configure.ac
index cb4be11facd..10027a4 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -3229,10 +3229,18 @@ AC_MSG_RESULT($gcc_cv_ld_ro_rw_mix)
 
 gcc_AC_INITFINI_ARRAY
 
+# Some assemblers (GNU as for LoongArch) generates relocations for
+# leb128 symbol arithmetic for relaxation, we need to disable relaxation
+# probing leb128 support then.
+gcc_GAS_CHECK_FEATURE([-mno-relax support],
+  gcc_cv_as_mno_relax,[-mno-relax],[.text],,
+  [check_leb128_asflags=-mno-relax])
+
 # Check if we have .[us]leb128, and support symbol arithmetic with it.
 # Older versions of GAS and some non-GNU assemblers, have a bugs handling
 # these directives, even when they appear to accept them.
-gcc_GAS_CHECK_FEATURE([.sleb128 and .uleb128], gcc_cv_as_leb128,,
+gcc_GAS_CHECK_FEATURE([.sleb128 and .uleb128], gcc_cv_as_leb128,
+[$check_leb128_asflags],
 [  .data
.uleb128 L2 - L1
 L1:



-- 
Xi Ruoyao 
School of Aerospace Science and Technology, Xidian University

Re: [PATCH 01/13] [APX EGPR] middle-end: Add insn argument to base_reg_class

[Vladimir Makarov via Gcc-patches]

On 9/10/23 00:49, Hongyu Wang wrote:

Vladimir Makarov via Gcc-patches  于2023年9月9日周六 01:04写道：


On 8/31/23 04:20, Hongyu Wang wrote:

@@ -2542,6 +2542,8 @@ the code of the immediately enclosing expression 
(@code{MEM} for the top level
   of an address, @code{ADDRESS} for something that occurs in an
   @code{address_operand}).  @var{index_code} is the code of the corresponding
   index expression if @var{outer_code} is @code{PLUS}; @code{SCRATCH} 
otherwise.
+@code{insn} indicates insn specific base register class should be subset
+of the original base register class.
   @end defmac

I'd prefer more general description of 'insn' argument for the macros.
Something like that:

@code{insn} can be used to define an insn-specific base register class.


Sure, will adjust in the V2 patch.
Also, currently we reuse the old macro MODE_CODE_BASE_REG_CLASS, do
you think we need a new macro like INSN_BASE_REG_CLASS as other
parameters are actually unused? Then we don't need to change other
targets like avr/gcn.

I thought about this too.  Using new macros would be definitely worth to 
add, especially when you are already adding INSN_INDEX_REG_CLASS.


The names INSN_BASE_REG_CLASS instead of MODE_CODE_BASE_REG_CLASS and 
REGNO_OK_FOR_INSN_BASE_P instead of REGNO_MODE_CODE_OK_FOR_BASE_P are ok 
for me too.


When you submit the v2 patch, I'll review the RA part as soon as 
possible (actually I already looked at this) and most probably give my 
approval for the RA part because I prefer you current approach for RA 
instead of introducing new memory constraints.

RE: [PING][PATCH 2/2] arm: Add support for MVE Tail-Predicated Low Overhead Loops

[Kyrylo Tkachov via Gcc-patches]

Hi Stam,

> -Original Message-
> From: Stam Markianos-Wright 
> Sent: Wednesday, September 6, 2023 6:19 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov ; Richard Earnshaw
> 
> Subject: [PING][PATCH 2/2] arm: Add support for MVE Tail-Predicated Low
> Overhead Loops
> 
> Hi all,
> 
> This is the 2/2 patch that contains the functional changes needed
> for MVE Tail Predicated Low Overhead Loops.  See my previous email
> for a general introduction of MVE LOLs.
> 
> This support is added through the already existing loop-doloop
> mechanisms that are used for non-MVE dls/le looping.
> 
> Mid-end changes are:
> 
> 1) Relax the loop-doloop mechanism in the mid-end to allow for
>     decrement numbers other that -1 and for `count` to be an
>     rtx containing a simple REG (which in this case will contain
>     the number of elements to be processed), rather
>     than an expression for calculating the number of iterations.
> 2) Added a new df utility function: `df_bb_regno_only_def_find` that
>     will return the DEF of a REG if it is DEF-ed only once within the
>     basic block.
> 
> And many things in the backend to implement the above optimisation:
> 
> 3)  Implement the `arm_predict_doloop_p` target hook to instruct the
>      mid-end about Low Overhead Loops (MVE or not), as well as
>      `arm_loop_unroll_adjust` which will prevent unrolling of any loops
>      that are valid for becoming MVE Tail_Predicated Low Overhead Loops
>      (unrolling can transform a loop in ways that invalidate the dlstp/
>      letp tranformation logic and the benefit of the dlstp/letp loop
>      would be considerably higher than that of unrolling)
> 4)  Appropriate changes to the define_expand of doloop_end, new
>      patterns for dlstp and letp, new iterators,  unspecs, etc.
> 5) `arm_mve_loop_valid_for_dlstp` and a number of checking functions:
>     * `arm_mve_dlstp_check_dec_counter`
>     * `arm_mve_dlstp_check_inc_counter`
>     * `arm_mve_check_reg_origin_is_num_elems`
>     * `arm_mve_check_df_chain_back_for_implic_predic`
>     * `arm_mve_check_df_chain_fwd_for_implic_predic_impact`
>     This all, in smoe way or another, are running checks on the loop
>     structure in order to determine if the loop is valid for dlstp/letp
>     transformation.
> 6) `arm_attempt_dlstp_transform`: (called from the define_expand of
>      doloop_end) this function re-checks for the loop's suitability for
>      dlstp/letp transformation and then implements it, if possible.
> 7) Various utility functions:
>     *`arm_mve_get_vctp_lanes` to map
>     from vctp unspecs to number of lanes, and `arm_get_required_vpr_reg`
>     to check an insn to see if it requires the VPR or not.
>     * `arm_mve_get_loop_vctp`
>     * `arm_mve_get_vctp_lanes`
>     * `arm_emit_mve_unpredicated_insn_to_seq`
>     * `arm_get_required_vpr_reg`
>     * `arm_get_required_vpr_reg_param`
>     * `arm_get_required_vpr_reg_ret_val`
>     * `arm_mve_is_across_vector_insn`
>     * `arm_is_mve_load_store_insn`
>     * `arm_mve_vec_insn_is_predicated_with_this_predicate`
>     * `arm_mve_vec_insn_is_unpredicated_or_uses_other_predicate`
> 
> No regressions on arm-none-eabi with various targets and on
> aarch64-none-elf. Thoughts on getting this into trunk?

The arm parts look sensible but we'd need review for the df-core.h and 
df-core.cc changes.
Maybe Jeff can help or can recommend someone to take a look?
Thanks,
Kyrill

> 
> Thank you,
> Stam Markianos-Wright
> 
> gcc/ChangeLog:
> 
>      * config/arm/arm-protos.h (arm_target_insn_ok_for_lob): Rename to...
>      (arm_target_bb_ok_for_lob): ...this
>      (arm_attempt_dlstp_transform): New.
>      * config/arm/arm.cc (TARGET_LOOP_UNROLL_ADJUST): New.
>      (TARGET_PREDICT_DOLOOP_P): New.
>      (arm_block_set_vect):
>      (arm_target_insn_ok_for_lob): Rename from arm_target_insn_ok_for_lob.
>      (arm_target_bb_ok_for_lob): New.
>      (arm_mve_get_vctp_lanes): New.
>      (arm_get_required_vpr_reg): New.
>      (arm_get_required_vpr_reg_param): New.
>      (arm_get_required_vpr_reg_ret_val): New.
>      (arm_mve_get_loop_vctp): New.
>      (arm_mve_vec_insn_is_unpredicated_or_uses_other_predicate): New.
>      (arm_mve_vec_insn_is_predicated_with_this_predicate): New.
>      (arm_mve_check_df_chain_back_for_implic_predic): New.
>      (arm_mve_check_df_chain_fwd_for_implic_predic_impact): New.
>      (arm_mve_check_reg_origin_is_num_elems): New.
>      (arm_mve_dlstp_check_inc_counter): New.
>      (arm_mve_dlstp_check_dec_counter): New.
>      (arm_mve_loop_valid_for_dlstp): New.
>      (arm_mve_is_across_vector_insn): New.
>      (arm_is_mve_load_store_insn): New.
>      (arm_predict_doloop_p): New.
>      (arm_loop_unroll_adjust): New.
>      (arm_emit_mve_unpredicated_insn_to_seq): New.
>      (arm_attempt_dlstp_transform): New.
>      * config/arm/iterators.md (DLSTP): New.
>      (mode1): Add DLSTP mappings.
>      * config/arm/mve.md (*predicated_doloop_end_internal): New.
>  

[PATCH v4] [tree-optimization/110279] Consider FMA in get_reassociation_width

[Di Zhao OS via Gcc-patches]

This is a new version of the patch on "nested FMA".
Sorry for updating this after so long, I've been studying and
writing micro cases to sort out the cause of the regression.

First, following previous discussion:
(https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629080.html)

1. From testing more altered cases, I don't think the
problem is that reassociation works locally. In that:

  1) On the example with multiplications:

tmp1 = a + c * c + d * d + x * y;
tmp2 = x * tmp1;
result += (a + c + d + tmp2);

  Given "result" rewritten by width=2, the performance is
  worse if we rewrite "tmp1" with width=2. In contrast, if we
  remove the multiplications from the example (and make "tmp1"
  not singe used), and still rewrite "result" by width=2, then
  rewriting "tmp1" with width=2 is better. (Make sense because
  the tree's depth at "result" is still smaller if we rewrite
  "tmp1".)

  2) I tried to modify the assembly code of the example without
  FMA, so the width of "result" is 4. On Ampere1 there's no
  obvious improvement. So although this is an interesting
  problem, it doesn't seem like the cause of the regression.

2. From assembly code of the case with FMA, one problem is
that, rewriting "tmp1" to parallel didn't decrease the
minimum CPU cycles (taking MULT_EXPRs into account), but
increased code size, so the overhead is increased.

   a) When "tmp1" is not re-written to parallel:
fmadd d31, d2, d2, d30
fmadd d31, d3, d3, d31
fmadd d31, d4, d5, d31  //"tmp1"
fmadd d31, d31, d4, d3

   b) When "tmp1" is re-written to parallel:
fmul  d31, d4, d5  
fmadd d27, d2, d2, d30 
fmadd d31, d3, d3, d31 
fadd  d31, d31, d27 //"tmp1"
fmadd d31, d31, d4, d3

For version a), there are 3 dependent FMAs to calculate "tmp1".
For version b), there are also 3 dependent instructions in the
longer path: the 1st, 3rd and 4th.

So it seems to me the current get_reassociation_width algorithm
isn't optimal in the presence of FMA. So I modified the patch to
improve get_reassociation_width, rather than check for code
patterns. (Although there could be some other complicated
factors so the regression is more obvious when there's "nested
FMA". But with this patch that should be avoided or reduced.)

With this patch 508.namd_r 1-copy run has 7% improvement on
Ampere1, on Intel Xeon there's about 3%. While I'm still
collecting data on other CPUs, I'd like to know how do you
think of this.

About changes in the patch:

1. When the op list forms a complete FMA chain, try to search
for a smaller width considering the benefit of using FMA. With
a smaller width, the increment of code size is smaller when
breaking the chain.

2. To avoid regressions, included the other patch
(https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629203.html)
on this tracker again. This is because more FMA will be kept
with 1., so we need to rule out the loop dependent
FMA chains when param_avoid_fma_max_bits is set.

Thanks,
Di Zhao



PR tree-optimization/110279

gcc/ChangeLog:

* tree-ssa-reassoc.cc (rank_ops_for_better_parallelism_p):
New function to check whether ranking the ops results in
better parallelism.
(get_reassociation_width): Add new parameters. Search for
smaller width considering the benefit of FMA.
(rank_ops_for_fma): Change return value to be number of
MULT_EXPRs.
(reassociate_bb): For 3 ops, refine the condition to call
swap_ops_for_binary_stmt.

gcc/testsuite/ChangeLog:

* gcc.dg/pr110279.c: New test.


0001-Consider-FMA-in-get_reassociation_width.patch
Description: 0001-Consider-FMA-in-get_reassociation_width.patch

[PATCH] RISC-V: Support VLS modes mask operations

[Juzhe-Zhong]

This patch support mask operations (comparison and logical).

This patch reduce these FAILs of "vect" testsuite:
FAIL: gcc.dg/vect/vect-bic-bitmask-12.c -flto -ffat-lto-objects  scan-tree-dump 
dce7 "<=\\s*.+{ 255,.+}"
FAIL: gcc.dg/vect/vect-bic-bitmask-12.c scan-tree-dump dce7 "<=\\s*.+{ 255,.+}"
FAIL: gcc.dg/vect/vect-bic-bitmask-23.c -flto -ffat-lto-objects  scan-tree-dump 
dce7 "<=\\s*.+{ 255, 15, 1, 65535 }"
FAIL: gcc.dg/vect/vect-bic-bitmask-23.c scan-tree-dump dce7 "<=\\s*.+{ 255, 15, 
1, 65535 }"

Full regression passed (with reducing 4 FAILs).

gcc/ChangeLog:

* config/riscv/autovec-opt.md: Add VLS mask modes.
* config/riscv/autovec.md (@vcond_mask_): Remove @.
(vcond_mask_): Add VLS mask modes.
* config/riscv/vector.md: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS tests.
* gcc.target/riscv/rvv/autovec/vls/cmp-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cmp-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cmp-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cmp-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cmp-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cmp-6.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mask-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mask-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mask-3.c: New test.

---
 gcc/config/riscv/autovec-opt.md   |  18 +--
 gcc/config/riscv/autovec.md   |  32 +++---
 gcc/config/riscv/vector.md|  60 +-
 .../gcc.target/riscv/rvv/autovec/vls/cmp-1.c  | 106 ++
 .../gcc.target/riscv/rvv/autovec/vls/cmp-2.c  | 106 ++
 .../gcc.target/riscv/rvv/autovec/vls/cmp-3.c  | 106 ++
 .../gcc.target/riscv/rvv/autovec/vls/cmp-4.c  | 106 ++
 .../gcc.target/riscv/rvv/autovec/vls/cmp-5.c  | 106 ++
 .../gcc.target/riscv/rvv/autovec/vls/cmp-6.c  | 106 ++
 .../gcc.target/riscv/rvv/autovec/vls/def.h|   9 ++
 .../gcc.target/riscv/rvv/autovec/vls/mask-1.c |  69 
 .../gcc.target/riscv/rvv/autovec/vls/mask-2.c |  69 
 .../gcc.target/riscv/rvv/autovec/vls/mask-3.c |  69 
 13 files changed, 907 insertions(+), 55 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-3.c

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index e26c01856ff..22ab8afc994 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -67,10 +67,10 @@
 ;; -
 
 (define_insn_and_split "*not"
-  [(set (match_operand:VB 0 "register_operand"   "=vr")
-   (bitmanip_bitwise:VB
- (not:VB (match_operand:VB 2 "register_operand" " vr"))
- (match_operand:VB 1 "register_operand" " vr")))]
+  [(set (match_operand:VB_VLS 0 "register_operand"   "=vr")
+   (bitmanip_bitwise:VB_VLS
+ (not:VB_VLS (match_operand:VB_VLS 2 "register_operand" " vr"))
+ (match_operand:VB_VLS 1 "register_operand" " vr")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
@@ -93,11 +93,11 @@
 ;; -
 
 (define_insn_and_split "*n"
-  [(set (match_operand:VB 0 "register_operand" "=vr")
-   (not:VB
- (any_bitwise:VB
-   (match_operand:VB 1 "register_operand" " vr")
-   (match_operand:VB 2 "register_operand" " vr"]
+  [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
+   (not:VB_VLS
+ (any_bitwise:VB_VLS
+   (match_operand:VB_VLS 1 "register_operand" " vr")
+   (match_operand:VB_VLS 2 "register_operand" " vr"]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 7121bab1716..d2002a8ee26 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -495,9 +495,9 @@
 ;; -
 
 (define_insn_and_split "3"
-  [(set (match_operand:VB 0 "register_operand" "=vr")
-   (any_bitwise:VB (match_operand:VB 1 "register_operand" " vr")
-

[COMMITTED] ada: Fix premature finalization in loop over limited iterable container

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

This happens when the iterable container is obtained as the result of a
call to a function that is a subprogram parameter of a generic construct.

gcc/ada/

* exp_util.adb (Initialized_By_Aliased_BIP_Func_Call): Make the name
matching more robust.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_util.adb | 88 
 1 file changed, 48 insertions(+), 40 deletions(-)

diff --git a/gcc/ada/exp_util.adb b/gcc/ada/exp_util.adb
index a4b5ec366f3..0dafa1cd6be 100644
--- a/gcc/ada/exp_util.adb
+++ b/gcc/ada/exp_util.adb
@@ -8399,65 +8399,73 @@ package body Exp_Util is
 
  Call := Unqual_Conv (Call);
 
+ --  We search for a formal with a matching suffix. We can't search
+ --  for the full name, because of the code at the end of Sem_Ch6.-
+ --  Create_Extra_Formals, which copies the Extra_Formals over to
+ --  the Alias of an instance, which will cause the formals to have
+ --  "incorrect" names. See also Exp_Ch6.Build_In_Place_Formal.
+
  if Is_Build_In_Place_Function_Call (Call) then
 declare
Caller_Allocation_Val : constant Uint :=
  UI_From_Int (BIP_Allocation_Form'Pos (Caller_Allocation));
+   Access_Suffix : constant String :=
+ BIP_Formal_Suffix (BIP_Object_Access);
+   Alloc_Suffix  : constant String :=
+ BIP_Formal_Suffix (BIP_Alloc_Form);
+
+   function Has_Suffix (Name, Suffix : String) return Boolean;
+   --  Return True if Name has suffix Suffix
+
+   
+   -- Has_Suffix --
+   
+
+   function Has_Suffix (Name, Suffix : String) return Boolean is
+  Len : constant Natural := Suffix'Length;
+
+   begin
+  return Name'Length > Len
+and then Name (Name'Last - Len + 1 .. Name'Last) = Suffix;
+   end Has_Suffix;
 
-   Access_Nam : Name_Id := No_Name;
Access_OK  : Boolean := False;
-   Actual : Node_Id;
-   Alloc_Nam  : Name_Id := No_Name;
Alloc_OK   : Boolean := True;
-   Formal : Node_Id;
-   Func_Id: Entity_Id;
Param  : Node_Id;
 
 begin
--  Examine all parameter associations of the function call
 
Param := First (Parameter_Associations (Call));
+
while Present (Param) loop
   if Nkind (Param) = N_Parameter_Association
 and then Nkind (Selector_Name (Param)) = N_Identifier
   then
- Actual := Explicit_Actual_Parameter (Param);
- Formal := Selector_Name (Param);
-
- --  Construct the names of formals BIPaccess and BIPalloc
- --  using the function name retrieved from an arbitrary
- --  formal.
-
- if Access_Nam = No_Name
-   and then Alloc_Nam = No_Name
-   and then Present (Entity (Formal))
- then
-Func_Id := Scope (Entity (Formal));
-
-Access_Nam :=
-  New_External_Name (Chars (Func_Id),
-BIP_Formal_Suffix (BIP_Object_Access));
-
-Alloc_Nam :=
-  New_External_Name (Chars (Func_Id),
-BIP_Formal_Suffix (BIP_Alloc_Form));
- end if;
+ declare
+Actual : constant Node_Id
+  := Explicit_Actual_Parameter (Param);
+Formal : constant Node_Id
+  := Selector_Name (Param);
+Name   : constant String
+  := Get_Name_String (Chars (Formal));
 
- --  A nonnull BIPaccess has been found
+ begin
+--  A nonnull BIPaccess has been found
 
- if Chars (Formal) = Access_Nam
-   and then Nkind (Actual) /= N_Null
- then
-Access_OK := True;
- end if;
+if Has_Suffix (Name, Access_Suffix)
+  and then Nkind (Actual) /= N_Null
+then
+   Access_OK := True;
 
- --  A BIPalloc has been found
+--  A BIPalloc has been found
 
- if Chars (Formal) = Alloc_Nam
-   and then Nkind (Actual) = N_Integer_Literal
- then
-Alloc_OK := Intval (Actual) = Caller_Allocati

[COMMITTED] ada: Assertion failure adding extra formals to late overriding subp.

[Marc Poulhiès via Gcc-patches]

From: Javier Miranda 

gcc/ada/

* sem_ch6.adb (Parent_Subprogram): Complete assertion.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_ch6.adb | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/ada/sem_ch6.adb b/gcc/ada/sem_ch6.adb
index 297371a2c16..612a9e97221 100644
--- a/gcc/ada/sem_ch6.adb
+++ b/gcc/ada/sem_ch6.adb
@@ -8789,7 +8789,8 @@ package body Sem_Ch6 is
  and then Has_Controlling_Result (Subp_Id))
or else Has_Suffix (Ovr_E, 'P')
or else Is_RACW_Stub_Type
- (Find_Dispatching_Type (Subp_Id)));
+ (Find_Dispatching_Type (Subp_Id))
+   or else No (Overridden_Operation (Ovr_E)));
 
if Present (Overridden_Operation (Ovr_E)) then
   Ovr_E := Overridden_Operation (Ovr_E);
-- 
2.40.0

[COMMITTED] ada: Assertion failure on for-of loop iterating on selected component

[Marc Poulhiès via Gcc-patches]

From: Javier Miranda 

gcc/ada/

* sem_util.adb (Is_Dependent_Component_Of_Mutable_Object): Protect
access to Entity attribute and add missing code to check function
selector in a prefix form call.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_util.adb | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index 35ec296ab93..3229f4e9dd2 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -16509,8 +16509,13 @@ package body Sem_Util is
 --  False (it could be a function selector in a prefix form call
 --  occurring in an iterator specification).
 
-if Ekind (Entity (Selector_Name (Object))) not in
- E_Component | E_Discriminant
+if (Present (Entity (Selector_Name (Object)))
+  and then Ekind (Entity (Selector_Name (Object))) not in
+ E_Component | E_Discriminant)
+  or else
+(Inside_A_Generic
+   and then Nkind (Parent (Selector_Name (Object)))
+  = N_Function_Call)
 then
return False;
 end if;
-- 
2.40.0

[COMMITTED] ada: Improve detection of deactivated code for warnings with -gnatwt

[Marc Poulhiès via Gcc-patches]

From: Yannick Moy 

Switch -gnatwt is used in GNAT to track deleted code. It can be emitted
by GNAT on code that is intentionally deactivated for a given configuration.
The current test to suppress spurious warnings is not complex enough to
detect all such cases. Now improved, by using the same test as used in
GNATprove to suppress warnings related to a "statically disabled condition
which evaluates to a given value", as described in SPARK UG 7.3.2.

gcc/ada/

* exp_util.adb (Is_Statically_Disabled): New function to detect a
"statically disabled condition which evaluates to a given value",
as described in SPARK UG 7.3.2.
(Kill_Dead_Code): Call the new function Is_Statically_Disabled for
conditions of if statements.
* exp_util.ads (Is_Statically_Disabled): New function spec.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_util.adb | 159 ---
 gcc/ada/exp_util.ads |  17 +
 2 files changed, 167 insertions(+), 9 deletions(-)

diff --git a/gcc/ada/exp_util.adb b/gcc/ada/exp_util.adb
index 5cfadc5245e..b2542d4ae59 100644
--- a/gcc/ada/exp_util.adb
+++ b/gcc/ada/exp_util.adb
@@ -30,7 +30,6 @@ with Checks; use Checks;
 with Debug;  use Debug;
 with Einfo;  use Einfo;
 with Einfo.Entities; use Einfo.Entities;
-with Einfo.Utils;use Einfo.Utils;
 with Elists; use Elists;
 with Errout; use Errout;
 with Exp_Aggr;   use Exp_Aggr;
@@ -9401,6 +9400,135 @@ package body Exp_Util is
 and then Has_Controlling_Result (Id);
end Is_Secondary_Stack_Thunk;
 
+   
+   -- Is_Statically_Disabled --
+   
+
+   function Is_Statically_Disabled
+ (N : Node_Id;
+  Value : Boolean;
+  Include_Valid : Boolean)
+  return Boolean
+   is
+  function Is_Discrete_Literal (N : Node_Id) return Boolean;
+  --  Returns whether N is an integer, character or enumeration literal
+
+  -
+  -- Is_Discrete_Literal --
+  -
+
+  function Is_Discrete_Literal (N : Node_Id) return Boolean is
+(Nkind (N) in N_Integer_Literal | N_Character_Literal
+  or else (Nkind (N) in N_Identifier | N_Expanded_Name
+and then Ekind (Entity (N)) = E_Enumeration_Literal));
+
+  Expr_N : constant Node_Id :=
+(if Is_Static_Expression (N)
+   and then Entity (N) in Standard_True | Standard_False
+   and then Is_Rewrite_Substitution (N)
+ then Original_Node (N)
+ else N);
+
+   --  Start of processing for Is_Statically_Disabled
+
+   begin
+  --  A "statically disabled" condition which evaluates to Value is either:
+
+  case Nkind (Expr_N) is
+
+ --  an AND or AND THEN operator when:
+ --  - Value is True and both operands are statically disabled
+ --conditions evaluated to True.
+ --  - Value is False and at least one operand is a statically disabled
+ --condition evaluated to False.
+
+ when N_Op_And | N_And_Then =>
+return
+  (if Value then
+ (Is_Statically_Disabled
+(Left_Opnd (Expr_N), Value, Include_Valid)
+  and then Is_Statically_Disabled
+(Right_Opnd (Expr_N), Value, Include_Valid))
+   else
+ (Is_Statically_Disabled
+(Left_Opnd (Expr_N), Value, Include_Valid)
+  or else Is_Statically_Disabled
+(Right_Opnd (Expr_N), Value, Include_Valid)));
+
+ --  an OR or OR ELSE operator when:
+ --  - Value is True and at least one operand is a statically disabled
+ --condition evaluated to True.
+ --  - Value is False and both operands are statically disabled
+ --conditions evaluated to False.
+
+ when N_Op_Or | N_Or_Else =>
+return
+  (if Value then
+ (Is_Statically_Disabled
+(Left_Opnd (Expr_N), Value, Include_Valid)
+  or else Is_Statically_Disabled
+(Right_Opnd (Expr_N), Value, Include_Valid))
+   else
+ (Is_Statically_Disabled
+(Left_Opnd (Expr_N), Value, Include_Valid)
+  and then Is_Statically_Disabled
+(Right_Opnd (Expr_N), Value, Include_Valid)));
+
+ --  a NOT operator when the right operand is a statically disabled
+ --  condition evaluated to the negation of Value.
+
+ when N_Op_Not =>
+return Is_Statically_Disabled
+  (Right_Opnd (Expr_N), not Value, Include_Valid);
+
+ --  a static constant when it is of a boolean type with aspect
+ --  Warnings Off.
+
+ when N_Identifier | N_Expanded_Name =>
+return Is_Stat

[COMMITTED] ada: Fix late finalization for function call in delta aggregate

[Marc Poulhiès via Gcc-patches]

From: Eric Botcazou 

The problem occurs at library level because the temporary created for the
function call lives in the elaboration routine but is finalized only when
the package itself is.

It turns out that there is no need for this temporary, since the expansion
of delta aggregates already creates a (properly finalized) temporary.

gcc/ada/

* exp_ch6.adb (Expand_Ctrl_Function_Call): Also do nothing for the
expression of a delta aggregate.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_ch6.adb | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/gcc/ada/exp_ch6.adb b/gcc/ada/exp_ch6.adb
index 0d1f1fb1c3b..da1c9e66102 100644
--- a/gcc/ada/exp_ch6.adb
+++ b/gcc/ada/exp_ch6.adb
@@ -5424,9 +5424,13 @@ package body Exp_Ch6 is
   --  object, then no need to copy/readjust/finalize, we can initialize it
   --  in place. However, if the call returns on the secondary stack, then
   --  we need the expansion because we'll be renaming the temporary as the
-  --  (permanent) object.
+  --  (permanent) object. We also apply it in the case of the expression of
+  --  a delta aggregate, since it is used only to initialize a temporary.
 
-  if Nkind (Par) = N_Object_Declaration and then not Use_Sec_Stack then
+  if Nkind (Par) in N_Object_Declaration | N_Delta_Aggregate
+and then Expression (Par) = N
+and then not Use_Sec_Stack
+  then
  return;
   end if;
 
-- 
2.40.0

[COMMITTED] ada: Assertion failure on calculation of Large_Max_Size_Mutable

[Marc Poulhiès via Gcc-patches]

From: Javier Miranda 

gcc/ada/

* sem_util.adb (Large_Max_Size_Mutable): Protect access to
attribute Is_Array_Type.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/sem_util.adb | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/ada/sem_util.adb b/gcc/ada/sem_util.adb
index 3229f4e9dd2..cc9dcb30b18 100644
--- a/gcc/ada/sem_util.adb
+++ b/gcc/ada/sem_util.adb
@@ -22580,7 +22580,9 @@ package body Sem_Util is
  Ityp : Entity_Id;
 
   begin
- if Is_Array_Type (Comp_Type) then
+ if Present (Comp_Type)
+   and then Is_Array_Type (Comp_Type)
+ then
 Indx := First_Index (Comp_Type);
 
 while Present (Indx) loop
-- 
2.40.0

[COMMITTED] ada: Assertion failure on expansion of record with invariant

[Marc Poulhiès via Gcc-patches]

From: Javier Miranda 

gcc/ada/

* exp_util.adb (Process_Record_Component): Adjust assertion on the
availablity of the invariant procedure; required because the
invariant procedure is built by the expander, and hence it is not
available compiling generic units or when the sources have errors,
since expansion is then disabled.

Tested on x86_64-pc-linux-gnu, committed on master.

---
 gcc/ada/exp_util.adb | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/gcc/ada/exp_util.adb b/gcc/ada/exp_util.adb
index 0dafa1cd6be..5cfadc5245e 100644
--- a/gcc/ada/exp_util.adb
+++ b/gcc/ada/exp_util.adb
@@ -3324,7 +3324,13 @@ package body Exp_Util is
   --  if it has invariants of its own or inherits class-wide
   --  invariants from parent or interface types.
 
-  pragma Assert (Present (Proc_Id));
+  --  However, given that the invariant procedure is built by
+  --  the expander, it is not available compiling generic units
+  --  or when the sources have errors, since expansion is then
+  --  disabled.
+
+  pragma Assert (Present (Proc_Id)
+or else not Expander_Active);
 
   --  Generate:
   --Invariant (T (_object).);
@@ -,7 +3339,9 @@ package body Exp_Util is
   --  assertions are disabled or Assertion_Policy Ignore is in
   --  effect.
 
-  if not Has_Null_Body (Proc_Id) then
+  if Present (Proc_Id)
+and then not Has_Null_Body (Proc_Id)
+  then
  Append_New_To (Comp_Checks,
Make_Procedure_Call_Statement (Loc,
  Name   =>
-- 
2.40.0

[PATCH] tree-optimization/111294 - backwards threader PHI costing

[Richard Biener via Gcc-patches]

This revives an earlier patch since the problematic code applying
extra costs to PHIs in copied blocks we couldn't make any sense of
prevents a required threading in this case.  Instead of coming up
with an artificial other costing the following simply removes the
bits.

As with all threading changes this requires a plethora of testsuite
adjustments, but only the last three are unfortunate as is the
libgomp team.c adjustment which is required to avoid a bogus -Werror
diagnostic during bootstrap.

Bootstrapped and tested on x86_64-unknown-linux-gnu.

Any objections?

Thanks,
Richard.

PR tree-optimization/111294
gcc/
* tree-ssa-threadbackward.cc (back_threader_profitability::m_name):
Remove
(back_threader::find_paths_to_names): Adjust.
(back_threader::maybe_thread_block): Likewise.
(back_threader_profitability::possibly_profitable_path_p): Remove
code applying extra costs to copies PHIs.

libgomp/
* team.c (gomp_team_start): Guard gomp_alloca to avoid false
positive alloc-size diagnostic.

gcc/testsuite/
* gcc.dg/tree-ssa/pr111294.c: New test.
* gcc.dg/tree-ssa/phi_on_compare-4.c: Adjust.
* gcc.dg/tree-ssa/pr59597.c: Likewise.
* gcc.dg/tree-ssa/pr61839_2.c: Likewise.
* gcc.dg/tree-ssa/ssa-sink-18.c: Likewise.
* g++.dg/warn/Wstringop-overflow-4.C: XFAIL subtest on ilp32.
* gcc.dg/uninit-pred-9_b.c: XFAIL subtest everywhere.
* gcc.dg/vect/vect-117.c: Make scan for not Invalid sum
conditional on lp64.
---
 .../g++.dg/warn/Wstringop-overflow-4.C|  4 +-
 .../gcc.dg/tree-ssa/phi_on_compare-4.c|  4 +-
 gcc/testsuite/gcc.dg/tree-ssa/pr111294.c  | 32 ++
 gcc/testsuite/gcc.dg/tree-ssa/pr59597.c   |  8 +--
 gcc/testsuite/gcc.dg/tree-ssa/pr61839_2.c |  4 +-
 gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c   |  6 +-
 gcc/testsuite/gcc.dg/uninit-pred-9_b.c|  2 +-
 gcc/testsuite/gcc.dg/vect/vect-117.c  |  2 +-
 gcc/tree-ssa-threadbackward.cc| 60 ++-
 libgomp/team.c|  5 +-
 10 files changed, 57 insertions(+), 70 deletions(-)
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr111294.c

diff --git a/gcc/testsuite/g++.dg/warn/Wstringop-overflow-4.C 
b/gcc/testsuite/g++.dg/warn/Wstringop-overflow-4.C
index faad5bed074..275ecac01b5 100644
--- a/gcc/testsuite/g++.dg/warn/Wstringop-overflow-4.C
+++ b/gcc/testsuite/g++.dg/warn/Wstringop-overflow-4.C
@@ -151,7 +151,9 @@ void test_strcpy_new_int16_t (size_t n, const size_t vals[])
as size_t as a result of threading.  See PR 101688 comment #2.  */
 T (S (1), new int16_t[r_0_imax]);
 
-  T (S (2), new int16_t[r_0_imax + 1]);
+  /* Similar to PR 101688 the following can result in a bougs warning because
+ of threading.  */
+  T (S (2), new int16_t[r_0_imax + 1]); // { dg-bogus "into a region of size" 
"" { xfail { ilp32 } } }
   T (S (9), new int16_t[r_0_imax * 2 + 1]);
 
   int r_1_imax = SR (1, INT_MAX);
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/phi_on_compare-4.c 
b/gcc/testsuite/gcc.dg/tree-ssa/phi_on_compare-4.c
index 1e09f89af9f..6240d1cdd6d 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/phi_on_compare-4.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/phi_on_compare-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-Ofast -fdump-tree-dom2" } */
+/* { dg-options "-Ofast -fdump-tree-threadfull1-stats" } */
 
 void g (int);
 void g1 (int);
@@ -37,4 +37,4 @@ f (long a, long b, long c, long d, int x)
   g (c + d);
 }
 
-/* { dg-final { scan-tree-dump-times "Removing basic block" 1 "dom2" } } */
+/* { dg-final { scan-tree-dump "Jumps threaded: 2" "threadfull1" } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr111294.c 
b/gcc/testsuite/gcc.dg/tree-ssa/pr111294.c
new file mode 100644
index 000..9ad912bad0b
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr111294.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -fdump-tree-optimized" } */
+
+void foo(void);
+static short a;
+static int b, c, d;
+static int *e, *f = &d;
+static int **g = &e;
+static unsigned char h;
+static short(i)(short j, int k) { return j > k ?: j; }
+static char l() {
+if (a) return b;
+return c;
+}
+int main() {
+b = 0;
+for (; b < 5; ++b)
+;
+h = l();
+if (a ^ 3 >= i(h, 11))
+a = 0;
+else {
+*g = f;
+if (e == &d & b) {
+__builtin_unreachable();
+} else
+foo();
+;
+}
+}
+
+/* { dg-final { scan-tree-dump-not "foo" "optimized" } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr59597.c 
b/gcc/testsuite/gcc.dg/tree-ssa/pr59597.c
index 0f66aae87bb..26c81d9dbb7 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/pr59597.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr59597.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-Ofast -fdisable-tree-cunrolli 
-fdump-tree-threadfull1-details" } */
+/* { dg-options "-Ofast -fdump-tree-et

[PATCH] tree optimization/111407--SSA corruption due to widening_mul opt

[Qing Zhao via Gcc-patches]

on conflict across an abnormal edge

This is a bug in tree-ssa-math-opts.cc, when applying the widening mul
optimization, the compiler needs to check whether the operand is in a
ABNORMAL PHI, if YES, we should avoid the transformation.

bootstrapped and regression tested on both aarch64 and x86, no issue.

Okay for committing?

thanks.

Qing

=

PR tree-optimization/111407

gcc/ChangeLog:

* tree-ssa-math-opts.cc (convert_mult_to_widen): Avoid the transform
when one of the operands is subject to abnormal coalescing.

gcc/testsuite/ChangeLog:

* gcc.dg/pr111407.c: New test.
---
 gcc/testsuite/gcc.dg/pr111407.c | 21 +
 gcc/tree-ssa-math-opts.cc   |  8 
 2 files changed, 29 insertions(+)
 create mode 100644 gcc/testsuite/gcc.dg/pr111407.c

diff --git a/gcc/testsuite/gcc.dg/pr111407.c b/gcc/testsuite/gcc.dg/pr111407.c
new file mode 100644
index 000..a171074753f
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr111407.c
@@ -0,0 +1,21 @@
+/* PR tree-optimization/111407*/
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+enum { SEND_TOFILE } __sigsetjmp();
+void fclose();
+void foldergets();
+void sendpart_stats(int *p1, int a1, int b1) {
+ int *a = p1;
+ fclose();
+ p1 = 0;
+ long t = b1;
+ if (__sigsetjmp()) {
+   {
+ long t1 = a1;
+ a1+=1;
+ fclose(a1*(long)t1);
+   }
+ }
+ if (p1)
+   fclose();
+}
diff --git a/gcc/tree-ssa-math-opts.cc b/gcc/tree-ssa-math-opts.cc
index 3db69ad5733..51c14d6bad9 100644
--- a/gcc/tree-ssa-math-opts.cc
+++ b/gcc/tree-ssa-math-opts.cc
@@ -2755,6 +2755,14 @@ convert_mult_to_widen (gimple *stmt, 
gimple_stmt_iterator *gsi)
   if (!is_widening_mult_p (stmt, &type1, &rhs1, &type2, &rhs2))
 return false;
 
+  /* if any one of rhs1 and rhs2 is subject to abnormal coalescing,
+ avoid the tranform. */
+  if ((TREE_CODE (rhs1) == SSA_NAME
+   && SSA_NAME_OCCURS_IN_ABNORMAL_PHI (rhs1))
+  || (TREE_CODE (rhs2) == SSA_NAME
+ && SSA_NAME_OCCURS_IN_ABNORMAL_PHI (rhs2)))
+return false;
+
   to_mode = SCALAR_INT_TYPE_MODE (type);
   from_mode = SCALAR_INT_TYPE_MODE (type1);
   if (to_mode == from_mode)
-- 
2.31.1

[committed] libstdc++: Remove some more unconditional uses of atomics

[Jonathan Wakely via Gcc-patches]

Tested aarch64-linux. Pushed to trunk.

-- >8 --

These atomics cause linker errors on arm4t where __sync_synchronize is
not defined. For single-threaded targets we don't need the atomics.

libstdc++-v3/ChangeLog:

* include/experimental/io_context (io_context) [!_GLIBCXX_HAS_GTHREADS]:
Use a plain integer for _M_work_count for single-threaded
targets.
* include/experimental/memory_resource (__get_default_resource)
[!_GLIBCXX_HAS_GTHREADS]: Use unsynchronized type for
single-threaded targets.
* src/c++17/default_resource.h: Adjust preprocessor conditions
to match memory_resource.cc.
* src/c++17/memory_resource.cc [!_GLIBCXX_HAS_GTHREADS]
(atomic_mem_res): Use unsynchronized type for single-threaded
targets.
---
 libstdc++-v3/include/experimental/io_context  |  4 ++
 .../include/experimental/memory_resource  | 12 -
 libstdc++-v3/src/c++17/default_resource.h |  6 ++-
 libstdc++-v3/src/c++17/memory_resource.cc | 49 ++-
 4 files changed, 45 insertions(+), 26 deletions(-)

diff --git a/libstdc++-v3/include/experimental/io_context 
b/libstdc++-v3/include/experimental/io_context
index c59f8c8e73b..c878d5a7025 100644
--- a/libstdc++-v3/include/experimental/io_context
+++ b/libstdc++-v3/include/experimental/io_context
@@ -562,7 +562,11 @@ inline namespace v1
}
   };
 
+#ifdef _GLIBCXX_HAS_GTHREADS
 atomic _M_work_count;
+#else
+count_type _M_work_count;
+#endif
 mutable execution_context::mutex_type  _M_mtx;
 queue>_M_op;
 bool   _M_stopped = false;
diff --git a/libstdc++-v3/include/experimental/memory_resource 
b/libstdc++-v3/include/experimental/memory_resource
index 9f1cb42373e..6f419a0a929 100644
--- a/libstdc++-v3/include/experimental/memory_resource
+++ b/libstdc++-v3/include/experimental/memory_resource
@@ -549,10 +549,20 @@ namespace pmr {
   // The default memory resource
 
   /// @cond undocumented
-  inline std::atomic&
+  inline auto&
   __get_default_resource()
   {
+#ifndef _GLIBCXX_HAS_GTHREADS
+struct type {
+  using value_type = memory_resource*;
+  explicit type(value_type __r) : _M_r(__r) { }
+  value_type _M_r;
+  value_type load() const { return _M_r; }
+  value_type exchange(value_type __r) { return std::__exchange(_M_r, __r); 
}
+};
+#else
 using type = atomic;
+#endif
 alignas(type) static unsigned char __buf[sizeof(type)];
 static type* __r = new(__buf) type(new_delete_resource());
 return *__r;
diff --git a/libstdc++-v3/src/c++17/default_resource.h 
b/libstdc++-v3/src/c++17/default_resource.h
index 522cee13b90..f8d03d7d3bc 100644
--- a/libstdc++-v3/src/c++17/default_resource.h
+++ b/libstdc++-v3/src/c++17/default_resource.h
@@ -2,7 +2,11 @@
 // to suppress the warning caused by using a reserved init_priority.
 #pragma GCC system_header
 
-#if ATOMIC_POINTER_LOCK_FREE == 2 || defined(__GTHREAD_MUTEX_INIT)
+#ifndef _GLIBCXX_HAS_GTHREADS
+# error "This file should not be included for this build"
+#elif ATOMIC_POINTER_LOCK_FREE == 2
+# error "This file should not be included for this build"
+#elif defined __GTHREAD_MUTEX_INIT
 # error "This file should not be included for this build"
 #endif
 
diff --git a/libstdc++-v3/src/c++17/memory_resource.cc 
b/libstdc++-v3/src/c++17/memory_resource.cc
index c0c7cf0cf83..63856eadaf5 100644
--- a/libstdc++-v3/src/c++17/memory_resource.cc
+++ b/libstdc++-v3/src/c++17/memory_resource.cc
@@ -27,9 +27,9 @@
 #include 
 #include  // has_single_bit, bit_ceil, bit_width
 #include 
+#include  // std::__exchange
 #if ATOMIC_POINTER_LOCK_FREE != 2
 # include// std::mutex, std::lock_guard
-# include // std::__exchange
 #endif
 
 #if __has_cpp_attribute(clang::require_constant_initialization)
@@ -94,10 +94,31 @@ namespace pmr
 
 __constinit constant_init newdel_res{};
 __constinit constant_init null_res{};
-#if ATOMIC_POINTER_LOCK_FREE == 2
+
+#ifndef _GLIBCXX_HAS_GTHREADS
+# define _GLIBCXX_ATOMIC_MEM_RES_CAN_BE_CONSTANT_INITIALIZED
+// Single-threaded, no need for synchronization
+struct atomic_mem_res
+{
+  constexpr
+  atomic_mem_res(memory_resource* r) : val(r) { }
+
+  memory_resource* val;
+
+  memory_resource* load(std::memory_order) const
+  {
+   return val;
+  }
+
+  memory_resource* exchange(memory_resource* r, std::memory_order)
+  {
+   return std::__exchange(val, r);
+  }
+};
+#elif ATOMIC_POINTER_LOCK_FREE == 2
 using atomic_mem_res = atomic;
 # define _GLIBCXX_ATOMIC_MEM_RES_CAN_BE_CONSTANT_INITIALIZED
-#elif defined(_GLIBCXX_HAS_GTHREADS)
+#else
 // Can't use pointer-width atomics, define a type using a mutex instead:
 struct atomic_mem_res
 {
@@ -123,27 +144,7 @@ namespace pmr
return std::__exchange(val, r);
   }
 };
-#else
-# define _GLIBCX

[committed] libstdc++: Support dg-additional-files in tests

[Jonathan Wakely via Gcc-patches]

Tested aarch64-linux. Pushed to trunk.

The text files that these tests use are all identical. Now that each
test starts with a fresh copy of the file it needs, there's no reason to
have different files for each test, so we could remove the duplicates
and change the tests to use the same file name. There are several other
duplicate files in the testsuite/data directory, so they could all be
de-duped later after migrating all tests to dg-additional-files.

-- >8 --

Some tests rely on text files with specific content being present in the
test directory.  This has historically been done by copying
testsuite/data/*.tst and testsuite/data/*.txt to the test dir at the
start, in the libstdc++_init procedure.  Some tests modify their data
files, so if the same test runs more than once in the same directory the
second and subsequent tests will see the modified files, and FAIL
because the content of the file is not in the expected state.

This change adds support for the dg-additional-files directive from the
main compiler testsuite and changes v3_target_compile to copy the
specified files to the directory where the test will run.  This ensures
that a fresh copy of the files is present each time the test runs.

Eventually all tests could be transitioned to use dg-additional-files
and then libstdc++_init could be changed to remove the initial copy of
all files.  This change only adds dg-additional-files to the tests that
modify their files and FAIL when re-run in the same directory.

The tests that rely on additional data files have comments containing
the strings "@require@" and "@diff@" which seem to be related to the
libstdc++-v3/mkcheck.in testing script that was removed in 2003.  Those
comments can be used to find tests that should be migrated to use the
new dg-additional-files support, and then the comments can be removed.

libstdc++-v3/ChangeLog:

* testsuite/27_io/basic_filebuf/seekoff/char/1-io.cc: Use
dg-additional-files. Remove @require@ and @diff@ comments.
* testsuite/27_io/basic_filebuf/seekoff/char/2-io.cc: Likewise.
* testsuite/27_io/basic_filebuf/seekpos/char/1-io.cc: Likewise.
* testsuite/27_io/basic_filebuf/seekpos/char/2-io.cc: Likewise.
* testsuite/lib/dg-options.exp (v3_additional_files): New
global variable.
(dg-additional-files): New proc.
* testsuite/lib/libstdc++.exp (v3_target_compile): Copy
additional files to test directory.
---
 .../testsuite/27_io/basic_filebuf/seekoff/char/1-io.cc   | 4 +---
 .../testsuite/27_io/basic_filebuf/seekoff/char/2-io.cc   | 4 +---
 .../testsuite/27_io/basic_filebuf/seekpos/char/1-io.cc   | 4 +---
 .../testsuite/27_io/basic_filebuf/seekpos/char/2-io.cc   | 4 +---
 libstdc++-v3/testsuite/lib/dg-options.exp| 8 
 libstdc++-v3/testsuite/lib/libstdc++.exp | 9 -
 6 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/libstdc++-v3/testsuite/27_io/basic_filebuf/seekoff/char/1-io.cc 
b/libstdc++-v3/testsuite/27_io/basic_filebuf/seekoff/char/1-io.cc
index c812c528f26..5afa33e596e 100644
--- a/libstdc++-v3/testsuite/27_io/basic_filebuf/seekoff/char/1-io.cc
+++ b/libstdc++-v3/testsuite/27_io/basic_filebuf/seekoff/char/1-io.cc
@@ -21,14 +21,12 @@
 
 // { dg-require-fileio "" }
 // { dg-require-binary-io "" }
+// { dg-additional-files "seekoff-1io.tst" }
 
 #include 
 #include 
 #include 
 
-// @require@ %-*.tst %-*.txt
-// @diff@ %-*.tst %*.txt
-
 const char name_01[] = "seekoff-1io.tst";
 
 void test05() 
diff --git a/libstdc++-v3/testsuite/27_io/basic_filebuf/seekoff/char/2-io.cc 
b/libstdc++-v3/testsuite/27_io/basic_filebuf/seekoff/char/2-io.cc
index 4cfaf68c74e..cd3f765d236 100644
--- a/libstdc++-v3/testsuite/27_io/basic_filebuf/seekoff/char/2-io.cc
+++ b/libstdc++-v3/testsuite/27_io/basic_filebuf/seekoff/char/2-io.cc
@@ -21,14 +21,12 @@
 
 // { dg-require-fileio "" }
 // { dg-require-binary-io "" }
+// { dg-additional-files "seekoff-2io.tst" }
 
 #include 
 #include 
 #include 
 
-// @require@ %-*.tst %-*.txt
-// @diff@ %-*.tst %*.txt
-
 const char name_01[] = "seekoff-2io.tst";
 
 void test05() 
diff --git a/libstdc++-v3/testsuite/27_io/basic_filebuf/seekpos/char/1-io.cc 
b/libstdc++-v3/testsuite/27_io/basic_filebuf/seekpos/char/1-io.cc
index 57eabe38214..4566ebd27d9 100644
--- a/libstdc++-v3/testsuite/27_io/basic_filebuf/seekpos/char/1-io.cc
+++ b/libstdc++-v3/testsuite/27_io/basic_filebuf/seekpos/char/1-io.cc
@@ -20,14 +20,12 @@
 // 27.8.1.4 Overridden virtual functions
 
 // { dg-require-fileio "" }
+// { dg-additional-files "seekpos-1io.tst" }
 
 #include 
 #include 
 #include 
 
-// @require@ %-*.tst %-*.txt
-// @diff@ %-*.tst %*.txt
-
 const char name_01[] = "seekpos-1io.tst"; // file with data in it
 
 void test05() 
diff --git a/libstdc++-v3/testsuite/27_io/basic_filebuf/seekpos/char/2-io.cc 
b/libstdc++-v3/testsuite/27_io/basic_filebuf/seekpos/char/2-io.cc
index 714c3d60d2c..8500dd59df8 100644
--- a/libstdc++-v3/testsuite

[committed] libstdc++: Add testcase for std::make_integer_sequence bug [PR111357]

[Jonathan Wakely via Gcc-patches]

Tested aarch64-linux. Pushed to trunk.

I'll backport the test and a library workaround to the release branches.

-- >8 --

The compiler bug has been fixed on trunk, but this adds a regression test
for the library component.

libstdc++-v3/ChangeLog:

PR c++/111357
* testsuite/20_util/integer_sequence/pr111357.cc: New test.
---
 .../20_util/integer_sequence/pr111357.cc  | 34 +++
 1 file changed, 34 insertions(+)
 create mode 100644 libstdc++-v3/testsuite/20_util/integer_sequence/pr111357.cc

diff --git a/libstdc++-v3/testsuite/20_util/integer_sequence/pr111357.cc 
b/libstdc++-v3/testsuite/20_util/integer_sequence/pr111357.cc
new file mode 100644
index 000..1ad06b732af
--- /dev/null
+++ b/libstdc++-v3/testsuite/20_util/integer_sequence/pr111357.cc
@@ -0,0 +1,34 @@
+// { dg-do compile { target c++14 } }
+
+// PR c++/111357 - __integer_pack fails to work with values of dependent type
+// convertible to integers in noexcept context
+
+#include 
+
+using std::integer_sequence;
+using std::make_integer_sequence;
+
+template
+void g(integer_sequence)
+{}
+
+template
+struct c1
+{
+  static constexpr int value = 1;
+  constexpr operator int() { return value; }
+};
+
+template
+struct R
+{
+  using S = make_integer_sequence{}>;
+
+  R() noexcept(noexcept(g(S( // { dg-bogus "argument to .__integer_pack." }
+  {}
+};
+
+int main()
+{
+  R();
+}
-- 
2.41.0

Re: [PATCHSET] Reintroduce targetrustm hooks

[Arthur Cohen]

On 9/14/23 12:12, Richard Biener wrote:

On Wed, Sep 13, 2023 at 10:14 PM Iain Buclaw via Gcc-patches
 wrote:


Excerpts from Arthur Cohen's message of September 7, 2023 3:41 pm:

Alright, was not expecting to mess up this patchset so bad so here we go:

This patchset reintroduces proper targetrustm hooks without the old
problematic mess of macros we had, which had been removed for the first
merge of gccrs upstream.

Tested on x86-64 GNU Linux, and has also been present in our development
repository for a long time - added by this pull-request from Iain [1]
which was merged in October 2022.

Ok for trunk?

[PATCH 01/14] rust: Add skeleton support and documentation for
[PATCH 02/14] rust: Reintroduce TARGET_RUST_CPU_INFO hook
[PATCH 03/14] rust: Reintroduce TARGET_RUST_OS_INFO hook
[PATCH 04/14] rust: Implement TARGET_RUST_CPU_INFO for i[34567]86-*-*
[PATCH 05/14] rust: Implement TARGET_RUST_OS_INFO for *-*-darwin*
[PATCH 06/14] rust: Implement TARGET_RUST_OS_INFO for *-*-freebsd*
[PATCH 07/14] rust: Implement TARGET_RUST_OS_INFO for *-*-netbsd*
[PATCH 08/14] rust: Implement TARGET_RUST_OS_INFO for *-*-openbsd*
[PATCH 09/14] rust: Implement TARGET_RUST_OS_INFO for *-*-solaris2*.
[PATCH 10/14] rust: Implement TARGET_RUST_OS_INFO for *-*-dragonfly*
[PATCH 11/14] rust: Implement TARGET_RUST_OS_INFO for *-*-vxworks*
[PATCH 12/14] rust: Implement TARGET_RUST_OS_INFO for *-*-fuchsia*.
[PATCH 13/14] rust: Implement TARGET_RUST_OS_INFO for
[PATCH 14/14] rust: Implement TARGET_RUST_OS_INFO for *-*-*linux*.



Thanks for eventually getting round to this.

As the co-author of this patch series, I'm not going to look at it.

FWIW, these being Rust-specific target changes isolated to just
Rust-specific files, you should have the automony to commit without
needing any request for review - at least this is my understanding when
have made D-specific target changes in the past that have not touched
common back-end headers.


Yes, the reason I sent them in is that they still touch common GCC 
folders even if the changes are Rust specific - so I did not want to 
overuse my write rights.



I'll let someone else confirm and check over the shared parts touched by
the patch however.


I confirm.  I briefly went over the shared parts and they look OK.


Thanks for the review Richard! And thank you Iain for the patches.

I will commit them upstream tomorrow.

All the best,

Arthur


Thanks,
Richard.


For reviewers, this is pretty much a mirror of the D front-end's CPU and
OS-specific target hooks (D has built-in version identifiers, not
built-in attributes, but both Rust and D are otherwise the same in the
kind of information exposed by them).


[1]: https://github.com/Rust-GCC/gccrs/pull/1543



The other GitHub pull request that added these is here.

https://github.com/Rust-GCC/gccrs/pull/1596

Regards,
Iain.

Question on -fwrapv and -fwrapv-pointer

[Qing Zhao via Gcc-patches]

Hi,

I have several questions on these options:

1.are pointers treated as signed integers in general? (I thought that pointers 
are addresses to the memory, should be treated as unsigned integer…)
2. If Yes, why? 
3. why a separate option for pointesr -fwrapv-pointer in addition to -fwrapv if 
they are treated as signed integers?

Thanks for your help.

Qing

Re: Question on -fwrapv and -fwrapv-pointer

[Richard Biener via Gcc-patches]

On Thu, Sep 14, 2023 at 3:42 PM Qing Zhao via Gcc-patches
 wrote:
>
> Hi,
>
> I have several questions on these options:
>
> 1.are pointers treated as signed integers in general? (I thought that 
> pointers are addresses to the memory, should be treated as unsigned integer…)
> 2. If Yes, why?
> 3. why a separate option for pointesr -fwrapv-pointer in addition to -fwrapv 
> if they are treated as signed integers?

Pointers are unsigned, they might sign-extend to Pmode though.
-fwrapv-pointer is to enable wrapping over zero,
we don't have many places using this, ISTR kernel folks requested to
disable specific folding - digging in history
might reveal the case/PR.

Richard.

> Thanks for your help.
>
> Qing
>

Re: [PATCH 1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode

[钟居哲]

Thanks for cleaning up.
LGTM.



juzhe.zh...@rivai.ai
 
From: Lehua Ding
Date: 2023-09-13 20:31
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH 1/2] RISC-V: Cleanup redundant reduction patterns after 
refactor vector mode
This patch cleanups redundant reduction patterns after Juzhe change vector mode
from fixed-size to scalable-size. For example, whether it is zvl32b, zvl64b,
zvl128b, RVVM1SI indicates that it occupies a vector register. Therefore, it is
easy to map vector modes to LMUL1 vector modes with define_mode_attr without
creating a separate pattern for each LMUL1 Mode. For example, this patch can
combine four patterns (@pred_reduc_,
@pred_reduc_
@pred_reduc_,
@pred_reduc_) to a single pattern
@pred_reduc_.
 
gcc/ChangeLog:
 
* config/riscv/riscv-v.cc (expand_reduction): Adjust call.
* config/riscv/riscv-vector-builtins-bases.cc: Adjust call.
* config/riscv/vector-iterators.md: New iterators and attrs.
* config/riscv/vector.md (@pred_reduc_):
Removed.
(@pred_reduc_): Removed.
(@pred_reduc_): Removed.
(@pred_reduc_): Removed.
(@pred_reduc_): Added.
(@pred_widen_reduc_plus): Removed.
(@pred_widen_reduc_plus): Removed.
(@pred_widen_reduc_plus): Added.
(@pred_widen_reduc_plus): Removed.
(@pred_reduc_): Removed.
(@pred_reduc_): Removed.
(@pred_reduc_): Removed.
(@pred_reduc_plus): Removed.
(@pred_reduc_plus): Removed.
(@pred_reduc_plus): Added.
(@pred_reduc_plus): Removed.
(@pred_widen_reduc_plus): Removed.
(@pred_widen_reduc_plus): Removed.
(@pred_widen_reduc_plus): Added.
 
---
gcc/config/riscv/riscv-v.cc   |   4 +-
.../riscv/riscv-vector-builtins-bases.cc  |  15 +-
gcc/config/riscv/vector-iterators.md  |  47 ++-
gcc/config/riscv/vector.md| 369 +++---
4 files changed, 101 insertions(+), 334 deletions(-)
 
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 76e6094f45b..68b36d9dc4f 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -3230,7 +3230,7 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, 
reduction_type type)
= code_for_pred_reduc_plus (type == reduction_type::UNORDERED
  ? UNSPEC_UNORDERED
  : UNSPEC_ORDERED,
- vmode, m1_mode);
+ vmode);
   if (type == reduction_type::MASK_LEN_FOLD_LEFT)
{
  rtx mask = ops[3];
@@ -3243,7 +3243,7 @@ expand_reduction (rtx_code code, rtx *ops, rtx init, 
reduction_type type)
 }
   else
 {
-  insn_code icode = code_for_pred_reduc (code, vmode, m1_mode);
+  insn_code icode = code_for_pred_reduc (code, vmode);
   emit_vlmax_insn (icode, REDUCE_OP, reduc_ops);
 }
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index ee218a03017..c54ea6f0560 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1541,8 +1541,7 @@ public:
   rtx expand (function_expander &e) const override
   {
-return e.use_exact_insn (
-  code_for_pred_reduc (CODE, e.vector_mode (), e.ret_mode ()));
+return e.use_exact_insn (code_for_pred_reduc (CODE, e.vector_mode ()));
   }
};
@@ -1555,9 +1554,8 @@ public:
   rtx expand (function_expander &e) const override
   {
-return e.use_exact_insn (code_for_pred_widen_reduc_plus (UNSPEC,
-  e.vector_mode (),
-  e.ret_mode ()));
+return e.use_exact_insn (
+  code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ()));
   }
};
@@ -1576,7 +1574,7 @@ public:
   rtx expand (function_expander &e) const override
   {
 return e.use_exact_insn (
-  code_for_pred_reduc_plus (UNSPEC, e.vector_mode (), e.ret_mode ()));
+  code_for_pred_reduc_plus (UNSPEC, e.vector_mode ()));
   }
};
@@ -1594,9 +1592,8 @@ public:
   rtx expand (function_expander &e) const override
   {
-return e.use_exact_insn (code_for_pred_widen_reduc_plus (UNSPEC,
-  e.vector_mode (),
-  e.ret_mode ()));
+return e.use_exact_insn (
+  code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ()));
   }
};
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index e70a9bc5c74..deb89cbcedc 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -671,6 +671,15 @@
   RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
])
+(define_mode_iterator VF_HS [
+  (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH")
+  (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH")
+  (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
+
+  (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") 
(RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
+  (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && 
TARGET_MIN_VLEN > 32")
+])
+
(define_mode_iterator V_VLSI_QHS [
   RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN 
> 32")
@@ -1237,32 +1246,32 @@
   (RVVM2DF "TARGET_VECTOR_

Re: [PATCH 2/2] RISC-V: Refactor vector reduction patterns

[钟居哲]

LGTM. 
It's obvious you fixed my previous redundant codes.
Thanks.



juzhe.zh...@rivai.ai
 
From: Lehua Ding
Date: 2023-09-13 20:31
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH 2/2] RISC-V: Refactor vector reduction patterns
This patch adjust reduction patterns struct, change it from:
   (any_reduc:VI
 (vec_duplicate:VI
   (vec_select:
 (match_operand: 4 "register_operand"  "   vr,   
vr")
 (parallel [(const_int 0)])))
 (match_operand:VI   3 "register_operand"  "   vr,   
vr"))
to:
   (unspec: [
 (match_operand:VI3 "register_operand"  "   vr,   
vr")
 (match_operand: 4 "register_operand"  "   vr,   
vr")
   ] ANY_REDUC)
 
The reason for the change is that the semantics of the previous pattern is 
incorrect.
GCC does not have a standard rtx code to express the reduction calculation 
process.
It makes more sense to use UNSPEC.
 
Further, all reduction icode are geted by the UNSPEC and MODE (code_for_pred 
(unspec, mode)),
so that all reduction patterns can have a uniform icode name. After this 
adjust, widen_reducop
and widen_freducop are redundant.
 
gcc/ChangeLog:
 
* config/riscv/autovec.md: Change rtx code to unspec.
* config/riscv/riscv-protos.h (expand_reduction): Change prototype.
* config/riscv/riscv-v.cc (expand_reduction): Change prototype.
* config/riscv/riscv-vector-builtins-bases.cc (class widen_reducop):
Removed.
(class widen_freducop): Removed.
* config/riscv/vector-iterators.md (minu): Add reduc unspec, iterators, attrs.
* config/riscv/vector.md (@pred_reduc_): Change name.
(@pred_): New name.
(@pred_widen_reduc_plus): Change name.
(@pred_reduc_plus): Change name.
(@pred_widen_reduc_plus): Change name.
 
---
gcc/config/riscv/autovec.md   |  27 ++--
gcc/config/riscv/riscv-protos.h   |   2 +-
gcc/config/riscv/riscv-v.cc   |  13 +-
.../riscv/riscv-vector-builtins-bases.cc  |  82 
gcc/config/riscv/vector-iterators.md  |  62 +++--
gcc/config/riscv/vector.md| 118 +-
6 files changed, 152 insertions(+), 152 deletions(-)
 
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 4a6b8f8c939..16ac125f53f 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2091,7 +2091,7 @@
(match_operand:VI 1 "register_operand")]
   "TARGET_VECTOR"
{
-  riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands, CONST0_RTX 
(mode));
   DONE;
})
@@ -2102,7 +2102,7 @@
{
   int prec = GET_MODE_PRECISION (mode);
   rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED), mode);
-  riscv_vector::expand_reduction (SMAX, operands, min);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, min);
   DONE;
})
@@ -2111,7 +2111,7 @@
(match_operand:VI 1 "register_operand")]
   "TARGET_VECTOR"
{
-  riscv_vector::expand_reduction (UMAX, operands, CONST0_RTX (mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, operands, CONST0_RTX 
(mode));
   DONE;
})
@@ -2122,7 +2122,7 @@
{
   int prec = GET_MODE_PRECISION (mode);
   rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED), mode);
-  riscv_vector::expand_reduction (SMIN, operands, max);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, max);
   DONE;
})
@@ -2133,7 +2133,7 @@
{
   int prec = GET_MODE_PRECISION (mode);
   rtx max = immed_wide_int_const (wi::max_value (prec, UNSIGNED), mode);
-  riscv_vector::expand_reduction (UMIN, operands, max);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, operands, max);
   DONE;
})
@@ -2142,7 +2142,7 @@
(match_operand:VI 1 "register_operand")]
   "TARGET_VECTOR"
{
-  riscv_vector::expand_reduction (AND, operands, CONSTM1_RTX (mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_AND, operands, CONSTM1_RTX 
(mode));
   DONE;
})
@@ -2151,7 +2151,7 @@
(match_operand:VI 1 "register_operand")]
   "TARGET_VECTOR"
{
-  riscv_vector::expand_reduction (IOR, operands, CONST0_RTX (mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_OR, operands, CONST0_RTX 
(mode));
   DONE;
})
@@ -2160,7 +2160,7 @@
(match_operand:VI 1 "register_operand")]
   "TARGET_VECTOR"
{
-  riscv_vector::expand_reduction (XOR, operands, CONST0_RTX (mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_XOR, operands, CONST0_RTX 
(mode));
   DONE;
})
@@ -2178,7 +2178,8 @@
(match_operand:VF 1 "register_operand")]
   "TARGET_VECTOR"
{
-  riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_UNORDERED, operands,
+  CONST0_RTX (mode));
   DONE;
})
@@ -2190,7 +2191,7 @@
   REAL_VALUE_TYPE rv;
   real_inf (&rv, true);
   rtx f = const_double_from_real_value (rv, mode);
-  riscv_vect

[PATCH] libstdc++: Use C++20 constraints in

[Patrick Palka via Gcc-patches]

Tested on x86_64-pc-linux-gnu, does this look OK for trunk?

-- >8 --

By now it's probably safe to assume supported compilers have full
concepts support in C++20 mode.  And using a requires-clase instead
enable_if_t inside the return type greatly reduces the sizes of the
corresponding symbol names.

libstdc++-v3/ChangeLog:

* include/std/bit: Include .
(byteswap): Use a requires-clause instead of enable_if_t
inside the return type.
(_If_is_unsigned_integer): Replace with ...
(__unsigned_integer): ... this.
(rotl): Use a requires-clause instead of enable_if_t
inside the return type.
(countl_zero): Likewise.
(countl_one): Likewise.
(countr_zero): Likewise.
(countr_one): Likewise.
(popcount): Likewise.
(has_single_bit): Likewise.
(bit_ceil): Likewise.
(bit_floor): Likewise.
(bit_width): Likewise.
---
 libstdc++-v3/include/std/bit | 54 ++--
 1 file changed, 27 insertions(+), 27 deletions(-)

diff --git a/libstdc++-v3/include/std/bit b/libstdc++-v3/include/std/bit
index 987b6cdbb35..dce61b440c5 100644
--- a/libstdc++-v3/include/std/bit
+++ b/libstdc++-v3/include/std/bit
@@ -33,6 +33,7 @@
 
 #if __cplusplus >= 201402L
 
+#include  // for std::integral
 #include 
 
 #if _GLIBCXX_HOSTED || __has_include()
@@ -103,9 +104,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
* @return An object of the same type, with the bytes reversed.
* @since C++23
*/
-  template
+  template
 [[nodiscard]]
-constexpr enable_if_t::value, _Tp>
+constexpr _Tp
 byteswap(_Tp __value) noexcept
 {
   if constexpr (sizeof(_Tp) == 1)
@@ -378,54 +379,53 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
 #ifdef __cpp_lib_bitops // C++ >= 20
 
   /// @cond undocumented
-  template
-using _If_is_unsigned_integer
-  = enable_if_t<__is_unsigned_integer<_Tp>::value, _Up>;
+  template
+concept __unsigned_integer = __is_unsigned_integer<_Tp>::value;
   /// @endcond
 
   // [bit.rot], rotating
 
   /// Rotate `x` to the left by `s` bits.
-  template
-[[nodiscard]] constexpr _If_is_unsigned_integer<_Tp>
+  template<__unsigned_integer _Tp>
+[[nodiscard]] constexpr _Tp
 rotl(_Tp __x, int __s) noexcept
 { return std::__rotl(__x, __s); }
 
   /// Rotate `x` to the right by `s` bits.
-  template
-[[nodiscard]] constexpr _If_is_unsigned_integer<_Tp>
+  template<__unsigned_integer _Tp>
+[[nodiscard]] constexpr _Tp
 rotr(_Tp __x, int __s) noexcept
 { return std::__rotr(__x, __s); }
 
   // [bit.count], counting
 
   /// The number of contiguous zero bits, starting from the highest bit.
-  template
-constexpr _If_is_unsigned_integer<_Tp, int>
+  template<__unsigned_integer _Tp>
+constexpr int
 countl_zero(_Tp __x) noexcept
 { return std::__countl_zero(__x); }
 
   /// The number of contiguous one bits, starting from the highest bit.
-  template
-constexpr _If_is_unsigned_integer<_Tp, int>
+  template<__unsigned_integer _Tp>
+constexpr int
 countl_one(_Tp __x) noexcept
 { return std::__countl_one(__x); }
 
   /// The number of contiguous zero bits, starting from the lowest bit.
-  template
-constexpr _If_is_unsigned_integer<_Tp, int>
+  template<__unsigned_integer _Tp>
+constexpr int
 countr_zero(_Tp __x) noexcept
 { return std::__countr_zero(__x); }
 
   /// The number of contiguous one bits, starting from the lowest bit.
-  template
-constexpr _If_is_unsigned_integer<_Tp, int>
+  template<__unsigned_integer _Tp>
+constexpr int
 countr_one(_Tp __x) noexcept
 { return std::__countr_one(__x); }
 
   /// The number of bits set in `x`.
-  template
-constexpr _If_is_unsigned_integer<_Tp, int>
+  template<__unsigned_integer _Tp>
+constexpr int
 popcount(_Tp __x) noexcept
 { return std::__popcount(__x); }
 #endif // __cpp_lib_bitops
@@ -434,28 +434,28 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
   // [bit.pow.two], integral powers of 2
 
   /// True if `x` is a power of two, false otherwise.
-  template
-constexpr _If_is_unsigned_integer<_Tp, bool>
+  template<__unsigned_integer _Tp>
+constexpr bool
 has_single_bit(_Tp __x) noexcept
 { return std::__has_single_bit(__x); }
 
   /// The smallest power-of-two not less than `x`.
-  template
-constexpr _If_is_unsigned_integer<_Tp>
+  template<__unsigned_integer _Tp>
+constexpr _Tp
 bit_ceil(_Tp __x) noexcept
 { return std::__bit_ceil(__x); }
 
   /// The largest power-of-two not greater than `x`.
-  template
-constexpr _If_is_unsigned_integer<_Tp>
+  template<__unsigned_integer _Tp>
+constexpr _Tp
 bit_floor(_Tp __x) noexcept
 { return std::__bit_floor(__x); }
 
   // _GLIBCXX_RESOLVE_LIB_DEFECTS
   // 3656. Inconsistent bit operations returning a count
   /// The smallest integer greater than the base-2 logarithm of `x`.
-  template
-constexpr _If_is_unsigned_integer<_Tp, int>
+  te

Re: [PATCH] RISC-V: Support VLS modes mask operations

[Kito Cheng via Gcc-patches]

LGTM

Juzhe-Zhong  於 2023年9月14日 週四 20:44 寫道：

> This patch support mask operations (comparison and logical).
>
> This patch reduce these FAILs of "vect" testsuite:
> FAIL: gcc.dg/vect/vect-bic-bitmask-12.c -flto -ffat-lto-objects
> scan-tree-dump dce7 "<=\\s*.+{ 255,.+}"
> FAIL: gcc.dg/vect/vect-bic-bitmask-12.c scan-tree-dump dce7 "<=\\s*.+{
> 255,.+}"
> FAIL: gcc.dg/vect/vect-bic-bitmask-23.c -flto -ffat-lto-objects
> scan-tree-dump dce7 "<=\\s*.+{ 255, 15, 1, 65535 }"
> FAIL: gcc.dg/vect/vect-bic-bitmask-23.c scan-tree-dump dce7 "<=\\s*.+{
> 255, 15, 1, 65535 }"
>
> Full regression passed (with reducing 4 FAILs).
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Add VLS mask modes.
> * config/riscv/autovec.md (@vcond_mask_): Remove @.
> (vcond_mask_): Add VLS mask modes.
> * config/riscv/vector.md: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS tests.
> * gcc.target/riscv/rvv/autovec/vls/cmp-1.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-2.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-3.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-4.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-5.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-6.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/mask-1.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/mask-2.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/mask-3.c: New test.
>
> ---
>  gcc/config/riscv/autovec-opt.md   |  18 +--
>  gcc/config/riscv/autovec.md   |  32 +++---
>  gcc/config/riscv/vector.md|  60 +-
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-1.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-2.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-3.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-4.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-5.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-6.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/def.h|   9 ++
>  .../gcc.target/riscv/rvv/autovec/vls/mask-1.c |  69 
>  .../gcc.target/riscv/rvv/autovec/vls/mask-2.c |  69 
>  .../gcc.target/riscv/rvv/autovec/vls/mask-3.c |  69 
>  13 files changed, 907 insertions(+), 55 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-5.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-6.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-3.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md
> b/gcc/config/riscv/autovec-opt.md
> index e26c01856ff..22ab8afc994 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -67,10 +67,10 @@
>  ;;
> -
>
>  (define_insn_and_split "*not"
> -  [(set (match_operand:VB 0 "register_operand"   "=vr")
> -   (bitmanip_bitwise:VB
> - (not:VB (match_operand:VB 2 "register_operand" " vr"))
> - (match_operand:VB 1 "register_operand" " vr")))]
> +  [(set (match_operand:VB_VLS 0 "register_operand"   "=vr")
> +   (bitmanip_bitwise:VB_VLS
> + (not:VB_VLS (match_operand:VB_VLS 2 "register_operand" " vr"))
> + (match_operand:VB_VLS 1 "register_operand" " vr")))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> @@ -93,11 +93,11 @@
>  ;;
> -
>
>  (define_insn_and_split "*n"
> -  [(set (match_operand:VB 0 "register_operand" "=vr")
> -   (not:VB
> - (any_bitwise:VB
> -   (match_operand:VB 1 "register_operand" " vr")
> -   (match_operand:VB 2 "register_operand" " vr"]
> +  [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
> +   (not:VB_VLS
> + (any_bitwise:VB_VLS
> +   (match_operand:VB_VLS 1 "register_operand" " vr")
> +   (match_operand:VB_VLS 2 "register_operand" " vr"]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 7121bab1716..d2002a8ee26 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -495,9 +495,9 @@
>  ;;
> ---

[PATCH] Harmonize headers between both dg-extract-results scripts

[Paul Iannetta via Gcc-patches]

Hi,

This is a small patch so that both dg-extract-results.py and
dg-extract-results.sh share the same header.  In particular, it fixes
the fact that the regexp r'^Test Run By (\S+) on (.*)$' was never
matched in the python file.

Thanks,
--
Paul
Kalray


Author: Paul Iannetta 
Date:   Thu Sep 14 15:43:58 2023 +0200

Harmonize headers between both dg-extract-results scripts

The header of the python version looked like:
Target is ...
Host   is ...
The header of the bash version looked like:
Test run by ... on ...
Target is ...

After this change both headers look like:
Test run by ... on ...
Target is ...
Host   is ...

The order of the tests is not the same but since dg-cmp-results.sh it
does not matter much.

contrib/ChangeLog:

2023-09-14  Paul Iannetta  

* dg-extract-results.py: Print the "Test run" line.
* dg-extract-results.sh: Print the "Host" line.

diff --git a/contrib/dg-extract-results.py b/contrib/dg-extract-results.py
index 30aa68771d4..34da1808c5f 100644
--- a/contrib/dg-extract-results.py
+++ b/contrib/dg-extract-results.py
@@ -113,7 +113,7 @@ class Prog:
 # Whether to create .sum rather than .log output.
 self.do_sum = True
 # Regexps used while parsing.
-self.test_run_re = re.compile (r'^Test Run By (\S+) on (.*)$')
+self.test_run_re = re.compile (r'^Test run by (\S+) on (.*)$')
 self.tool_re = re.compile (r'^\t\t=== (.*) tests ===$')
 self.result_re = re.compile (r'^(PASS|XPASS|FAIL|XFAIL|UNRESOLVED'
  r'|WARNING|ERROR|UNSUPPORTED|UNTESTED'
diff --git a/contrib/dg-extract-results.sh b/contrib/dg-extract-results.sh
index ff6c50d029c..57f6fe0e997 100755
--- a/contrib/dg-extract-results.sh
+++ b/contrib/dg-extract-results.sh
@@ -271,7 +271,7 @@ cat $SUM_FILES \
 
 # Write the begining of the combined summary file.
 
-head -n 2 $FIRST_SUM
+head -n 3 $FIRST_SUM
 echo
 echo " === $TOOL tests ==="
 echo

RE: [PATCH] RISC-V: Support VLS modes mask operations

[Li, Pan2 via Gcc-patches]

Committed, thanks Kito.

Pan

-Original Message-
From: Gcc-patches  On Behalf 
Of Kito Cheng via Gcc-patches
Sent: Thursday, September 14, 2023 10:23 PM
To: Juzhe-Zhong 
Cc: GCC Patches ; Kito Cheng ; 
Jeff Law ; Robin Dapp 
Subject: Re: [PATCH] RISC-V: Support VLS modes mask operations

LGTM

Juzhe-Zhong  於 2023年9月14日 週四 20:44 寫道：

> This patch support mask operations (comparison and logical).
>
> This patch reduce these FAILs of "vect" testsuite:
> FAIL: gcc.dg/vect/vect-bic-bitmask-12.c -flto -ffat-lto-objects
> scan-tree-dump dce7 "<=\\s*.+{ 255,.+}"
> FAIL: gcc.dg/vect/vect-bic-bitmask-12.c scan-tree-dump dce7 "<=\\s*.+{
> 255,.+}"
> FAIL: gcc.dg/vect/vect-bic-bitmask-23.c -flto -ffat-lto-objects
> scan-tree-dump dce7 "<=\\s*.+{ 255, 15, 1, 65535 }"
> FAIL: gcc.dg/vect/vect-bic-bitmask-23.c scan-tree-dump dce7 "<=\\s*.+{
> 255, 15, 1, 65535 }"
>
> Full regression passed (with reducing 4 FAILs).
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Add VLS mask modes.
> * config/riscv/autovec.md (@vcond_mask_): Remove @.
> (vcond_mask_): Add VLS mask modes.
> * config/riscv/vector.md: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/def.h: Add VLS tests.
> * gcc.target/riscv/rvv/autovec/vls/cmp-1.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-2.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-3.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-4.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-5.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/cmp-6.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/mask-1.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/mask-2.c: New test.
> * gcc.target/riscv/rvv/autovec/vls/mask-3.c: New test.
>
> ---
>  gcc/config/riscv/autovec-opt.md   |  18 +--
>  gcc/config/riscv/autovec.md   |  32 +++---
>  gcc/config/riscv/vector.md|  60 +-
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-1.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-2.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-3.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-4.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-5.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/cmp-6.c  | 106 ++
>  .../gcc.target/riscv/rvv/autovec/vls/def.h|   9 ++
>  .../gcc.target/riscv/rvv/autovec/vls/mask-1.c |  69 
>  .../gcc.target/riscv/rvv/autovec/vls/mask-2.c |  69 
>  .../gcc.target/riscv/rvv/autovec/vls/mask-3.c |  69 
>  13 files changed, 907 insertions(+), 55 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-5.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cmp-6.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mask-3.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md
> b/gcc/config/riscv/autovec-opt.md
> index e26c01856ff..22ab8afc994 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -67,10 +67,10 @@
>  ;;
> -
>
>  (define_insn_and_split "*not"
> -  [(set (match_operand:VB 0 "register_operand"   "=vr")
> -   (bitmanip_bitwise:VB
> - (not:VB (match_operand:VB 2 "register_operand" " vr"))
> - (match_operand:VB 1 "register_operand" " vr")))]
> +  [(set (match_operand:VB_VLS 0 "register_operand"   "=vr")
> +   (bitmanip_bitwise:VB_VLS
> + (not:VB_VLS (match_operand:VB_VLS 2 "register_operand" " vr"))
> + (match_operand:VB_VLS 1 "register_operand" " vr")))]
>"TARGET_VECTOR && can_create_pseudo_p ()"
>"#"
>"&& 1"
> @@ -93,11 +93,11 @@
>  ;;
> -
>
>  (define_insn_and_split "*n"
> -  [(set (match_operand:VB 0 "register_operand" "=vr")
> -   (not:VB
> - (any_bitwise:VB
> -   (match_operand:VB 1 "register_operand" " vr")
> -   (match_operand:VB 2 "register_operand" " vr"]
> +  [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
> +   (not:VB_VLS
> + (any_bitwise:VB_VLS
> +   (match_operand:VB_VLS 1 "register_operand" " vr")
> +   (match_operand:VB_VLS 2 "register_operand" " vr")))

[PATCH] aarch64: Restore SVE WHILE costing

[Richard Sandiford via Gcc-patches]

AArch64 previously costed WHILELO instructions on the first call
to add_stmt_cost.  This was because, at the time, only add_stmt_cost
had access to the loop_vec_info.

However, after the AVX512 changes, we only calculate the masks later.
This patch moves the WHILELO costing to finish_cost, which is in any
case a more logical place for it to be.  It also means that we can
check the final decision about whether to use predicated loops.

Tested on aarch64-linux-gnu & applied.

Richard


gcc/
* config/aarch64/aarch64.cc (aarch64_vector_costs::analyze_loop_info):
Move WHILELO handling to...
(aarch64_vector_costs::finish_cost): ...here.  Check whether the
vectorizer has decided to use a predicated loop.

gcc/testsuite/
* gcc.target/aarch64/sve/cost_model_15.c: New test.
---
 gcc/config/aarch64/aarch64.cc | 36 ++-
 .../gcc.target/aarch64/sve/cost_model_15.c| 13 +++
 2 files changed, 32 insertions(+), 17 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/cost_model_15.c

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 3739a44bfd9..0962fc4f56e 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -16310,22 +16310,6 @@ aarch64_vector_costs::analyze_loop_vinfo 
(loop_vec_info loop_vinfo)
   /* Detect whether we're vectorizing for SVE and should apply the unrolling
  heuristic described above m_unrolled_advsimd_niters.  */
   record_potential_advsimd_unrolling (loop_vinfo);
-
-  /* Record the issue information for any SVE WHILE instructions that the
- loop needs.  */
-  if (!m_ops.is_empty () && !LOOP_VINFO_MASKS (loop_vinfo).is_empty ())
-{
-  unsigned int num_masks = 0;
-  rgroup_controls *rgm;
-  unsigned int num_vectors_m1;
-  FOR_EACH_VEC_ELT (LOOP_VINFO_MASKS (loop_vinfo).rgc_vec,
-   num_vectors_m1, rgm)
-   if (rgm->type)
- num_masks += num_vectors_m1 + 1;
-  for (auto &ops : m_ops)
-   if (auto *issue = ops.sve_issue_info ())
- ops.pred_ops += num_masks * issue->while_pred_ops;
-}
 }
 
 /* Implement targetm.vectorize.builtin_vectorization_cost.  */
@@ -17507,9 +17491,27 @@ adjust_body_cost (loop_vec_info loop_vinfo,
 void
 aarch64_vector_costs::finish_cost (const vector_costs *uncast_scalar_costs)
 {
+  /* Record the issue information for any SVE WHILE instructions that the
+ loop needs.  */
+  loop_vec_info loop_vinfo = dyn_cast (m_vinfo);
+  if (!m_ops.is_empty ()
+  && loop_vinfo
+  && LOOP_VINFO_FULLY_MASKED_P (loop_vinfo))
+{
+  unsigned int num_masks = 0;
+  rgroup_controls *rgm;
+  unsigned int num_vectors_m1;
+  FOR_EACH_VEC_ELT (LOOP_VINFO_MASKS (loop_vinfo).rgc_vec,
+   num_vectors_m1, rgm)
+   if (rgm->type)
+ num_masks += num_vectors_m1 + 1;
+  for (auto &ops : m_ops)
+   if (auto *issue = ops.sve_issue_info ())
+ ops.pred_ops += num_masks * issue->while_pred_ops;
+}
+
   auto *scalar_costs
 = static_cast (uncast_scalar_costs);
-  loop_vec_info loop_vinfo = dyn_cast (m_vinfo);
   if (loop_vinfo
   && m_vec_flags
   && aarch64_use_new_vector_costs_p ())
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/cost_model_15.c 
b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_15.c
new file mode 100644
index 000..b9e6306bb59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/cost_model_15.c
@@ -0,0 +1,13 @@
+/* { dg-options "-Ofast -mtune=neoverse-v1" } */
+
+double f(double *restrict x, double *restrict y, int *restrict z)
+{
+  double res = 0.0;
+  for (int i = 0; i < 100; ++i)
+res += x[i] * y[z[i]];
+  return res;
+}
+
+/* { dg-final { scan-assembler-times {\tld1sw\tz[0-9]+\.d,} 1 } } */
+/* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d,} 2 } } */
+/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.d,} 1 } } */
-- 
2.25.1

Re: RFC: Introduce -fhardened to enable security-related flags

[Hongtao Liu via Gcc-patches]

On Wed, Aug 30, 2023 at 3:42 AM Marek Polacek via Gcc-patches
 wrote:
>
> Improving the security of software has been a major trend in the recent
> years.  Fortunately, GCC offers a wide variety of flags that enable extra
> hardening.  These flags aren't enabled by default, though.  And since
> there are a lot of hardening flags, with more to come, it's been difficult
> to keep on top of them; more so for the users of GCC who ought not to be
> expected to keep track of all the new options.
>
> To alleviate some of the problems I mentioned, we thought it would
> be useful to provide a new umbrella option that enables a reasonable set
> of hardening flags.  What's "reasonable" in this context is not easy to
> pin down.  Surely, there must be no ABI impact, the option cannot cause
> severe performance issues, and, I suspect, it should not cause build
> errors by enabling stricter compile-time errors (such as, -Wimplicit-int,
> -Wint-conversion).  Including a controversial option in -fhardened
> would likely cause that users would not use -fhardened at all.  It's
> roughly akin to -Wall or -O2 -- those also enable a reasonable set of
> options, and evolve over time, and are not kept in sync with other
> compilers.
>
> Currently, -fhardened enables:
>
>   -D_FORTIFY_SOURCE=3 (or =2 for older glibcs)
>   -D_GLIBCXX_ASSERTIONS
>   -ftrivial-auto-var-init=zero
>   -fPIE  -pie  -Wl,-z,relro,-z,now
>   -fstack-protector-strong
>   -fstack-clash-protection
>   -fcf-protection=full (x86 GNU/Linux only)
>
> -fsanitize=undefined is specifically not enabled.  -fstrict-flex-arrays is
> also liable to break a lot of code so I didn't include it.
>
> Appended is a proof-of-concept patch.  It doesn't implement --help=hardened
> yet.  A fairly crucial point is that -fhardened will not override options
> that were specified on the command line (before or after -fhardened).  For
> example,
>
>  -D_FORTIFY_SOURCE=1 -fhardened
>
> means that _FORTIFY_SOURCE=1 will be used.  Similarly,
>
>   -fhardened -fstack-protector
>
> will not enable -fstack-protector-strong.
>
> Thoughts?
>
> ---
>  gcc/c-family/c-opts.cc | 25 
>  gcc/common.opt |  4 +++
>  gcc/config/i386/i386-options.cc| 11 ++-
>  gcc/doc/invoke.texi| 29 +-
>  gcc/gcc.cc | 35 +-
>  gcc/opts.cc| 15 --
>  gcc/testsuite/c-c++-common/fhardened-1.S   |  6 
>  gcc/testsuite/c-c++-common/fhardened-1.c   | 18 +++
>  gcc/testsuite/c-c++-common/fhardened-10.c  | 10 +++
>  gcc/testsuite/c-c++-common/fhardened-2.c   | 12 
>  gcc/testsuite/c-c++-common/fhardened-3.c   | 12 
>  gcc/testsuite/c-c++-common/fhardened-5.c   | 11 +++
>  gcc/testsuite/c-c++-common/fhardened-6.c   | 11 +++
>  gcc/testsuite/c-c++-common/fhardened-7.c   |  7 +
>  gcc/testsuite/c-c++-common/fhardened-8.c   |  7 +
>  gcc/testsuite/c-c++-common/fhardened-9.c   |  6 
>  gcc/testsuite/gcc.misc-tests/help.exp  |  2 ++
>  gcc/testsuite/gcc.target/i386/cf_check-6.c | 12 
>  gcc/toplev.cc  |  6 
>  19 files changed, 233 insertions(+), 6 deletions(-)
>  create mode 100644 gcc/testsuite/c-c++-common/fhardened-1.S
>  create mode 100644 gcc/testsuite/c-c++-common/fhardened-1.c
>  create mode 100644 gcc/testsuite/c-c++-common/fhardened-10.c
>  create mode 100644 gcc/testsuite/c-c++-common/fhardened-2.c
>  create mode 100644 gcc/testsuite/c-c++-common/fhardened-3.c
>  create mode 100644 gcc/testsuite/c-c++-common/fhardened-5.c
>  create mode 100644 gcc/testsuite/c-c++-common/fhardened-6.c
>  create mode 100644 gcc/testsuite/c-c++-common/fhardened-7.c
>  create mode 100644 gcc/testsuite/c-c++-common/fhardened-8.c
>  create mode 100644 gcc/testsuite/c-c++-common/fhardened-9.c
>  create mode 100644 gcc/testsuite/gcc.target/i386/cf_check-6.c
>
> diff --git a/gcc/c-family/c-opts.cc b/gcc/c-family/c-opts.cc
> index 4961af63de8..764714ba8a5 100644
> --- a/gcc/c-family/c-opts.cc
> +++ b/gcc/c-family/c-opts.cc
> @@ -1514,6 +1514,9 @@ c_finish_options (void)
>cb_file_change (parse_in, cmd_map);
>linemap_line_start (line_table, 0, 1);
>
> +  bool fortify_seen_p = false;
> +  bool cxx_assert_seen_p = false;
> +
>/* All command line defines must have the same location.  */
>cpp_force_token_locations (parse_in, line_table->highest_line);
>for (size_t i = 0; i < deferred_count; i++)
> @@ -1531,6 +1534,28 @@ c_finish_options (void)
>   else
> cpp_assert (parse_in, opt->arg);
> }
> +
> + if (UNLIKELY (flag_hardened)
> + && (opt->code == OPT_D || opt->code == OPT_U))
> +   {
> + if (!fortify_seen_p)
> +   fortify_seen_p = !strncmp (opt->arg, "_FORTIFY_SOURCE", 15);
> + if (!cxx_assert_

Re: [PATCH 2/2] RISC-V: Refactor vector reduction patterns

[Kito Cheng via Gcc-patches]

LGTM too :)

On Thu, Sep 14, 2023 at 10:11 PM 钟居哲  wrote:
>
> LGTM.
> It's obvious you fixed my previous redundant codes.
> Thanks.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: Lehua Ding
> Date: 2023-09-13 20:31
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
> Subject: [PATCH 2/2] RISC-V: Refactor vector reduction patterns
> This patch adjust reduction patterns struct, change it from:
>(any_reduc:VI
>  (vec_duplicate:VI
>(vec_select:
>  (match_operand: 4 "register_operand"  "   vr,   
> vr")
>  (parallel [(const_int 0)])))
>  (match_operand:VI   3 "register_operand"  "   vr,   
> vr"))
> to:
>(unspec: [
>  (match_operand:VI3 "register_operand"  "   vr,   
> vr")
>  (match_operand: 4 "register_operand"  "   vr,   
> vr")
>] ANY_REDUC)
>
> The reason for the change is that the semantics of the previous pattern is 
> incorrect.
> GCC does not have a standard rtx code to express the reduction calculation 
> process.
> It makes more sense to use UNSPEC.
>
> Further, all reduction icode are geted by the UNSPEC and MODE (code_for_pred 
> (unspec, mode)),
> so that all reduction patterns can have a uniform icode name. After this 
> adjust, widen_reducop
> and widen_freducop are redundant.
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Change rtx code to unspec.
> * config/riscv/riscv-protos.h (expand_reduction): Change prototype.
> * config/riscv/riscv-v.cc (expand_reduction): Change prototype.
> * config/riscv/riscv-vector-builtins-bases.cc (class widen_reducop):
> Removed.
> (class widen_freducop): Removed.
> * config/riscv/vector-iterators.md (minu): Add reduc unspec, iterators, attrs.
> * config/riscv/vector.md (@pred_reduc_): Change name.
> (@pred_): New name.
> (@pred_widen_reduc_plus): Change name.
> (@pred_reduc_plus): Change name.
> (@pred_widen_reduc_plus): Change name.
>
> ---
> gcc/config/riscv/autovec.md   |  27 ++--
> gcc/config/riscv/riscv-protos.h   |   2 +-
> gcc/config/riscv/riscv-v.cc   |  13 +-
> .../riscv/riscv-vector-builtins-bases.cc  |  82 
> gcc/config/riscv/vector-iterators.md  |  62 +++--
> gcc/config/riscv/vector.md| 118 +-
> 6 files changed, 152 insertions(+), 152 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 4a6b8f8c939..16ac125f53f 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -2091,7 +2091,7 @@
> (match_operand:VI 1 "register_operand")]
>"TARGET_VECTOR"
> {
> -  riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (mode));
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands, CONST0_RTX 
> (mode));
>DONE;
> })
> @@ -2102,7 +2102,7 @@
> {
>int prec = GET_MODE_PRECISION (mode);
>rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED), mode);
> -  riscv_vector::expand_reduction (SMAX, operands, min);
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, min);
>DONE;
> })
> @@ -2111,7 +2111,7 @@
> (match_operand:VI 1 "register_operand")]
>"TARGET_VECTOR"
> {
> -  riscv_vector::expand_reduction (UMAX, operands, CONST0_RTX (mode));
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, operands, CONST0_RTX 
> (mode));
>DONE;
> })
> @@ -2122,7 +2122,7 @@
> {
>int prec = GET_MODE_PRECISION (mode);
>rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED), mode);
> -  riscv_vector::expand_reduction (SMIN, operands, max);
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, max);
>DONE;
> })
> @@ -2133,7 +2133,7 @@
> {
>int prec = GET_MODE_PRECISION (mode);
>rtx max = immed_wide_int_const (wi::max_value (prec, UNSIGNED), mode);
> -  riscv_vector::expand_reduction (UMIN, operands, max);
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, operands, max);
>DONE;
> })
> @@ -2142,7 +2142,7 @@
> (match_operand:VI 1 "register_operand")]
>"TARGET_VECTOR"
> {
> -  riscv_vector::expand_reduction (AND, operands, CONSTM1_RTX (mode));
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_AND, operands, CONSTM1_RTX 
> (mode));
>DONE;
> })
> @@ -2151,7 +2151,7 @@
> (match_operand:VI 1 "register_operand")]
>"TARGET_VECTOR"
> {
> -  riscv_vector::expand_reduction (IOR, operands, CONST0_RTX (mode));
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_OR, operands, CONST0_RTX 
> (mode));
>DONE;
> })
> @@ -2160,7 +2160,7 @@
> (match_operand:VI 1 "register_operand")]
>"TARGET_VECTOR"
> {
> -  riscv_vector::expand_reduction (XOR, operands, CONST0_RTX (mode));
> +  riscv_vector::expand_reduction (UNSPEC_REDUC_XOR, operands, CONST0_RTX 
> (mode));
>DONE;
> })
> @@ -2178,7 +2178,8 @@
> (match_operand:VF 1 "register_operand")]
>"TARGET_VECTOR"
> {
> -  riscv_vector:

Re: Question on -fwrapv and -fwrapv-pointer

[Qing Zhao via Gcc-patches]

Thanks for the info.

> On Sep 14, 2023, at 10:06 AM, Richard Biener  
> wrote:
> 
> On Thu, Sep 14, 2023 at 3:42 PM Qing Zhao via Gcc-patches
>  wrote:
>> 
>> Hi,
>> 
>> I have several questions on these options:
>> 
>> 1.are pointers treated as signed integers in general? (I thought that 
>> pointers are addresses to the memory, should be treated as unsigned integer…)
>> 2. If Yes, why?
>> 3. why a separate option for pointesr -fwrapv-pointer in addition to -fwrapv 
>> if they are treated as signed integers?
> 
> Pointers are unsigned, they might sign-extend to Pmode though.
If they are unsigned, why they are sign-extend to Pmode? Is there any special 
reason for this? 
In another word, can we consistently treat pointers as unsigned? 

> -fwrapv-pointer is to enable wrapping over zero,

If we always treat pointers are unsigned, then we don’t need the 
-fwrapv-pointer anymore, right? 

> we don't have many places using this, ISTR kernel folks requested to
> disable specific folding - digging in history
> might reveal the case/PR.

Do you mean that this -fwrapv-pointer was introduced for kernel?

I will try to dig a little bit here.

thanks.

Qing
> 
> Richard.
> 
>> Thanks for your help.
>> 
>> Qing
>> 

Re: [PATCH 1/2] RISC-V: Cleanup redundant reduction patterns after refactor vector mode

[Lehua Ding]

Committed, thanks Juzhe.

On 2023/9/14 22:10, 钟居哲 wrote:

Thanks for cleaning up.
LGTM.


juzhe.zh...@rivai.ai

*From:* Lehua Ding 
*Date:* 2023-09-13 20:31
*To:* gcc-patches 
*CC:* juzhe.zhong ; kito.cheng
; rdapp.gcc
; palmer ;
jeffreyalaw ; lehua.ding

*Subject:* [PATCH 1/2] RISC-V: Cleanup redundant reduction patterns
after refactor vector mode
This patch cleanups redundant reduction patterns after Juzhe change
vector mode
from fixed-size to scalable-size. For example, whether it is zvl32b,
zvl64b,
zvl128b, RVVM1SI indicates that it occupies a vector register.
Therefore, it is
easy to map vector modes to LMUL1 vector modes with define_mode_attr
without
creating a separate pattern for each LMUL1 Mode. For example, this
patch can
combine four patterns (@pred_reduc_,
@pred_reduc_
@pred_reduc_,
@pred_reduc_) to a single pattern
@pred_reduc_.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_reduction): Adjust call.
* config/riscv/riscv-vector-builtins-bases.cc: Adjust call.
* config/riscv/vector-iterators.md: New iterators and attrs.
* config/riscv/vector.md
(@pred_reduc_):
Removed.
(@pred_reduc_): Removed.
(@pred_reduc_): Removed.
(@pred_reduc_): Removed.
(@pred_reduc_): Added.
(@pred_widen_reduc_plus): Removed.
(@pred_widen_reduc_plus): Removed.
(@pred_widen_reduc_plus): Added.
(@pred_widen_reduc_plus): Removed.
(@pred_reduc_): Removed.
(@pred_reduc_): Removed.
(@pred_reduc_): Removed.
(@pred_reduc_plus): Removed.
(@pred_reduc_plus): Removed.
(@pred_reduc_plus): Added.
(@pred_reduc_plus): Removed.
(@pred_widen_reduc_plus): Removed.
(@pred_widen_reduc_plus): Removed.
(@pred_widen_reduc_plus): Added.
---
gcc/config/riscv/riscv-v.cc   |   4 +-
.../riscv/riscv-vector-builtins-bases.cc  |  15 +-
gcc/config/riscv/vector-iterators.md  |  47 ++-
gcc/config/riscv/vector.md    | 369 +++---
4 files changed, 101 insertions(+), 334 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 76e6094f45b..68b36d9dc4f 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -3230,7 +3230,7 @@ expand_reduction (rtx_code code, rtx *ops, rtx
init, reduction_type type)
= code_for_pred_reduc_plus (type == reduction_type::UNORDERED
   ? UNSPEC_UNORDERED
   : UNSPEC_ORDERED,
-     vmode, m1_mode);
+     vmode);
    if (type == reduction_type::MASK_LEN_FOLD_LEFT)
{
   rtx mask = ops[3];
@@ -3243,7 +3243,7 @@ expand_reduction (rtx_code code, rtx *ops, rtx
init, reduction_type type)
  }
    else
  {
-  insn_code icode = code_for_pred_reduc (code, vmode, m1_mode);
+  insn_code icode = code_for_pred_reduc (code, vmode);
    emit_vlmax_insn (icode, REDUCE_OP, reduc_ops);
  }
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index ee218a03017..c54ea6f0560 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1541,8 +1541,7 @@ public:
    rtx expand (function_expander &e) const override
    {
-    return e.use_exact_insn (
-  code_for_pred_reduc (CODE, e.vector_mode (), e.ret_mode ()));
+    return e.use_exact_insn (code_for_pred_reduc (CODE,
e.vector_mode ()));
    }
};
@@ -1555,9 +1554,8 @@ public:
    rtx expand (function_expander &e) const override
    {
-    return e.use_exact_insn (code_for_pred_widen_reduc_plus (UNSPEC,
-  e.vector_mode (),
-  e.ret_mode ()));
+    return e.use_exact_insn (
+  code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ()));
    }
};
@@ -1576,7 +1574,7 @@ public:
    rtx expand (function_expander &e) const override
    {
  return e.use_exact_insn (
-  code_for_pred_reduc_plus (UNSPEC, e.vector_mode (),
e.ret_mode ()));
+  code_for_pred_reduc_plus (UNSPEC, e.vector_mode ()));
    }
};
@@ -1594,9 +1592,8 @@ public:
    rtx expand (function_expander &e) const override
    {
-    return e.use_exact_insn (code_for_pred_widen_reduc_plus (UNSPEC,
-  e.vector_mode (),
-  e.ret_mode ()));
+    return e.use_exact_insn (
+  code_for_pred_widen_reduc_plus (UNSPEC, e.vector_mode ()));
    }
};
diff --git a/gcc/config/riscv/vector

Re: [PATCH 2/2] RISC-V: Refactor vector reduction patterns

[Lehua Ding]

Committed, thanks Kito and Juzhe.

On 2023/9/14 22:53, Kito Cheng wrote:

LGTM too :)

On Thu, Sep 14, 2023 at 10:11 PM 钟居哲  wrote:


LGTM.
It's obvious you fixed my previous redundant codes.
Thanks.



juzhe.zh...@rivai.ai

From: Lehua Ding
Date: 2023-09-13 20:31
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw; lehua.ding
Subject: [PATCH 2/2] RISC-V: Refactor vector reduction patterns
This patch adjust reduction patterns struct, change it from:
(any_reduc:VI
  (vec_duplicate:VI
(vec_select:
  (match_operand: 4 "register_operand"  "   vr,   
vr")
  (parallel [(const_int 0)])))
  (match_operand:VI   3 "register_operand"  "   vr,   
vr"))
to:
(unspec: [
  (match_operand:VI3 "register_operand"  "   vr,   
vr")
  (match_operand: 4 "register_operand"  "   vr,   
vr")
] ANY_REDUC)

The reason for the change is that the semantics of the previous pattern is 
incorrect.
GCC does not have a standard rtx code to express the reduction calculation 
process.
It makes more sense to use UNSPEC.

Further, all reduction icode are geted by the UNSPEC and MODE (code_for_pred 
(unspec, mode)),
so that all reduction patterns can have a uniform icode name. After this 
adjust, widen_reducop
and widen_freducop are redundant.

gcc/ChangeLog:

* config/riscv/autovec.md: Change rtx code to unspec.
* config/riscv/riscv-protos.h (expand_reduction): Change prototype.
* config/riscv/riscv-v.cc (expand_reduction): Change prototype.
* config/riscv/riscv-vector-builtins-bases.cc (class widen_reducop):
Removed.
(class widen_freducop): Removed.
* config/riscv/vector-iterators.md (minu): Add reduc unspec, iterators, attrs.
* config/riscv/vector.md (@pred_reduc_): Change name.
(@pred_): New name.
(@pred_widen_reduc_plus): Change name.
(@pred_reduc_plus): Change name.
(@pred_widen_reduc_plus): Change name.

---
gcc/config/riscv/autovec.md   |  27 ++--
gcc/config/riscv/riscv-protos.h   |   2 +-
gcc/config/riscv/riscv-v.cc   |  13 +-
.../riscv/riscv-vector-builtins-bases.cc  |  82 
gcc/config/riscv/vector-iterators.md  |  62 +++--
gcc/config/riscv/vector.md| 118 +-
6 files changed, 152 insertions(+), 152 deletions(-)

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 4a6b8f8c939..16ac125f53f 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2091,7 +2091,7 @@
 (match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
-  riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands, CONST0_RTX 
(mode));
DONE;
})
@@ -2102,7 +2102,7 @@
{
int prec = GET_MODE_PRECISION (mode);
rtx min = immed_wide_int_const (wi::min_value (prec, SIGNED), mode);
-  riscv_vector::expand_reduction (SMAX, operands, min);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MAX, operands, min);
DONE;
})
@@ -2111,7 +2111,7 @@
 (match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
-  riscv_vector::expand_reduction (UMAX, operands, CONST0_RTX (mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MAXU, operands, CONST0_RTX 
(mode));
DONE;
})
@@ -2122,7 +2122,7 @@
{
int prec = GET_MODE_PRECISION (mode);
rtx max = immed_wide_int_const (wi::max_value (prec, SIGNED), mode);
-  riscv_vector::expand_reduction (SMIN, operands, max);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MIN, operands, max);
DONE;
})
@@ -2133,7 +2133,7 @@
{
int prec = GET_MODE_PRECISION (mode);
rtx max = immed_wide_int_const (wi::max_value (prec, UNSIGNED), mode);
-  riscv_vector::expand_reduction (UMIN, operands, max);
+  riscv_vector::expand_reduction (UNSPEC_REDUC_MINU, operands, max);
DONE;
})
@@ -2142,7 +2142,7 @@
 (match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
-  riscv_vector::expand_reduction (AND, operands, CONSTM1_RTX (mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_AND, operands, CONSTM1_RTX 
(mode));
DONE;
})
@@ -2151,7 +2151,7 @@
 (match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
-  riscv_vector::expand_reduction (IOR, operands, CONST0_RTX (mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_OR, operands, CONST0_RTX 
(mode));
DONE;
})
@@ -2160,7 +2160,7 @@
 (match_operand:VI 1 "register_operand")]
"TARGET_VECTOR"
{
-  riscv_vector::expand_reduction (XOR, operands, CONST0_RTX (mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_XOR, operands, CONST0_RTX 
(mode));
DONE;
})
@@ -2178,7 +2178,8 @@
 (match_operand:VF 1 "register_operand")]
"TARGET_VECTOR"
{
-  riscv_vector::expand_reduction (PLUS, operands, CONST0_RTX (mode));
+  riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_UNORDERED, operands,
+  CONS

Re: Question on -fwrapv and -fwrapv-pointer

[Richard Biener via Gcc-patches]

> Am 14.09.2023 um 17:01 schrieb Qing Zhao :
> 
> Thanks for the info.
> 
>> On Sep 14, 2023, at 10:06 AM, Richard Biener  
>> wrote:
>> 
>>> On Thu, Sep 14, 2023 at 3:42 PM Qing Zhao via Gcc-patches
>>>  wrote:
>>> 
>>> Hi,
>>> 
>>> I have several questions on these options:
>>> 
>>> 1.are pointers treated as signed integers in general? (I thought that 
>>> pointers are addresses to the memory, should be treated as unsigned 
>>> integer…)
>>> 2. If Yes, why?
>>> 3. why a separate option for pointesr -fwrapv-pointer in addition to 
>>> -fwrapv if they are treated as signed integers?
>> 
>> Pointers are unsigned, they might sign-extend to Pmode though.
> If they are unsigned, why they are sign-extend to Pmode? Is there any special 
> reason for this? 

Some targets require this.  See POINTERS_EXTEND_UNSIGNED

> In another word, can we consistently treat pointers as unsigned? 

We do, but on GIMPLE it doesn’t matter.

>> -fwrapv-pointer is to enable wrapping over zero,
> 
> If we always treat pointers are unsigned, then we don’t need the 
> -fwrapv-pointer anymore, right? 

No, the naming is just ‚bad‘

> 
>> we don't have many places using this, ISTR kernel folks requested to
>> disable specific folding - digging in history
>> might reveal the case/PR.
> 
> Do you mean that this -fwrapv-pointer was introduced for kernel?

I think it was introduced when removing the separate fstrict-overflow flag and 
since that covered also some pointer transforms the wraps-pointer flag was 
introduced.

> 
> I will try to dig a little bit here.
> 
> thanks.
> 
> Qing
>> 
>> Richard.
>> 
>>> Thanks for your help.
>>> 
>>> Qing
>>> 
> 

Re: [PATCH 8/8] OpenMP: Fortran "!$omp declare mapper" support

[Bernhard Reutner-Fischer via Gcc-patches]

On Tue, 5 Sep 2023 12:28:28 -0700
Julian Brown  wrote:

> +  static bool
> +  equal (const omp_name_type &a,
> +  const omp_name_type &b)
> +  {
> +if (a.name == NULL_TREE && b.name == NULL_TREE)
> +  return a.type == b.type;

I'm curious if (and why) the type comparison above is safe and does not
use gfc_compare_types () ?

thanks,

> +else if (a.name == NULL_TREE || b.name == NULL_TREE)
> +  return false;
> +else
> +  return a.name == b.name && gfc_compare_types (a.type, b.type);
> +  }

[PATCH] AArch64: Improve immediate expansion [PR105928]

[Wilco Dijkstra via Gcc-patches]

Support immediate expansion of immediates which can be created from 2 MOVKs
and a shifted ORR or BIC instruction.  Change aarch64_split_dimode_const_store
to apply if we save one instruction.

This reduces the number of 4-instruction immediates in SPECINT/FP by 5%.

Passes regress, OK for commit?

gcc/ChangeLog:
PR target/105928
* config/aarch64/aarch64.cc (aarch64_internal_mov_immediate)
Add support for immediates using shifted ORR/BIC.
(aarch64_split_dimode_const_store): Apply if we save one instruction.
* config/aarch64/aarch64.md (_3): 
Make pattern global.

gcc/testsuite:
PR target/105928
* gcc.target/aarch64/pr105928.c: Add new test.
* gcc.target/aarch64/vect-cse-codegen.c: Fix test.

---

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 
c44c0b979d0cc3755c61dcf566cfddedccebf1ea..832f8197ac8d1a04986791e6f3e51861e41944b2
 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -5639,7 +5639,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool 
generate,
machine_mode mode)
 {
   int i;
-  unsigned HOST_WIDE_INT val, val2, mask;
+  unsigned HOST_WIDE_INT val, val2, val3, mask;
   int one_match, zero_match;
   int num_insns;
 
@@ -5721,6 +5721,35 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool 
generate,
}
  return 3;
}
+
+  /* Try shifting and inserting the bottom 32-bits into the top bits.  */
+  val2 = val & 0x;
+  val3 = 0x;
+  val3 = val2 | (val3 << 32);
+  for (i = 17; i < 48; i++)
+   if ((val2 | (val2 << i)) == val)
+ {
+   if (generate)
+ {
+   emit_insn (gen_rtx_SET (dest, GEN_INT (val2 & 0x)));
+   emit_insn (gen_insv_immdi (dest, GEN_INT (16),
+  GEN_INT (val2 >> 16)));
+   emit_insn (gen_ior_ashldi3 (dest, dest, GEN_INT (i), dest));
+ }
+   return 3;
+ }
+   else if ((val3 & ~(val3 << i)) == val)
+ {
+   if (generate)
+ {
+   emit_insn (gen_rtx_SET (dest, GEN_INT (val3 | 0x)));
+   emit_insn (gen_insv_immdi (dest, GEN_INT (16),
+  GEN_INT (val2 >> 16)));
+   emit_insn (gen_and_one_cmpl_ashldi3 (dest, dest, GEN_INT (i),
+ dest));
+ }
+   return 3;
+ }
 }
 
   /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
@@ -25506,8 +25535,6 @@ aarch64_split_dimode_const_store (rtx dst, rtx src)
   rtx lo = gen_lowpart (SImode, src);
   rtx hi = gen_highpart_mode (SImode, DImode, src);
 
-  bool size_p = optimize_function_for_size_p (cfun);
-
   if (!rtx_equal_p (lo, hi))
 return false;
 
@@ -25526,14 +25553,8 @@ aarch64_split_dimode_const_store (rtx dst, rtx src)
  MOV   w1, 49370
  MOVK  w1, 0x140, lsl 16
  STP   w1, w1, [x0]
-   So we want to perform this only when we save two instructions
-   or more.  When optimizing for size, however, accept any code size
-   savings we can.  */
-  if (size_p && orig_cost <= lo_cost)
-return false;
-
-  if (!size_p
-  && (orig_cost <= lo_cost + 1))
+   So we want to perform this when we save at least one instruction.  */
+  if (orig_cost <= lo_cost)
 return false;
 
   rtx mem_lo = adjust_address (dst, SImode, 0);
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 
97f70d39cc0ddeb330e044bae0544d85a695567d..932d4d47a5db1a74e0d0565b565afbd769090853
 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4618,7 +4618,7 @@ (define_insn "*and_si3_compare0_uxtw"
   [(set_attr "type" "logics_shift_imm")]
 )
 
-(define_insn "*_3"
+(define_insn "_3"
   [(set (match_operand:GPI 0 "register_operand" "=r")
(LOGICAL:GPI (SHIFT:GPI
  (match_operand:GPI 1 "register_operand" "r")
diff --git a/gcc/testsuite/gcc.target/aarch64/pr105928.c 
b/gcc/testsuite/gcc.target/aarch64/pr105928.c
new file mode 100644
index 
..ab52247df66020d0b8fe70bc81f572e8b64c2bb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr105928.c
@@ -0,0 +1,43 @@
+/* { dg-do assemble } */
+/* { dg-options "-O2 --save-temps" } */
+
+long f1 (void)
+{
+  return 0x80402010080400;
+}
+
+long f2 (void)
+{
+  return 0x1234567812345678;
+}
+
+long f3 (void)
+{
+  return 0x4567800012345678;
+}
+
+long f4 (void)
+{
+  return 0x3ecd3ecd;
+}
+
+long f5 (void)
+{
+  return 0x38e38e38e38e38e;
+}
+
+long f6 (void)
+{
+  return 0x1745d1745d1745d;
+}
+
+void f7 (long *p)
+{
+  *p = 0x1234567812345678;
+}
+
+/* { dg-final { scan-assembler-times {\tmovk\t} 7 } } */
+/* { dg-final { scan-assembler-times {\tmov\t} 7 } } */
+/* { dg-final { scan-assembl

[pushed] [RA]: Improve cost calculation of pseudos with equivalences

[Vladimir Makarov via Gcc-patches]

I've committed the following patch.  The reason for this patch is 
explained in its commit message.


The patch was successfully bootstrapped and tested on x86-64, aarch64, 
and ppc64le.


commit 3c834d85f2ec42c60995c2b678196a06cb744959
Author: Vladimir N. Makarov 
Date:   Thu Sep 14 10:26:48 2023 -0400

[RA]: Improve cost calculation of pseudos with equivalences

RISCV target developers reported that RA can spill pseudo used in a
loop although there are enough registers to assign.  It happens when
the pseudo has an equivalence outside the loop and the equivalence is
not merged into insns using the pseudo.  IRA sets up that memory cost
to zero when the pseudo has an equivalence and it means that the
pseudo will be probably spilled.  This approach worked well for i686
(different approaches were benchmarked long time ago on spec2k).
Although common sense says that the code is wrong and this was
confirmed by RISCV developers.

I've tried the following patch on I7-9700k and it improved spec17 fp
by 1.5% (21.1 vs 20.8) although spec17 int is a bit worse by 0.45%
(8.54 vs 8.58).  The average generated code size is practically the
same (0.001% difference).

In the future we probably need to try more sophisticated cost
calculation which should take into account that the equiv can not be
combined in usage insns and the costs of reloads because of this.

gcc/ChangeLog:

* ira-costs.cc (find_costs_and_classes): Decrease memory cost
by equiv savings.

diff --git a/gcc/ira-costs.cc b/gcc/ira-costs.cc
index d9e700e8947..8c93ace5094 100644
--- a/gcc/ira-costs.cc
+++ b/gcc/ira-costs.cc
@@ -1947,15 +1947,8 @@ find_costs_and_classes (FILE *dump_file)
 	}
 	  if (i >= first_moveable_pseudo && i < last_moveable_pseudo)
 	i_mem_cost = 0;
-	  else if (equiv_savings < 0)
-	i_mem_cost = -equiv_savings;
-	  else if (equiv_savings > 0)
-	{
-	  i_mem_cost = 0;
-	  for (k = cost_classes_ptr->num - 1; k >= 0; k--)
-		i_costs[k] += equiv_savings;
-	}
-
+	  else
+	i_mem_cost -= equiv_savings;
 	  best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
 	  best = ALL_REGS;
 	  alt_class = NO_REGS;

[PATCH] RISC-V: Support combine extend and reduce sum to widen reduce sum

[Lehua Ding]

This patch add combine pattern to combine extend and reduce sum
to widen reduce sum. The pattern in autovec.md was adjusted as
needed. Note that the current vectorization cannot generate reduce
openrand which is LMUL=M8, because this means that we need an LMUL=M16
for the extended openrand, which is currently not possible. So I've
added VI_QHS_NO_M8 and VF_HS_NO_M8 mode iterator, which exclude
mode which is LMUL=M8.

PR target/111381

gcc/ChangeLog:

* config/riscv/autovec-opt.md (*reduc_plus_scal_):
New combine pattern.
(*fold_left_widen_plus_): Ditto.
(*mask_len_fold_left_widen_plus_): Ditto.
* config/riscv/autovec.md (reduc_plus_scal_):
Change from define_expand to define_insn_and_split.
(fold_left_plus_): Ditto.
(mask_len_fold_left_plus_): Ditto.
* config/riscv/riscv-v.cc (expand_reduction):
Support widen reduction.
* config/riscv/vector-iterators.md (UNSPEC_WREDUC_SUM):
Add new iterators and attrs.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: New 
test.
* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: New 
test.
* gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: New test.

---
 gcc/config/riscv/autovec-opt.md   | 82 +++
 gcc/config/riscv/autovec.md   | 74 +++--
 gcc/config/riscv/riscv-v.cc   |  7 +-
 gcc/config/riscv/vector-iterators.md  | 51 
 .../riscv/rvv/autovec/widen/widen_reduc-1.c   | 27 ++
 .../rvv/autovec/widen/widen_reduc_order-1.c   | 20 +
 .../rvv/autovec/widen/widen_reduc_order-2.c   | 19 +
 .../autovec/widen/widen_reduc_order_run-1.c   | 24 ++
 .../autovec/widen/widen_reduc_order_run-2.c   | 22 +
 .../rvv/autovec/widen/widen_reduc_run-1.c | 22 +
 10 files changed, 321 insertions(+), 27 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 22ab8afc994..df516849527 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1196,6 +1196,88 @@
 }
 [(set_attr "type" "vfwmul")])
 
+;; Combine extend + vredsum to vwredsum[u]
+(define_insn_and_split "*reduc_plus_scal_"
+  [(set (match_operand: 0 "register_operand")
+(unspec: [
+  (any_extend:
+(match_operand:VI_QHS_NO_M8 1 "register_operand"))
+] UNSPEC_REDUC_SUM))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  riscv_vector::expand_reduction (, operands,
+  CONST0_RTX (mode));
+  DONE;
+}
+[(set_attr "type" "vector")])
+
+;; Combine extend + vfredusum to vfwredusum
+(define_insn_and_split "*reduc_plus_scal_"
+  [(set (match_operand: 0 "register_operand")
+(unspec: [
+  (float_extend:
+(match_operand:VF_HS_NO_M8 1 "register_operand"))
+] UNSPEC_REDUC_SUM_UNORDERED))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED, operands,
+  CONST0_RTX (mode));
+  DONE;
+}
+[(set_attr "type" "vector")])
+
+;; Combine extend + vfredosum to vfwredosum
+(define_insn_and_split "*fold_left_widen_plus_"
+  [(set (match_operand: 0 "register_operand")
+(unspec: [
+  (float_extend:
+(match_operand:VF_HS_NO_M8 2 "register_operand"))
+  (match_operand: 1 "register_operand")
+] UNSPEC_REDUC_SUM_ORDERED))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED, operands,
+ operands[1],
+ riscv_vector::reduction_type::FOLD_LEFT);
+  DONE;
+}
+[(set_attr "type" "vector")])
+
+;; Combine extend + mask vfredosum to mask vfwredosum
+(define_insn_and_split "*mask_len_fold_left_widen_plus_"
+  [(set (match_operand: 0 "register_operand")
+(unspec: [
+  (float_extend:
+(match_operand:VF_HS_NO_M8 2 "register_operand"))
+  (match_operand

Re: Question on -fwrapv and -fwrapv-pointer

[Qing Zhao via Gcc-patches]

> On Sep 14, 2023, at 11:12 AM, Richard Biener  
> wrote:
> 
> 
> 
>> Am 14.09.2023 um 17:01 schrieb Qing Zhao :
>> 
>> Thanks for the info.
>> 
>>> On Sep 14, 2023, at 10:06 AM, Richard Biener  
>>> wrote:
>>> 
 On Thu, Sep 14, 2023 at 3:42 PM Qing Zhao via Gcc-patches
  wrote:
 
 Hi,
 
 I have several questions on these options:
 
 1.are pointers treated as signed integers in general? (I thought that 
 pointers are addresses to the memory, should be treated as unsigned 
 integer…)
 2. If Yes, why?
 3. why a separate option for pointesr -fwrapv-pointer in addition to 
 -fwrapv if they are treated as signed integers?
>>> 
>>> Pointers are unsigned, they might sign-extend to Pmode though.
>> If they are unsigned, why they are sign-extend to Pmode? Is there any 
>> special reason for this? 
> 
> Some targets require this.  See POINTERS_EXTEND_UNSIGNED

Okay, I see.
> 
>> In another word, can we consistently treat pointers as unsigned? 
> 
> We do, but on GIMPLE it doesn’t matter.

Currently, GCC behaves as following:

/* True if overflow wraps around for the given integral or pointer type.  That
   is, TYPE_MAX + 1 == TYPE_MIN.  */
#define TYPE_OVERFLOW_WRAPS(TYPE) \
  (POINTER_TYPE_P (TYPE)\
   ? flag_wrapv_pointer \
   : (ANY_INTEGRAL_TYPE_CHECK(TYPE)->base.u.bits.unsigned_flag  \
  || flag_wrapv))

/* True if overflow is undefined for the given integral or pointer type.
   We may optimize on the assumption that values in the type never overflow.

   IMPORTANT NOTE: Any optimization based on TYPE_OVERFLOW_UNDEFINED
   must issue a warning based on warn_strict_overflow.  In some cases
   it will be appropriate to issue the warning immediately, and in
   other cases it will be appropriate to simply set a flag and let the
   caller decide whether a warning is appropriate or not.  */
#define TYPE_OVERFLOW_UNDEFINED(TYPE)   \
  (POINTER_TYPE_P (TYPE)\
   ? !flag_wrapv_pointer\
   : (!ANY_INTEGRAL_TYPE_CHECK(TYPE)->base.u.bits.unsigned_flag \
  && !flag_wrapv && !flag_trapv))

The logic above seems treating the pointer default as signed integer, right?

Qing

> 
>>> -fwrapv-pointer is to enable wrapping over zero,
>> 
>> If we always treat pointers are unsigned, then we don’t need the 
>> -fwrapv-pointer anymore, right? 
> 
> No, the naming is just ‚bad‘
> 
>> 
>>> we don't have many places using this, ISTR kernel folks requested to
>>> disable specific folding - digging in history
>>> might reveal the case/PR.
>> 
>> Do you mean that this -fwrapv-pointer was introduced for kernel?
> 
> I think it was introduced when removing the separate fstrict-overflow flag 
> and since that covered also some pointer transforms the wraps-pointer flag 
> was introduced.
> 
>> 
>> I will try to dig a little bit here.
>> 
>> thanks.
>> 
>> Qing
>>> 
>>> Richard.
>>> 
 Thanks for your help.
 
 Qing
 
>> 

Re: [PATCH] RISC-V: Support combine extend and reduce sum to widen reduce sum

[Kito Cheng via Gcc-patches]

LGTM

On Thu, Sep 14, 2023 at 11:51 PM Lehua Ding  wrote:
>
> This patch add combine pattern to combine extend and reduce sum
> to widen reduce sum. The pattern in autovec.md was adjusted as
> needed. Note that the current vectorization cannot generate reduce
> openrand which is LMUL=M8, because this means that we need an LMUL=M16
> for the extended openrand, which is currently not possible. So I've
> added VI_QHS_NO_M8 and VF_HS_NO_M8 mode iterator, which exclude
> mode which is LMUL=M8.
>
> PR target/111381
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md (*reduc_plus_scal_):
> New combine pattern.
> (*fold_left_widen_plus_): Ditto.
> (*mask_len_fold_left_widen_plus_): Ditto.
> * config/riscv/autovec.md (reduc_plus_scal_):
> Change from define_expand to define_insn_and_split.
> (fold_left_plus_): Ditto.
> (mask_len_fold_left_plus_): Ditto.
> * config/riscv/riscv-v.cc (expand_reduction):
> Support widen reduction.
> * config/riscv/vector-iterators.md (UNSPEC_WREDUC_SUM):
> Add new iterators and attrs.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: New test.
> * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: New test.
> * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: New test.
> * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: New 
> test.
> * gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: New test.
>
> ---
>  gcc/config/riscv/autovec-opt.md   | 82 +++
>  gcc/config/riscv/autovec.md   | 74 +++--
>  gcc/config/riscv/riscv-v.cc   |  7 +-
>  gcc/config/riscv/vector-iterators.md  | 51 
>  .../riscv/rvv/autovec/widen/widen_reduc-1.c   | 27 ++
>  .../rvv/autovec/widen/widen_reduc_order-1.c   | 20 +
>  .../rvv/autovec/widen/widen_reduc_order-2.c   | 19 +
>  .../autovec/widen/widen_reduc_order_run-1.c   | 24 ++
>  .../autovec/widen/widen_reduc_order_run-2.c   | 22 +
>  .../rvv/autovec/widen/widen_reduc_run-1.c | 22 +
>  10 files changed, 321 insertions(+), 27 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index 22ab8afc994..df516849527 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -1196,6 +1196,88 @@
>  }
>  [(set_attr "type" "vfwmul")])
>
> +;; Combine extend + vredsum to vwredsum[u]
> +(define_insn_and_split "*reduc_plus_scal_"
> +  [(set (match_operand: 0 "register_operand")
> +(unspec: [
> +  (any_extend:
> +(match_operand:VI_QHS_NO_M8 1 "register_operand"))
> +] UNSPEC_REDUC_SUM))]
> +  "TARGET_VECTOR && can_create_pseudo_p ()"
> +  "#"
> +  "&& 1"
> +  [(const_int 0)]
> +{
> +  riscv_vector::expand_reduction (, operands,
> +  CONST0_RTX (mode));
> +  DONE;
> +}
> +[(set_attr "type" "vector")])
> +
> +;; Combine extend + vfredusum to vfwredusum
> +(define_insn_and_split "*reduc_plus_scal_"
> +  [(set (match_operand: 0 "register_operand")
> +(unspec: [
> +  (float_extend:
> +(match_operand:VF_HS_NO_M8 1 "register_operand"))
> +] UNSPEC_REDUC_SUM_UNORDERED))]
> +  "TARGET_VECTOR && can_create_pseudo_p ()"
> +  "#"
> +  "&& 1"
> +  [(const_int 0)]
> +{
> +  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_UNORDERED, operands,
> +  CONST0_RTX (mode));
> +  DONE;
> +}
> +[(set_attr "type" "vector")])
> +
> +;; Combine extend + vfredosum to vfwredosum
> +(define_insn_and_split "*fold_left_widen_plus_"
> +  [(set (match_operand: 0 "register_operand")
> +(unspec: [
> +  (float_extend:
> +(match_operand:VF_HS_NO_M8 2 "register_operand"))
> +  (match_operand: 1 "register_operand")
> +] UNSPEC_REDUC_SUM_ORDERED))]
> +  "TARGET_VECTOR && can_create_pseudo_p ()"
> +  "#"
> +  "&& 1"
> +  [(const_int 0)]
> +{
> +  riscv_vector::expand_reduction (UNSPEC_WREDUC_SUM_ORDERED, operands,
> + operands[1],
> + riscv_vector::reduction_type::FOLD_LEFT);
> +  DONE;
> +}
> +[(set_attr "type" "vector")

Re: [PATCH V4] RISC-V: Expand VLS mode to scalar mode move[PR111391]

[Kito Cheng via Gcc-patches]

I am thinking what we are doing is something like we are allowing
scalar mode within the vector register, so...not sure should we try to
implement that within the mov pattern?

I guess we need some inputs from Jeff.


e.g.
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0ecda795b38..ffced41588d 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7621,6 +7621,9 @@ riscv_hard_regno_mode_ok (unsigned int regno,
machine_mode mode)
}
  else if (V_REG_P (regno))
{
+  if (mode is scalar)
+   return true;
+
  if (!riscv_v_ext_mode_p (mode))
   return false;

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 6d6a2b3748c..50bac39f125 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2035,8 +2035,8 @@ (define_insn "*movdi_32bit"
   (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")])

(define_insn "*movdi_64bit"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m,
*f,*f,*r,*f,*m,r")
-   (match_operand:DI 1 "move_operand" "
r,T,m,rJ,*r*J,*m,*f,*f,*f,vp"))]
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m,
*f,*f,*r,*f,*m,r,*vr,*r,*vr,*vr,*m")
+   (match_operand:DI 1 "move_operand" "
r,T,m,rJ,*r*J,*m,*f,*f,*f,vp,vr,vr,r,m,vr"))]
  "TARGET_64BIT
   && (register_operand (operands[0], DImode)
   || reg_or_0_operand (operands[1], DImode))"

Re: Question on -fwrapv and -fwrapv-pointer

[Xi Ruoyao via Gcc-patches]

On Thu, 2023-09-14 at 15:57 +, Qing Zhao via Gcc-patches wrote:
> Currently, GCC behaves as following:
> 
> /* True if overflow wraps around for the given integral or pointer type.  That
>    is, TYPE_MAX + 1 == TYPE_MIN.  */
> #define TYPE_OVERFLOW_WRAPS(TYPE) \
>   (POINTER_TYPE_P (TYPE)    \
>    ? flag_wrapv_pointer \
>    : (ANY_INTEGRAL_TYPE_CHECK(TYPE)->base.u.bits.unsigned_flag  \
>   || flag_wrapv))
> 
> /* True if overflow is undefined for the given integral or pointer type.
>    We may optimize on the assumption that values in the type never overflow.
> 
>    IMPORTANT NOTE: Any optimization based on TYPE_OVERFLOW_UNDEFINED
>    must issue a warning based on warn_strict_overflow.  In some cases
>    it will be appropriate to issue the warning immediately, and in
>    other cases it will be appropriate to simply set a flag and let the
>    caller decide whether a warning is appropriate or not.  */
> #define TYPE_OVERFLOW_UNDEFINED(TYPE)   \
>   (POINTER_TYPE_P (TYPE)    \
>    ? !flag_wrapv_pointer    \
>    : (!ANY_INTEGRAL_TYPE_CHECK(TYPE)->base.u.bits.unsigned_flag \
>   && !flag_wrapv && !flag_trapv))
> 
> The logic above seems treating the pointer default as signed integer, right?

It only says the pointers cannot overflow, not the pointers are signed.

printf("%d\n", (char *)(intptr_t)-1 > (char *)(intptr_t)1);

produces 1 instead of 0.  Technically this is invoking undefined
behavior and a conforming implementation can output anything.  But
consider a 32-bit bare metal target where the linker can locate a "char
x[512]" at [0x7f00, 0x8100).  The standard then requires &x[512]
> &x[0], but if we do a signed comparison here we'll end up "&x[512] <
&x[0]", this is non-conforming.

IIUC, pointers are not integers, at all.  If we treat them as integers
in the brain we'll end up invoking undefined behavior sooner or later. 
Thus the wrapping/overflowing behavior of pointer is controlled by a
different option than integers.

-- 
Xi Ruoyao 
School of Aerospace Science and Technology, Xidian University

[PATCH] aarch64: Ensure const and sign correctness

[Pekka Seppänen]

Be const and sign correct by using a matching CIE augmentation type.
Use a builtin instead of relying  being included.

libgcc/ChangeLog:

* config/aarch64/aarch64-unwind.h (aarch64_cie_signed_with_b_key):
Use const unsigned type and a builtin.

Signed-off-by: Pekka Seppänen 
---
 libgcc/config/aarch64/aarch64-unwind.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/libgcc/config/aarch64/aarch64-unwind.h 
b/libgcc/config/aarch64/aarch64-unwind.h
index 3ad2f8239ed..d669edd671b 100644
--- a/libgcc/config/aarch64/aarch64-unwind.h
+++ b/libgcc/config/aarch64/aarch64-unwind.h
@@ -40,8 +40,9 @@ aarch64_cie_signed_with_b_key (struct _Unwind_Context 
*context)
   const struct dwarf_cie *cie = get_cie (fde);
   if (cie != NULL)
{
- char *aug_str = cie->augmentation;
- return strchr (aug_str, 'B') == NULL ? 0 : 1;
+ const unsigned char *aug_str = cie->augmentation;
+ return __builtin_strchr ((const char *) aug_str,
+  'B') == NULL ? 0 : 1;
}
 }
   return 0;
-- 
2.34.1