[clang] ecd682b - [ARM] Add __bf16 as new Bfloat16 C Type
Author: Ties Stuij Date: 2020-06-05T10:32:43+01:00 New Revision: ecd682bbf5e69e8690b7e3634258f05ae0a70448 URL: https://github.com/llvm/llvm-project/commit/ecd682bbf5e69e8690b7e3634258f05ae0a70448 DIFF: https://github.com/llvm/llvm-project/commit/ecd682bbf5e69e8690b7e3634258f05ae0a70448.diff LOG: [ARM] Add __bf16 as new Bfloat16 C Type Summary: This patch upstreams support for a new storage only bfloat16 C type. This type is used to implement primitive support for bfloat16 data, in line with the Bfloat16 extension of the Armv8.6-a architecture, as detailed here: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a The bfloat type, and its properties are specified in the Arm Architecture Reference Manual: https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile In detail this patch: - introduces an opaque, storage-only C-type __bf16, which introduces a new bfloat IR type. This is part of a patch series, starting with command-line and Bfloat16 assembly support. The subsequent patches will upstream intrinsics support for BFloat16, followed by Matrix Multiplication and the remaining Virtualization features of the armv8.6-a architecture. The following people contributed to this patch: - Luke Cheeseman - Momchil Velikov - Alexandros Lamprineas - Luke Geeson - Simon Tatham - Ties Stuij Reviewers: SjoerdMeijer, rjmccall, rsmith, liutianle, RKSimon, craig.topper, jfb, LukeGeeson, fpetrogalli Reviewed By: SjoerdMeijer Subscribers: labrinea, majnemer, asmith, dexonsmith, kristof.beyls, arphaman, danielkiss, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D76077 Added: clang/test/CodeGen/arm-bf16-params-returns.c clang/test/CodeGen/arm-bf16-softfloat.c clang/test/CodeGen/arm-mangle-bf16.cpp clang/test/Sema/arm-bf16-forbidden-ops.c clang/test/Sema/arm-bf16-forbidden-ops.cpp clang/test/Sema/arm-bfloat.cpp Modified: clang/docs/LanguageExtensions.rst clang/include/clang-c/Index.h clang/include/clang/AST/ASTContext.h clang/include/clang/AST/BuiltinTypes.def clang/include/clang/AST/Type.h clang/include/clang/Basic/DiagnosticSemaKinds.td clang/include/clang/Basic/Specifiers.h clang/include/clang/Basic/TargetBuiltins.h clang/include/clang/Basic/TargetInfo.h clang/include/clang/Basic/TokenKinds.def clang/include/clang/Sema/DeclSpec.h clang/include/clang/Serialization/ASTBitCodes.h clang/lib/AST/ASTContext.cpp clang/lib/AST/ItaniumMangle.cpp clang/lib/AST/MicrosoftMangle.cpp clang/lib/AST/NSAPI.cpp clang/lib/AST/PrintfFormatString.cpp clang/lib/AST/Type.cpp clang/lib/AST/TypeLoc.cpp clang/lib/Basic/TargetInfo.cpp clang/lib/Basic/Targets/AArch64.cpp clang/lib/Basic/Targets/AArch64.h clang/lib/Basic/Targets/ARM.cpp clang/lib/Basic/Targets/ARM.h clang/lib/CodeGen/ABIInfo.h clang/lib/CodeGen/CGBuiltin.cpp clang/lib/CodeGen/CGDebugInfo.cpp clang/lib/CodeGen/CodeGenModule.cpp clang/lib/CodeGen/CodeGenTypeCache.h clang/lib/CodeGen/CodeGenTypes.cpp clang/lib/CodeGen/ItaniumCXXABI.cpp clang/lib/CodeGen/TargetInfo.cpp clang/lib/Format/FormatToken.cpp clang/lib/Index/USRGeneration.cpp clang/lib/Parse/ParseDecl.cpp clang/lib/Parse/ParseExpr.cpp clang/lib/Parse/ParseExprCXX.cpp clang/lib/Parse/ParseTentative.cpp clang/lib/Sema/DeclSpec.cpp clang/lib/Sema/SemaCast.cpp clang/lib/Sema/SemaChecking.cpp clang/lib/Sema/SemaDecl.cpp clang/lib/Sema/SemaExpr.cpp clang/lib/Sema/SemaOverload.cpp clang/lib/Sema/SemaTemplateVariadic.cpp clang/lib/Sema/SemaType.cpp clang/lib/Serialization/ASTCommon.cpp clang/lib/Serialization/ASTReader.cpp clang/tools/libclang/CXType.cpp Removed: diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index d3d73bf238f9..ba0a7d9cf95c 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -516,8 +516,8 @@ float matrices and add the result to a third 4x4 matrix. Half-Precision Floating Point = -Clang supports two half-precision (16-bit) floating point types: ``__fp16`` and -``_Float16``. These types are supported in all language modes. +Clang supports three half-precision (16-bit) floating point types: ``__fp16``, +``_Float16`` and ``__bf16``. These types are supported in all language modes. ``__fp16`` is supported on every target, as it is purely a storage format; see below. ``_Float16`` is currently only supported on the following targets, with further @@ -529,6 +529,12 @@ targets pending ABI standardization: ``_Float16`` will be supported on more targets as they define ABIs for it. +``__bf16`` is purely a storage format; it is cur
[clang] 1e44731 - [ARM] Add poly64_t on AArch32.
Author: Ties Stuij
Date: 2020-06-05T13:04:21+01:00
New Revision: 1e447318339a6e740819ec1568002f4751527efe
URL:
https://github.com/llvm/llvm-project/commit/1e447318339a6e740819ec1568002f4751527efe
DIFF:
https://github.com/llvm/llvm-project/commit/1e447318339a6e740819ec1568002f4751527efe.diff
LOG: [ARM] Add poly64_t on AArch32.
Summary:
The poly64 types are guarded with ifdefs for AArch64 only. This is wrong. This
was also incorrectly documented in the ACLE spec, but this has been rectified in
the latest release. See paragraph 13.1.2 "Vector data types":
https://developer.arm.com/docs/101028/latest
This patch was written by Alexandros Lamprineas.
Reviewers: ostannard, sdesmalen, fpetrogalli, labrinea, t.p.northover,
LukeGeeson
Reviewed By: ostannard
Subscribers: pbarrio, LukeGeeson, kristof.beyls, danielkiss, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D79711
Added:
clang/test/CodeGen/arm-poly64.c
Modified:
clang/include/clang/Basic/TargetBuiltins.h
clang/lib/AST/ItaniumMangle.cpp
clang/lib/Sema/SemaType.cpp
clang/utils/TableGen/NeonEmitter.cpp
Removed:
diff --git a/clang/include/clang/Basic/TargetBuiltins.h
b/clang/include/clang/Basic/TargetBuiltins.h
index b20a544b7889..5fa5f9f0bcef 100644
--- a/clang/include/clang/Basic/TargetBuiltins.h
+++ b/clang/include/clang/Basic/TargetBuiltins.h
@@ -157,7 +157,7 @@ namespace clang {
EltType getEltType() const { return (EltType)(Flags & EltTypeMask); }
bool isPoly() const {
EltType ET = getEltType();
- return ET == Poly8 || ET == Poly16;
+ return ET == Poly8 || ET == Poly16 || ET == Poly64;
}
bool isUnsigned() const { return (Flags & UnsignedFlag) != 0; }
bool isQuad() const { return (Flags & QuadFlag) != 0; }
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index aae33c5962e0..46815e5a107e 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -3167,6 +3167,7 @@ void CXXNameMangler::mangleNeonVectorType(const
VectorType *T) {
case BuiltinType::UShort:
EltName = "poly16_t";
break;
+case BuiltinType::LongLong:
case BuiltinType::ULongLong:
EltName = "poly64_t";
break;
diff --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp
index 93bb2e15c4da..46fa8bc0608b 100644
--- a/clang/lib/Sema/SemaType.cpp
+++ b/clang/lib/Sema/SemaType.cpp
@@ -7650,15 +7650,16 @@ static bool isPermittedNeonBaseType(QualType &Ty,
Triple.getArch() == llvm::Triple::aarch64_be;
if (VecKind == VectorType::NeonPolyVector) {
if (IsPolyUnsigned) {
- // AArch64 polynomial vectors are unsigned and support poly64.
+ // AArch64 polynomial vectors are unsigned.
return BTy->getKind() == BuiltinType::UChar ||
BTy->getKind() == BuiltinType::UShort ||
BTy->getKind() == BuiltinType::ULong ||
BTy->getKind() == BuiltinType::ULongLong;
} else {
- // AArch32 polynomial vector are signed.
+ // AArch32 polynomial vectors are signed.
return BTy->getKind() == BuiltinType::SChar ||
- BTy->getKind() == BuiltinType::Short;
+ BTy->getKind() == BuiltinType::Short ||
+ BTy->getKind() == BuiltinType::LongLong;
}
}
diff --git a/clang/test/CodeGen/arm-poly64.c b/clang/test/CodeGen/arm-poly64.c
new file mode 100644
index ..52c757f0acbb
--- /dev/null
+++ b/clang/test/CodeGen/arm-poly64.c
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi -target-feature +neon \
+// RUN: -emit-llvm -o - %s | FileCheck %s
+
+// Test that we can use the poly64 type on AArch32
+
+#include
+
+// CHECK-LABEL: @test_poly64
+// CHECK: ret i64 %0
+poly64_t test_poly64(poly64_t a) {
+ return a;
+}
diff --git a/clang/utils/TableGen/NeonEmitter.cpp
b/clang/utils/TableGen/NeonEmitter.cpp
index 625954fe8a04..e93c4c653edf 100644
--- a/clang/utils/TableGen/NeonEmitter.cpp
+++ b/clang/utils/TableGen/NeonEmitter.cpp
@@ -2233,6 +2233,7 @@ void NeonEmitter::run(raw_ostream &OS) {
OS << "#else\n";
OS << "typedef int8_t poly8_t;\n";
OS << "typedef int16_t poly16_t;\n";
+ OS << "typedef int64_t poly64_t;\n";
OS << "#endif\n";
// Emit Neon vector typedefs.
@@ -2245,7 +2246,7 @@ void NeonEmitter::run(raw_ostream &OS) {
for (auto &TS : TDTypeVec) {
bool IsA64 = false;
Type T(TS, ".");
-if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+if (T.isDouble())
IsA64 = true;
if (InIfdef && !IsA64) {
@@ -2278,7 +2279,7 @@ void NeonEmitter::run(raw_ostream &OS) {
for (auto &TS : TDTypeVec) {
bool IsA64 = false;
Type T(TS, ".");
- if (T.isDouble() || (T.isPoly() && T.getElementSizeInBits() == 64))
+ if (T.isDouble())
IsA64 = true;
if (InIfdef && !IsA64) {
[clang] a6fcf5c - [clang][BFloat] add NEON emitter for bfloat
Author: Ties Stuij
Date: 2020-06-05T14:11:51+01:00
New Revision: a6fcf5ca033a83b815f760664e0cff91c2c13dcd
URL:
https://github.com/llvm/llvm-project/commit/a6fcf5ca033a83b815f760664e0cff91c2c13dcd
DIFF:
https://github.com/llvm/llvm-project/commit/a6fcf5ca033a83b815f760664e0cff91c2c13dcd.diff
LOG: [clang][BFloat] add NEON emitter for bfloat
Summary:
This patch adds the bfloat16_t struct typedefs (e.g. bfloat16x8x2_t) to
arm_neon.h
This patch is part of a series implementing the Bfloat16 extension of the
Armv8.6-a architecture, as detailed here:
https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a
The bfloat type, and its properties are specified in the Arm Architecture
Reference Manual:
https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
The following people contributed to this patch:
- Luke Cheeseman
- Simon Tatham
- Ties Stuij
Reviewers: t.p.northover, fpetrogalli, sdesmalen, az, LukeGeeson
Reviewed By: fpetrogalli
Subscribers: SjoerdMeijer, LukeGeeson, pbarrio, mgorny, kristof.beyls,
ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D79708
Added:
clang/include/clang/Basic/arm_bf16.td
Modified:
clang/include/clang/Basic/arm_neon_incl.td
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/ARM.cpp
clang/lib/Headers/CMakeLists.txt
clang/test/CodeGen/arm-bf16-params-returns.c
clang/test/Preprocessor/aarch64-target-features.c
clang/test/Preprocessor/arm-target-features.c
clang/utils/TableGen/NeonEmitter.cpp
clang/utils/TableGen/TableGen.cpp
clang/utils/TableGen/TableGenBackends.h
Removed:
diff --git a/clang/include/clang/Basic/arm_bf16.td
b/clang/include/clang/Basic/arm_bf16.td
new file mode 100644
index ..d837a7666d40
--- /dev/null
+++ b/clang/include/clang/Basic/arm_bf16.td
@@ -0,0 +1,14 @@
+//===--- arm_fp16.td - ARM BF16 compiler interface
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file defines the TableGen definitions from which the ARM BF16 header
+// file will be generated.
+//
+//===--===//
+
+include "arm_neon_incl.td"
diff --git a/clang/include/clang/Basic/arm_neon_incl.td
b/clang/include/clang/Basic/arm_neon_incl.td
index 7593fdcfb486..a1031fe4ad4f 100644
--- a/clang/include/clang/Basic/arm_neon_incl.td
+++ b/clang/include/clang/Basic/arm_neon_incl.td
@@ -215,6 +215,7 @@ def OP_UNAVAILABLE : Operation {
// f: float
// h: half-float
// d: double
+// b: bfloat16
//
// Typespec modifiers
// --
@@ -236,6 +237,7 @@ def OP_UNAVAILABLE : Operation {
// S: change to signed integer category.
// U: change to unsigned integer category.
// F: change to floating category.
+// B: change to BFloat16
// P: change to polynomial category.
// p: change polynomial to equivalent integer category. Otherwise nop.
//
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 080571c6ea4f..b474d1203dee 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -286,6 +286,12 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
if (HasMatMul)
Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
+ if (HasBFloat16) {
+Builder.defineMacro("__ARM_FEATURE_BF16", "1");
+Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
+Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
+ }
+
if ((FPU & NeonMode) && HasFP16FML)
Builder.defineMacro("__ARM_FEATURE_FP16FML", "1");
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index 5e605abfc137..21cfe0107bbb 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -838,6 +838,12 @@ void ARMTargetInfo::getTargetDefines(const LangOptions
&Opts,
if (HasMatMul)
Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
+ if (HasBFloat16) {
+Builder.defineMacro("__ARM_FEATURE_BF16", "1");
+Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
+Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
+ }
+
switch (ArchKind) {
default:
break;
diff --git a/clang/lib/Headers/CMakeLists.txt
b/clang/lib/Headers/CMakeLists.txt
index c5215eede3f9..1a1f7b30f106 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -190,6 +190,8 @@ clang_generate_hea
[clang] 8b137a4 - [clang][BFloat] Add create/set/get/dup intrinsics
Author: Ties Stuij
Date: 2020-06-05T14:35:10+01:00
New Revision: 8b137a430636c6626fcc6ef93b05eb69d6183e57
URL:
https://github.com/llvm/llvm-project/commit/8b137a430636c6626fcc6ef93b05eb69d6183e57
DIFF:
https://github.com/llvm/llvm-project/commit/8b137a430636c6626fcc6ef93b05eb69d6183e57.diff
LOG: [clang][BFloat] Add create/set/get/dup intrinsics
Summary:
This patch is part of a series that adds support for the Bfloat16 extension of
the Armv8.6-a architecture, as detailed here:
https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a
The bfloat type and its properties are specified in the Arm Architecture
Reference Manual:
https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
The following people contributed to this patch:
- Luke Cheeseman
- Momchil Velikov
- Luke Geeson
- Ties Stuij
- Mikhail Maltsev
Reviewers: t.p.northover, sdesmalen, fpetrogalli, LukeGeeson, stuij, labrinea
Reviewed By: labrinea
Subscribers: miyuki, dmgreen, labrinea, kristof.beyls, ilya-biryukov, MaskRay,
jkorous, arphaman, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D79710
Added:
clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c
clang/test/CodeGen/arm-bf16-getset-intrinsics.c
Modified:
clang/include/clang/Basic/arm_neon.td
clang/lib/CodeGen/CGBuiltin.cpp
Removed:
diff --git a/clang/include/clang/Basic/arm_neon.td
b/clang/include/clang/Basic/arm_neon.td
index 82e44aaec69b..98fda8b13142 100644
--- a/clang/include/clang/Basic/arm_neon.td
+++ b/clang/include/clang/Basic/arm_neon.td
@@ -190,20 +190,28 @@ def OP_SCALAR_QRDMLAH_LN : Op<(call "vqadd", $p0, (call
"vqrdmulh", $p1,
def OP_SCALAR_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1,
(call "vget_lane", $p2, $p3)))>;
-def OP_SCALAR_HALF_GET_LN : Op<(bitcast "float16_t",
- (call "vget_lane",
- (bitcast "int16x4_t", $p0), $p1))>;
-def OP_SCALAR_HALF_GET_LNQ : Op<(bitcast "float16_t",
-(call "vget_lane",
- (bitcast "int16x8_t", $p0), $p1))>;
-def OP_SCALAR_HALF_SET_LN : Op<(bitcast "float16x4_t",
- (call "vset_lane",
- (bitcast "int16_t", $p0),
- (bitcast "int16x4_t", $p1), $p2))>;
-def OP_SCALAR_HALF_SET_LNQ : Op<(bitcast "float16x8_t",
-(call "vset_lane",
- (bitcast "int16_t", $p0),
- (bitcast "int16x8_t", $p1), $p2))>;
+multiclass ScalarGetSetLaneOpsF16 {
+ def _GET_LN : Op<(bitcast scalarTy,
+(call "vget_lane",
+(bitcast "int16x4_t", $p0), $p1))>;
+ def _GET_LNQ : Op<(bitcast scalarTy,
+(call "vget_lane",
+(bitcast "int16x8_t", $p0), $p1))>;
+ def _SET_LN : Op<(bitcast vectorTy4,
+(call "vset_lane",
+(bitcast "int16_t", $p0),
+(bitcast "int16x4_t", $p1), $p2))>;
+ def _SET_LNQ : Op<(bitcast vectorTy8,
+(call "vset_lane",
+(bitcast "int16_t", $p0),
+(bitcast "int16x8_t", $p1), $p2))>;
+}
+
+defm OP_SCALAR_HALF: ScalarGetSetLaneOpsF16<"float16_t",
+"float16x4_t", "float16x8_t">;
+defm OP_SCALAR_BF16: ScalarGetSetLaneOpsF16<"bfloat16_t",
+"bfloat16x4_t", "bfloat16x8_t">;
def OP_DOT_LN
: Op<(call "vdot", $p0, $p1,
@@ -247,6 +255,12 @@ def SPLATQ : WInst<"splat_laneq", ".(!Q)I",
"UcUsUicsilPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUlhdQhQdPlQPl"> {
let isLaneQ = 1;
}
+let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)" in {
+ def SPLAT_BF : WInst<"splat_lane", ".(!q)I", "bQb">;
+ def SPLATQ_BF : WInst<"splat_laneq", ".(!Q)I", "bQb"> {
+let isLaneQ = 1;
+ }
+}
//===--===//
// Intrinsics
@@ -1841,3 +1855,39 @@ let ArchGuard = "defined(__ARM_FEATURE_COMPLEX) &&
defined(__aarch64__)" in {
def VCADDQ_ROT90_FP64 : SInst<"vcaddq_rot90", "QQQ", "d">;
def VCADDQ_ROT270_FP64 : SInst<"vcaddq_rot270", "QQQ", "d">;
}
+
+// V8.2-A BFloat intrinsics
+let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)" in {
+ def VCREATE_BF : NoTestOpInst<"vcreate", ".(IU>)", "b", OP_CAST> {
+let BigEndianSafe = 1;
+ }
+
+ def VDUP_N_BF: WOpInst<"vdup_n", ".1", "bQb", OP_DUP>;
+
+ def VDUP_LANE_BF : WOpInst
[clang] 5945e97 - [clang][BFloat] Add reinterpret cast intrinsics
Author: Ties Stuij
Date: 2020-06-07T14:32:37+01:00
New Revision: 5945e9799e77c30baffd0da4a9b735262cda3361
URL:
https://github.com/llvm/llvm-project/commit/5945e9799e77c30baffd0da4a9b735262cda3361
DIFF:
https://github.com/llvm/llvm-project/commit/5945e9799e77c30baffd0da4a9b735262cda3361.diff
LOG: [clang][BFloat] Add reinterpret cast intrinsics
Summary:
This patch is part of a series implementing the Bfloat16 extension of the
Armv8.6-a architecture, as detailed here:
https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a
The bfloat type, and its properties is specified in the Arm C language
extension specification:
https://developer.arm.com/docs/ihi0055/d/procedure-call-standard-for-the-arm-64-bit-architecture
Subscribers: kristof.beyls, ilya-biryukov, MaskRay, jkorous, arphaman,
kadircet, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D79869
The following people contributed to this patch:
- Luke Cheeseman
- Alexandros Lamprineas
- Luke Geeson
- Ties Stuij
Added:
clang/test/CodeGen/aarch64-bf16-reinterpret-intrinsics.c
clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c
Modified:
clang/include/clang/Basic/arm_neon.td
clang/include/clang/Basic/arm_neon_incl.td
clang/utils/TableGen/NeonEmitter.cpp
Removed:
diff --git a/clang/include/clang/Basic/arm_neon.td
b/clang/include/clang/Basic/arm_neon.td
index 98fda8b13142..12481cfb145d 100644
--- a/clang/include/clang/Basic/arm_neon.td
+++ b/clang/include/clang/Basic/arm_neon.td
@@ -635,11 +635,23 @@ def VZIP : WInst<"vzip", "2..",
"csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
def VUZP : WInst<"vuzp", "2..", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
+
+class REINTERPRET_CROSS_SELF :
+ NoTestOpInst<"vreinterpret", "..", Types, OP_REINT> {
+let CartesianProductWith = Types;
+}
+
+multiclass REINTERPRET_CROSS_TYPES {
+ def AXB: NoTestOpInst<"vreinterpret", "..", TypesA, OP_REINT> {
+let CartesianProductWith = TypesB;
+ }
+ def BXA: NoTestOpInst<"vreinterpret", "..", TypesB, OP_REINT> {
+let CartesianProductWith = TypesA;
+ }
+}
+
// E.3.31 Vector reinterpret cast operations
-def VREINTERPRET
- : NoTestOpInst<"vreinterpret", "..",
- "csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs", OP_REINT> {
- let CartesianProductOfTypes = 1;
+def VREINTERPRET :
REINTERPRET_CROSS_SELF<"csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs"> {
let ArchGuard = "!defined(__aarch64__)";
let BigEndianSafe = 1;
}
@@ -1188,12 +1200,9 @@ def VQTBX4_A64 : WInst<"vqtbx4", "..(4Q)U",
"UccPcQUcQcQPc">;
// NeonEmitter implicitly takes the cartesian product of the type string with
// itself during generation so, unlike all other intrinsics, this one should
// include *all* types, not just additional ones.
-def VVREINTERPRET
- : NoTestOpInst<"vreinterpret", "..",
- "csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk",
OP_REINT> {
- let CartesianProductOfTypes = 1;
- let BigEndianSafe = 1;
+def VVREINTERPRET :
REINTERPRET_CROSS_SELF<"csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk">
{
let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)";
+ let BigEndianSafe = 1;
}
@@ -1891,3 +1900,17 @@ let ArchGuard =
"defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC) && defined(__aarc
let isLaneQ = 1;
}
}
+
+let ArchGuard = "defined(__ARM_FEATURE_BF16) && !defined(__aarch64__)" in {
+ let BigEndianSafe = 1 in {
+defm VREINTERPRET_BF : REINTERPRET_CROSS_TYPES<
+"csilUcUsUiUlhfPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQPcQPsQPl", "bQb">;
+ }
+}
+
+let ArchGuard = "defined(__ARM_FEATURE_BF16) && defined(__aarch64__)" in {
+ let BigEndianSafe = 1 in {
+defm VVREINTERPRET_BF : REINTERPRET_CROSS_TYPES<
+"csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk", "bQb">;
+ }
+}
diff --git a/clang/include/clang/Basic/arm_neon_incl.td
b/clang/include/clang/Basic/arm_neon_incl.td
index a1031fe4ad4f..dd20b70433ef 100644
--- a/clang/include/clang/Basic/arm_neon_incl.td
+++ b/clang/include/clang/Basic/arm_neon_incl.td
@@ -267,7 +267,6 @@ class Inst {
string ArchGuard = "";
Operation Operation = o;
- bit CartesianProductOfTypes = 0;
bit BigEndianSafe = 0;
bit isShift = 0;
bit isScalarShift = 0;
@@ -289,6 +288,8 @@ class Inst {
// this. Ex: vset_lane which outputs vmov instructions.
bit isHiddenWInst = 0;
bit isHiddenLInst = 0;
+
+ string CartesianProductWith = "";
}
// The following instruction classes are implemented via builtins.
diff --git a/clang/test/CodeGen/aarch64-bf16-reinterpret-intrinsics.c
b/clang/test/CodeGen/aarch64-bf16-reinterpret-intrinsics.c
new file mode 100644
index 000
[clang] 0357956 - [ARM][bfloat] Do not coerce bfloat arguments and returns to integers
Author: Ties Stuij
Date: 2020-06-18T18:26:01+01:00
New Revision: 035795659b604246b873f659f8feed8084898247
URL:
https://github.com/llvm/llvm-project/commit/035795659b604246b873f659f8feed8084898247
DIFF:
https://github.com/llvm/llvm-project/commit/035795659b604246b873f659f8feed8084898247.diff
LOG: [ARM][bfloat] Do not coerce bfloat arguments and returns to integers
Summary:
As part of moving the argument lowering handling for bfloat arguments and
returns to the backend, this patch removes the code that was responsible for
handling the coercion of those arguments in Clang's Codegen.
Subscribers: kristof.beyls, danielkiss, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D81837
Added:
Modified:
clang/lib/CodeGen/TargetInfo.cpp
clang/test/CodeGen/arm-bf16-params-returns.c
clang/test/CodeGen/arm-mangle-bf16.cpp
Removed:
diff --git a/clang/lib/CodeGen/TargetInfo.cpp
b/clang/lib/CodeGen/TargetInfo.cpp
index 44be42aaefde..9710e676e58f 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -6265,13 +6265,6 @@ ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty,
bool isVariadic,
if (isIllegalVectorType(Ty))
return coerceIllegalVector(Ty);
- // __bf16 gets passed using the bfloat IR type, or using i32 but
- // with the top 16 bits unspecified.
- if (Ty->isBFloat16Type() && IsFloatABISoftFP) {
-llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
-return ABIArgInfo::getDirect(ResType);
- }
-
if (!isAggregateTypeForABI(Ty)) {
// Treat an enum type as its underlying type.
if (const EnumType *EnumTy = Ty->getAs()) {
@@ -6475,15 +6468,6 @@ ABIArgInfo ARMABIInfo::classifyReturnType(QualType
RetTy, bool isVariadic,
return coerceIllegalVector(RetTy);
}
- // if we're using the softfp float abi, __bf16 get returned as if it were an
- // int but with the top 16 bits unspecified.
- if (RetTy->isBFloat16Type()) {
-llvm::Type *ResType = IsAAPCS_VFP ?
- llvm::Type::getBFloatTy(getVMContext()) :
- llvm::Type::getInt32Ty(getVMContext());
-return ABIArgInfo::getDirect(ResType);
- }
-
if (!isAggregateTypeForABI(RetTy)) {
// Treat an enum type as its underlying type.
if (const EnumType *EnumTy = RetTy->getAs())
diff --git a/clang/test/CodeGen/arm-bf16-params-returns.c
b/clang/test/CodeGen/arm-bf16-params-returns.c
index 11e236c51530..ee89bbb96f3f 100644
--- a/clang/test/CodeGen/arm-bf16-params-returns.c
+++ b/clang/test/CodeGen/arm-bf16-params-returns.c
@@ -1,7 +1,6 @@
// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs
-mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o
- %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK32-HARD
-// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -mfloat-abi
hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt
-S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK64-HARD
// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs
-mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2
-o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK32-SOFTFP
-// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -mfloat-abi
softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt
-S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK64-SOFTFP
+// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs
-target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S
-mem2reg -sroa | FileCheck %s --check-prefix=CHECK64
#include
@@ -11,22 +10,17 @@ __bf16 test_ret_bf16(__bf16 v) {
}
// CHECK32-HARD: define arm_aapcs_vfpcc bfloat @test_ret_bf16(bfloat returned
%v) {{.*}} {
// CHECK32-HARD: ret bfloat %v
-// CHECK64-HARD: define bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
-// CHECK64-HARD: ret bfloat %v
-// CHECK32-SOFTFP: define i32 @test_ret_bf16(i32 [[V0:.*]]) {{.*}} {
-// CHECK32-SOFTFP: %tmp2.0.insert.ext = and i32 [[V0]], 65535
-// CHECK32-SOFTFP: ret i32 %tmp2.0.insert.ext
-// CHECK64-SOFTFP: define bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
-// CHECK64-SOFTFP: ret bfloat %v
+// CHECK32-SOFTFP: define bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
+// CHECK32-SOFTFP: ret bfloat %v
+// CHECK64: define bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
+// CHECK64: ret bfloat %v
bfloat16x4_t test_ret_bf16x4_t(bfloat16x4_t v) {
return v;
}
// CHECK32-HARD: define arm_aapcs_vfpcc <4 x bfloat> @test_ret_bf16x4_t(<4 x
bfloat> returned %v) {{.*}} {
// CHECK32-HARD: ret <4 x bfloat> %v
-// CHECK64-HARD: define <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> returned
%v) {{.*}} {
-// CHECK64-HARD: ret <4 x bfloat> %v
// CHECK32-SOFTFP: define <2 x i32> @test_ret_bf16x4_t(<2 x i32> [[V0:.*]])
{{.*}} {
// CHEC
[clang] 8c24f33 - [IR][BFloat] Add BFloat IR type
Author: Ties Stuij
Date: 2020-05-15T14:43:43+01:00
New Revision: 8c24f33158d81d5f4b0c5d27c2f07396f0f1484b
URL:
https://github.com/llvm/llvm-project/commit/8c24f33158d81d5f4b0c5d27c2f07396f0f1484b
DIFF:
https://github.com/llvm/llvm-project/commit/8c24f33158d81d5f4b0c5d27c2f07396f0f1484b.diff
LOG: [IR][BFloat] Add BFloat IR type
Summary:
The BFloat IR type is introduced to provide support for, initially, the BFloat16
datatype introduced with the Armv8.6 architecture (optional from Armv8.2
onwards). It has an 8-bit exponent and a 7-bit mantissa and behaves like an IEEE
754 floating point IR type.
This is part of a patch series upstreaming Armv8.6 features. Subsequent patches
will upstream intrinsics support and C-lang support for BFloat.
Reviewers: SjoerdMeijer, rjmccall, rsmith, liutianle, RKSimon, craig.topper,
jfb, LukeGeeson, sdesmalen, deadalnix, ctetreau
Subscribers: hiraditya, llvm-commits, danielkiss, arphaman, kristof.beyls,
dexonsmith
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78190
Added:
llvm/test/Assembler/bfloat.ll
Modified:
clang/lib/Sema/SemaOpenMP.cpp
llvm/docs/BitCodeFormat.rst
llvm/docs/LangRef.rst
llvm/include/llvm-c/Core.h
llvm/include/llvm/ADT/APFloat.h
llvm/include/llvm/Bitcode/LLVMBitCodes.h
llvm/include/llvm/IR/Constants.h
llvm/include/llvm/IR/DataLayout.h
llvm/include/llvm/IR/IRBuilder.h
llvm/include/llvm/IR/Type.h
llvm/lib/AsmParser/LLLexer.cpp
llvm/lib/AsmParser/LLParser.cpp
llvm/lib/Bitcode/Reader/BitcodeReader.cpp
llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
llvm/lib/CodeGen/MIRParser/MILexer.cpp
llvm/lib/IR/AsmWriter.cpp
llvm/lib/IR/Constants.cpp
llvm/lib/IR/Core.cpp
llvm/lib/IR/DataLayout.cpp
llvm/lib/IR/Function.cpp
llvm/lib/IR/LLVMContextImpl.cpp
llvm/lib/IR/LLVMContextImpl.h
llvm/lib/IR/Type.cpp
llvm/lib/Support/APFloat.cpp
llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/tools/llvm-c-test/echo.cpp
Removed:
diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp
index 544dc6134387..e03b926bc581 100644
--- a/clang/lib/Sema/SemaOpenMP.cpp
+++ b/clang/lib/Sema/SemaOpenMP.cpp
@@ -14936,9 +14936,9 @@ static bool actOnOMPReductionKindClause(
if (auto *ComplexTy = OrigType->getAs())
Type = ComplexTy->getElementType();
if (Type->isRealFloatingType()) {
- llvm::APFloat InitValue =
- llvm::APFloat::getAllOnesValue(Context.getTypeSize(Type),
- /*isIEEE=*/true);
+ llvm::APFloat InitValue = llvm::APFloat::getAllOnesValue(
+ Context.getFloatTypeSemantics(Type),
+ Context.getTypeSize(Type));
Init = FloatingLiteral::Create(Context, InitValue, /*isexact=*/true,
Type, ELoc);
} else if (Type->isScalarType()) {
diff --git a/llvm/docs/BitCodeFormat.rst b/llvm/docs/BitCodeFormat.rst
index dce84620fd7b..4fdccc87cfd2 100644
--- a/llvm/docs/BitCodeFormat.rst
+++ b/llvm/docs/BitCodeFormat.rst
@@ -1107,6 +1107,14 @@ TYPE_CODE_HALF Record
The ``HALF`` record (code 10) adds a ``half`` (16-bit floating point) type to
the type table.
+TYPE_CODE_BFLOAT Record
+^
+
+``[BFLOAT]``
+
+The ``BFLOAT`` record (code 23) adds a ``bfloat`` (16-bit brain floating point)
+type to the type table.
+
TYPE_CODE_FLOAT Record
^^
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index 240dbd68e9e0..07320de7cf4b 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -2963,6 +2963,12 @@ Floating-Point Types
* - ``half``
- 16-bit floating-point value
+ * - ``bfloat``
+ - 16-bit "brain" floating-point value (7-bit significand). Provides the
+ same number of exponent bits as ``float``, so that it matches its
dynamic
+ range, but with greatly reduced precision. Used in Intel's AVX-512 BF16
+ extensions and Arm's ARMv8.6-A extensions, among others.
+
* - ``float``
- 32-bit floating-point value
@@ -2970,7 +2976,7 @@ Floating-Point Types
- 64-bit floating-point value
* - ``fp128``
- - 128-bit floating-point value (112-bit mantissa)
+ - 128-bit floating-point value (112-bit significand)
* - ``x86_fp80``
- 80-bit floating-point value (X87)
@@ -3303,20 +3309,20 @@ number of digits. For example, NaN's, infinities, and
other special
values are represented in their IEEE hexadecimal format so that assembly
and disassembly do not cause any bits to change in the constants.
-When using the hexadecimal form, constants of types half, float, and
-double are represented using the 16-digit form shown above (which
-matches the IEEE754 representation for double); half and float values
-must, however, be exac
[clang] 3524535 - [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77
Author: Ties Stuij
Date: 2022-03-15T13:44:20Z
New Revision: 352453569b2b044ddd5bd4df0074ff9863828b6f
URL:
https://github.com/llvm/llvm-project/commit/352453569b2b044ddd5bd4df0074ff9863828b6f
DIFF:
https://github.com/llvm/llvm-project/commit/352453569b2b044ddd5bd4df0074ff9863828b6f.diff
LOG: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c,
cortex-a77
Reviewed By: amilendra
Differential Revision: https://reviews.llvm.org/D121206
Added:
Modified:
clang/test/Driver/aarch64-ssbs.c
clang/test/Preprocessor/aarch64-target-features.c
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Target/AArch64/AArch64.td
Removed:
diff --git a/clang/test/Driver/aarch64-ssbs.c
b/clang/test/Driver/aarch64-ssbs.c
index 86c93ae926404..209255405d28d 100644
--- a/clang/test/Driver/aarch64-ssbs.c
+++ b/clang/test/Driver/aarch64-ssbs.c
@@ -1,7 +1,11 @@
// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8a+ssbs %s
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-x1 %s
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-x1c %s
2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-a77 %s
2>&1 | FileCheck %s
// CHECK: "-target-feature" "+ssbs"
// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8a+nossbs %s
2>&1 | FileCheck %s --check-prefix=NOSSBS
+// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-x1c+nossbs %s
2>&1 | FileCheck %s --check-prefix=NOSSBS
// NOSSBS: "-target-feature" "-ssbs"
// RUN: %clang -### -target aarch64-none-none-eabi %s
2>&1 | FileCheck %s --check-prefix=ABSENTSSBS
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index 833d75b7e5b9e..b7e0113131ea7 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -285,7 +285,7 @@
// CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon"
"-target-feature" "+crc" "-target-feature" "+crypto"
// CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon"
"-target-feature" "+crc" "-target-feature" "+crypto"
// CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"
"-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature"
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
-// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature"
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature"
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature"
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+fullfp16"
+// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}"
"-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature"
"+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature"
"+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature"
"+rdm" "-target-feature" "+rcpc" "-target-feature" "+ssbs" "-target-feature"
"+fullfp16"
// CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon"
"-target-feature" "+crc" "-target-feature" "+crypto"
// CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature"
"+dotprod" "-target-feature" "+fullfp16"
// CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature"
"+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon"
"-target-feature" "+crc" "-target-feature" "+crypto"
diff --git a/llvm/lib/Support/AArch64TargetParser.cpp
b/llvm/lib/Support/AArch64TargetParser.cpp
index cdf7c8ade9aac..bb19e2714be10 100644
--- a/llvm/lib/Support/AArch64TargetParser.cpp
+++ b/llvm/lib/Support/AArch64TargetParser.cpp
@@ -120,6 +120,8 @@ bool AArch64::getExtensionFeatures(uint64_t Extensions,
Features.push_back("+mops");
if (Extensions & AArch64::AEK_PERFMON)
Features.push_back("+perfmon");
+ if (Extensions & AArch64::AEK_SSBS)
+Features.push_back("+ssbs");
return true;
}
diff --git a/llvm/lib/Target/AArch64/AArch64.td
b/llvm/lib/Target/AArch64/AArch64.td
index f53218c35d46e..872343e8b8f89 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -957,7 +957,7 @@ def ProcessorFeatures {
FeatureRCPC, FeatureSSBS, FeaturePerfMon];
list A77 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
FeatureNEO
[clang] 5f7715d - Pass the cmdline aapcs bitfield options to cc1
Author: Ties Stuij
Date: 2021-02-18T15:41:20Z
New Revision: 5f7715d8780a1d16ad023995d282a7d94cb923a9
URL:
https://github.com/llvm/llvm-project/commit/5f7715d8780a1d16ad023995d282a7d94cb923a9
DIFF:
https://github.com/llvm/llvm-project/commit/5f7715d8780a1d16ad023995d282a7d94cb923a9.diff
LOG: Pass the cmdline aapcs bitfield options to cc1
The following commits added commandline arguments to control following the Arm
Procedure Call Standard for certain volatile bitfield operations:
- https://reviews.llvm.org/D67399
- https://reviews.llvm.org/D72932
This commit fixes the oversight that these args weren't passed from the driver
to cc1 if appropriate.
Where *appropriate* means:
- `-faapcs-bitfield-width`: is the default, so won't be passed
- `-fno-aapcs-bitfield-width`: should be passed
- `-faapcs-bitfield-load`: should be passed
Differential Revision: https://reviews.llvm.org/D96784
Added:
clang/test/Driver/arm-aarch64-bitfield-flags.c
Modified:
clang/lib/Driver/ToolChains/Clang.cpp
Removed:
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index eaaef6b78ffb..2fe5bbe2f06c 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -1528,6 +1528,15 @@ static void renderRemarksOptions(const ArgList &Args,
ArgStringList &CmdArgs,
}
}
+void AddAAPCSVolatileBitfieldArgs(const ArgList &Args, ArgStringList &CmdArgs)
{
+ if (!Args.hasFlag(options::OPT_faapcs_bitfield_width,
+options::OPT_fno_aapcs_bitfield_width, true))
+CmdArgs.push_back("-fno-aapcs-bitfield-width");
+
+ if (Args.getLastArg(options::OPT_ForceAAPCSBitfieldLoad))
+CmdArgs.push_back("-faapcs-bitfield-load");
+}
+
namespace {
void RenderARMABI(const llvm::Triple &Triple, const ArgList &Args,
ArgStringList &CmdArgs) {
@@ -1586,6 +1595,8 @@ void Clang::AddARMTargetArgs(const llvm::Triple &Triple,
const ArgList &Args,
if (Args.getLastArg(options::OPT_mcmse))
CmdArgs.push_back("-mcmse");
+
+ AddAAPCSVolatileBitfieldArgs(Args, CmdArgs);
}
void Clang::RenderTargetOptions(const llvm::Triple &EffectiveTriple,
@@ -1774,6 +1785,8 @@ void Clang::AddAArch64TargetArgs(const ArgList &Args,
D.Diag(diag::err_drv_unsupported_option_argument)
<< A->getOption().getName() << Val;
}
+
+ AddAAPCSVolatileBitfieldArgs(Args, CmdArgs);
}
void Clang::AddMIPSTargetArgs(const ArgList &Args,
diff --git a/clang/test/Driver/arm-aarch64-bitfield-flags.c
b/clang/test/Driver/arm-aarch64-bitfield-flags.c
new file mode 100644
index ..a7961c6eedc3
--- /dev/null
+++ b/clang/test/Driver/arm-aarch64-bitfield-flags.c
@@ -0,0 +1,18 @@
+/// check -faapcs-bitfield-width/-fno-aapcs-bitfield-width
+// RUN: %clang -target arm-arm-none-eabi -march=armv8-m.main
-faapcs-bitfield-width -### %s 2>&1 | FileCheck
--check-prefixes=WIDTH,INVERSE-WIDTH %s
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-m.main
-faapcs-bitfield-width -### %s 2>&1 | FileCheck
--check-prefixes=WIDTH,INVERSE-WIDTH %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8-m.main
-fno-aapcs-bitfield-width -### %s 2>&1 | FileCheck
--check-prefixes=NO-WIDTH,WIDTH %s
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-m.main
-fno-aapcs-bitfield-width -### %s 2>&1 | FileCheck
--check-prefixes=NO-WIDTH,WIDTH %s
+// WIDTH-NOT: -faapcs-bitfield-width
+// NO-WIDTH: -fno-aapcs-bitfield-width
+
+/// check -faapcs-bitfield-load
+// RUN: %clang -target arm-arm-none-eabi -march=armv8-m.main
-faapcs-bitfield-load -### %s 2>&1 | FileCheck --check-prefix=LOAD %s
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-m.main
-faapcs-bitfield-load -### %s 2>&1 | FileCheck --check-prefix=LOAD %s
+// LOAD: -faapcs-bitfield-load
+
+/// check absence of the above argument when not given
+// RUN: %clang -target arm-arm-none-eabi -march=armv8-m.main -### %s 2>&1 |
FileCheck --check-prefixes=INVERSE-WIDTH,INVERSE-LOAD %s
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8-m.main -### %s 2>&1
| FileCheck --check-prefixes=INVERSE-WIDTH,INVERSE-LOAD %s
+// INVERSE-WIDTH-NOT: -fno-aapcs-bitfield-width
+// INVERSE-LOAD-NOT: -fno-aapcs-bitfield-load
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[clang] e3b2f02 - [clang][ARM] PACBTI-M frontend support
Author: Ties Stuij
Date: 2021-12-01T10:37:16Z
New Revision: e3b2f0226bc09f16d5cdba9b94d1db3f15ee7d4a
URL:
https://github.com/llvm/llvm-project/commit/e3b2f0226bc09f16d5cdba9b94d1db3f15ee7d4a
DIFF:
https://github.com/llvm/llvm-project/commit/e3b2f0226bc09f16d5cdba9b94d1db3f15ee7d4a.diff
LOG: [clang][ARM] PACBTI-M frontend support
Handle branch protection option on the commandline as well as a function
attribute. One patch for both mechanisms, as they use the same underlying
parsing mechanism.
These are recorded in a set of LLVM IR module-level attributes like we do for
AArch64 PAC/BTI (see https://reviews.llvm.org/D85649):
- command-line options are "translated" to module-level LLVM IR
attributes (metadata).
- functions have PAC/BTI specific attributes iff the
__attribute__((target("branch-protection=...))) was used in the function
declaration.
- command-line option -mbranch-protection to armclang targeting Arm,
following this grammar:
branch-protection ::= "-mbranch-protection="
protection ::= "none" | "standard" | "bti" [ "+" ]
| [ "+" "bti"]
pac-ret-clause ::= "pac-ret" [ "+" ]
pac-ret-option ::= "leaf" ["+" "b-key"] | "b-key" ["+" "leaf"]
b-key is simply a placeholder to make it consistent with AArch64's
version. In Arm, however, it triggers a warning informing that b-key is
unsupported and a-key will be selected instead.
- Handle _attribute_((target(("branch-protection=..."))) for AArch32 with the
same grammer as the commandline options.
This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:
https://developer.arm.com/documentation/ddi0553/latest
The following people contributed to this patch:
- Momchil Velikov
- Victor Campos
- Ties Stuij
Reviewed By: vhscampos
Differential Revision: https://reviews.llvm.org/D112421
Added:
clang/test/CodeGen/arm-branch-protection-attr-1.c
clang/test/CodeGen/arm-branch-protection-attr-2.c
clang/test/Driver/arm-security-options.c
clang/test/Frontend/arm-invalid-branch-protection.c
clang/test/Sema/aarch64-branch-protection-attr-err.c
clang/test/Sema/arm-branch-protection-attr-err.c
Modified:
clang/include/clang/Basic/DiagnosticDriverKinds.td
clang/include/clang/Basic/DiagnosticGroups.td
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/ARM.cpp
clang/lib/Basic/Targets/ARM.h
clang/lib/CodeGen/CodeGenModule.cpp
clang/lib/CodeGen/TargetInfo.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Sema/SemaDeclAttr.cpp
clang/test/CodeGen/arm_neon_intrinsics.c
clang/test/Driver/aarch64-security-options.c
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/include/llvm/Support/TargetParser.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Support/TargetParser.cpp
Removed:
clang/test/Sema/branch-protection-attr-err.c
diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td
b/clang/include/clang/Basic/DiagnosticDriverKinds.td
index 74dbb3d98a86..2f50918b527b 100644
--- a/clang/include/clang/Basic/DiagnosticDriverKinds.td
+++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td
@@ -400,6 +400,8 @@ def warn_ignoring_verify_debuginfo_preserve_export :
Warning<
InGroup;
def err_invalid_branch_protection: Error <
"invalid branch protection option '%0' in '%1'">;
+def warn_unsupported_branch_protection: Warning <
+ "invalid branch protection option '%0' in '%1'">, InGroup;
def err_invalid_sls_hardening : Error<
"invalid sls hardening option '%0' in '%1'">;
def err_sls_hardening_arm_not_supported : Error<
diff --git a/clang/include/clang/Basic/DiagnosticGroups.td
b/clang/include/clang/Basic/DiagnosticGroups.td
index 629e553d66e3..90df3a424406 100644
--- a/clang/include/clang/Basic/DiagnosticGroups.td
+++ b/clang/include/clang/Basic/DiagnosticGroups.td
@@ -1338,3 +1338,6 @@ def PedanticMacros : DiagGroup<"pedantic-macros",
BuiltinMacroRedefined,
RestrictExpansionMacro,
FinalMacro]>;
+
+def BranchProtection : DiagGroup<"branch-protection">;
+
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index d37bc86ce073..fb5bd53f7432 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -2979,6 +2979,9 @@ def err_attribute_requires_opencl_version : Error<
"attribute %0 is supported in the OpenCL version %1%select{| onwards}2">;
def err_invalid_branch_protection_spec : Error<
"in
[clang] ab2611d - [clang][ARM] emit PACBTI-M feature defines
Author: Ties Stuij
Date: 2021-12-01T10:46:29Z
New Revision: ab2611d0998c7acade219f1ccb511d3a7e76a681
URL:
https://github.com/llvm/llvm-project/commit/ab2611d0998c7acade219f1ccb511d3a7e76a681
DIFF:
https://github.com/llvm/llvm-project/commit/ab2611d0998c7acade219f1ccb511d3a7e76a681.diff
LOG: [clang][ARM] emit PACBTI-M feature defines
emit __ARM_FEATURE_BTI_DEFAULT and __ARM_FEATURE_PAC_DEFAULT defines when those
features have been enabled
This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:
https://developer.arm.com/documentation/ddi0553/latest
The following people contributed to this patch:
- Victor Campos
- Ties Stuij
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D112422
Added:
Modified:
clang/lib/Basic/Targets/ARM.cpp
clang/test/Preprocessor/arm-target-features.c
Removed:
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index 032f6b5bc398..f330780300f2 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -896,6 +896,16 @@ void ARMTargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__ARM_BF16_FORMAT_ALTERNATIVE", "1");
}
+ if (Opts.BranchTargetEnforcement)
+Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
+
+ if (Opts.hasSignReturnAddress()) {
+unsigned Value = Opts.isSignReturnAddressWithAKey() ? 1 : 2;
+if (Opts.isSignReturnAddressScopeAll())
+ Value |= 1 << 2;
+Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", Twine(Value));
+ }
+
switch (ArchKind) {
default:
break;
diff --git a/clang/test/Preprocessor/arm-target-features.c
b/clang/test/Preprocessor/arm-target-features.c
index e26b3cad651f..7fb3323cd409 100644
--- a/clang/test/Preprocessor/arm-target-features.c
+++ b/clang/test/Preprocessor/arm-target-features.c
@@ -877,6 +877,25 @@
// RUN: %clang -target arm-none-none-eabi -march=armv7-m -mfpu=softvfp -x c -E
-dM %s -o - | FileCheck --check-prefix=CHECK-SOFTVFP %s
// CHECK-SOFTVFP-NOT: #define __ARM_FP 0x
+// Test Armv8.1-M PACBTI
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s
-o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=bti -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-BTI,CHECK-NOPAC %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC-BKEY,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=pac-ret+leaf -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=bti+pac-ret -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC-BKEY,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=bti+pac-ret+leaf -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-BTI %s
+// CHECK-NOBTI-NOT: #define __ARM_FEATURE_BTI_DEFAULT
+// CHECK-NOPAC-NOT: #define __ARM_FEATURE_PAC_DEFAULT
+// CHECK-BTI: #define __ARM_FEATURE_BTI_DEFAULT 1
+// CHECK-PAC: #define __ARM_FEATURE_PAC_DEFAULT 1
+// CHECK-PAC-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 2
+// CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
+// CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
+
// == Check BFloat16 Extensions.
// RUN: %clang -target arm-arm-none-eabi -march=armv8.6-a+bf16 -x c -E -dM %s
-o - 2>&1 | FileCheck -check-prefix=CHECK-BFLOAT %s
// CHECK-BFLOAT: #define __ARM_BF16_FORMAT_ALTERNATIVE 1
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[clang] 5b4746f - [clang][ARM] removing branch protection error cmdline test
Author: Ties Stuij
Date: 2021-12-01T12:09:08Z
New Revision: 5b4746f94aed5548cd918357299c585a89e3b524
URL:
https://github.com/llvm/llvm-project/commit/5b4746f94aed5548cd918357299c585a89e3b524
DIFF:
https://github.com/llvm/llvm-project/commit/5b4746f94aed5548cd918357299c585a89e3b524.diff
LOG: [clang][ARM] removing branch protection error cmdline test
This test which was just introduced in the PACBTI-M frontend
patch (https://reviews.llvm.org/D112421) is currently failing on some
platforms. Removing temporarily.
Added:
Modified:
Removed:
clang/test/Frontend/arm-invalid-branch-protection.c
diff --git a/clang/test/Frontend/arm-invalid-branch-protection.c
b/clang/test/Frontend/arm-invalid-branch-protection.c
deleted file mode 100644
index 2e2a26a8b576c..0
--- a/clang/test/Frontend/arm-invalid-branch-protection.c
+++ /dev/null
@@ -1,6 +0,0 @@
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key -c
%s -o /dev/null 2>&1 | FileCheck %s
-// RUN: %clang -target arm-arm-none-eabi
-mbranch-protection=pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=bti+pac-ret+b-key
-c %s -o /dev/null 2>&1 | FileCheck %s
-// RUN: %clang -target arm-arm-none-eabi
-mbranch-protection=bti+pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck
%s
-
-// CHECK: warning: invalid branch protection option 'b-key' in
'-mbranch-protection={{[a-z+-]*}}' [-Wbranch-protection]
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[clang] 0fbb174 - [ARM] Implement setjmp BTI placement for PACBTI-M
Author: Ties Stuij
Date: 2021-12-06T11:07:10Z
New Revision: 0fbb17458a01a6b388fc67661ffb92969503e977
URL:
https://github.com/llvm/llvm-project/commit/0fbb17458a01a6b388fc67661ffb92969503e977
DIFF:
https://github.com/llvm/llvm-project/commit/0fbb17458a01a6b388fc67661ffb92969503e977.diff
LOG: [ARM] Implement setjmp BTI placement for PACBTI-M
This patch intends to guard indirect branches performed by longjmp
by inserting BTI instructions after calls to setjmp.
Calls with 'returns-twice' are lowered to a new pseudo-instruction
named t2CALL_BTI that is later expanded to a bundle of {tBL,t2BTI}.
This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:
https://developer.arm.com/documentation/ddi0553/latest
The following people contributed to this patch:
- Alexandros Lamprineas
- Ties Stuij
Reviewed By: labrinea
Differential Revision: https://reviews.llvm.org/D112427
Added:
clang/test/Driver/arm-bti-return-twice.c
llvm/test/CodeGen/ARM/setjmp-bti-basic.ll
llvm/test/CodeGen/ARM/setjmp-bti-outliner.ll
Modified:
clang/docs/ClangCommandLineReference.rst
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Arch/ARM.cpp
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.h
llvm/lib/Target/ARM/ARMInstrThumb2.td
llvm/lib/Target/ARM/ARMSubtarget.h
Removed:
diff --git a/clang/docs/ClangCommandLineReference.rst
b/clang/docs/ClangCommandLineReference.rst
index 8d4ffa6a38fc4..97807009fd911 100644
--- a/clang/docs/ClangCommandLineReference.rst
+++ b/clang/docs/ClangCommandLineReference.rst
@@ -3260,6 +3260,11 @@ Thread pointer access method (AArch32/AArch64 only)
Allow memory accesses to be unaligned (AArch32/AArch64 only)
+.. option:: -mno-bti-at-return-twice
+
+Do not add a BTI instruction after a setjmp or other return-twice construct
(Arm
+only)
+
Hexagon
---
.. option:: -mieee-rnd-near
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 4e6dd20503446..7c257e4a474fa 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -3338,6 +3338,11 @@ def mno_fix_cortex_a53_835769 : Flag<["-"],
"mno-fix-cortex-a53-835769">,
def mmark_bti_property : Flag<["-"], "mmark-bti-property">,
Group,
HelpText<"Add .note.gnu.property with BTI to assembly files (AArch64 only)">;
+def mno_bti_at_return_twice : Flag<["-"], "mno-bti-at-return-twice">,
+ Group,
+ HelpText<"Do not add a BTI instruction after a setjmp or other"
+ " return-twice construct (Arm only)">;
+
foreach i = {1-31} in
def ffixed_x#i : Flag<["-"], "ffixed-x"#i>, Group,
HelpText<"Reserve the x"#i#" register (AArch64/RISC-V only)">;
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index 8d5c64d975502..e03bed0a6de64 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -875,6 +875,8 @@ void arm::getARMTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
}
}
+ if (Args.getLastArg(options::OPT_mno_bti_at_return_twice))
+Features.push_back("+no-bti-at-return-twice");
}
std::string arm::getARMArch(StringRef Arch, const llvm::Triple &Triple) {
diff --git a/clang/test/Driver/arm-bti-return-twice.c
b/clang/test/Driver/arm-bti-return-twice.c
new file mode 100644
index 0..c5cd385a34e20
--- /dev/null
+++ b/clang/test/Driver/arm-bti-return-twice.c
@@ -0,0 +1,7 @@
+// RUN: %clang -target arm-arm-none-eabi -march=armv8-m.main
-mbranch-protection=bti \
+// RUN: -mno-bti-at-return-twice -### %s 2>&1 | FileCheck %s
--check-prefix=FEAT
+// RUN: %clang -target arm-arm-none-eabi -march=armv8-m.main
-mbranch-protection=bti \
+// RUN: -### %s 2>&1 | FileCheck %s --check-prefix=NOFEAT
+
+// FEAT: "+no-bti-at-return-twice"
+// NOFEAT-NOT: "+no-bti-at-return-twice"
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index e03dd597eb650..8173fe4036a85 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -446,6 +446,11 @@ def FeaturePACBTI : SubtargetFeature<"pacbti",
"HasPACBTI", "true",
"Enable Pointer Authentication
and Branch "
"Target Identification">;
+def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice",
+ "NoBTIAtReturnTwice", "true",
+
[clang] 95bbe9a - [clang][ARM] follow GCC behavior for defining __SOFTFP__
Author: Ties Stuij
Date: 2022-10-18T14:38:03+01:00
New Revision: 95bbe9a1930886cffc79f1f5b953f5aafff1557f
URL:
https://github.com/llvm/llvm-project/commit/95bbe9a1930886cffc79f1f5b953f5aafff1557f
DIFF:
https://github.com/llvm/llvm-project/commit/95bbe9a1930886cffc79f1f5b953f5aafff1557f.diff
LOG: [clang][ARM] follow GCC behavior for defining __SOFTFP__
GCC behavior regarding defining __SOFTFP__ when (implicitly) specifying
-mfloat-abi=softfp:
- compile without (implicit) FP: define __SOFTFP__
- compile with (implicit) FP: don't define __SOFTFP__
Currently Clang doesn't define __SOFTFP__ when softfp is specified, either with
or without FP. This patch brings Clang in line with GCC behavior.
This was raised by itaig1 over on Github:
https://github.com/llvm/llvm-project/issues/55755
Reviewed By: pratlucas
Differential Revision: https://reviews.llvm.org/D135680
Added:
Modified:
clang/lib/Basic/Targets/ARM.cpp
clang/test/Preprocessor/init-arm.c
Removed:
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index 948f0bae4f0f8..c750a3cf126c6 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -801,7 +801,7 @@ void ARMTargetInfo::getTargetDefines(const LangOptions
&Opts,
if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || ABI == "aapcs16")
Builder.defineMacro("__ARM_PCS_VFP", "1");
- if (SoftFloat)
+ if (SoftFloat || (SoftFloatABI && !FPU))
Builder.defineMacro("__SOFTFP__");
// ACLE position independent code macros.
diff --git a/clang/test/Preprocessor/init-arm.c
b/clang/test/Preprocessor/init-arm.c
index 58ee6981bfb47..e317ffa67393d 100644
--- a/clang/test/Preprocessor/init-arm.c
+++ b/clang/test/Preprocessor/init-arm.c
@@ -395,199 +395,593 @@
// ARM-BE:#define __arm 1
// ARM-BE:#define __arm__ 1
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-none-linux-gnueabi
-target-feature +soft-float -target-feature +soft-float-abi < /dev/null |
FileCheck -match-full-lines -check-prefix ARMEABISOFTFP %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-none-linux-gnueabi
-target-feature +soft-float -target-feature +soft-float-abi < /dev/null |
FileCheck -match-full-lines -check-prefix ARMEABISOFT %s
//
-// ARMEABISOFTFP-NOT:#define _LP64
-// ARMEABISOFTFP:#define __APCS_32__ 1
-// ARMEABISOFTFP-NOT:#define __ARMEB__ 1
-// ARMEABISOFTFP:#define __ARMEL__ 1
-// ARMEABISOFTFP:#define __ARM_ARCH 4
-// ARMEABISOFTFP:#define __ARM_ARCH_4T__ 1
-// ARMEABISOFTFP-NOT:#define __ARM_BIG_ENDIAN 1
-// ARMEABISOFTFP:#define __ARM_EABI__ 1
-// ARMEABISOFTFP:#define __ARM_PCS 1
-// ARMEABISOFTFP-NOT:#define __ARM_PCS_VFP 1
-// ARMEABISOFTFP:#define __BIGGEST_ALIGNMENT__ 8
-// ARMEABISOFTFP:#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
-// ARMEABISOFTFP:#define __CHAR16_TYPE__ unsigned short
-// ARMEABISOFTFP:#define __CHAR32_TYPE__ unsigned int
-// ARMEABISOFTFP:#define __CHAR_BIT__ 8
-// ARMEABISOFTFP:#define __DBL_DENORM_MIN__ 4.9406564584124654e-324
-// ARMEABISOFTFP:#define __DBL_DIG__ 15
-// ARMEABISOFTFP:#define __DBL_EPSILON__ 2.2204460492503131e-16
-// ARMEABISOFTFP:#define __DBL_HAS_DENORM__ 1
-// ARMEABISOFTFP:#define __DBL_HAS_INFINITY__ 1
-// ARMEABISOFTFP:#define __DBL_HAS_QUIET_NAN__ 1
-// ARMEABISOFTFP:#define __DBL_MANT_DIG__ 53
-// ARMEABISOFTFP:#define __DBL_MAX_10_EXP__ 308
-// ARMEABISOFTFP:#define __DBL_MAX_EXP__ 1024
-// ARMEABISOFTFP:#define __DBL_MAX__ 1.7976931348623157e+308
-// ARMEABISOFTFP:#define __DBL_MIN_10_EXP__ (-307)
-// ARMEABISOFTFP:#define __DBL_MIN_EXP__ (-1021)
-// ARMEABISOFTFP:#define __DBL_MIN__ 2.2250738585072014e-308
-// ARMEABISOFTFP:#define __DECIMAL_DIG__ __LDBL_DECIMAL_DIG__
-// ARMEABISOFTFP:#define __FLT_DENORM_MIN__ 1.40129846e-45F
-// ARMEABISOFTFP:#define __FLT_DIG__ 6
-// ARMEABISOFTFP:#define __FLT_EPSILON__ 1.19209290e-7F
-// ARMEABISOFTFP:#define __FLT_HAS_DENORM__ 1
-// ARMEABISOFTFP:#define __FLT_HAS_INFINITY__ 1
-// ARMEABISOFTFP:#define __FLT_HAS_QUIET_NAN__ 1
-// ARMEABISOFTFP:#define __FLT_MANT_DIG__ 24
-// ARMEABISOFTFP:#define __FLT_MAX_10_EXP__ 38
-// ARMEABISOFTFP:#define __FLT_MAX_EXP__ 128
-// ARMEABISOFTFP:#define __FLT_MAX__ 3.40282347e+38F
-// ARMEABISOFTFP:#define __FLT_MIN_10_EXP__ (-37)
-// ARMEABISOFTFP:#define __FLT_MIN_EXP__ (-125)
-// ARMEABISOFTFP:#define __FLT_MIN__ 1.17549435e-38F
-// ARMEABISOFTFP:#define __FLT_RADIX__ 2
-// ARMEABISOFTFP:#define __INT16_C_SUFFIX__
-// ARMEABISOFTFP:#define __INT16_FMTd__ "hd"
-// ARMEABISOFTFP:#define __INT16_FMTi__ "hi"
-// ARMEABISOFTFP:#define __INT16_MAX__ 32767
-// ARMEABISOFTFP:#define __INT16_TYPE__ short
-// ARMEABISOFTFP:#define __INT32_C_SUFFIX__
-// ARMEABISOFTFP:#define __INT32_FMTd__ "d"
-// ARMEABISOFTFP:#define __INT32_FMTi__ "i"
-// ARMEABISOFTFP:#define __INT32_MAX__ 2147483647
-// ARMEABISOFTFP:#define __INT32_TYPE__ int
-// ARMEABISOFTFP:#define __INT64_C_SUFFIX__ LL
-// ARMEABISO
[clang] 27cbfa7 - [Clang] Propagate const context info when emitting compound literal
Author: Ties Stuij
Date: 2022-08-18T11:25:20+01:00
New Revision: 27cbfa7cc8cdab121842adf4dd31f6811f523928
URL:
https://github.com/llvm/llvm-project/commit/27cbfa7cc8cdab121842adf4dd31f6811f523928
DIFF:
https://github.com/llvm/llvm-project/commit/27cbfa7cc8cdab121842adf4dd31f6811f523928.diff
LOG: [Clang] Propagate const context info when emitting compound literal
This patch fixes a crash when trying to emit a constant compound literal.
For C++ Clang evaluates either casts or binary operations at translation time,
but doesn't pass on the InConstantContext information that was inferred when
parsing the statement. Because of this, strict FP evaluation (-ftrapping-math)
which shouldn't be in effect yet, then causes checkFloatingpointResult to return
false, which in tryEmitGlobalCompoundLiteral will trigger an assert that the
compound literal wasn't constant.
The discussion here around 'manifestly constant evaluated contexts' was very
helpful to me when trying to understand what LLVM's position is on what
evaluation context should be in effect, together with the explanatory text in
that patch itself:
https://reviews.llvm.org/D87528
Reviewed By: rjmccall, DavidSpickett
Differential Revision: https://reviews.llvm.org/D131555
Added:
Modified:
clang/lib/CodeGen/CGExprConstant.cpp
clang/lib/CodeGen/ConstantEmitter.h
clang/test/CodeGen/const-init.c
Removed:
diff --git a/clang/lib/CodeGen/CGExprConstant.cpp
b/clang/lib/CodeGen/CGExprConstant.cpp
index f00ada98aa55b..db6341e87933a 100644
--- a/clang/lib/CodeGen/CGExprConstant.cpp
+++ b/clang/lib/CodeGen/CGExprConstant.cpp
@@ -913,17 +913,16 @@ bool ConstStructBuilder::UpdateStruct(ConstantEmitter
&Emitter,
// ConstExprEmitter
//===--===//
-static ConstantAddress tryEmitGlobalCompoundLiteral(CodeGenModule &CGM,
-CodeGenFunction *CGF,
- const CompoundLiteralExpr *E) {
+static ConstantAddress
+tryEmitGlobalCompoundLiteral(ConstantEmitter &emitter,
+ const CompoundLiteralExpr *E) {
+ CodeGenModule &CGM = emitter.CGM;
CharUnits Align = CGM.getContext().getTypeAlignInChars(E->getType());
if (llvm::GlobalVariable *Addr =
CGM.getAddrOfConstantCompoundLiteralIfEmitted(E))
return ConstantAddress(Addr, Addr->getValueType(), Align);
LangAS addressSpace = E->getType().getAddressSpace();
-
- ConstantEmitter emitter(CGM, CGF);
llvm::Constant *C = emitter.tryEmitForInitializer(E->getInitializer(),
addressSpace,
E->getType());
if (!C) {
@@ -1967,7 +1966,9 @@ ConstantLValueEmitter::VisitConstantExpr(const
ConstantExpr *E) {
ConstantLValue
ConstantLValueEmitter::VisitCompoundLiteralExpr(const CompoundLiteralExpr *E) {
- return tryEmitGlobalCompoundLiteral(CGM, Emitter.CGF, E);
+ ConstantEmitter CompoundLiteralEmitter(CGM, Emitter.CGF);
+ CompoundLiteralEmitter.setInConstantContext(Emitter.isInConstantContext());
+ return tryEmitGlobalCompoundLiteral(CompoundLiteralEmitter, E);
}
ConstantLValue
@@ -2211,7 +2212,8 @@ void CodeGenModule::setAddrOfConstantCompoundLiteral(
ConstantAddress
CodeGenModule::GetAddrOfConstantCompoundLiteral(const CompoundLiteralExpr *E) {
assert(E->isFileScope() && "not a file-scope compound literal expr");
- return tryEmitGlobalCompoundLiteral(*this, nullptr, E);
+ ConstantEmitter emitter(*this);
+ return tryEmitGlobalCompoundLiteral(emitter, E);
}
llvm::Constant *
diff --git a/clang/lib/CodeGen/ConstantEmitter.h
b/clang/lib/CodeGen/ConstantEmitter.h
index 188b82e56f536..1a7a181ca7f03 100644
--- a/clang/lib/CodeGen/ConstantEmitter.h
+++ b/clang/lib/CodeGen/ConstantEmitter.h
@@ -67,6 +67,9 @@ class ConstantEmitter {
return Abstract;
}
+ bool isInConstantContext() const { return InConstantContext; }
+ void setInConstantContext(bool var) { InConstantContext = var; }
+
/// Try to emit the initiaizer of the given declaration as an abstract
/// constant. If this succeeds, the emission must be finalized.
llvm::Constant *tryEmitForInitializer(const VarDecl &D);
diff --git a/clang/test/CodeGen/const-init.c b/clang/test/CodeGen/const-init.c
index 551c63e3a4be0..4748d71dca966 100644
--- a/clang/test/CodeGen/const-init.c
+++ b/clang/test/CodeGen/const-init.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu
-ffreestanding -Wno-pointer-to-int-cast -Wno-int-conversion -emit-llvm -o - %s
| FileCheck %s
+// setting strict FP behaviour in the run line below tests that the compiler
+// does the right thing for global compound literals (compoundliteral test)
+// RUN: %clang_cc1 -no-opaque-pointers -triple i386-pc-linux-gnu
-ffreestanding -Wno-pointer-to-int-cast -Wn
[clang] 983f63f - [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support
Author: Ties Stuij
Date: 2022-11-16T10:20:14Z
New Revision: 983f63f7f0d1643eb138db004351a18d1b3e91a3
URL:
https://github.com/llvm/llvm-project/commit/983f63f7f0d1643eb138db004351a18d1b3e91a3
DIFF:
https://github.com/llvm/llvm-project/commit/983f63f7f0d1643eb138db004351a18d1b3e91a3.diff
LOG: [AArch64][ARM] add Armv8.9-a/Armv9.4-a identifier support
For both ARM and AArch64 add support for specifying -march=armv8.9a/armv9.4a to
clang. Add backend plumbing like target parser and predicate support.
For a summary of Amv8.9/Armv9.4 features, see:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022
For detailed information, consult the Arm Architecture Reference Manual for
A-profile architecture:
https://developer.arm.com/documentation/ddi0487/latest/
People who contributed to this patch:
- Keith Walker
- Ties Stuij
Reviewed By: tmatheson
Differential Revision: https://reviews.llvm.org/D138010
Added:
clang/test/Driver/aarch64-v89a.c
clang/test/Driver/aarch64-v94a.c
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
clang/lib/Basic/Targets/ARM.cpp
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
clang/test/Driver/arm-cortex-cpus-1.c
clang/test/Preprocessor/arm-target-features.c
llvm/include/llvm/ADT/Triple.h
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/ARMTargetParser.def
llvm/lib/Support/ARMTargetParser.cpp
llvm/lib/Support/ARMTargetParserCommon.cpp
llvm/lib/Support/Triple.cpp
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index c070462bc5d1f..c283aca85f4e2 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -50,6 +50,7 @@ static StringRef getArchVersionString(llvm::AArch64::ArchKind
Kind) {
case llvm::AArch64::ArchKind::ARMV9_1A:
case llvm::AArch64::ArchKind::ARMV9_2A:
case llvm::AArch64::ArchKind::ARMV9_3A:
+ case llvm::AArch64::ArchKind::ARMV9_4A:
return "9";
default:
return "8";
@@ -235,6 +236,12 @@ void AArch64TargetInfo::getTargetDefinesARMV88A(const
LangOptions &Opts,
getTargetDefinesARMV87A(Opts, Builder);
}
+void AArch64TargetInfo::getTargetDefinesARMV89A(const LangOptions &Opts,
+MacroBuilder &Builder) const {
+ // Also include the Armv8.8 defines
+ getTargetDefinesARMV88A(Opts, Builder);
+}
+
void AArch64TargetInfo::getTargetDefinesARMV9A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Armv9-A maps to Armv8.5-A
@@ -259,6 +266,12 @@ void AArch64TargetInfo::getTargetDefinesARMV93A(const
LangOptions &Opts,
getTargetDefinesARMV88A(Opts, Builder);
}
+void AArch64TargetInfo::getTargetDefinesARMV94A(const LangOptions &Opts,
+MacroBuilder &Builder) const {
+ // Armv9.4-A maps to Armv8.9-A
+ getTargetDefinesARMV89A(Opts, Builder);
+}
+
void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Target identification.
@@ -473,6 +486,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
case llvm::AArch64::ArchKind::ARMV8_8A:
getTargetDefinesARMV88A(Opts, Builder);
break;
+ case llvm::AArch64::ArchKind::ARMV8_9A:
+getTargetDefinesARMV89A(Opts, Builder);
+break;
case llvm::AArch64::ArchKind::ARMV9A:
getTargetDefinesARMV9A(Opts, Builder);
break;
@@ -485,6 +501,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
case llvm::AArch64::ArchKind::ARMV9_3A:
getTargetDefinesARMV93A(Opts, Builder);
break;
+ case llvm::AArch64::ArchKind::ARMV9_4A:
+getTargetDefinesARMV94A(Opts, Builder);
+break;
}
// All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
@@ -658,6 +677,8 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
ArchKind = llvm::AArch64::ArchKind::ARMV8_7A;
if (Feature == "+v8.8a" && ArchKind < llvm::AArch64::ArchKind::ARMV8_8A)
ArchKind = llvm::AArch64::ArchKind::ARMV8_8A;
+if (Feature == "+v8.9a" && ArchKind < llvm::AArch64::ArchKind::ARMV8_9A)
+ ArchKind = llvm::AArch64::ArchKind::ARMV8_9A;
if (Feature == "+v9a" && ArchKind < llvm::AArch64::ArchKind::ARMV9A)
ArchKind = llvm::AArch64::ArchKind::ARMV9A;
if (Feature == "+v9.1a" && ArchKind < llvm::AArch64::ArchKind::AR
[clang] 479955a - [ARM] Allow codegen for Armv6m eXecute-Only (XO) sections
Author: Ties Stuij
Date: 2023-08-09T14:16:11+01:00
New Revision: 479955a42a71242e3577c639ca276c75f1a3c2b2
URL:
https://github.com/llvm/llvm-project/commit/479955a42a71242e3577c639ca276c75f1a3c2b2
DIFF:
https://github.com/llvm/llvm-project/commit/479955a42a71242e3577c639ca276c75f1a3c2b2.diff
LOG: [ARM] Allow codegen for Armv6m eXecute-Only (XO) sections
This patch moves the overall lower-bound arch restriction for Arm XO sections
from v8m to v6m. Actual implementation of code-gen for v6m will follow in
follow-up patches, which will include an implementation of relocations needed to
support this.
Reviewed By: simonwallis2, MaskRay
Differential Revision: https://reviews.llvm.org/D149444
Added:
Modified:
clang/lib/Driver/ToolChains/Arch/ARM.cpp
clang/test/Driver/arm-execute-only.c
Removed:
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index 1893bde99cd8bf..dad1e9e5bd3304 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -844,7 +844,8 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver
&D,
if (Arg *A = Args.getLastArg(options::OPT_mexecute_only,
options::OPT_mno_execute_only)) {
if (A->getOption().matches(options::OPT_mexecute_only)) {
if (getARMSubArchVersionNumber(Triple) < 7 &&
-llvm::ARM::parseArch(Triple.getArchName()) !=
llvm::ARM::ArchKind::ARMV6T2)
+llvm::ARM::parseArch(Triple.getArchName()) !=
llvm::ARM::ArchKind::ARMV6T2 &&
+llvm::ARM::parseArch(Triple.getArchName()) !=
llvm::ARM::ArchKind::ARMV6M)
D.Diag(diag::err_target_unsupported_execute_only) <<
Triple.getArchName();
else if (Arg *B = Args.getLastArg(options::OPT_mno_movt))
D.Diag(diag::err_opt_not_valid_with_opt)
diff --git a/clang/test/Driver/arm-execute-only.c
b/clang/test/Driver/arm-execute-only.c
index f69571de10c2ac..3c3af5fd690db4 100644
--- a/clang/test/Driver/arm-execute-only.c
+++ b/clang/test/Driver/arm-execute-only.c
@@ -1,19 +1,22 @@
-// RUN: not %clang -c -target thumbv6m-eabi -mexecute-only %s 2>&1 | \
+// RUN: %clang -c -fdriver-only -Werror --target=arm-arm-none-eabi \
+// RUN: -march=armv6-m -mexecute-only %s 2>&1 | count 0
+
+// RUN: not %clang -### -c --target=arm-arm-none-eabi -march=armv6
-mexecute-only %s 2>&1 |\
// RUN: FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
-// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for
the thumbv6m sub-architecture
+// CHECK-EXECUTE-ONLY-NOT-SUPPORTED: error: execute only is not supported for
the armv6 sub-architecture
-// RUN: not %clang -target armv8m.main-eabi -mexecute-only -mno-movt %s 2>&1 \
+// RUN: not %clang -### --target=arm-arm-none-eabi -march=armv8-m.main
-mexecute-only -mno-movt %s 2>&1 \
// RUN:| FileCheck %s -check-prefix CHECK-EXECUTE-ONLY-NO-MOVT
// CHECK-EXECUTE-ONLY-NO-MOVT: error: option '-mexecute-only' cannot be
specified with '-mno-movt'
-// RUN: %clang -target armv7m-eabi -x assembler -mexecute-only %s -c -### 2>&1
\
+// RUN: %clang -### --target=arm-arm-none-eabi -march=armv7-m -x assembler
-mexecute-only %s -c -### 2>&1 \
// RUN:| FileCheck %s --check-prefix=CHECK-NO-EXECUTE-ONLY-ASM
// CHECK-NO-EXECUTE-ONLY-ASM: warning: argument unused during compilation:
'-mexecute-only'
// -mpure-code flag for GCC compatibility
-// RUN: not %clang -c -target thumbv6m-eabi -mpure-code %s 2>&1 | \
+// RUN: not %clang -### -c --target=arm-arm-none-eabi -march=armv6 -mpure-code
%s 2>&1 | \
// RUN: FileCheck --check-prefix CHECK-EXECUTE-ONLY-NOT-SUPPORTED %s
-// RUN: not %clang -target armv8m.main-eabi -mpure-code -mno-movt %s 2>&1 \
+// RUN: not %clang -### --target=arm-arm-none-eabi -march=armv8-m.main
-mpure-code -mno-movt %s 2>&1 \
// RUN:| FileCheck %s -check-prefix CHECK-PURE-CODE-NO-MOVT
// CHECK-PURE-CODE-NO-MOVT: error: option '-mpure-code' cannot be specified
with '-mno-movt'
___
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[clang] cb261e3 - [AArch64][clang] implement 2022 General Data-Processing instructions
Author: Ties Stuij Date: 2022-11-22T14:23:12Z New Revision: cb261e30fbb174085d2eea4f4afc3cef2838b7f7 URL: https://github.com/llvm/llvm-project/commit/cb261e30fbb174085d2eea4f4afc3cef2838b7f7 DIFF: https://github.com/llvm/llvm-project/commit/cb261e30fbb174085d2eea4f4afc3cef2838b7f7.diff LOG: [AArch64][clang] implement 2022 General Data-Processing instructions This patch implements the 2022 Architecture General Data-Processing Instructions They include: Common Short Sequence Compression (CSSC) instructions - scalar comparison instructions SMAX, SMIN, UMAX, UMIN (32/64 bits) with or without immediate - ABS (absolute), CNT (count non-zero bits), CTZ (count trailing zeroes) - command-line options for CSSC Associated with these instructions in the documentation is the Range Prefetch Memory (RPRFM) instruction, which signals to the memory system that data memory accesses from a specified range of addresses are likely to occur in the near future. The instruction lies in hint space, and is made unconditional. Specs for the individual instructions can be found here: https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/ contributors to this patch: - Cullen Rhodes - Son Tuan Vu - Mark Murray - Tomas Matheson - Sam Elliott - Ties Stuij Reviewed By: lenary Differential Revision: https://reviews.llvm.org/D138488 Added: clang/test/Driver/aarch64-cssc.c llvm/test/MC/AArch64/CSSC/abs_32.s llvm/test/MC/AArch64/CSSC/abs_64.s llvm/test/MC/AArch64/CSSC/cnt_32.s llvm/test/MC/AArch64/CSSC/cnt_64.s llvm/test/MC/AArch64/CSSC/ctz_32.s llvm/test/MC/AArch64/CSSC/ctz_64.s llvm/test/MC/AArch64/CSSC/smax_32_imm.s llvm/test/MC/AArch64/CSSC/smax_32_reg.s llvm/test/MC/AArch64/CSSC/smax_64_imm.s llvm/test/MC/AArch64/CSSC/smax_64_reg.s llvm/test/MC/AArch64/CSSC/smin_32_imm.s llvm/test/MC/AArch64/CSSC/smin_32_reg.s llvm/test/MC/AArch64/CSSC/smin_64_imm.s llvm/test/MC/AArch64/CSSC/smin_64_reg.s llvm/test/MC/AArch64/CSSC/umax_32_imm.s llvm/test/MC/AArch64/CSSC/umax_32_reg.s llvm/test/MC/AArch64/CSSC/umax_64_imm.s llvm/test/MC/AArch64/CSSC/umax_64_reg.s llvm/test/MC/AArch64/CSSC/umin_32_imm.s llvm/test/MC/AArch64/CSSC/umin_32_reg.s llvm/test/MC/AArch64/CSSC/umin_64_imm.s llvm/test/MC/AArch64/CSSC/umin_64_reg.s llvm/test/MC/AArch64/armv8.9a-cssc.s llvm/test/MC/AArch64/rprfm.s llvm/test/MC/Disassembler/AArch64/armv8.9a-cssc.txt Modified: llvm/include/llvm/Support/AArch64TargetParser.def llvm/include/llvm/Support/AArch64TargetParser.h llvm/lib/Target/AArch64/AArch64.td llvm/lib/Target/AArch64/AArch64InstrFormats.td llvm/lib/Target/AArch64/AArch64InstrInfo.td llvm/lib/Target/AArch64/AArch64SystemOperands.td llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h llvm/lib/Target/AArch64/SVEInstrFormats.td llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h llvm/unittests/Support/TargetParserTest.cpp Removed: diff --git a/clang/test/Driver/aarch64-cssc.c b/clang/test/Driver/aarch64-cssc.c new file mode 100644 index 0..0ecda98d69504 --- /dev/null +++ b/clang/test/Driver/aarch64-cssc.c @@ -0,0 +1,15 @@ +// Test that target feature cssc is implemented and available correctly +// RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc %s 2>&1 | FileCheck %s +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a%s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc %s 2>&1 | FileCheck %s +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc %s 2>&1 | FileCheck %s +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a%s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc %s 2>&1 | FileCheck %s +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC + +// CHECK: "-target-feature" "+cssc" +// NO_CSSC: "-target-feature" "-cssc" +// ABSENT_CSSC-NOT: "-target-feature" "+cssc" +// ABSENT_CSSC-NOT: "-target-feature" "-cssc" diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def b/llvm/include/llvm/Support/AArch64TargetParser.def index 5f6ef92a14ed6..f016c9147a7bb 100644 --- a/llvm/include/llvm/Suppor
[clang] 71ae267 - [PATCH] [ARM] ARMv8.6-a command-line + BFloat16 Asm Support
Author: Ties Stuij
Date: 2020-03-26T09:17:20Z
New Revision: 71ae267d1f4117473eb00d9fd3391733b843ca3c
URL:
https://github.com/llvm/llvm-project/commit/71ae267d1f4117473eb00d9fd3391733b843ca3c
DIFF:
https://github.com/llvm/llvm-project/commit/71ae267d1f4117473eb00d9fd3391733b843ca3c.diff
LOG: [PATCH] [ARM] ARMv8.6-a command-line + BFloat16 Asm Support
Summary:
This patch introduces command-line support for the Armv8.6-a architecture and
assembly support for BFloat16. Details can be found
https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a
in addition to the GCC patch for the 8..6-a CLI:
https://gcc.gnu.org/legacy-ml/gcc-patches/2019-11/msg02647.html
In detail this patch
- march options for armv8.6-a
- BFloat16 assembly
This is part of a patch series, starting with command-line and Bfloat16
assembly support. The subsequent patches will upstream intrinsics
support for BFloat16, followed by Matrix Multiplication and the
remaining Virtualization features of the armv8.6-a architecture.
Based on work by:
- labrinea
- MarkMurrayARM
- Luke Cheeseman
- Javed Asbar
- Mikhail Maltsev
- Luke Geeson
Reviewers: SjoerdMeijer, craig.topper, rjmccall, jfb, LukeGeeson
Reviewed By: SjoerdMeijer
Subscribers: stuij, kristof.beyls, hiraditya, dexonsmith, danielkiss,
cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D76062
Added:
llvm/test/MC/AArch64/SVE/bfcvt-diagnostics.s
llvm/test/MC/AArch64/SVE/bfcvt.s
llvm/test/MC/AArch64/SVE/bfcvtnt-diagnostics.s
llvm/test/MC/AArch64/SVE/bfcvtnt.s
llvm/test/MC/AArch64/SVE/bfdot-diagnostics.s
llvm/test/MC/AArch64/SVE/bfdot.s
llvm/test/MC/AArch64/SVE/bfmlal-diagnostics.s
llvm/test/MC/AArch64/SVE/bfmlal.s
llvm/test/MC/AArch64/SVE/bfmmla-diagnostics.s
llvm/test/MC/AArch64/SVE/bfmmla.s
llvm/test/MC/AArch64/armv8.6a-bf16.s
llvm/test/MC/ARM/bfloat16-a32-errors.s
llvm/test/MC/ARM/bfloat16-a32-errors2.s
llvm/test/MC/ARM/bfloat16-a32.s
llvm/test/MC/ARM/bfloat16-t32-errors.s
llvm/test/MC/ARM/bfloat16-t32.s
llvm/test/MC/Disassembler/AArch64/armv8.6a-bf16.txt
llvm/test/MC/Disassembler/ARM/bfloat16-a32_1.txt
llvm/test/MC/Disassembler/ARM/bfloat16-a32_2.txt
llvm/test/MC/Disassembler/ARM/bfloat16-t32.txt
llvm/test/MC/Disassembler/ARM/bfloat16-t32_errors.txt
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
clang/lib/Basic/Targets/ARM.cpp
clang/test/Driver/aarch64-cpus.c
clang/test/Driver/arm-cortex-cpus.c
clang/test/Preprocessor/arm-target-features.c
llvm/include/llvm/ADT/Triple.h
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/include/llvm/Support/ARMTargetParser.def
llvm/include/llvm/Support/ARMTargetParser.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Support/ARMTargetParser.cpp
llvm/lib/Support/Triple.cpp
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMInstrNEON.td
llvm/lib/Target/ARM/ARMInstrVFP.td
llvm/lib/Target/ARM/ARMPredicates.td
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 74bb6900b19e..e7bfff504a7c 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -151,6 +151,7 @@ void AArch64TargetInfo::fillValidCPUList(
void AArch64TargetInfo::getTargetDefinesARMV81A(const LangOptions &Opts,
MacroBuilder &Builder) const {
+ // FIXME: Armv8.1 makes __ARM_FEATURE_CRC32 mandatory. Handle it here.
Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
}
@@ -171,17 +172,26 @@ void AArch64TargetInfo::getTargetDefinesARMV83A(const
LangOptions &Opts,
void AArch64TargetInfo::getTargetDefinesARMV84A(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Also include the Armv8.3 defines
- // FIXME: Armv8.4 makes some extensions mandatory. Handle them here.
+ // FIXME: Armv8.4 makes __ARM_FEATURE_ATOMICS, defined in GCC, mandatory.
+ // Add and handle it here.
getTargetDefinesARMV83A(Opts, Builder);
}
void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts,
[clang] [llvm] [AArch64] Add soft-float ABI (PR #74460)
https://github.com/stuij approved this pull request. This seems like a sensible and unobtrusive solution to me. Also the change is backed by a change in the Arm ABI, and it looks like the other review comments have been addressed. I've also built this change locally and ran the lit tests, and everything passes. https://github.com/llvm/llvm-project/pull/74460 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Arm][AArch64][Clang] Respect function's branch protection attributes. (PR #101978)
@@ -209,9 +209,28 @@ llvm::Value *TargetCodeGenInfo::createEnqueuedBlockKernel(
void TargetCodeGenInfo::setBranchProtectionFnAttributes(
const TargetInfo::BranchProtectionInfo &BPI, llvm::Function &F) {
- llvm::AttrBuilder FuncAttrs(F.getContext());
- setBranchProtectionFnAttributes(BPI, FuncAttrs);
- F.addFnAttrs(FuncAttrs);
+ if (BPI.SignReturnAddr != LangOptions::SignReturnAddressScopeKind::None) {
+F.addFnAttr("sign-return-address", BPI.getSignReturnAddrStr());
+F.addFnAttr("sign-return-address-key", BPI.getSignKeyStr());
+ } else {
+if (F.hasFnAttribute("sign-return-address"))
+ F.removeFnAttr("sign-return-address");
+if (F.hasFnAttribute("sign-return-address-key"))
+ F.removeFnAttr("sign-return-address-key");
+ }
+
+ auto AddRemoveAttributeAsSet = [&](bool Set, const StringRef &ModAttr) {
+if (Set)
+ F.addFnAttr(ModAttr);
+else if (F.hasFnAttribute(ModAttr))
+ F.removeFnAttr(ModAttr);
+ };
+
+ AddRemoveAttributeAsSet(BPI.BranchTargetEnforcement,
+ "branch-target-enforcement");
+ AddRemoveAttributeAsSet(BPI.BranchProtectionPAuthLR,
+ "branch-protection-pauth-lr");
+ AddRemoveAttributeAsSet(BPI.GuardedControlStack, "guarded-control-stack");
}
void TargetCodeGenInfo::setBranchProtectionFnAttributes(
stuij wrote:
I can see that this AttrBuilder version of the fn is still used in
`getTrivialDefaultFunctionAttributes` in `CGCall.cpp`. I guess in practice the
outcome would still be the same for this use case between old and new
implementation, but even if I didn't miss something it does feel a bit icky to
do so.
Perhaps add a comment to explain the code duplication?
https://github.com/llvm/llvm-project/pull/101978
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[clang] [Arm][AArch64][Clang] Respect function's branch protection attributes. (PR #101978)
https://github.com/stuij commented: LGTM, thanks! https://github.com/llvm/llvm-project/pull/101978 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 1adfbfc - Add info on PACBTI-M to the Clang release notes
Author: Ties Stuij
Date: 2022-01-31T19:01:25Z
New Revision: 1adfbfcf39f95106861ebe8a7b4245acb0bc6e69
URL:
https://github.com/llvm/llvm-project/commit/1adfbfcf39f95106861ebe8a7b4245acb0bc6e69
DIFF:
https://github.com/llvm/llvm-project/commit/1adfbfcf39f95106861ebe8a7b4245acb0bc6e69.diff
LOG: Add info on PACBTI-M to the Clang release notes
Differential Revision: https://reviews.llvm.org/D118380
Added:
Modified:
clang/docs/ReleaseNotes.rst
Removed:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 4b444bece68a7..3a42b4252ed73 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -77,6 +77,9 @@ New Compiler Flags
- Clang plugin arguments can now be passed through the compiler driver via
``-fplugin-arg-pluginname-arg``, similar to GCC's ``-fplugin-arg``.
+- The ``-mno-bti-at-return-twice`` flag will make sure a BTI instruction won't
+ be added after a setjmp or possible other return-twice construct (ARM backend
+ only).
Deprecated Compiler Flags
-
@@ -293,6 +296,11 @@ Arm and AArch64 Support in Clang
GNU driver. Programs that depend on clang invoking GCC as the linker driver
should use GCC as the linker in the build system.
+- The ``-mbranch-protection`` flag will now also work for the ARM backend.
+
+- The ``attribute((target("branch-protection=...)))`` attributes will now also
+ work for the ARM backend.
+
Floating Point Support in Clang
---
- The default setting of FP contraction (FMA) is now -ffp-contract=on (for
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[clang] 53154a8 - [ARM][clang] Add back branch protection tests
Author: Ties Stuij
Date: 2021-12-06T15:03:33Z
New Revision: 53154a83aee0ce969dc07e7168b3914ca1025030
URL:
https://github.com/llvm/llvm-project/commit/53154a83aee0ce969dc07e7168b3914ca1025030
DIFF:
https://github.com/llvm/llvm-project/commit/53154a83aee0ce969dc07e7168b3914ca1025030.diff
LOG: [ARM][clang] Add back branch protection tests
When committing the PACBTI-M frontend support
patch (https://reviews.llvm.org/D112421), the tests in
arm-invalid-branch-protection.c were failing on certain test setups, so it was
removed to make the llvm test suite pass. The fix is to require
arm-registered-target.
This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:
https://developer.arm.com/documentation/ddi0553/latest
Reviewed By: erichkeane
Differential Revision: https://reviews.llvm.org/D115141
Added:
clang/test/Frontend/arm-invalid-branch-protection.c
Modified:
Removed:
diff --git a/clang/test/Frontend/arm-invalid-branch-protection.c
b/clang/test/Frontend/arm-invalid-branch-protection.c
new file mode 100644
index 0..f7bbd5941b024
--- /dev/null
+++ b/clang/test/Frontend/arm-invalid-branch-protection.c
@@ -0,0 +1,7 @@
+// REQUIRES: arm-registered-target
+// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key -c
%s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi
-mbranch-protection=pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=bti+pac-ret+b-key
-c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi
-mbranch-protection=bti+pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck
%s
+
+// CHECK: warning: invalid branch protection option 'b-key' in
'-mbranch-protection={{[a-z+-]*}}' [-Wbranch-protection]
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[clang] e6d0b85 - [ARM][libunwind] add PACBTI-M support for libunwind
Author: Ties Stuij
Date: 2021-12-08T09:44:45Z
New Revision: e6d0b851f854849240bc1f02901b0dbb3be84388
URL:
https://github.com/llvm/llvm-project/commit/e6d0b851f854849240bc1f02901b0dbb3be84388
DIFF:
https://github.com/llvm/llvm-project/commit/e6d0b851f854849240bc1f02901b0dbb3be84388.diff
LOG: [ARM][libunwind] add PACBTI-M support for libunwind
This patch implements the following:
- Emit PACBTI-M build attributes in libunwind asm files
- Authenticate LR in DWARF32 using PACBTI
Use Armv8.1-M.Main PACBTI extension to authenticate the return address
(stored in the LR register) before moving it to the PC (IP) register.
The AUTG instruction is used with the candidate return address, the CFA,
and the authentication code that is retrieved from the saved
pseudo-register RA_AUTH_CODE.
- Authenticate LR in EHABI using PACBTI
Authenticate the contents of the LR register using Armv8.1-M.Main PACBTI
extension.
A new frame unwinding instruction is introduced (0xb4). This
instruction pops out of the stack the return address authentication
code, which is then used in conjunction with the SP and the next-to-be
instruction pointer to perform authentication.
This authentication code is popped into a new register,
UNW_ARM_PSEUDO_PAC, which is a pseudo-register.
This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:
https://developer.arm.com/documentation/ddi0553/latest
The following people contributed to this patch:
- Momchil Velikov
- Victor Campos
- Ties Stuij
Reviewed By: #libunwind, danielkiss, mstorsjo
Differential Revision: https://reviews.llvm.org/D112430
Added:
Modified:
clang/lib/Headers/unwind.h
libunwind/include/libunwind.h
libunwind/include/unwind_arm_ehabi.h
libunwind/src/DwarfInstructions.hpp
libunwind/src/Registers.hpp
libunwind/src/Unwind-EHABI.cpp
libunwind/src/UnwindCursor.hpp
libunwind/src/UnwindRegistersRestore.S
libunwind/src/assembly.h
Removed:
diff --git a/clang/lib/Headers/unwind.h b/clang/lib/Headers/unwind.h
index 029524b7bc84c..6e069798f02d6 100644
--- a/clang/lib/Headers/unwind.h
+++ b/clang/lib/Headers/unwind.h
@@ -172,7 +172,8 @@ typedef enum {
_UVRSC_CORE = 0,/* integer register */
_UVRSC_VFP = 1, /* vfp */
_UVRSC_WMMXD = 3, /* Intel WMMX data register */
- _UVRSC_WMMXC = 4/* Intel WMMX control register */
+ _UVRSC_WMMXC = 4, /* Intel WMMX control register */
+ _UVRSC_PSEUDO = 5 /* Special purpose pseudo register */
} _Unwind_VRS_RegClass;
typedef enum {
diff --git a/libunwind/include/libunwind.h b/libunwind/include/libunwind.h
index e187ee27b0dba..9a74faa48d6ff 100644
--- a/libunwind/include/libunwind.h
+++ b/libunwind/include/libunwind.h
@@ -718,7 +718,8 @@ enum {
UNW_ARM_WR14 = 126,
UNW_ARM_WR15 = 127,
// 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC}
- // 134-143 -- Reserved
+ // 134-142 -- Reserved
+ UNW_ARM_RA_AUTH_CODE = 143,
// 144-150 -- R8_USR-R14_USR
// 151-157 -- R8_FIQ-R14_FIQ
// 158-159 -- R13_IRQ-R14_IRQ
diff --git a/libunwind/include/unwind_arm_ehabi.h
b/libunwind/include/unwind_arm_ehabi.h
index dc9d403e264cf..6277a1457f896 100644
--- a/libunwind/include/unwind_arm_ehabi.h
+++ b/libunwind/include/unwind_arm_ehabi.h
@@ -87,10 +87,11 @@ extern void _Unwind_Resume(_Unwind_Exception
*exception_object);
extern void _Unwind_DeleteException(_Unwind_Exception *exception_object);
typedef enum {
- _UVRSC_CORE = 0, /* integer register */
- _UVRSC_VFP = 1, /* vfp */
+ _UVRSC_CORE = 0, /* integer register */
+ _UVRSC_VFP = 1, /* vfp */
_UVRSC_WMMXD = 3, /* Intel WMMX data register */
- _UVRSC_WMMXC = 4 /* Intel WMMX control register */
+ _UVRSC_WMMXC = 4, /* Intel WMMX control register */
+ _UVRSC_PSEUDO = 5 /* Special purpose pseudo register */
} _Unwind_VRS_RegClass;
typedef enum {
diff --git a/libunwind/src/DwarfInstructions.hpp
b/libunwind/src/DwarfInstructions.hpp
index 19835aad668f9..1c50941680b33 100644
--- a/libunwind/src/DwarfInstructions.hpp
+++ b/libunwind/src/DwarfInstructions.hpp
@@ -242,6 +242,20 @@ int DwarfInstructions::stepWithDwarf(A
&addressSpace, pint_t pc,
}
#endif
+#if defined(_LIBUNWIND_IS_NATIVE_ONLY) && defined(_LIBUNWIND_TARGET_ARM) &&
\
+defined(__ARM_FEATURE_PAUTH)
+ if ((R::getArch() == REGISTERS_ARM) &&
+ prolog.savedRegisters[UNW_ARM_RA_AUTH_CODE].value) {
+pint_t pac =
+getSavedRegister(addressSpace, registers, cfa,
+ prolog.savedRegisters[UNW_ARM_RA_AUTH_CODE]);
+__asm__ __volatile__("autg %0, %1, %2"
[clang] e32b818 - [ARM][clang] Define feature test macro for the PACBTI-M extension
Author: Ties Stuij
Date: 2021-12-09T10:39:06Z
New Revision: e32b818db187a6519ee5eba47e8d7dae1d58a723
URL:
https://github.com/llvm/llvm-project/commit/e32b818db187a6519ee5eba47e8d7dae1d58a723
DIFF:
https://github.com/llvm/llvm-project/commit/e32b818db187a6519ee5eba47e8d7dae1d58a723.diff
LOG: [ARM][clang] Define feature test macro for the PACBTI-M extension
If the extension string "+pacbti" was given in -march=... or -mcpu=... options
the compiler shall define the following preprocessor macros:
__ARM_FEATURE_PAUTH with value 1.
__ARM_FEATURE_BTI with value 1.
This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:
https://developer.arm.com/documentation/ddi0553/latest
The following people contributed to this patch:
- Momchil Velikov
- Ties Stuij
Reviewed By: miyuki
Differential Revision: https://reviews.llvm.org/D112431
Added:
Modified:
clang/lib/Basic/Targets/ARM.cpp
clang/lib/Basic/Targets/ARM.h
clang/test/Preprocessor/arm-target-features.c
Removed:
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index f330780300f29..81b79cfe19e47 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -465,6 +465,8 @@ bool
ARMTargetInfo::handleTargetFeatures(std::vector &Features,
HWDiv = 0;
DotProd = 0;
HasMatMul = 0;
+ HasPAC = 0;
+ HasBTI = 0;
HasFloat16 = true;
ARMCDECoprocMask = 0;
HasBFloat16 = false;
@@ -547,6 +549,9 @@ bool
ARMTargetInfo::handleTargetFeatures(std::vector &Features,
HasBFloat16 = true;
} else if (Feature == "-fpregs") {
FPRegsDisabled = true;
+} else if (Feature == "+pacbti") {
+ HasPAC = 1;
+ HasBTI = 1;
}
}
@@ -890,6 +895,12 @@ void ARMTargetInfo::getTargetDefines(const LangOptions
&Opts,
if (HasMatMul)
Builder.defineMacro("__ARM_FEATURE_MATMUL_INT8", "1");
+ if (HasPAC)
+Builder.defineMacro("__ARM_FEATURE_PAUTH", "1");
+
+ if (HasBTI)
+Builder.defineMacro("__ARM_FEATURE_BTI", "1");
+
if (HasBFloat16) {
Builder.defineMacro("__ARM_FEATURE_BF16", "1");
Builder.defineMacro("__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", "1");
diff --git a/clang/lib/Basic/Targets/ARM.h b/clang/lib/Basic/Targets/ARM.h
index f939904f8d8c5..40c658f3f40e2 100644
--- a/clang/lib/Basic/Targets/ARM.h
+++ b/clang/lib/Basic/Targets/ARM.h
@@ -79,6 +79,8 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public
TargetInfo {
unsigned DotProd : 1;
unsigned HasMatMul : 1;
unsigned FPRegsDisabled : 1;
+ unsigned HasPAC : 1;
+ unsigned HasBTI : 1;
enum {
LDREX_B = (1 << 0), /// byte (8-bit)
diff --git a/clang/test/Preprocessor/arm-target-features.c
b/clang/test/Preprocessor/arm-target-features.c
index 7fb3323cd4092..49a5516e15d0d 100644
--- a/clang/test/Preprocessor/arm-target-features.c
+++ b/clang/test/Preprocessor/arm-target-features.c
@@ -896,6 +896,13 @@
// CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 5
// CHECK-PAC-BKEY-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 6
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s
-o - | FileCheck --check-prefixes=CHECK-NOBTI-EXT,CHECK-NOPAC-EXT %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv7-m+pacbti -x c -E -dM %s
-o - | FileCheck --check-prefixes=CHECK-PACBTI-EXT %s
+// CHECK-NOBTI-EXT-NOT: #define __ARM_FEATURE_BTI 1
+// CHECK-NOPAC-EXT-NOT: #define __ARM_FEATURE_PAUTH 1
+// CHECK-PACBTI-EXT: #define __ARM_FEATURE_BTI 1
+// CHECK-PACBTI-EXT: #define __ARM_FEATURE_PAUTH 1
+
// == Check BFloat16 Extensions.
// RUN: %clang -target arm-arm-none-eabi -march=armv8.6-a+bf16 -x c -E -dM %s
-o - 2>&1 | FileCheck -check-prefix=CHECK-BFLOAT %s
// CHECK-BFLOAT: #define __ARM_BF16_FORMAT_ALTERNATIVE 1
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[clang] bfe0719 - [ARM][clang] Option b-key must not affect __ARM_FEATURE_PAC_DEFAULT
Author: Ties Stuij
Date: 2021-12-09T13:37:52Z
New Revision: bfe07195bb1f517b2809107098b91767ad8c9460
URL:
https://github.com/llvm/llvm-project/commit/bfe07195bb1f517b2809107098b91767ad8c9460
DIFF:
https://github.com/llvm/llvm-project/commit/bfe07195bb1f517b2809107098b91767ad8c9460.diff
LOG: [ARM][clang] Option b-key must not affect __ARM_FEATURE_PAC_DEFAULT
When using -mbranch-protection=pac-ret+b-key, macro __ARM_FEATURE_PAC_DEFAULT
should still have the value corresponding to a-key, because b-key is only valid
for AArch64.
This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:
https://developer.arm.com/documentation/ddi0553/latest
The following people contributed to this patch:
- Victor Campos
Reviewed By: danielkiss
Differential Revision: https://reviews.llvm.org/D115140
Added:
Modified:
clang/lib/Basic/Targets/ARM.cpp
clang/test/Preprocessor/arm-target-features.c
Removed:
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index 81b79cfe19e47..c619d6cde41df 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -911,7 +911,7 @@ void ARMTargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
if (Opts.hasSignReturnAddress()) {
-unsigned Value = Opts.isSignReturnAddressWithAKey() ? 1 : 2;
+unsigned Value = 1;
if (Opts.isSignReturnAddressScopeAll())
Value |= 1 << 2;
Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", Twine(Value));
diff --git a/clang/test/Preprocessor/arm-target-features.c
b/clang/test/Preprocessor/arm-target-features.c
index 49a5516e15d0d..bf4e7c41e3e23 100644
--- a/clang/test/Preprocessor/arm-target-features.c
+++ b/clang/test/Preprocessor/arm-target-features.c
@@ -881,20 +881,18 @@
// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s
-o - | FileCheck --check-prefixes=CHECK-NOBTI,CHECK-NOPAC %s
// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=bti -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-BTI,CHECK-NOPAC %s
// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=pac-ret -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC-BKEY,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC,CHECK-NOBTI %s
// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=pac-ret+leaf -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-NOBTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC-LEAF,CHECK-NOBTI %s
// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=bti+pac-ret -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC,CHECK-BTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC-BKEY,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=bti+pac-ret+b-key -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC,CHECK-BTI %s
// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=bti+pac-ret+leaf -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
-// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC-BKEY-LEAF,CHECK-BTI %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main
-mbranch-protection=bti+pac-ret+b-key+leaf -x c -E -dM %s -o - | FileCheck
--check-prefixes=CHECK-PAC-LEAF,CHECK-BTI %s
// CHECK-NOBTI-NOT: #define __ARM_FEATURE_BTI_DEFAULT
// CHECK-NOPAC-NOT: #define __ARM_FEATURE_PAC_DEFAULT
// CHECK-BTI: #define __ARM_FEATURE_BTI_DEFAULT 1
// CHECK-PAC: #define __ARM_FEATURE_PAC_DEFAULT 1
-// CHECK-PAC-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 2
// CHECK-PAC-LEAF: #define __ARM_FEATURE_PAC_DEFAUL
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
stuij wrote: I feel that in `useFramePointerForTargetByDef` fn, in general things are predicated first on platform and then on arch. That L85 arch switch statement seems to serve as a "these arches don't do anything special" early return. It's up to interpretation, but putting the different Arm variants there seems less elegant to me (that might not be saying much..). I'd say let's leave it alone for now, and if the bare metal logic gets more impenetrable at some point, refactor. https://github.com/llvm/llvm-project/pull/117140 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
https://github.com/stuij updated
https://github.com/llvm/llvm-project/pull/117140
>From 4a85a0cd98bf328f31465d47c56640abdf7ec08c Mon Sep 17 00:00:00 2001
From: Ties Stuij
Date: Fri, 15 Nov 2024 13:19:08 +
Subject: [PATCH 1/6] [clang][ARM] disable frame pointers by default for bare
metal ARM targets
because:
- This brings Clang in line with GCC for which this is the default for ARM
- It frees up a register, so performance increase, especially on Thumb/6-M
- It will also decrease code size
---
clang/lib/Driver/ToolChains/BareMetal.cpp | 8 +-
clang/lib/Driver/ToolChains/BareMetal.h| 2 ++
clang/lib/Driver/ToolChains/CommonArgs.cpp | 5
clang/test/Driver/frame-pointer-elim.c | 29 ++
4 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index f9a73f60973e4c..13b510e7e70994 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -128,8 +128,11 @@ BareMetal::BareMetal(const Driver &D, const llvm::Triple
&Triple,
}
}
+namespace clang {
+namespace driver {
+namespace toolchains {
/// Is the triple {arm,armeb,thumb,thumbeb}-none-none-{eabi,eabihf} ?
-static bool isARMBareMetal(const llvm::Triple &Triple) {
+bool isARMBareMetal(const llvm::Triple &Triple) {
if (Triple.getArch() != llvm::Triple::arm &&
Triple.getArch() != llvm::Triple::thumb &&
Triple.getArch() != llvm::Triple::armeb &&
@@ -148,6 +151,9 @@ static bool isARMBareMetal(const llvm::Triple &Triple) {
return true;
}
+} // namespace clang
+} // namespace driver
+} // namespace clang
/// Is the triple {aarch64.aarch64_be}-none-elf?
static bool isAArch64BareMetal(const llvm::Triple &Triple) {
diff --git a/clang/lib/Driver/ToolChains/BareMetal.h
b/clang/lib/Driver/ToolChains/BareMetal.h
index b385c8cf76aab0..ae09bcedd78a28 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.h
+++ b/clang/lib/Driver/ToolChains/BareMetal.h
@@ -19,6 +19,8 @@ namespace driver {
namespace toolchains {
+bool isARMBareMetal(const llvm::Triple &Triple);
+
class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain {
public:
BareMetal(const Driver &D, const llvm::Triple &Triple,
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 8d977149e62485..8d54d0a8649cc9 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -19,6 +19,7 @@
#include "Arch/SystemZ.h"
#include "Arch/VE.h"
#include "Arch/X86.h"
+#include "BareMetal.h"
#include "HIPAMD.h"
#include "Hexagon.h"
#include "MSP430.h"
@@ -151,6 +152,10 @@ static bool useFramePointerForTargetByDefault(const
llvm::opt::ArgList &Args,
}
}
+ if (toolchains::isARMBareMetal(Triple)) {
+return false;
+ }
+
return true;
}
diff --git a/clang/test/Driver/frame-pointer-elim.c
b/clang/test/Driver/frame-pointer-elim.c
index cdedcc7ae4c89f..667c47b34bc703 100644
--- a/clang/test/Driver/frame-pointer-elim.c
+++ b/clang/test/Driver/frame-pointer-elim.c
@@ -162,5 +162,34 @@
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
// RUN: not %clang -### --target=riscv64-linux-android -mbig-endian -O1 -S %s
2>&1 | \
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+
+// On ARM backend bare metal targets, frame pointer is omitted
+// RUN: %clang -### --target=arm-arm-none-eabi -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -O1 -fno-omit-frame-pointer
%s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -O1
-fno-omit-frame-pointer %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+
+// AArch64 bare metal targets behave like hosted targets
+// RUN: %clang -### --target=aarch64-none-elf -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -O1 -fno-omit-frame-pointer
%s 2>&1 | \
+// RUN: FileCheck --check-prefix=KE
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
@@ -151,6 +152,9 @@ static bool useFramePointerForTargetByDefault(const llvm::opt::ArgList &Args, } } + if (toolchains::isARMBareMetal(Triple)) stuij wrote: done! https://github.com/llvm/llvm-project/pull/117140 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
@@ -148,6 +151,9 @@ static bool isARMBareMetal(const llvm::Triple &Triple) {
return true;
}
+} // namespace clang
stuij wrote:
thanks! done!
https://github.com/llvm/llvm-project/pull/117140
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[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
@@ -151,6 +152,9 @@ static bool useFramePointerForTargetByDefault(const llvm::opt::ArgList &Args, } } + if (toolchains::isARMBareMetal(Triple)) stuij wrote: Perhaps renaming `isARMBareMetal` to `isEABIBareMetal` would make things clearer? https://github.com/llvm/llvm-project/pull/117140 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
@@ -151,6 +152,9 @@ static bool useFramePointerForTargetByDefault(const llvm::opt::ArgList &Args, } } + if (toolchains::isARMBareMetal(Triple)) stuij wrote: `isArmEABIBareMetal`? https://github.com/llvm/llvm-project/pull/117140 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
@@ -151,6 +152,9 @@ static bool useFramePointerForTargetByDefault(const llvm::opt::ArgList &Args, } } + if (toolchains::isARMBareMetal(Triple)) stuij wrote: Hi @jroelofs, adding the check for Apple shouldn't be necessary. `isARMBareMetal` is trying to stay in it's lane by only returning true if the vendor is `none` and the environment is `eabi` or `eabihf`. >From grepping the LLVM tests I understand the Apple firmware triple would be >something like `arm/thumb-apple-none-macho`, correct? I've added a number of >tests to cover this. https://github.com/llvm/llvm-project/pull/117140 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
https://github.com/stuij updated
https://github.com/llvm/llvm-project/pull/117140
>From 4a85a0cd98bf328f31465d47c56640abdf7ec08c Mon Sep 17 00:00:00 2001
From: Ties Stuij
Date: Fri, 15 Nov 2024 13:19:08 +
Subject: [PATCH 1/5] [clang][ARM] disable frame pointers by default for bare
metal ARM targets
because:
- This brings Clang in line with GCC for which this is the default for ARM
- It frees up a register, so performance increase, especially on Thumb/6-M
- It will also decrease code size
---
clang/lib/Driver/ToolChains/BareMetal.cpp | 8 +-
clang/lib/Driver/ToolChains/BareMetal.h| 2 ++
clang/lib/Driver/ToolChains/CommonArgs.cpp | 5
clang/test/Driver/frame-pointer-elim.c | 29 ++
4 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index f9a73f60973e4c..13b510e7e70994 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -128,8 +128,11 @@ BareMetal::BareMetal(const Driver &D, const llvm::Triple
&Triple,
}
}
+namespace clang {
+namespace driver {
+namespace toolchains {
/// Is the triple {arm,armeb,thumb,thumbeb}-none-none-{eabi,eabihf} ?
-static bool isARMBareMetal(const llvm::Triple &Triple) {
+bool isARMBareMetal(const llvm::Triple &Triple) {
if (Triple.getArch() != llvm::Triple::arm &&
Triple.getArch() != llvm::Triple::thumb &&
Triple.getArch() != llvm::Triple::armeb &&
@@ -148,6 +151,9 @@ static bool isARMBareMetal(const llvm::Triple &Triple) {
return true;
}
+} // namespace clang
+} // namespace driver
+} // namespace clang
/// Is the triple {aarch64.aarch64_be}-none-elf?
static bool isAArch64BareMetal(const llvm::Triple &Triple) {
diff --git a/clang/lib/Driver/ToolChains/BareMetal.h
b/clang/lib/Driver/ToolChains/BareMetal.h
index b385c8cf76aab0..ae09bcedd78a28 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.h
+++ b/clang/lib/Driver/ToolChains/BareMetal.h
@@ -19,6 +19,8 @@ namespace driver {
namespace toolchains {
+bool isARMBareMetal(const llvm::Triple &Triple);
+
class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain {
public:
BareMetal(const Driver &D, const llvm::Triple &Triple,
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 8d977149e62485..8d54d0a8649cc9 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -19,6 +19,7 @@
#include "Arch/SystemZ.h"
#include "Arch/VE.h"
#include "Arch/X86.h"
+#include "BareMetal.h"
#include "HIPAMD.h"
#include "Hexagon.h"
#include "MSP430.h"
@@ -151,6 +152,10 @@ static bool useFramePointerForTargetByDefault(const
llvm::opt::ArgList &Args,
}
}
+ if (toolchains::isARMBareMetal(Triple)) {
+return false;
+ }
+
return true;
}
diff --git a/clang/test/Driver/frame-pointer-elim.c
b/clang/test/Driver/frame-pointer-elim.c
index cdedcc7ae4c89f..667c47b34bc703 100644
--- a/clang/test/Driver/frame-pointer-elim.c
+++ b/clang/test/Driver/frame-pointer-elim.c
@@ -162,5 +162,34 @@
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
// RUN: not %clang -### --target=riscv64-linux-android -mbig-endian -O1 -S %s
2>&1 | \
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+
+// On ARM backend bare metal targets, frame pointer is omitted
+// RUN: %clang -### --target=arm-arm-none-eabi -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -O1 -fno-omit-frame-pointer
%s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -O1
-fno-omit-frame-pointer %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+
+// AArch64 bare metal targets behave like hosted targets
+// RUN: %clang -### --target=aarch64-none-elf -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -O1 -fno-omit-frame-pointer
%s 2>&1 | \
+// RUN: FileCheck --check-prefix=KE
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
https://github.com/stuij updated
https://github.com/llvm/llvm-project/pull/117140
>From 4a85a0cd98bf328f31465d47c56640abdf7ec08c Mon Sep 17 00:00:00 2001
From: Ties Stuij
Date: Fri, 15 Nov 2024 13:19:08 +
Subject: [PATCH 1/4] [clang][ARM] disable frame pointers by default for bare
metal ARM targets
because:
- This brings Clang in line with GCC for which this is the default for ARM
- It frees up a register, so performance increase, especially on Thumb/6-M
- It will also decrease code size
---
clang/lib/Driver/ToolChains/BareMetal.cpp | 8 +-
clang/lib/Driver/ToolChains/BareMetal.h| 2 ++
clang/lib/Driver/ToolChains/CommonArgs.cpp | 5
clang/test/Driver/frame-pointer-elim.c | 29 ++
4 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index f9a73f60973e4c..13b510e7e70994 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -128,8 +128,11 @@ BareMetal::BareMetal(const Driver &D, const llvm::Triple
&Triple,
}
}
+namespace clang {
+namespace driver {
+namespace toolchains {
/// Is the triple {arm,armeb,thumb,thumbeb}-none-none-{eabi,eabihf} ?
-static bool isARMBareMetal(const llvm::Triple &Triple) {
+bool isARMBareMetal(const llvm::Triple &Triple) {
if (Triple.getArch() != llvm::Triple::arm &&
Triple.getArch() != llvm::Triple::thumb &&
Triple.getArch() != llvm::Triple::armeb &&
@@ -148,6 +151,9 @@ static bool isARMBareMetal(const llvm::Triple &Triple) {
return true;
}
+} // namespace clang
+} // namespace driver
+} // namespace clang
/// Is the triple {aarch64.aarch64_be}-none-elf?
static bool isAArch64BareMetal(const llvm::Triple &Triple) {
diff --git a/clang/lib/Driver/ToolChains/BareMetal.h
b/clang/lib/Driver/ToolChains/BareMetal.h
index b385c8cf76aab0..ae09bcedd78a28 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.h
+++ b/clang/lib/Driver/ToolChains/BareMetal.h
@@ -19,6 +19,8 @@ namespace driver {
namespace toolchains {
+bool isARMBareMetal(const llvm::Triple &Triple);
+
class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain {
public:
BareMetal(const Driver &D, const llvm::Triple &Triple,
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 8d977149e62485..8d54d0a8649cc9 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -19,6 +19,7 @@
#include "Arch/SystemZ.h"
#include "Arch/VE.h"
#include "Arch/X86.h"
+#include "BareMetal.h"
#include "HIPAMD.h"
#include "Hexagon.h"
#include "MSP430.h"
@@ -151,6 +152,10 @@ static bool useFramePointerForTargetByDefault(const
llvm::opt::ArgList &Args,
}
}
+ if (toolchains::isARMBareMetal(Triple)) {
+return false;
+ }
+
return true;
}
diff --git a/clang/test/Driver/frame-pointer-elim.c
b/clang/test/Driver/frame-pointer-elim.c
index cdedcc7ae4c89f..667c47b34bc703 100644
--- a/clang/test/Driver/frame-pointer-elim.c
+++ b/clang/test/Driver/frame-pointer-elim.c
@@ -162,5 +162,34 @@
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
// RUN: not %clang -### --target=riscv64-linux-android -mbig-endian -O1 -S %s
2>&1 | \
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+
+// On ARM backend bare metal targets, frame pointer is omitted
+// RUN: %clang -### --target=arm-arm-none-eabi -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -O1 -fno-omit-frame-pointer
%s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -O1
-fno-omit-frame-pointer %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+
+// AArch64 bare metal targets behave like hosted targets
+// RUN: %clang -### --target=aarch64-none-elf -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -O1 -fno-omit-frame-pointer
%s 2>&1 | \
+// RUN: FileCheck --check-prefix=KE
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
@@ -128,12 +128,14 @@ BareMetal::BareMetal(const Driver &D, const llvm::Triple
&Triple,
}
}
+namespace clang {
+namespace driver {
+namespace toolchains {
/// Is the triple {arm,armeb,thumb,thumbeb}-none-none-{eabi,eabihf} ?
-static bool isARMBareMetal(const llvm::Triple &Triple) {
- if (Triple.getArch() != llvm::Triple::arm &&
- Triple.getArch() != llvm::Triple::thumb &&
- Triple.getArch() != llvm::Triple::armeb &&
- Triple.getArch() != llvm::Triple::thumbeb)
+bool isARMEABIBareMetal(const llvm::Triple &Triple) {
stuij wrote:
Yes, that makes total sense. Done!
https://github.com/llvm/llvm-project/pull/117140
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
https://github.com/stuij updated
https://github.com/llvm/llvm-project/pull/117140
>From 4a85a0cd98bf328f31465d47c56640abdf7ec08c Mon Sep 17 00:00:00 2001
From: Ties Stuij
Date: Fri, 15 Nov 2024 13:19:08 +
Subject: [PATCH 1/7] [clang][ARM] disable frame pointers by default for bare
metal ARM targets
because:
- This brings Clang in line with GCC for which this is the default for ARM
- It frees up a register, so performance increase, especially on Thumb/6-M
- It will also decrease code size
---
clang/lib/Driver/ToolChains/BareMetal.cpp | 8 +-
clang/lib/Driver/ToolChains/BareMetal.h| 2 ++
clang/lib/Driver/ToolChains/CommonArgs.cpp | 5
clang/test/Driver/frame-pointer-elim.c | 29 ++
4 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index f9a73f60973e4c..13b510e7e70994 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -128,8 +128,11 @@ BareMetal::BareMetal(const Driver &D, const llvm::Triple
&Triple,
}
}
+namespace clang {
+namespace driver {
+namespace toolchains {
/// Is the triple {arm,armeb,thumb,thumbeb}-none-none-{eabi,eabihf} ?
-static bool isARMBareMetal(const llvm::Triple &Triple) {
+bool isARMBareMetal(const llvm::Triple &Triple) {
if (Triple.getArch() != llvm::Triple::arm &&
Triple.getArch() != llvm::Triple::thumb &&
Triple.getArch() != llvm::Triple::armeb &&
@@ -148,6 +151,9 @@ static bool isARMBareMetal(const llvm::Triple &Triple) {
return true;
}
+} // namespace clang
+} // namespace driver
+} // namespace clang
/// Is the triple {aarch64.aarch64_be}-none-elf?
static bool isAArch64BareMetal(const llvm::Triple &Triple) {
diff --git a/clang/lib/Driver/ToolChains/BareMetal.h
b/clang/lib/Driver/ToolChains/BareMetal.h
index b385c8cf76aab0..ae09bcedd78a28 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.h
+++ b/clang/lib/Driver/ToolChains/BareMetal.h
@@ -19,6 +19,8 @@ namespace driver {
namespace toolchains {
+bool isARMBareMetal(const llvm::Triple &Triple);
+
class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain {
public:
BareMetal(const Driver &D, const llvm::Triple &Triple,
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 8d977149e62485..8d54d0a8649cc9 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -19,6 +19,7 @@
#include "Arch/SystemZ.h"
#include "Arch/VE.h"
#include "Arch/X86.h"
+#include "BareMetal.h"
#include "HIPAMD.h"
#include "Hexagon.h"
#include "MSP430.h"
@@ -151,6 +152,10 @@ static bool useFramePointerForTargetByDefault(const
llvm::opt::ArgList &Args,
}
}
+ if (toolchains::isARMBareMetal(Triple)) {
+return false;
+ }
+
return true;
}
diff --git a/clang/test/Driver/frame-pointer-elim.c
b/clang/test/Driver/frame-pointer-elim.c
index cdedcc7ae4c89f..667c47b34bc703 100644
--- a/clang/test/Driver/frame-pointer-elim.c
+++ b/clang/test/Driver/frame-pointer-elim.c
@@ -162,5 +162,34 @@
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
// RUN: not %clang -### --target=riscv64-linux-android -mbig-endian -O1 -S %s
2>&1 | \
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+
+// On ARM backend bare metal targets, frame pointer is omitted
+// RUN: %clang -### --target=arm-arm-none-eabi -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -O1 -fno-omit-frame-pointer
%s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -O1
-fno-omit-frame-pointer %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+
+// AArch64 bare metal targets behave like hosted targets
+// RUN: %clang -### --target=aarch64-none-elf -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -O1 -fno-omit-frame-pointer
%s 2>&1 | \
+// RUN: FileCheck --check-prefix=KE
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
https://github.com/stuij closed https://github.com/llvm/llvm-project/pull/117140 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
https://github.com/stuij updated
https://github.com/llvm/llvm-project/pull/117140
>From 4a85a0cd98bf328f31465d47c56640abdf7ec08c Mon Sep 17 00:00:00 2001
From: Ties Stuij
Date: Fri, 15 Nov 2024 13:19:08 +
Subject: [PATCH 1/2] [clang][ARM] disable frame pointers by default for bare
metal ARM targets
because:
- This brings Clang in line with GCC for which this is the default for ARM
- It frees up a register, so performance increase, especially on Thumb/6-M
- It will also decrease code size
---
clang/lib/Driver/ToolChains/BareMetal.cpp | 8 +-
clang/lib/Driver/ToolChains/BareMetal.h| 2 ++
clang/lib/Driver/ToolChains/CommonArgs.cpp | 5
clang/test/Driver/frame-pointer-elim.c | 29 ++
4 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index f9a73f60973e4c..13b510e7e70994 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -128,8 +128,11 @@ BareMetal::BareMetal(const Driver &D, const llvm::Triple
&Triple,
}
}
+namespace clang {
+namespace driver {
+namespace toolchains {
/// Is the triple {arm,armeb,thumb,thumbeb}-none-none-{eabi,eabihf} ?
-static bool isARMBareMetal(const llvm::Triple &Triple) {
+bool isARMBareMetal(const llvm::Triple &Triple) {
if (Triple.getArch() != llvm::Triple::arm &&
Triple.getArch() != llvm::Triple::thumb &&
Triple.getArch() != llvm::Triple::armeb &&
@@ -148,6 +151,9 @@ static bool isARMBareMetal(const llvm::Triple &Triple) {
return true;
}
+} // namespace clang
+} // namespace driver
+} // namespace clang
/// Is the triple {aarch64.aarch64_be}-none-elf?
static bool isAArch64BareMetal(const llvm::Triple &Triple) {
diff --git a/clang/lib/Driver/ToolChains/BareMetal.h
b/clang/lib/Driver/ToolChains/BareMetal.h
index b385c8cf76aab0..ae09bcedd78a28 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.h
+++ b/clang/lib/Driver/ToolChains/BareMetal.h
@@ -19,6 +19,8 @@ namespace driver {
namespace toolchains {
+bool isARMBareMetal(const llvm::Triple &Triple);
+
class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain {
public:
BareMetal(const Driver &D, const llvm::Triple &Triple,
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 8d977149e62485..8d54d0a8649cc9 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -19,6 +19,7 @@
#include "Arch/SystemZ.h"
#include "Arch/VE.h"
#include "Arch/X86.h"
+#include "BareMetal.h"
#include "HIPAMD.h"
#include "Hexagon.h"
#include "MSP430.h"
@@ -151,6 +152,10 @@ static bool useFramePointerForTargetByDefault(const
llvm::opt::ArgList &Args,
}
}
+ if (toolchains::isARMBareMetal(Triple)) {
+return false;
+ }
+
return true;
}
diff --git a/clang/test/Driver/frame-pointer-elim.c
b/clang/test/Driver/frame-pointer-elim.c
index cdedcc7ae4c89f..667c47b34bc703 100644
--- a/clang/test/Driver/frame-pointer-elim.c
+++ b/clang/test/Driver/frame-pointer-elim.c
@@ -162,5 +162,34 @@
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
// RUN: not %clang -### --target=riscv64-linux-android -mbig-endian -O1 -S %s
2>&1 | \
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+
+// On ARM backend bare metal targets, frame pointer is omitted
+// RUN: %clang -### --target=arm-arm-none-eabi -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -O1 -fno-omit-frame-pointer
%s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -O1
-fno-omit-frame-pointer %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+
+// AArch64 bare metal targets behave like hosted targets
+// RUN: %clang -### --target=aarch64-none-elf -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -O1 -fno-omit-frame-pointer
%s 2>&1 | \
+// RUN: FileCheck --check-prefix=KE
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
https://github.com/stuij created
https://github.com/llvm/llvm-project/pull/117140
because:
- This brings Clang in line with GCC for which this is the default for ARM
- It frees up a register, so performance increase, especially on Thumb/6-M
- It will decrease code size
>From 4a85a0cd98bf328f31465d47c56640abdf7ec08c Mon Sep 17 00:00:00 2001
From: Ties Stuij
Date: Fri, 15 Nov 2024 13:19:08 +
Subject: [PATCH] [clang][ARM] disable frame pointers by default for bare metal
ARM targets
because:
- This brings Clang in line with GCC for which this is the default for ARM
- It frees up a register, so performance increase, especially on Thumb/6-M
- It will also decrease code size
---
clang/lib/Driver/ToolChains/BareMetal.cpp | 8 +-
clang/lib/Driver/ToolChains/BareMetal.h| 2 ++
clang/lib/Driver/ToolChains/CommonArgs.cpp | 5
clang/test/Driver/frame-pointer-elim.c | 29 ++
4 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index f9a73f60973e4c..13b510e7e70994 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -128,8 +128,11 @@ BareMetal::BareMetal(const Driver &D, const llvm::Triple
&Triple,
}
}
+namespace clang {
+namespace driver {
+namespace toolchains {
/// Is the triple {arm,armeb,thumb,thumbeb}-none-none-{eabi,eabihf} ?
-static bool isARMBareMetal(const llvm::Triple &Triple) {
+bool isARMBareMetal(const llvm::Triple &Triple) {
if (Triple.getArch() != llvm::Triple::arm &&
Triple.getArch() != llvm::Triple::thumb &&
Triple.getArch() != llvm::Triple::armeb &&
@@ -148,6 +151,9 @@ static bool isARMBareMetal(const llvm::Triple &Triple) {
return true;
}
+} // namespace clang
+} // namespace driver
+} // namespace clang
/// Is the triple {aarch64.aarch64_be}-none-elf?
static bool isAArch64BareMetal(const llvm::Triple &Triple) {
diff --git a/clang/lib/Driver/ToolChains/BareMetal.h
b/clang/lib/Driver/ToolChains/BareMetal.h
index b385c8cf76aab0..ae09bcedd78a28 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.h
+++ b/clang/lib/Driver/ToolChains/BareMetal.h
@@ -19,6 +19,8 @@ namespace driver {
namespace toolchains {
+bool isARMBareMetal(const llvm::Triple &Triple);
+
class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain {
public:
BareMetal(const Driver &D, const llvm::Triple &Triple,
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 8d977149e62485..8d54d0a8649cc9 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -19,6 +19,7 @@
#include "Arch/SystemZ.h"
#include "Arch/VE.h"
#include "Arch/X86.h"
+#include "BareMetal.h"
#include "HIPAMD.h"
#include "Hexagon.h"
#include "MSP430.h"
@@ -151,6 +152,10 @@ static bool useFramePointerForTargetByDefault(const
llvm::opt::ArgList &Args,
}
}
+ if (toolchains::isARMBareMetal(Triple)) {
+return false;
+ }
+
return true;
}
diff --git a/clang/test/Driver/frame-pointer-elim.c
b/clang/test/Driver/frame-pointer-elim.c
index cdedcc7ae4c89f..667c47b34bc703 100644
--- a/clang/test/Driver/frame-pointer-elim.c
+++ b/clang/test/Driver/frame-pointer-elim.c
@@ -162,5 +162,34 @@
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
// RUN: not %clang -### --target=riscv64-linux-android -mbig-endian -O1 -S %s
2>&1 | \
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+
+// On ARM backend bare metal targets, frame pointer is omitted
+// RUN: %clang -### --target=arm-arm-none-eabi -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -O1 -fno-omit-frame-pointer
%s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -O1
-fno-omit-frame-pointer %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+
+// AArch64 bare metal targets behave like hosted targets
+// RUN: %clang -### --target=aarch64-none-elf -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -fno-omit-frame-pointer %s
2>&1 |
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
stuij wrote: This change was discussed in the LLVM Embedded Toolchains working group sync up two weeks ago, and at the time people were in agreement that it made sense: https://discourse.llvm.org/t/llvm-embedded-toolchains-working-group-sync-up/63270/73#p-334070-peter-frame-pointers-on-or-off-by-default-7 https://github.com/llvm/llvm-project/pull/117140 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
https://github.com/stuij updated
https://github.com/llvm/llvm-project/pull/117140
>From 4a85a0cd98bf328f31465d47c56640abdf7ec08c Mon Sep 17 00:00:00 2001
From: Ties Stuij
Date: Fri, 15 Nov 2024 13:19:08 +
Subject: [PATCH 1/3] [clang][ARM] disable frame pointers by default for bare
metal ARM targets
because:
- This brings Clang in line with GCC for which this is the default for ARM
- It frees up a register, so performance increase, especially on Thumb/6-M
- It will also decrease code size
---
clang/lib/Driver/ToolChains/BareMetal.cpp | 8 +-
clang/lib/Driver/ToolChains/BareMetal.h| 2 ++
clang/lib/Driver/ToolChains/CommonArgs.cpp | 5
clang/test/Driver/frame-pointer-elim.c | 29 ++
4 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index f9a73f60973e4c..13b510e7e70994 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -128,8 +128,11 @@ BareMetal::BareMetal(const Driver &D, const llvm::Triple
&Triple,
}
}
+namespace clang {
+namespace driver {
+namespace toolchains {
/// Is the triple {arm,armeb,thumb,thumbeb}-none-none-{eabi,eabihf} ?
-static bool isARMBareMetal(const llvm::Triple &Triple) {
+bool isARMBareMetal(const llvm::Triple &Triple) {
if (Triple.getArch() != llvm::Triple::arm &&
Triple.getArch() != llvm::Triple::thumb &&
Triple.getArch() != llvm::Triple::armeb &&
@@ -148,6 +151,9 @@ static bool isARMBareMetal(const llvm::Triple &Triple) {
return true;
}
+} // namespace clang
+} // namespace driver
+} // namespace clang
/// Is the triple {aarch64.aarch64_be}-none-elf?
static bool isAArch64BareMetal(const llvm::Triple &Triple) {
diff --git a/clang/lib/Driver/ToolChains/BareMetal.h
b/clang/lib/Driver/ToolChains/BareMetal.h
index b385c8cf76aab0..ae09bcedd78a28 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.h
+++ b/clang/lib/Driver/ToolChains/BareMetal.h
@@ -19,6 +19,8 @@ namespace driver {
namespace toolchains {
+bool isARMBareMetal(const llvm::Triple &Triple);
+
class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain {
public:
BareMetal(const Driver &D, const llvm::Triple &Triple,
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 8d977149e62485..8d54d0a8649cc9 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -19,6 +19,7 @@
#include "Arch/SystemZ.h"
#include "Arch/VE.h"
#include "Arch/X86.h"
+#include "BareMetal.h"
#include "HIPAMD.h"
#include "Hexagon.h"
#include "MSP430.h"
@@ -151,6 +152,10 @@ static bool useFramePointerForTargetByDefault(const
llvm::opt::ArgList &Args,
}
}
+ if (toolchains::isARMBareMetal(Triple)) {
+return false;
+ }
+
return true;
}
diff --git a/clang/test/Driver/frame-pointer-elim.c
b/clang/test/Driver/frame-pointer-elim.c
index cdedcc7ae4c89f..667c47b34bc703 100644
--- a/clang/test/Driver/frame-pointer-elim.c
+++ b/clang/test/Driver/frame-pointer-elim.c
@@ -162,5 +162,34 @@
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
// RUN: not %clang -### --target=riscv64-linux-android -mbig-endian -O1 -S %s
2>&1 | \
// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+
+// On ARM backend bare metal targets, frame pointer is omitted
+// RUN: %clang -### --target=arm-arm-none-eabi -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NONE %s
+// RUN: %clang -### --target=arm-arm-none-eabi -S -O1 -fno-omit-frame-pointer
%s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+// RUN: %clang -### --target=arm-arm-none-eabihf -S -O1
-fno-omit-frame-pointer %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-ALL %s
+
+// AArch64 bare metal targets behave like hosted targets
+// RUN: %clang -### --target=aarch64-none-elf -S %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -O1 %s 2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -fno-omit-frame-pointer %s
2>&1 | \
+// RUN: FileCheck --check-prefix=KEEP-NON-LEAF %s
+// RUN: %clang -### --target=aarch64-none-elf -S -O1 -fno-omit-frame-pointer
%s 2>&1 | \
+// RUN: FileCheck --check-prefix=KE
[clang] [clang][ARM] disable frame pointers by default for bare metal ARM targets (PR #117140)
@@ -151,6 +152,10 @@ static bool useFramePointerForTargetByDefault(const
llvm::opt::ArgList &Args,
}
}
+ if (toolchains::isARMBareMetal(Triple)) {
+return false;
+ }
stuij wrote:
done!
https://github.com/llvm/llvm-project/pull/117140
___
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[clang] [clang] document that by default FP turned off for ARM baremetal (PR #122881)
@@ -1076,6 +1076,8 @@ Arm and AArch64 Support in leaf functions after enabling ``-fno-omit-frame-pointer``, you can do so by adding the ``-momit-leaf-frame-pointer`` option. +- For ARM baremetal targets, the frame pointer (FP) is now turned off by default. stuij wrote: done https://github.com/llvm/llvm-project/pull/122881 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] document that by default FP turned off for ARM baremetal (PR #122881)
https://github.com/stuij updated https://github.com/llvm/llvm-project/pull/122881 >From 7865fd2bf4e0bb9c35b3d14f362732c994914568 Mon Sep 17 00:00:00 2001 From: Ties Stuij Date: Tue, 14 Jan 2025 10:01:33 + Subject: [PATCH 1/2] [clang] document that by default FP turned off for ARM baremetal As per #117140. --- clang/docs/ReleaseNotes.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 794943b24a003c..663e7561f715c0 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -1076,6 +1076,8 @@ Arm and AArch64 Support in leaf functions after enabling ``-fno-omit-frame-pointer``, you can do so by adding the ``-momit-leaf-frame-pointer`` option. +- For ARM baremetal targets, the frame pointer (FP) is now turned off by default. + - Support has been added for the following processors (-mcpu identifiers in parenthesis): For AArch64: >From 69669604d4b37193ef8487af13043cd9d78484e3 Mon Sep 17 00:00:00 2001 From: Ties Stuij Date: Tue, 14 Jan 2025 11:42:41 + Subject: [PATCH 2/2] Address review comment by moving text up and expanding on it --- clang/docs/ReleaseNotes.rst | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 663e7561f715c0..27193ca9349a6e 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -1071,13 +1071,15 @@ Arm and AArch64 Support - Implementation of SVE2.1 and SME2.1 in accordance with the Arm C Language Extensions (ACLE) is now available. +- For ARM baremetal targets, the frame pointer (FP) is now turned off by + default. To turn on frame pointers for Arm baremetal targets, use + the ``-fno-omit-frame-pointer`` command line option. + - In the ARM Target, the frame pointer (FP) of a leaf function can be retained by using the ``-fno-omit-frame-pointer`` option. If you want to eliminate the FP in leaf functions after enabling ``-fno-omit-frame-pointer``, you can do so by adding the ``-momit-leaf-frame-pointer`` option. -- For ARM baremetal targets, the frame pointer (FP) is now turned off by default. - - Support has been added for the following processors (-mcpu identifiers in parenthesis): For AArch64: ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] document that by default FP turned off for ARM baremetal (PR #122881)
https://github.com/stuij created https://github.com/llvm/llvm-project/pull/122881 As per #117140. >From 7865fd2bf4e0bb9c35b3d14f362732c994914568 Mon Sep 17 00:00:00 2001 From: Ties Stuij Date: Tue, 14 Jan 2025 10:01:33 + Subject: [PATCH] [clang] document that by default FP turned off for ARM baremetal As per #117140. --- clang/docs/ReleaseNotes.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 794943b24a003c..663e7561f715c0 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -1076,6 +1076,8 @@ Arm and AArch64 Support in leaf functions after enabling ``-fno-omit-frame-pointer``, you can do so by adding the ``-momit-leaf-frame-pointer`` option. +- For ARM baremetal targets, the frame pointer (FP) is now turned off by default. + - Support has been added for the following processors (-mcpu identifiers in parenthesis): For AArch64: ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
