Author: Ties Stuij Date: 2022-03-15T13:44:20Z New Revision: 352453569b2b044ddd5bd4df0074ff9863828b6f
URL: https://github.com/llvm/llvm-project/commit/352453569b2b044ddd5bd4df0074ff9863828b6f DIFF: https://github.com/llvm/llvm-project/commit/352453569b2b044ddd5bd4df0074ff9863828b6f.diff LOG: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77 Reviewed By: amilendra Differential Revision: https://reviews.llvm.org/D121206 Added: Modified: clang/test/Driver/aarch64-ssbs.c clang/test/Preprocessor/aarch64-target-features.c llvm/lib/Support/AArch64TargetParser.cpp llvm/lib/Target/AArch64/AArch64.td Removed: ################################################################################ diff --git a/clang/test/Driver/aarch64-ssbs.c b/clang/test/Driver/aarch64-ssbs.c index 86c93ae926404..209255405d28d 100644 --- a/clang/test/Driver/aarch64-ssbs.c +++ b/clang/test/Driver/aarch64-ssbs.c @@ -1,7 +1,11 @@ // RUN: %clang -### -target aarch64-none-none-eabi -march=armv8a+ssbs %s 2>&1 | FileCheck %s +// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-x1 %s 2>&1 | FileCheck %s +// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-x1c %s 2>&1 | FileCheck %s +// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-a77 %s 2>&1 | FileCheck %s // CHECK: "-target-feature" "+ssbs" // RUN: %clang -### -target aarch64-none-none-eabi -march=armv8a+nossbs %s 2>&1 | FileCheck %s --check-prefix=NOSSBS +// RUN: %clang -### -target aarch64-none-none-eabi -mcpu=cortex-x1c+nossbs %s 2>&1 | FileCheck %s --check-prefix=NOSSBS // NOSSBS: "-target-feature" "-ssbs" // RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENTSSBS diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c index 833d75b7e5b9e..b7e0113131ea7 100644 --- a/clang/test/Preprocessor/aarch64-target-features.c +++ b/clang/test/Preprocessor/aarch64-target-features.c @@ -285,7 +285,7 @@ // CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" // CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" // CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" -// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+fullfp16" +// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp16fml" "-target-feature" "+ras" "-target-feature" "+lse" "-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+ssbs" "-target-feature" "+fullfp16" // CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" // CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+dotprod" "-target-feature" "+fullfp16" // CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" diff --git a/llvm/lib/Support/AArch64TargetParser.cpp b/llvm/lib/Support/AArch64TargetParser.cpp index cdf7c8ade9aac..bb19e2714be10 100644 --- a/llvm/lib/Support/AArch64TargetParser.cpp +++ b/llvm/lib/Support/AArch64TargetParser.cpp @@ -120,6 +120,8 @@ bool AArch64::getExtensionFeatures(uint64_t Extensions, Features.push_back("+mops"); if (Extensions & AArch64::AEK_PERFMON) Features.push_back("+perfmon"); + if (Extensions & AArch64::AEK_SSBS) + Features.push_back("+ssbs"); return true; } diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index f53218c35d46e..872343e8b8f89 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -957,7 +957,7 @@ def ProcessorFeatures { FeatureRCPC, FeatureSSBS, FeaturePerfMon]; list<SubtargetFeature> A77 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeatureFullFP16, FeatureDotProd, - FeatureRCPC, FeaturePerfMon]; + FeatureRCPC, FeaturePerfMon, FeatureSSBS]; list<SubtargetFeature> A78 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeatureFullFP16, FeatureDotProd, FeatureRCPC, FeaturePerfMon, FeatureSPE, @@ -975,11 +975,12 @@ def ProcessorFeatures { FeatureSB]; list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeatureRCPC, FeaturePerfMon, - FeatureSPE, FeatureFullFP16, FeatureDotProd]; + FeatureSPE, FeatureFullFP16, FeatureDotProd, + FeatureSSBS]; list<SubtargetFeature> X1C = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeatureRCPC, FeaturePerfMon, FeatureSPE, FeatureFullFP16, FeatureDotProd, - FeaturePAuth]; + FeaturePAuth, FeatureSSBS]; list<SubtargetFeature> X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon, FeatureMatMulInt8, FeatureBF16, FeatureAM, FeatureMTE, FeatureETE, FeatureSVE2BitPerm, _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
