from:"Sander de Smalen via Phabricator via cfe\-commits"

[PATCH] D43189: [DebugInfo] Avoid name conflict of generated VLA expression variable.

2018-02-12 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: CarlosAlbertoEnciso, probinson, aprantl.
Herald added a subscriber: JDevlieghere.

This patch also adds the 'DW_AT_artificial' flag to the generated variable.


https://reviews.llvm.org/D43189

Files:
  lib/CodeGen/CGDecl.cpp
  test/CodeGen/debug-info-vla.c
  test/CodeGenCXX/debug-info-vla.cpp
  test/OpenMP/target_codegen.cpp
  test/OpenMP/target_parallel_codegen.cpp
  test/OpenMP/target_parallel_for_codegen.cpp
  test/OpenMP/target_parallel_for_simd_codegen.cpp
  test/OpenMP/target_simd_codegen.cpp
  test/OpenMP/target_teams_codegen.cpp
  test/OpenMP/target_teams_distribute_codegen.cpp
  test/OpenMP/target_teams_distribute_simd_codegen.cpp

Index: test/OpenMP/target_teams_distribute_simd_codegen.cpp
===
--- test/OpenMP/target_teams_distribute_simd_codegen.cpp
+++ test/OpenMP/target_teams_distribute_simd_codegen.cpp
@@ -553,7 +553,7 @@
 // CHECK-64:   store i32 %{{.+}}, i32* [[B_ADDR]],
 // CHECK-64:   [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_CADDR]],
 
-// CHECK-32:   store i32 %{{.+}}, i32* %vla_expr
+// CHECK-32:   store i32 %{{.+}}, i32* %__vla_expr
 // CHECK-32:   store i32 %{{.+}}, i32* [[B_ADDR:%.+]],
 // CHECK-32:   [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_ADDR]],
 
Index: test/OpenMP/target_teams_distribute_codegen.cpp
===
--- test/OpenMP/target_teams_distribute_codegen.cpp
+++ test/OpenMP/target_teams_distribute_codegen.cpp
@@ -564,7 +564,7 @@
 // CHECK-64:   store i32 %{{.+}}, i32* [[B_ADDR]],
 // CHECK-64:   [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_CADDR]],
 
-// CHECK-32:   store i32 %{{.+}}, i32* %vla_expr
+// CHECK-32:   store i32 %{{.+}}, i32* %__vla_expr
 // CHECK-32:   store i32 %{{.+}}, i32* [[B_ADDR:%.+]],
 // CHECK-32:   [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_ADDR]],
 
Index: test/OpenMP/target_teams_codegen.cpp
===
--- test/OpenMP/target_teams_codegen.cpp
+++ test/OpenMP/target_teams_codegen.cpp
@@ -553,7 +553,7 @@
 // CHECK-64:   store i32 %{{.+}}, i32* [[B_ADDR]],
 // CHECK-64:   [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_CADDR]],
 
-// CHECK-32:   store i32 %{{.+}}, i32* %vla_expr
+// CHECK-32:   store i32 %{{.+}}, i32* %__vla_expr
 // CHECK-32:   store i32 %{{.+}}, i32* [[B_ADDR:%.+]],
 // CHECK-32:   [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_ADDR]],
 
Index: test/OpenMP/target_simd_codegen.cpp
===
--- test/OpenMP/target_simd_codegen.cpp
+++ test/OpenMP/target_simd_codegen.cpp
@@ -478,7 +478,7 @@
 // CHECK-64:   store i32 %{{.+}}, i32* [[B_ADDR]],
 // CHECK-64:   [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_CADDR]],
 
-// CHECK-32:   store i32 %{{.+}}, i32* %vla_expr
+// CHECK-32:   store i32 %{{.+}}, i32* %__vla_expr
 // CHECK-32:   store i32 %{{.+}}, i32* [[B_ADDR:%.+]],
 // CHECK-32:   [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_ADDR]],
 
Index: test/OpenMP/target_parallel_for_simd_codegen.cpp
===
--- test/OpenMP/target_parallel_for_simd_codegen.cpp
+++ test/OpenMP/target_parallel_for_simd_codegen.cpp
@@ -555,7 +555,7 @@
 // CHECK-64:   store i32 %{{.+}}, i32* [[B_ADDR]],
 // CHECK-64:   [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_CADDR]],
 
-// CHECK-32:   store i32 %{{.+}}, i32* %vla_expr
+// CHECK-32:   store i32 %{{.+}}, i32* %__vla_expr
 // CHECK-32:   store i32 %{{.+}}, i32* [[B_ADDR:%.+]],
 // CHECK-32:   [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_ADDR]],
 
Index: test/OpenMP/target_parallel_for_codegen.cpp
===
--- test/OpenMP/target_parallel_for_codegen.cpp
+++ test/OpenMP/target_parallel_for_codegen.cpp
@@ -555,7 +555,7 @@
 // CHECK-64:   store i32 %{{.+}}, i32* [[B_ADDR]],
 // CHECK-64:   [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_CADDR]],
 
-// CHECK-32:   store i32 %{{.+}}, i32* %vla_expr
+// CHECK-32:   store i32 %{{.+}}, i32* %__vla_expr
 // CHECK-32:   store i32 %{{.+}}, i32* [[B_ADDR:%.+]],
 // CHECK-32:   [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_ADDR]],
 
Index: test/OpenMP/target_parallel_codegen.cpp
===
--- test/OpenMP/target_parallel_codegen.cpp
+++ test/OpenMP/target_parallel_codegen.cpp
@@ -528,7 +528,7 @@
 // CHECK-64:   store i32 %{{.+}}, i32* [[B_ADDR]],
 // CHECK-64:   [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_CADDR]],
 
-// CHECK-32:   store i32 %{{.+}}, i32* %vla_expr
+// CHECK-32:   store i32 %{{.+}}, i32* %__vla_expr
 // CHECK-32:   store i32 %{{.+}}, i32* [[B_ADDR:%.+]],
 // CHECK-32:   [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_ADDR]],
 
Index: test/OpenMP/tar

[PATCH] D33893: Align definition of DW_OP_plus with DWARF spec [2/3]

2017-06-05 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
Herald added a subscriber: aprantl.

This patch is part of 3 patches that together form a single patch, but must be 
introduced in stages in order not to break things.
 
The way that LLVM interprets DW_OP_plus in DIExpression nodes is basically that 
of the DW_OP_plus_uconst operator since LLVM expects an unsigned constant 
operand. This unnecessarily restricts the DW_OP_plus operator, preventing it 
from being used to describe the evaluation of runtime values on the expression 
stack. These patches try to align the semantics of DW_OP_plus and DW_OP_minus 
with that of the DWARF definition, which pops two elements off the expression 
stack, performs the operation and pushes the result back on the stack.
 
This is done in three stages:
•   The first patch (LLVM) adds support for DW_OP_plus_uconst and 
changes all uses (and tests) of DW_OP_plus to use DW_OP_plus_uconst.
 
•   The second patch (Clang) contains changes to use 
DW_OP_plus_uconst instead of DW_OP_plus.
 
•   The third patch (LLVM) changes the semantics of DW_OP_plus to 
be in line with it’s DWARF meaning. It also does this for DW_OP_minus.


https://reviews.llvm.org/D33893

Files:
  lib/CodeGen/CGDebugInfo.cpp


Index: lib/CodeGen/CGDebugInfo.cpp
===
--- lib/CodeGen/CGDebugInfo.cpp
+++ lib/CodeGen/CGDebugInfo.cpp
@@ -3480,13 +3480,13 @@
 if (VD->hasAttr()) {
   // Here, we need an offset *into* the alloca.
   CharUnits offset = CharUnits::fromQuantity(32);
-  Expr.push_back(llvm::dwarf::DW_OP_plus);
+  Expr.push_back(llvm::dwarf::DW_OP_plus_uconst);
   // offset of __forwarding field
   offset = CGM.getContext().toCharUnitsFromBits(
   CGM.getTarget().getPointerWidth(0));
   Expr.push_back(offset.getQuantity());
   Expr.push_back(llvm::dwarf::DW_OP_deref);
-  Expr.push_back(llvm::dwarf::DW_OP_plus);
+  Expr.push_back(llvm::dwarf::DW_OP_plus_uconst);
   // offset of x field
   offset = CGM.getContext().toCharUnitsFromBits(XOffset);
   Expr.push_back(offset.getQuantity());
@@ -3594,17 +3594,17 @@
 
   SmallVector addr;
   addr.push_back(llvm::dwarf::DW_OP_deref);
-  addr.push_back(llvm::dwarf::DW_OP_plus);
+  addr.push_back(llvm::dwarf::DW_OP_plus_uconst);
   addr.push_back(offset.getQuantity());
   if (isByRef) {
 addr.push_back(llvm::dwarf::DW_OP_deref);
-addr.push_back(llvm::dwarf::DW_OP_plus);
+addr.push_back(llvm::dwarf::DW_OP_plus_uconst);
 // offset of __forwarding field
 offset =
 CGM.getContext().toCharUnitsFromBits(target.getPointerSizeInBits(0));
 addr.push_back(offset.getQuantity());
 addr.push_back(llvm::dwarf::DW_OP_deref);
-addr.push_back(llvm::dwarf::DW_OP_plus);
+addr.push_back(llvm::dwarf::DW_OP_plus_uconst);
 // offset of x field
 offset = CGM.getContext().toCharUnitsFromBits(XOffset);
 addr.push_back(offset.getQuantity());


Index: lib/CodeGen/CGDebugInfo.cpp
===
--- lib/CodeGen/CGDebugInfo.cpp
+++ lib/CodeGen/CGDebugInfo.cpp
@@ -3480,13 +3480,13 @@
 if (VD->hasAttr()) {
   // Here, we need an offset *into* the alloca.
   CharUnits offset = CharUnits::fromQuantity(32);
-  Expr.push_back(llvm::dwarf::DW_OP_plus);
+  Expr.push_back(llvm::dwarf::DW_OP_plus_uconst);
   // offset of __forwarding field
   offset = CGM.getContext().toCharUnitsFromBits(
   CGM.getTarget().getPointerWidth(0));
   Expr.push_back(offset.getQuantity());
   Expr.push_back(llvm::dwarf::DW_OP_deref);
-  Expr.push_back(llvm::dwarf::DW_OP_plus);
+  Expr.push_back(llvm::dwarf::DW_OP_plus_uconst);
   // offset of x field
   offset = CGM.getContext().toCharUnitsFromBits(XOffset);
   Expr.push_back(offset.getQuantity());
@@ -3594,17 +3594,17 @@
 
   SmallVector addr;
   addr.push_back(llvm::dwarf::DW_OP_deref);
-  addr.push_back(llvm::dwarf::DW_OP_plus);
+  addr.push_back(llvm::dwarf::DW_OP_plus_uconst);
   addr.push_back(offset.getQuantity());
   if (isByRef) {
 addr.push_back(llvm::dwarf::DW_OP_deref);
-addr.push_back(llvm::dwarf::DW_OP_plus);
+addr.push_back(llvm::dwarf::DW_OP_plus_uconst);
 // offset of __forwarding field
 offset =
 CGM.getContext().toCharUnitsFromBits(target.getPointerSizeInBits(0));
 addr.push_back(offset.getQuantity());
 addr.push_back(llvm::dwarf::DW_OP_deref);
-addr.push_back(llvm::dwarf::DW_OP_plus);
+addr.push_back(llvm::dwarf::DW_OP_plus_uconst);
 // offset of x field
 offset = CGM.getContext().toCharUnitsFromBits(XOffset);
 addr.push_back(offset.getQuantity());
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[PATCH] D41698: [DebugInfo] Enable debug information for C99 VLA types

2018-01-03 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: echristo, aprantl, dexonsmith, clayborg, pcc, 
kristof.beyls.
Herald added a subscriber: JDevlieghere.

This patch enables debugging of C99 VLA types by generating more precise
LLVM Debug metadata, using the extended DISubrange 'count' field that
takes a DIVariable.

  

This should implement:

  Bug 30553: Debug info generated for arrays is not what GDB expects (not as 
good as GCC's)

https://bugs.llvm.org/show_bug.cgi?id=30553


https://reviews.llvm.org/D41698

Files:
  lib/CodeGen/CGDebugInfo.cpp
  lib/CodeGen/CGDebugInfo.h
  lib/CodeGen/CGDecl.cpp
  lib/CodeGen/CodeGenFunction.cpp
  lib/CodeGen/CodeGenFunction.h
  test/CodeGen/debug-info-vla.c
  test/CodeGenCXX/debug-info-vla.cpp

Index: test/CodeGenCXX/debug-info-vla.cpp
===
--- test/CodeGenCXX/debug-info-vla.cpp
+++ test/CodeGenCXX/debug-info-vla.cpp
@@ -13,8 +13,10 @@
 // CHECK: [[ELEM_TYPE]] = !{[[NOCOUNT:.*]]}
 // CHECK: [[NOCOUNT]] = !DISubrange(count: -1)
 //
+// CHECK: [[VAR:![0-9]+]] = !DILocalVariable(name: "vla_expr"
 // CHECK: !DICompositeType(tag: DW_TAG_array_type,
 // CHECK-NOT:   size:
 // CHECK-SAME:  elements: [[ELEM_TYPE:![0-9]+]]
-// CHECK: [[ELEM_TYPE]] = !{[[THREE:.*]], [[NOCOUNT]]}
+// CHECK: [[ELEM_TYPE]] = !{[[THREE:.*]], [[VARRANGE:![0-9]+]]}
 // CHECK: [[THREE]] = !DISubrange(count: 3)
+// CHECK: [[VARRANGE]] = !DISubrange(count: [[VAR]])
Index: test/CodeGen/debug-info-vla.c
===
--- test/CodeGen/debug-info-vla.c
+++ test/CodeGen/debug-info-vla.c
@@ -2,9 +2,11 @@
 
 void testVLAwithSize(int s)
 {
-// CHECK: dbg.declare
-// CHECK: dbg.declare({{.*}}, metadata ![[VAR:.*]], metadata !DIExpression())
-// CHECK: ![[VAR]] = !DILocalVariable(name: "vla",{{.*}} line: [[@LINE+1]]
+// CHECK-DAG: dbg.declare({{.*}} %vla_expr, metadata ![[VLAEXPR:[0-9]+]]
+// CHECK-DAG: dbg.declare({{.*}} %vla, metadata ![[VAR:[0-9]+]]
+// CHECK-DAG: ![[VLAEXPR]] = !DILocalVariable(name: "vla_expr"
+// CHECK-DAG: ![[VAR]] = !DILocalVariable(name: "vla",{{.*}} line: [[@LINE+2]]
+// CHECK-DAG: !DISubrange(count: ![[VLAEXPR]])
   int vla[s];
   int i;
   for (i = 0; i < s; i++) {
Index: lib/CodeGen/CodeGenFunction.h
===
--- lib/CodeGen/CodeGenFunction.h
+++ lib/CodeGen/CodeGenFunction.h
@@ -2193,6 +2193,12 @@
   /// This function can be called with a null (unreachable) insert point.
   void EmitVariablyModifiedType(QualType Ty);
 
+  /// getVLAElements1D returns the number of elements for a single dimension
+  /// for the given array type.
+  std::pair
+  getVLAElements1D(const VariableArrayType *vla);
+  std::pair getVLAElements1D(QualType vla);
+
   /// getVLASize - Returns an LLVM value that corresponds to the size,
   /// in non-variably-sized elements, of a variable length array type,
   /// plus that largest non-variably-sized element type.  Assumes that
Index: lib/CodeGen/CodeGenFunction.cpp
===
--- lib/CodeGen/CodeGenFunction.cpp
+++ lib/CodeGen/CodeGenFunction.cpp
@@ -1948,6 +1948,21 @@
   return std::pair(numElements, elementType);
 }
 
+std::pair
+CodeGenFunction::getVLAElements1D(QualType type) {
+  const VariableArrayType *vla = getContext().getAsVariableArrayType(type);
+  assert(vla && "type was not a variable array type!");
+  return getVLAElements1D(vla);
+}
+
+std::pair
+CodeGenFunction::getVLAElements1D(const VariableArrayType *Vla) {
+  llvm::Value *VlaSize = VLASizeMap[Vla->getSizeExpr()];
+  assert(VlaSize && "no size for VLA!");
+  assert(VlaSize->getType() == SizeTy);
+  return std::pair(VlaSize, Vla->getElementType());
+}
+
 void CodeGenFunction::EmitVariablyModifiedType(QualType type) {
   assert(type->isVariablyModifiedType() &&
  "Must pass variably modified type to EmitVLASizes!");
Index: lib/CodeGen/CGDecl.cpp
===
--- lib/CodeGen/CGDecl.cpp
+++ lib/CodeGen/CGDecl.cpp
@@ -975,6 +975,10 @@
   if (Ty->isVariablyModifiedType())
 EmitVariablyModifiedType(Ty);
 
+  auto *DI = getDebugInfo();
+  bool EmitDebugInfo = DI && CGM.getCodeGenOpts().getDebugInfo() >=
+ codegenoptions::LimitedDebugInfo;
+
   Address address = Address::invalid();
   if (Ty->isConstantSizeType()) {
 bool NRVO = getLangOpts().ElideConstructors &&
@@ -1116,20 +1120,60 @@
 
 // Allocate memory for the array.
 address = CreateTempAlloca(llvmTy, alignment, "vla", elementCount);
+
+// If we have debug info enabled, describe the VLA dimensions properly.
+if (EmitDebugInfo) {
+  QualType Type1D = Ty;
+  while (getContext().getAsVariableArrayType(Type1D)) {
+llvm::Value *ElementCount1D;
+QualType ElementType1D;
+std::tie(ElementCount1D, Element

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

2018-11-12 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: ributzka, rjmccall, rnk, aaron.ballman.
Herald added subscribers: arphaman, kristof.beyls, javed.absar.

This is the Clang patch to complement the following LLVM patches:

  https://reviews.llvm.org/D51477
  https://reviews.llvm.org/D51479

More information describing the vector ABI and procedure call standard
can be found here:

https://developer.arm.com/products/software-development-tools/\

  hpc/arm-compiler-for-hpc/vector-function-abi

Patch by Kerry McLaughlin.


https://reviews.llvm.org/D54425

Files:
  include/clang-c/Index.h
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  include/clang/Basic/Specifiers.h
  lib/AST/ItaniumMangle.cpp
  lib/AST/Type.cpp
  lib/AST/TypePrinter.cpp
  lib/Basic/Targets/AArch64.cpp
  lib/CodeGen/CGCall.cpp
  lib/CodeGen/CGDebugInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  lib/Sema/SemaType.cpp
  test/CodeGen/aarch64-vpcs.c
  tools/libclang/CXType.cpp

Index: tools/libclang/CXType.cpp
===
--- tools/libclang/CXType.cpp
+++ tools/libclang/CXType.cpp
@@ -651,6 +651,7 @@
   TCALLINGCONV(X86Pascal);
   TCALLINGCONV(X86RegCall);
   TCALLINGCONV(X86VectorCall);
+  TCALLINGCONV(AArch64VectorCall);
   TCALLINGCONV(Win64);
   TCALLINGCONV(X86_64SysV);
   TCALLINGCONV(AAPCS);
Index: test/CodeGen/aarch64-vpcs.c
===
--- /dev/null
+++ test/CodeGen/aarch64-vpcs.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECKC
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -x c++ -o - %s | FileCheck %s -check-prefix=CHECKCXX
+// RUN: %clang_cc1 -triple i686-pc-linux-gnu -verify %s
+
+void __attribute__((aarch64_vector_pcs)) f(int *); // expected-warning {{calling convention 'aarch64_vector_pcs' ignored for this target}}
+
+// CHECKC: define void @g(
+// CHECKCXX: define void @_Z1gPi(
+void g(int *a) {
+
+// CHECKC: call aarch64_vector_pcs void @f(
+// CHECKCXX: call aarch64_vector_pcs void @_Z1fPi
+  f(a);
+}
+
+// CHECKC: declare aarch64_vector_pcs void @f(
+// CHECKCXX: declare aarch64_vector_pcs void @_Z1fPi
+
+void __attribute__((aarch64_vector_pcs)) h(int *a){ // expected-warning {{calling convention 'aarch64_vector_pcs' ignored for this target}}
+// CHECKC: define aarch64_vector_pcs void @h(
+// CHECKCXX: define aarch64_vector_pcs void @_Z1hPi(
+  f(a);
+}
Index: lib/Sema/SemaType.cpp
===
--- lib/Sema/SemaType.cpp
+++ lib/Sema/SemaType.cpp
@@ -116,6 +116,7 @@
   case ParsedAttr::AT_Pascal:  \
   case ParsedAttr::AT_SwiftCall:   \
   case ParsedAttr::AT_VectorCall:  \
+  case ParsedAttr::AT_AArch64VectorPcs:\
   case ParsedAttr::AT_MSABI:   \
   case ParsedAttr::AT_SysVABI: \
   case ParsedAttr::AT_Pcs: \
@@ -6657,6 +6658,8 @@
 return createSimpleAttr(Ctx, Attr);
   case ParsedAttr::AT_VectorCall:
 return createSimpleAttr(Ctx, Attr);
+  case ParsedAttr::AT_AArch64VectorPcs:
+return createSimpleAttr(Ctx, Attr);
   case ParsedAttr::AT_Pcs: {
 // The attribute may have had a fixit applied where we treated an
 // identifier as a string literal.  The contents of the string are valid,
Index: lib/Sema/SemaDeclAttr.cpp
===
--- lib/Sema/SemaDeclAttr.cpp
+++ lib/Sema/SemaDeclAttr.cpp
@@ -4291,6 +4291,11 @@
AL.getAttributeSpellingListIndex()));
 return;
   }
+  case ParsedAttr::AT_AArch64VectorPcs:
+D->addAttr(::new(S.Context)
+   AArch64VectorPcsAttr(AL.getRange(), S.Context,
+AL.getAttributeSpellingListIndex()));
+return;
   case ParsedAttr::AT_IntelOclBicc:
 D->addAttr(::new (S.Context)
IntelOclBiccAttr(AL.getRange(), S.Context,
@@ -4368,6 +4373,9 @@
   case ParsedAttr::AT_VectorCall:
 CC = CC_X86VectorCall;
 break;
+  case ParsedAttr::AT_AArch64VectorPcs:
+CC = CC_AArch64VectorCall;
+break;
   case ParsedAttr::AT_RegCall:
 CC = CC_X86RegCall;
 break;
@@ -5840,14 +5848,14 @@
   if (AL.isDeclspecAttribute() || AL.isCXX11Attribute())
 checkAttributeAtMostNumArgs(S, AL, 1);
   else if (AL.isArgExpr(1) && AL.getArgAsExpr(1) &&
-   !S.checkStringLiteralArgumentAttr(AL, 1, Replacement))
-return;
-
-  if (!S.getLangOpts().CPlusPlus14 && AL.isCXX11Attribute() && !AL.isGNUScope())
-S.Diag(AL.getLoc(), diag::ext_cxx14_attr) << AL;
-
-  D->addAttr(::new (S.Context)
- DeprecatedAttr(AL.getRange

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

2018-11-12 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: lib/CodeGen/CGDebugInfo.cpp:1101
   case CC_AAPCS:
+  case CC_AArch64VectorCall:
 return llvm::dwarf::DW_CC_LLVM_AAPCS;

I wasn't really sure whether this requires a corresponding DW_CC_LLVM_AAVPCS 
record in LLVM, as I couldn't find much about the DW_CC_LLVM_  encodings, 
specifically whether they align with some agreed encoding that is implemented 
by GDB/LLDB. Is this defined anywhere, or is it ignored by debuggers at the 
moment?


https://reviews.llvm.org/D54425



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[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

2018-11-13 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen marked an inline comment as done.
sdesmalen added inline comments.



Comment at: include/clang/Basic/Attr.td:1792
+  let Spellings = [GNU<"aarch64_vector_pcs">,
+   CXX11<"clang", "aarch64_vector_pcs">,
+   Keyword<"__aarch64_vector_pcs">,

aaron.ballman wrote:
> Rather than using GNU and CXX11 spellings, you should use the Clang spelling. 
> If the attribute is not useful in C, then set `allowInC` to 0 instead of its 
> default of 1.
Thanks for the suggestion! The attribute is valid in C as well, and is tested 
for both C and C++ in test/CodeGen/aarch64-vpcs.c.



Comment at: include/clang/Basic/Attr.td:1794
+   Keyword<"__aarch64_vector_pcs">,
+   Keyword<"_aarch64_vector_pcs">];
+  let Documentation = [AArch64VectorPcsDocs];

aaron.ballman wrote:
> This steps on the user's namespace -- is that intended and necessary?
That was not intended and looking at the spec, the keyword is not required so 
I'll remove it.


https://reviews.llvm.org/D54425



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[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

2018-11-13 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen updated this revision to Diff 173831.
sdesmalen added a comment.

- Removed `_aarch64_vector_pcs` and `__aarch64_vector_pcs` keywords in favour 
of supporting only `__attribute__(aarch64_vector_pcs))`.


https://reviews.llvm.org/D54425

Files:
  include/clang-c/Index.h
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  include/clang/Basic/Specifiers.h
  lib/AST/ItaniumMangle.cpp
  lib/AST/Type.cpp
  lib/AST/TypePrinter.cpp
  lib/Basic/Targets/AArch64.cpp
  lib/CodeGen/CGCall.cpp
  lib/CodeGen/CGDebugInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  lib/Sema/SemaType.cpp
  test/CodeGen/aarch64-vpcs.c
  tools/libclang/CXType.cpp

Index: tools/libclang/CXType.cpp
===
--- tools/libclang/CXType.cpp
+++ tools/libclang/CXType.cpp
@@ -651,6 +651,7 @@
   TCALLINGCONV(X86Pascal);
   TCALLINGCONV(X86RegCall);
   TCALLINGCONV(X86VectorCall);
+  TCALLINGCONV(AArch64VectorCall);
   TCALLINGCONV(Win64);
   TCALLINGCONV(X86_64SysV);
   TCALLINGCONV(AAPCS);
Index: test/CodeGen/aarch64-vpcs.c
===
--- /dev/null
+++ test/CodeGen/aarch64-vpcs.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECKC
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -x c++ -o - %s | FileCheck %s -check-prefix=CHECKCXX
+// RUN: %clang_cc1 -triple i686-pc-linux-gnu -verify %s
+
+void __attribute__((aarch64_vector_pcs)) f(int *); // expected-warning {{calling convention 'aarch64_vector_pcs' ignored for this target}}
+
+// CHECKC: define void @g(
+// CHECKCXX: define void @_Z1gPi(
+void g(int *a) {
+
+// CHECKC: call aarch64_vector_pcs void @f(
+// CHECKCXX: call aarch64_vector_pcs void @_Z1fPi
+  f(a);
+}
+
+// CHECKC: declare aarch64_vector_pcs void @f(
+// CHECKCXX: declare aarch64_vector_pcs void @_Z1fPi
+
+void __attribute__((aarch64_vector_pcs)) h(int *a){ // expected-warning {{calling convention 'aarch64_vector_pcs' ignored for this target}}
+// CHECKC: define aarch64_vector_pcs void @h(
+// CHECKCXX: define aarch64_vector_pcs void @_Z1hPi(
+  f(a);
+}
Index: lib/Sema/SemaType.cpp
===
--- lib/Sema/SemaType.cpp
+++ lib/Sema/SemaType.cpp
@@ -116,6 +116,7 @@
   case ParsedAttr::AT_Pascal:  \
   case ParsedAttr::AT_SwiftCall:   \
   case ParsedAttr::AT_VectorCall:  \
+  case ParsedAttr::AT_AArch64VectorPcs:\
   case ParsedAttr::AT_MSABI:   \
   case ParsedAttr::AT_SysVABI: \
   case ParsedAttr::AT_Pcs: \
@@ -6657,6 +6658,8 @@
 return createSimpleAttr(Ctx, Attr);
   case ParsedAttr::AT_VectorCall:
 return createSimpleAttr(Ctx, Attr);
+  case ParsedAttr::AT_AArch64VectorPcs:
+return createSimpleAttr(Ctx, Attr);
   case ParsedAttr::AT_Pcs: {
 // The attribute may have had a fixit applied where we treated an
 // identifier as a string literal.  The contents of the string are valid,
Index: lib/Sema/SemaDeclAttr.cpp
===
--- lib/Sema/SemaDeclAttr.cpp
+++ lib/Sema/SemaDeclAttr.cpp
@@ -4291,6 +4291,11 @@
AL.getAttributeSpellingListIndex()));
 return;
   }
+  case ParsedAttr::AT_AArch64VectorPcs:
+D->addAttr(::new(S.Context)
+   AArch64VectorPcsAttr(AL.getRange(), S.Context,
+AL.getAttributeSpellingListIndex()));
+return;
   case ParsedAttr::AT_IntelOclBicc:
 D->addAttr(::new (S.Context)
IntelOclBiccAttr(AL.getRange(), S.Context,
@@ -4368,6 +4373,9 @@
   case ParsedAttr::AT_VectorCall:
 CC = CC_X86VectorCall;
 break;
+  case ParsedAttr::AT_AArch64VectorPcs:
+CC = CC_AArch64VectorCall;
+break;
   case ParsedAttr::AT_RegCall:
 CC = CC_X86RegCall;
 break;
@@ -5840,14 +5848,14 @@
   if (AL.isDeclspecAttribute() || AL.isCXX11Attribute())
 checkAttributeAtMostNumArgs(S, AL, 1);
   else if (AL.isArgExpr(1) && AL.getArgAsExpr(1) &&
-   !S.checkStringLiteralArgumentAttr(AL, 1, Replacement))
-return;
-
-  if (!S.getLangOpts().CPlusPlus14 && AL.isCXX11Attribute() && !AL.isGNUScope())
-S.Diag(AL.getLoc(), diag::ext_cxx14_attr) << AL;
-
-  D->addAttr(::new (S.Context)
- DeprecatedAttr(AL.getRange(), S.Context, Str, Replacement,
+   !S.checkStringLiteralArgumentAttr(AL, 1, Replacement))
+return;
+
+  if (!S.getLangOpts().CPlusPlus14 && AL.isCXX11Attribute() && !AL.isGNUScope())
+S.Diag(AL.getLoc(), diag::ext_cxx14_attr) << AL;
+
+  D->addAttr(::new (S.Context)
+ DeprecatedAttr(AL

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

2018-11-19 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen updated this revision to Diff 174574.
sdesmalen marked an inline comment as done.
sdesmalen added a comment.

Thanks all for the suggestions and comments! I've updated the patch with a 
better description of the attribute's behaviour (thanks @rjmccall for the 
starting point!) and added Sema tests.


https://reviews.llvm.org/D54425

Files:
  include/clang-c/Index.h
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  include/clang/Basic/Specifiers.h
  lib/AST/ItaniumMangle.cpp
  lib/AST/Type.cpp
  lib/AST/TypePrinter.cpp
  lib/Basic/Targets/AArch64.cpp
  lib/CodeGen/CGCall.cpp
  lib/CodeGen/CGDebugInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  lib/Sema/SemaType.cpp
  test/CodeGen/aarch64-vpcs.c
  test/Sema/aarch64-vpcs.c
  test/Sema/callingconv.c
  tools/libclang/CXType.cpp

Index: tools/libclang/CXType.cpp
===
--- tools/libclang/CXType.cpp
+++ tools/libclang/CXType.cpp
@@ -651,6 +651,7 @@
   TCALLINGCONV(X86Pascal);
   TCALLINGCONV(X86RegCall);
   TCALLINGCONV(X86VectorCall);
+  TCALLINGCONV(AArch64VectorCall);
   TCALLINGCONV(Win64);
   TCALLINGCONV(X86_64SysV);
   TCALLINGCONV(AAPCS);
Index: test/Sema/callingconv.c
===
--- test/Sema/callingconv.c
+++ test/Sema/callingconv.c
@@ -51,6 +51,8 @@
 int __attribute__((pcs("aapcs-vfp"))) pcs6(void); // expected-warning {{calling convention 'pcs' ignored for this target}}
 int __attribute__((pcs("foo"))) pcs7(void); // expected-error {{invalid PCS type}}
 
+int __attribute__((aarch64_vector_pcs)) aavpcs(void); // expected-warning {{calling convention 'aarch64_vector_pcs' ignored for this target}}
+
 // PR6361
 void ctest3();
 void __attribute__((cdecl)) ctest3() {}
Index: test/Sema/aarch64-vpcs.c
===
--- /dev/null
+++ test/Sema/aarch64-vpcs.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -verify %s
+
+typedef __attribute__((aarch64_vector_pcs)) int invalid_typedef; // expected-warning {{'aarch64_vector_pcs' only applies to function types; type here is 'int'}}
+
+void __attribute__((aarch64_vector_pcs(0))) foo0(void); // expected-error {{'aarch64_vector_pcs' attribute takes no arguments}}
+
+void __attribute__((aarch64_vector_pcs, preserve_all)) foo1(void); // expected-error {{not compatible}}
+
+void __attribute__((cdecl)) foo2(void);// expected-note {{previous declaration is here}}
+void __attribute__((aarch64_vector_pcs)) foo2(void) {} // expected-error {{function declared 'aarch64_vector_pcs' here was previously declared 'cdecl'}}
+
+void foo3(void);   // expected-note {{previous declaration is here}}
+void __attribute__((aarch64_vector_pcs)) foo3(void) {} // expected-error {{function declared 'aarch64_vector_pcs' here was previously declared without calling convention}}
+
+typedef int (*fn_ty)(void);
+typedef int __attribute__((aarch64_vector_pcs)) (*aavpcs_fn_ty)(void);
+void foo4(fn_ty ptr1, aavpcs_fn_ty ptr2) {
+  ptr1 = ptr2; // expected-warning {{incompatible function pointer types}}
+}
Index: test/CodeGen/aarch64-vpcs.c
===
--- /dev/null
+++ test/CodeGen/aarch64-vpcs.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECKC
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -x c++ -o - %s | FileCheck %s -check-prefix=CHECKCXX
+// RUN: %clang_cc1 -triple i686-pc-linux-gnu -verify %s
+
+void __attribute__((aarch64_vector_pcs)) f(int *); // expected-warning {{calling convention 'aarch64_vector_pcs' ignored for this target}}
+
+// CHECKC: define void @g(
+// CHECKCXX: define void @_Z1gPi(
+void g(int *a) {
+
+// CHECKC: call aarch64_vector_pcs void @f(
+// CHECKCXX: call aarch64_vector_pcs void @_Z1fPi
+  f(a);
+}
+
+// CHECKC: declare aarch64_vector_pcs void @f(
+// CHECKCXX: declare aarch64_vector_pcs void @_Z1fPi
+
+void __attribute__((aarch64_vector_pcs)) h(int *a){ // expected-warning {{calling convention 'aarch64_vector_pcs' ignored for this target}}
+// CHECKC: define aarch64_vector_pcs void @h(
+// CHECKCXX: define aarch64_vector_pcs void @_Z1hPi(
+  f(a);
+}
Index: lib/Sema/SemaType.cpp
===
--- lib/Sema/SemaType.cpp
+++ lib/Sema/SemaType.cpp
@@ -116,6 +116,7 @@
   case ParsedAttr::AT_Pascal:  \
   case ParsedAttr::AT_SwiftCall:   \
   case ParsedAttr::AT_VectorCall:  \
+  case ParsedAttr::AT_AArch64VectorPcs:\
   case ParsedAttr::AT_MSABI:   \
   case ParsedAttr::AT_SysVABI: \
   case Parse

[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

2018-11-19 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a subscriber: keith.walker.arm.
sdesmalen added inline comments.



Comment at: lib/CodeGen/CGDebugInfo.cpp:1101
   case CC_AAPCS:
+  case CC_AArch64VectorCall:
 return llvm::dwarf::DW_CC_LLVM_AAPCS;

rjmccall wrote:
> rnk wrote:
> > sdesmalen wrote:
> > > I wasn't really sure whether this requires a corresponding 
> > > DW_CC_LLVM_AAVPCS record in LLVM, as I couldn't find much about the 
> > > DW_CC_LLVM_  encodings, specifically whether they align with some agreed 
> > > encoding that is implemented by GDB/LLDB. Is this defined anywhere, or is 
> > > it ignored by debuggers at the moment?
> > DWARF only allows encoding 256 conventions, and we grabbed 0xC[0-F], I 
> > guess for "clang", so we probably want to be careful about adding another. 
> > Do you anticipate making debuggers able to call such functions? If not, 
> > it's probably not worth it.
> They probably should be callable.
> 
> It looks like DWARF reserves the first 64 conventions for general/language 
> purposes and treats the rest of the range as "user" conventions.   If those 
> conventions are assumed to be universally unique, that's a really limiting 
> schema once you started dividing it up by vendor.  If I might make a 
> suggestion, while there are certainly many calling conventions that are meant 
> to have universal meaning (e.g. most language-specific conventions), there 
> are also a large number that are inherently target-specific.  DWARF already 
> uses a lot of numbers that only make sense in the context of a target (like 
> register numbers); it would make sense for DWARF to carve out a range of the 
> encoding space (maybe 16 or 32 numbers) for target-specific CCs.  This is 
> hardly the first example; consider also all the variant ARM32 CCs or the i386 
> fastcall CC.
Great feedback. I think this discussion has a wider scope than this patch and I 
think its probably best to keep this change as-is for now. We'll first work to 
add a section to the 'DWARF for the ARM 64-bit Architecture' document 
describing a DW_AT_calling_convention value for the AArch64 vector PCS and will 
create a separate patch to LLVM/Clang to implement its support. I've also asked 
@keith.walker.arm to raise this (encoding space) as a topic with the DWARF 
standardization committee.


https://reviews.llvm.org/D54425



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[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

2018-11-26 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a comment.

Just to double check before committing, @aaron.ballman are you happy with the 
tests?


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[PATCH] D54425: [AArch64] Add aarch64_vector_pcs function attribute to Clang

2018-11-26 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen updated this revision to Diff 175236.
sdesmalen added a comment.

- resolved editorial comments.


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Files:
  include/clang-c/Index.h
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  include/clang/Basic/Specifiers.h
  lib/AST/ItaniumMangle.cpp
  lib/AST/Type.cpp
  lib/AST/TypePrinter.cpp
  lib/Basic/Targets/AArch64.cpp
  lib/CodeGen/CGCall.cpp
  lib/CodeGen/CGDebugInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  lib/Sema/SemaType.cpp
  test/CodeGen/aarch64-vpcs.c
  test/Sema/aarch64-vpcs.c
  test/Sema/callingconv.c
  tools/libclang/CXType.cpp

Index: tools/libclang/CXType.cpp
===
--- tools/libclang/CXType.cpp
+++ tools/libclang/CXType.cpp
@@ -651,6 +651,7 @@
   TCALLINGCONV(X86Pascal);
   TCALLINGCONV(X86RegCall);
   TCALLINGCONV(X86VectorCall);
+  TCALLINGCONV(AArch64VectorCall);
   TCALLINGCONV(Win64);
   TCALLINGCONV(X86_64SysV);
   TCALLINGCONV(AAPCS);
Index: test/Sema/callingconv.c
===
--- test/Sema/callingconv.c
+++ test/Sema/callingconv.c
@@ -51,6 +51,8 @@
 int __attribute__((pcs("aapcs-vfp"))) pcs6(void); // expected-warning {{calling convention 'pcs' ignored for this target}}
 int __attribute__((pcs("foo"))) pcs7(void); // expected-error {{invalid PCS type}}
 
+int __attribute__((aarch64_vector_pcs)) aavpcs(void); // expected-warning {{calling convention 'aarch64_vector_pcs' ignored for this target}}
+
 // PR6361
 void ctest3();
 void __attribute__((cdecl)) ctest3() {}
Index: test/Sema/aarch64-vpcs.c
===
--- /dev/null
+++ test/Sema/aarch64-vpcs.c
@@ -0,0 +1,19 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -verify %s
+
+typedef __attribute__((aarch64_vector_pcs)) int invalid_typedef; // expected-warning {{'aarch64_vector_pcs' only applies to function types; type here is 'int'}}
+
+void __attribute__((aarch64_vector_pcs(0))) foo0(void); // expected-error {{'aarch64_vector_pcs' attribute takes no arguments}}
+
+void __attribute__((aarch64_vector_pcs, preserve_all)) foo1(void); // expected-error {{not compatible}}
+
+void __attribute__((cdecl)) foo2(void);// expected-note {{previous declaration is here}}
+void __attribute__((aarch64_vector_pcs)) foo2(void) {} // expected-error {{function declared 'aarch64_vector_pcs' here was previously declared 'cdecl'}}
+
+void foo3(void);   // expected-note {{previous declaration is here}}
+void __attribute__((aarch64_vector_pcs)) foo3(void) {} // expected-error {{function declared 'aarch64_vector_pcs' here was previously declared without calling convention}}
+
+typedef int (*fn_ty)(void);
+typedef int __attribute__((aarch64_vector_pcs)) (*aavpcs_fn_ty)(void);
+void foo4(fn_ty ptr1, aavpcs_fn_ty ptr2) {
+  ptr1 = ptr2; // expected-warning {{incompatible function pointer types}}
+}
Index: test/CodeGen/aarch64-vpcs.c
===
--- /dev/null
+++ test/CodeGen/aarch64-vpcs.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECKC
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -x c++ -o - %s | FileCheck %s -check-prefix=CHECKCXX
+// RUN: %clang_cc1 -triple i686-pc-linux-gnu -verify %s
+
+void __attribute__((aarch64_vector_pcs)) f(int *); // expected-warning {{calling convention 'aarch64_vector_pcs' ignored for this target}}
+
+// CHECKC: define void @g(
+// CHECKCXX: define void @_Z1gPi(
+void g(int *a) {
+
+// CHECKC: call aarch64_vector_pcs void @f(
+// CHECKCXX: call aarch64_vector_pcs void @_Z1fPi
+  f(a);
+}
+
+// CHECKC: declare aarch64_vector_pcs void @f(
+// CHECKCXX: declare aarch64_vector_pcs void @_Z1fPi
+
+void __attribute__((aarch64_vector_pcs)) h(int *a){ // expected-warning {{calling convention 'aarch64_vector_pcs' ignored for this target}}
+// CHECKC: define aarch64_vector_pcs void @h(
+// CHECKCXX: define aarch64_vector_pcs void @_Z1hPi(
+  f(a);
+}
Index: lib/Sema/SemaType.cpp
===
--- lib/Sema/SemaType.cpp
+++ lib/Sema/SemaType.cpp
@@ -116,6 +116,7 @@
   case ParsedAttr::AT_Pascal:  \
   case ParsedAttr::AT_SwiftCall:   \
   case ParsedAttr::AT_VectorCall:  \
+  case ParsedAttr::AT_AArch64VectorPcs:\
   case ParsedAttr::AT_MSABI:   \
   case ParsedAttr::AT_SysVABI: \
   case ParsedAttr::AT_Pcs: \
@@ -6653,6 +6654,8 @@
 return createSimpleAttr(Ctx, Attr);
   ca

[PATCH] D64739: [SVE][Inline-Asm] Add support to clang for SVE inline assembly

2019-07-17 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a comment.

Functionally the patch looks good, but the title suggests this adds full 
inline-asm support for SVE (which would require the ACLE types proposed in 
D62960 , as well as other changes), where this 
patch only adds support to specify SVE registers in the clobber list.




Comment at: clang/test/CodeGen/aarch64-sve-inline-asm.c:4
+long test_z0_p0()
+{
+  long t;

nit: there is no reason to have a different code-style for code and tests 
(curly brace is on next line here).
Maybe run this through clang-format?



Comment at: clang/test/CodeGen/aarch64-sve-inline-asm.c:7
+
+  asm volatile(
+"ptrue p0.d\n"

nit: The asm/instructions here don't really need to make sense (as in: they are 
not executed), so you can combine all three tests into one, as long as the 
instructions are valid and z0, p0, z31 and z15 are used.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D64739: [SVE][Inline-Asm] Add support to specify SVE registers in the clobber list

2019-07-22 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/test/CodeGen/aarch64-sve-inline-asm.c:1
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -target-feature 
+sve -o - %s | FileCheck %s
+

rovka wrote:
> Can you also add a test without +sve, to make sure we get a diagnostic?
Without the `-emit-llvm` part this test invokes (and tests the diagnostic of) 
the compiler. I don't think this is what we want. At the same time, this code 
should probably still continue match the z and p registers even if the target 
feature is not given, and thus leave it to LLVM to determine whether the use of 
these registers makes sense or not. So removing `-target-feature +sve` from the 
RUN line should be sufficient here. @rovka do you agree?



Comment at: clang/test/CodeGen/aarch64-sve-inline-asm.c:12
+  "add z31.d, p0/m, z31.d, z31.d\n"
+  : "=w"(t)
+  :

There is no variable linked to `t` in this inline asm, so you can remove this 
clause.


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[PATCH] D64739: [SVE][Inline-Asm] Add support to specify SVE registers in the clobber list

2019-07-23 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D65404: [AArch64] Disable __ARM_FEATURE_SVE without ACLE.

2019-07-29 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: c-rhodes, chill, rengolin, rovka.
Herald added subscribers: kristof.beyls, tschuett, javed.absar.

The Arm C Language Extensions for SVE document specifies that 
__ARM_FEATURE_SVE should be set when the compiler supports SVE and
implements all the extensions described in the document.

This is currently not yet the case, so the feature should be disabled
until the compiler can provide all the extensions as described.


https://reviews.llvm.org/D65404

Files:
  lib/Basic/Targets/AArch64.cpp
  test/Preprocessor/aarch64-target-features.c


Index: test/Preprocessor/aarch64-target-features.c
===
--- test/Preprocessor/aarch64-target-features.c
+++ test/Preprocessor/aarch64-target-features.c
@@ -88,7 +88,7 @@
 // RUN: %clang -target aarch64 -mtune=cyclone -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-MTUNE-CYCLONE %s
 
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+sve -x c -E -dM 
%s -o - | FileCheck --check-prefix=CHECK-SVE %s
-// CHECK-SVE: __ARM_FEATURE_SVE 1
+// CHECK-SVE-NOT: __ARM_FEATURE_SVE 1
 
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8.2a+dotprod -x c -E 
-dM %s -o - | FileCheck --check-prefix=CHECK-DOTPROD %s
 // CHECK-DOTPROD: __ARM_FEATURE_DOTPROD 1
Index: lib/Basic/Targets/AArch64.cpp
===
--- lib/Basic/Targets/AArch64.cpp
+++ lib/Basic/Targets/AArch64.cpp
@@ -196,9 +196,6 @@
 Builder.defineMacro("__ARM_NEON_FP", "0xE");
   }
 
-  if (FPU & SveMode)
-Builder.defineMacro("__ARM_FEATURE_SVE", "1");
-
   if (HasCRC)
 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
 


Index: test/Preprocessor/aarch64-target-features.c
===
--- test/Preprocessor/aarch64-target-features.c
+++ test/Preprocessor/aarch64-target-features.c
@@ -88,7 +88,7 @@
 // RUN: %clang -target aarch64 -mtune=cyclone -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MTUNE-CYCLONE %s
 
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+sve -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE %s
-// CHECK-SVE: __ARM_FEATURE_SVE 1
+// CHECK-SVE-NOT: __ARM_FEATURE_SVE 1
 
 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8.2a+dotprod -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-DOTPROD %s
 // CHECK-DOTPROD: __ARM_FEATURE_DOTPROD 1
Index: lib/Basic/Targets/AArch64.cpp
===
--- lib/Basic/Targets/AArch64.cpp
+++ lib/Basic/Targets/AArch64.cpp
@@ -196,9 +196,6 @@
 Builder.defineMacro("__ARM_NEON_FP", "0xE");
   }
 
-  if (FPU & SveMode)
-Builder.defineMacro("__ARM_FEATURE_SVE", "1");
-
   if (HasCRC)
 Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
 
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[PATCH] D65404: [AArch64] Disable __ARM_FEATURE_SVE without ACLE.

2019-07-30 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a comment.

Thanks, I see your argument for having the feature enabled even when the ACLE 
is still partially supported. At the moment however, LLVM still only support 
the assembler/disassembler and inline asm.
We'll be working to add support for the ACLE soon, but for now having the flag 
enabled sets the wrong expectations.


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[PATCH] D66302: [SVE][Inline-Asm] Support for SVE asm operands

2019-08-16 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a comment.

Thanks for this change @kmclaughlin.




Comment at: docs/LangRef.rst:3816
+- ``x``: Like w, but restricted to registers 0 to 15 inclusive.
+- ``y``: Like w, but restricted to registers 0 to 7 inclusive.
 

I noticed this comment does not match the code below, since `y` only seems to 
work for scalable vectors, which probably shows this case is missing a test.


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[PATCH] D67549: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & Subdivide4)

2019-09-19 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: include/llvm/IR/DerivedTypes.h:500
+default:
+  assert(0 && "Cannot create narrower fp vector element type");
+  break;

nit: Use `llvm_unreachable("message")` instead of `assert(0 && "message")`


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[PATCH] D67549: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & Subdivide4)

2019-09-19 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a comment.

Thanks for the changes @kmclaughlin! Just a few more nits from me, but looks 
good otherwise.




Comment at: include/llvm/IR/DerivedTypes.h:493
+llvm_unreachable("Cannot create narrower fp vector element type");
+break;
+  }

nit: I don't think the break is needed because of the `llvm_unreachable`



Comment at: lib/IR/Function.cpp:992
+assert(VTy && "Expected an argument of Vector Type");
+if (D.Kind == IITDescriptor::Subdivide2Argument)
+  return VectorType::getSubdividedVectorType(VTy, 1);

nit: you can simplify this by:
```
int SubDiv = D.Kind == IITDescriptor::Subdivide2Argument ? 1 : 2;
return VectorType::getSubdividedVectorType(VTy, SubDiv);
```



Comment at: lib/IR/Function.cpp:1302
+  Type *NewTy = ArgTys[D.getArgumentNumber()];
+  if (VectorType *VTy = dyn_cast(NewTy)) {
+if (D.Kind == IITDescriptor::Subdivide2Argument)

nit: you can use `auto *VTy` here since the `dyn_cast` makes it 
clear that the return type is `VectorType`.



Comment at: lib/IR/Function.cpp:1303
+  if (VectorType *VTy = dyn_cast(NewTy)) {
+if (D.Kind == IITDescriptor::Subdivide2Argument)
+  NewTy = VectorType::getSubdividedVectorType(VTy, 1);

nit: can be simplified by:
```int SubDiv = D.Kind == IITDescriptor::Subdivide2Argument ? 1 : 2;
NewTy = VectorType::getSubdividedVectorType(VTy, SubDiv);```



Comment at: lib/IR/Function.cpp:1310
+
+  return Ty != NewTy;
+}

nit: Move this return statement into the `if(VectorType *VTy = 
dyn_cast(NewTy))` block?


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[PATCH] D67549: [IntrinsicEmitter] Add overloaded types for SVE intrinsics (Subdivide2 & Subdivide4)

2019-09-20 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

Thanks, LGTM!


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[PATCH] D67830: [AArch64][SVE] Implement punpk[hi|lo] intrinsics

2019-09-20 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

LGTM. Looks like a straightforward fix and support for `punpk(hi|lo)` 
intrinsics.




Comment at: llvm/lib/IR/Function.cpp:1213
   // If this is a forward reference, defer the check for later.
-  return D.getArgumentNumber() >= ArgTys.size() ||
- !isa(ArgTys[D.getArgumentNumber()]) ||
+  if (D.getArgumentNumber() >= ArgTys.size())
+return IsDeferredCheck || DeferCheck(Ty);

Nice find!



Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll:1
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+

nit: You've added the file `sve-intrinsics-pred-operations.ll`. Is it worth 
putting these in a separate directory and separate out the tests per intrinsic, 
e.g. `test/CodeGen/AArch64/SVE/sve-intrinsics-punpkhi.ll`


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[PATCH] D53137: Scalable vector core instruction support + size queries

2019-10-02 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.

Thanks @huntergr , I think this interface looks really nice. LGTM!




Comment at: llvm/include/llvm/IR/DataLayout.h:456
+  TypeSize getTypeStoreSize(Type *Ty) const {
+auto BaseSize = getTypeSizeInBits(Ty);
+return { (BaseSize.getKnownMinSize() + 7) / 8, BaseSize.isScalable() };

nit: use TypeSize instead of auto.



Comment at: llvm/include/llvm/IR/DataLayout.h:622
   case Type::LabelTyID:
-return getPointerSizeInBits(0);
+return TypeSize::Fixed(getPointerSizeInBits(0));
   case Type::PointerTyID:

Nice, I like the interface of `TypeSize::Fixed()` for fixed-size types.



Comment at: llvm/lib/IR/Instructions.cpp:2990
   // Get the bit sizes, we'll need these
-  unsigned SrcBits = SrcTy->getPrimitiveSizeInBits();   // 0 for ptr
-  unsigned DestBits = DestTy->getPrimitiveSizeInBits(); // 0 for ptr
+  auto SrcBits = SrcTy->getPrimitiveSizeInBits();   // 0 for ptr
+  auto DestBits = DestTy->getPrimitiveSizeInBits(); // 0 for ptr

nit: auto -> TypeSize ?



Comment at: llvm/lib/IR/Instructions.cpp:3052
 
-  unsigned SrcBits = SrcTy->getPrimitiveSizeInBits();   // 0 for ptr
-  unsigned DestBits = DestTy->getPrimitiveSizeInBits(); // 0 for ptr
+  auto SrcBits = SrcTy->getPrimitiveSizeInBits();   // 0 for ptr
+  auto DestBits = DestTy->getPrimitiveSizeInBits(); // 0 for ptr

nit: auto -> TypeSize ?


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[PATCH] D67551: [AArch64][SVE] Implement sdot and udot (lane) intrinsics

2019-10-11 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D69378: [AArch64][SVE] Implement masked store intrinsics

2019-10-29 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a comment.

Thanks for the changes to the tests.




Comment at: llvm/test/CodeGen/AArch64/sve-masked-ldst-trunc.ll:9
+; CHECK-LABEL: masked_trunc_store_nxv2i8:
+; CHECK: st1b { [[IN:z[0-9]]].d }, [[PG:p[0-9]]], [x1]
+  %trunc = trunc  %val to 

I think it may be worth testing for z1.d explicitly and use CHECK-NEXT to make 
sure there are no other instructions that could do the truncation.


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[PATCH] D69567: [AArch64][SVE] Implement additional integer arithmetic intrinsics

2019-10-29 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

Thanks, LGTM


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[PATCH] D80740: [SveEmitter] Add SVE ACLE for svld1ro.

2020-05-29 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

LGTM!


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[PATCH] D84021: [Driver] Add suppoort for -msve-vector-bits=scalable.

2020-07-17 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

nit: s/suppoort/support/ (in title)
LGTM otherwise!


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[PATCH] D84021: [Driver] Add support for -msve-vector-bits=scalable.

2020-07-17 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a comment.

Still LGTM :)


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[PATCH] D76680: [SveEmitter] Add immediate checks for lanes and complex imms

2020-04-03 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a comment.

In D76680#1959217 , @SjoerdMeijer 
wrote:

> Looks good to me, but just one question about the tests. If I haven't 
> overlooked anything, I don't see tests that check the new diagnostics:
>  "argument should be the value 90 or 270"
>  "argument should be the value 0,90,180 or 270"
>
> Should they be here, or are they somewhere else?


Good point, I seem to have forgotten to add these tests. I'll update the patch!


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[PATCH] D76617: [SveEmitter] Fix encoding/decoding of SVETypeFlags

2020-04-03 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen updated this revision to Diff 254832.
sdesmalen marked an inline comment as done.
sdesmalen added a comment.

- Updated encode functions to take/return uint64_t instead of unsigned.


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Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -65,9 +65,6 @@
 applyModifier(CharMod);
   }
 
-  /// Return the value in SVETypeFlags for this type.
-  unsigned getTypeFlags() const;
-
   bool isPointer() const { return Pointer; }
   bool isVoidPointer() const { return Pointer && Void; }
   bool isSigned() const { return Signed; }
@@ -138,36 +135,22 @@
   /// The architectural #ifdef guard.
   std::string Guard;
 
+  // The merge suffix such as _m, _x or _z.
+  std::string MergeSuffix;
+
   /// The types of return value [0] and parameters [1..].
   std::vector Types;
 
   /// The "base type", which is VarType('d', BaseTypeSpec).
   SVEType BaseType;
 
-  unsigned Flags;
+  uint64_t Flags;
 
 public:
-  /// The type of predication.
-  enum MergeType {
-MergeNone,
-MergeAny,
-MergeOp1,
-MergeZero,
-MergeAnyExp,
-MergeZeroExp,
-MergeInvalid
-  } Merge;
-
-  Intrinsic(StringRef Name, StringRef Proto, int64_t MT, StringRef LLVMName,
-unsigned Flags, TypeSpec BT, ClassKind Class, SVEEmitter &Emitter,
-StringRef Guard)
-  : Name(Name.str()), LLVMName(LLVMName), Proto(Proto.str()),
-BaseTypeSpec(BT), Class(Class), Guard(Guard.str()), BaseType(BT, 'd'),
-Flags(Flags), Merge(MergeType(MT)) {
-// Types[0] is the return value.
-for (unsigned I = 0; I < Proto.size(); ++I)
-  Types.emplace_back(BaseTypeSpec, Proto[I]);
-  }
+  Intrinsic(StringRef Name, StringRef Proto, uint64_t MergeTy,
+StringRef MergeSuffix, uint64_t MemoryElementTy, StringRef LLVMName,
+uint64_t Flags, TypeSpec BT, ClassKind Class, SVEEmitter &Emitter,
+StringRef Guard);
 
   ~Intrinsic()=default;
 
@@ -179,14 +162,13 @@
 
   StringRef getGuard() const { return Guard; }
   ClassKind getClassKind() const { return Class; }
-  MergeType getMergeType() const { return Merge; }
 
   SVEType getReturnType() const { return Types[0]; }
   ArrayRef getTypes() const { return Types; }
   SVEType getParamType(unsigned I) const { return Types[I + 1]; }
   unsigned getNumParams() const { return Proto.size() - 1; }
 
-  unsigned getFlags() const { return Flags; }
+  uint64_t getFlags() const { return Flags; }
   bool isFlagSet(uint64_t Flag) const { return Flags & Flag;}
 
   /// Return the type string for a BUILTIN() macro in Builtins.def.
@@ -209,7 +191,7 @@
   void emitIntrinsic(raw_ostream &OS) const;
 
 private:
-  std::string getMergeSuffix() const;
+  std::string getMergeSuffix() const { return MergeSuffix; }
   std::string mangleName(ClassKind LocalCK) const;
   std::string replaceTemplatedArgs(std::string Name, TypeSpec TS,
std::string Proto) const;
@@ -221,8 +203,8 @@
   llvm::StringMap EltTypes;
   llvm::StringMap MemEltTypes;
   llvm::StringMap FlagTypes;
+  llvm::StringMap MergeTypes;
 
-  unsigned getTypeFlags(const SVEType &T);
 public:
   SVEEmitter(RecordKeeper &R) : Records(R) {
 for (auto *RV : Records.getAllDerivedDefinitions("EltType"))
@@ -231,8 +213,42 @@
   MemEltTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
 for (auto *RV : Records.getAllDerivedDefinitions("FlagType"))
   FlagTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+for (auto *RV : Records.getAllDerivedDefinitions("MergeType"))
+  MergeTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+  }
+
+  // Returns the SVETypeFlags for a given value and mask.
+  uint64_t encodeFlag(uint64_t V, StringRef MaskName) const {
+auto It = FlagTypes.find(MaskName);
+if (It != FlagTypes.end()) {
+  uint64_t Mask = It->getValue();
+  unsigned Shift = llvm::countTrailingZeros(Mask);
+  return (V << Shift) & Mask;
+}
+llvm_unreachable("Unsupported flag");
+  }
+
+  // Returns the SVETypeFlags for the given element type.
+  uint64_t encodeEltType(StringRef EltName) {
+auto It = EltTypes.find(EltName);
+if (It != EltTypes.end())
+  return encodeFlag(It->getValue(), "EltTypeMask");
+llvm_unreachable("Unsupported EltType");
+  }
+
+  // Returns the SVETypeFlags for the given memory element type.
+  uint64_t encodeMemoryElementType(unsigned MT) {
+return encodeFlag(MT, "MemEltTypeMask");
   }
 
+  // Returns the SVETypeFlags for the given merge type.
+  uint64_t encodeMergeType(unsigned MT) {
+return encodeFlag(MT, "MergeTypeMask");
+  }
+
+  // Returns the SVETypeFlags value

[PATCH] D76617: [SveEmitter] Fix encoding/decoding of SVETypeFlags

2020-04-03 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/utils/TableGen/SveEmitter.cpp:229
+  // Returns the SVETypeFlags for a given value and mask.
+  unsigned encodeFlag(unsigned V, StringRef MaskName) const {
+auto It = FlagTypes.find(MaskName);

SjoerdMeijer wrote:
> Should `V` now be an `uint64_t`?
Yes, good spot!


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[PATCH] D76679: [SveEmitter] Add more immediate operand checks.

2020-04-03 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a comment.

In D76679#1957399 , @SjoerdMeijer 
wrote:

> I think the float16 discussion is an interesting one, but doesn't necessarily 
> need to be done here. I am asking some questions offline, but if we ever come 
> to a different opinion on it, then we can follow up so it's somewhat 
> orthogonal to this change, and so this looks fine to me.


Thanks for reviewing the patch Sjoerd!


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[PATCH] D76617: [SveEmitter] Fix encoding/decoding of SVETypeFlags

2020-04-06 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen updated this revision to Diff 255276.
sdesmalen added a comment.

Changed `unsigned` -> `uint64_t` for `encodeMemoryElementType` and 
`encodeMergeType`.


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Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -65,9 +65,6 @@
 applyModifier(CharMod);
   }
 
-  /// Return the value in SVETypeFlags for this type.
-  unsigned getTypeFlags() const;
-
   bool isPointer() const { return Pointer; }
   bool isVoidPointer() const { return Pointer && Void; }
   bool isSigned() const { return Signed; }
@@ -138,36 +135,22 @@
   /// The architectural #ifdef guard.
   std::string Guard;
 
+  // The merge suffix such as _m, _x or _z.
+  std::string MergeSuffix;
+
   /// The types of return value [0] and parameters [1..].
   std::vector Types;
 
   /// The "base type", which is VarType('d', BaseTypeSpec).
   SVEType BaseType;
 
-  unsigned Flags;
+  uint64_t Flags;
 
 public:
-  /// The type of predication.
-  enum MergeType {
-MergeNone,
-MergeAny,
-MergeOp1,
-MergeZero,
-MergeAnyExp,
-MergeZeroExp,
-MergeInvalid
-  } Merge;
-
-  Intrinsic(StringRef Name, StringRef Proto, int64_t MT, StringRef LLVMName,
-unsigned Flags, TypeSpec BT, ClassKind Class, SVEEmitter &Emitter,
-StringRef Guard)
-  : Name(Name.str()), LLVMName(LLVMName), Proto(Proto.str()),
-BaseTypeSpec(BT), Class(Class), Guard(Guard.str()), BaseType(BT, 'd'),
-Flags(Flags), Merge(MergeType(MT)) {
-// Types[0] is the return value.
-for (unsigned I = 0; I < Proto.size(); ++I)
-  Types.emplace_back(BaseTypeSpec, Proto[I]);
-  }
+  Intrinsic(StringRef Name, StringRef Proto, uint64_t MergeTy,
+StringRef MergeSuffix, uint64_t MemoryElementTy, StringRef LLVMName,
+uint64_t Flags, TypeSpec BT, ClassKind Class, SVEEmitter &Emitter,
+StringRef Guard);
 
   ~Intrinsic()=default;
 
@@ -179,14 +162,13 @@
 
   StringRef getGuard() const { return Guard; }
   ClassKind getClassKind() const { return Class; }
-  MergeType getMergeType() const { return Merge; }
 
   SVEType getReturnType() const { return Types[0]; }
   ArrayRef getTypes() const { return Types; }
   SVEType getParamType(unsigned I) const { return Types[I + 1]; }
   unsigned getNumParams() const { return Proto.size() - 1; }
 
-  unsigned getFlags() const { return Flags; }
+  uint64_t getFlags() const { return Flags; }
   bool isFlagSet(uint64_t Flag) const { return Flags & Flag;}
 
   /// Return the type string for a BUILTIN() macro in Builtins.def.
@@ -209,7 +191,7 @@
   void emitIntrinsic(raw_ostream &OS) const;
 
 private:
-  std::string getMergeSuffix() const;
+  std::string getMergeSuffix() const { return MergeSuffix; }
   std::string mangleName(ClassKind LocalCK) const;
   std::string replaceTemplatedArgs(std::string Name, TypeSpec TS,
std::string Proto) const;
@@ -221,8 +203,8 @@
   llvm::StringMap EltTypes;
   llvm::StringMap MemEltTypes;
   llvm::StringMap FlagTypes;
+  llvm::StringMap MergeTypes;
 
-  unsigned getTypeFlags(const SVEType &T);
 public:
   SVEEmitter(RecordKeeper &R) : Records(R) {
 for (auto *RV : Records.getAllDerivedDefinitions("EltType"))
@@ -231,8 +213,42 @@
   MemEltTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
 for (auto *RV : Records.getAllDerivedDefinitions("FlagType"))
   FlagTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+for (auto *RV : Records.getAllDerivedDefinitions("MergeType"))
+  MergeTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+  }
+
+  // Returns the SVETypeFlags for a given value and mask.
+  uint64_t encodeFlag(uint64_t V, StringRef MaskName) const {
+auto It = FlagTypes.find(MaskName);
+if (It != FlagTypes.end()) {
+  uint64_t Mask = It->getValue();
+  unsigned Shift = llvm::countTrailingZeros(Mask);
+  return (V << Shift) & Mask;
+}
+llvm_unreachable("Unsupported flag");
+  }
+
+  // Returns the SVETypeFlags for the given element type.
+  uint64_t encodeEltType(StringRef EltName) {
+auto It = EltTypes.find(EltName);
+if (It != EltTypes.end())
+  return encodeFlag(It->getValue(), "EltTypeMask");
+llvm_unreachable("Unsupported EltType");
+  }
+
+  // Returns the SVETypeFlags for the given memory element type.
+  uint64_t encodeMemoryElementType(uint64_t MT) {
+return encodeFlag(MT, "MemEltTypeMask");
   }
 
+  // Returns the SVETypeFlags for the given merge type.
+  uint64_t encodeMergeType(uint64_t MT) {
+return encodeFlag(MT, "MergeTypeMask");
+  }
+
+  // Returns the SVETypeFlags value for the given SVEType.
+  ui

[PATCH] D76678: [SveEmitter] Add range checks for immediates and predicate patterns.

2020-04-06 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen updated this revision to Diff 255278.
sdesmalen marked 3 inline comments as done.
sdesmalen added a comment.

- Renamed `ImmCheckPredicatePattern` -> `ImmCheck0_31`
- Updated tests.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76678/new/

https://reviews.llvm.org/D76678

Files:
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Sema/Sema.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdech.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_qdech.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -95,6 +95,7 @@
 void EmitSveBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitSveBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitSveTypeFlags(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitSveRangeChecks(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitMveHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -74,6 +74,7 @@
   GenArmSveBuiltins,
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
+  GenArmSveRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -197,6 +198,8 @@
"Generate arm_sve_builtin_cg_map.inc for clang"),
 clEnumValN(GenArmSveTypeFlags, "gen-arm-sve-typeflags",
"Generate arm_sve_typeflags.inc for clang"),
+clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
+   "Generate arm_sve_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -390,6 +393,9 @@
   case GenArmSveTypeFlags:
 EmitSveTypeFlags(Records, OS);
 break;
+  case GenArmSveRangeChecks:
+EmitSveRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -46,6 +46,22 @@
 
 namespace {
 
+class ImmCheck {
+  unsigned Arg;
+  unsigned Kind;
+  unsigned ElementSizeInBits;
+
+public:
+  ImmCheck(unsigned Arg, unsigned Kind, unsigned ElementSizeInBits = 0)
+  : Arg(Arg), Kind(Kind), ElementSizeInBits(ElementSizeInBits) {}
+  ImmCheck(const ImmCheck &Other) = default;
+  ~ImmCheck() = default;
+
+  unsigned getArg() const { return Arg; }
+  unsigned getKind() const { return Kind; }
+  unsigned getElementSizeInBits() const { return ElementSizeInBits; }
+};
+
 class SVEType {
   TypeSpec TS;
   bool Float, Signed, Immediate, Void, Constant, Pointer;
@@ -146,11 +162,13 @@
 
   uint64_t Flags;
 
+  SmallVector ImmChecks;
+
 public:
   Intrinsic(StringRef Name, StringRef Proto, uint64_t MergeTy,
 StringRef MergeSuffix, uint64_t MemoryElementTy, StringRef LLVMName,
-uint64_t Flags, TypeSpec BT, ClassKind Class, SVEEmitter &Emitter,
-StringRef Guard);
+uint64_t Flags, ArrayRef ImmChecks, TypeSpec BT,
+ClassKind Class, SVEEmitter &Emitter, StringRef Guard);
 
   ~Intrinsic()=default;
 
@@ -171,6 +189,8 @@
   uint64_t getFlags() const { return Flags; }
   bool isFlagSet(uint64_t Flag) const { return Flags & Flag;}
 
+  ArrayRef getImmChecks() const { return ImmChecks; }
+
   /// Return the type string for a BUILTIN() macro in Builtins.def.
   std::string getBuiltinTypeStr();
 
@@ -204,6 +224,7 @@
   llvm::StringMap MemEltTypes;
   llvm::StringMap FlagTypes;
   llvm::StringMap MergeTypes;
+  llvm::StringMap ImmCheckTypes;
 
 public:
   SVEEmitter(RecordKeeper &R) : Records(R) {
@@ -215,6 +236,16 @@
   FlagTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
 for (auto *RV : Records.getAllDerivedDefinitions("MergeType"))
   MergeTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+for (auto *RV : Records.getAllDerivedDefinitions("ImmCheckType"))
+  ImmCheckTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+  }
+
+  /// Returns the enum value for the immcheck type
+  unsigned getEnumValueForImmCheck(StringRef C) const {
+auto It = ImmCheckTypes.find(C);
+if (It

[PATCH] D76680: [SveEmitter] Add immediate checks for lanes and complex imms

2020-04-06 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen updated this revision to Diff 255282.
sdesmalen added a comment.

- Updated tests.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76680/new/

https://reviews.llvm.org/D76680

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/arm_sve.td
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmla.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dot.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mla.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_cadd.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_cmla.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_dot.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_mla.c
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -455,9 +455,19 @@
 Bitwidth = ElementBitwidth;
 NumVectors = 0;
 break;
+  case 'e':
+Signed = false;
+ElementBitwidth /= 2;
+break;
   case 'h':
 ElementBitwidth /= 2;
 break;
+  case 'q':
+ElementBitwidth /= 4;
+break;
+  case 'o':
+ElementBitwidth *= 4;
+break;
   case 'P':
 Signed = true;
 Float = false;
Index: clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_mla.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_mla.c
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+#include 
+
+svfloat16_t test_svmla_lane_f16(svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 7]}}
+  return SVE_ACLE_FUNC(svmla_lane,_f16,,)(op1, op2, op3, 8);
+}
+
+svfloat32_t test_svmla_lane_f32(svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svmla_lane,_f32,,)(op1, op2, op3, -1);
+}
+
+svfloat64_t test_svmla_lane_f64(svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 1]}}
+  return SVE_ACLE_FUNC(svmla_lane,_f64,,)(op1, op2, op3, 2);
+}
Index: clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_dot.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_dot.c
@@ -0,0 +1,47 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+#include 
+
+svint32_t test_svdot_lane_s32(svint32_t op1, svint8_t op2, svint8_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svdot_lane,_s32,,)(op1, op2, op3, -1);
+}
+
+svint32_t test_svdot_lane_s32_1(svint32_t op1, svint8_t op2, svint8_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svdot_lane,_s32,,)(op1, op2, op3, 4);
+}
+
+svint64_t test_svdot_lane_s64(svint64_t op1, svint16_t op2, svint16_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 1]}}
+  return SVE_ACLE_FUNC(svdot_lane,_s64,,)(op1, op2, op3, -1);
+}
+
+svint64_t test_svdot_lane_s64_1(svint64_t op1, svint16_t op2, svint16_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 1]}}
+  return SVE_ACLE_FUNC(svdot_lane,_s64,,)(op1, op2, op3, 2);
+}
+
+svuint32_t test_svdot_lane_u32(svuint32_t op1, svuint8_t op2, svuint8_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svdot_lane,_u32,,)(op1, op2, op3, 4);
+}
+
+svuint64_t test_svdot_lane_u64(svuint64_t op1, svuint16_t op2, svuint

[PATCH] D76678: [SveEmitter] Add range checks for immediates and predicate patterns.

2020-04-06 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a comment.

In D76678#1963576 , @SjoerdMeijer 
wrote:

> LGTM, please wait a day in case Eli has more comments.


Will do, thanks Sjoerd!


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[PATCH] D77257: Clean up usages of asserting vector getters in Type

2020-04-06 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

LGTM!




Comment at: clang/lib/CodeGen/CGBuiltin.cpp:5830
 BuiltinID == NEON::BI__builtin_neon_vqrdmulhq_lane_v)
-  RTy = llvm::VectorType::get(Ty->getVectorElementType(),
-  Ty->getVectorNumElements() * 2);
+  RTy = llvm::VectorType::get(cast(Ty)->getElementType(),
+  cast(Ty)->getNumElements() 
*

nit: Can you pull this into a separate variable so you only have to cast once?
(possibly RTy can be re-used for this)


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D77257/new/

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[PATCH] D77591: [SveEmitter] Explicitly merge with zero/undef

2020-04-06 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: SjoerdMeijer, efriedma, rovka.
Herald added a subscriber: tschuett.
Herald added a project: clang.
sdesmalen added a child revision: D77593: [SveEmitter] Implement zeroing of 
false lanes.

Builtins that have the merge type MergeAnyExp or MergeZeroExp,
merge into a 'undef' or 'zero' vector respectively, which enables the
_x and _z behaviour for unary operations.

  

This patch also adds builtins for svabs and svneg.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77591

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abs.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_neg.c

Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_neg.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_neg.c
@@ -0,0 +1,197 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8_t test_svneg_s8_z(svbool_t pg, svint8_t op)
+{
+  // CHECK-LABEL: test_svneg_s8_z
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.neg.nxv16i8( zeroinitializer,  %pg,  %op)
+  // CHECK: ret  %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svneg,_s8,_z,)(pg, op);
+}
+
+svint16_t test_svneg_s16_z(svbool_t pg, svint16_t op)
+{
+  // CHECK-LABEL: test_svneg_s16_z
+  // CHECK: %[[PG:.*]] = call  @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.neg.nxv8i16( zeroinitializer,  %[[PG]],  %op)
+  // CHECK: ret  %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svneg,_s16,_z,)(pg, op);
+}
+
+svint32_t test_svneg_s32_z(svbool_t pg, svint32_t op)
+{
+  // CHECK-LABEL: test_svneg_s32_z
+  // CHECK: %[[PG:.*]] = call  @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.neg.nxv4i32( zeroinitializer,  %[[PG]],  %op)
+  // CHECK: ret  %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svneg,_s32,_z,)(pg, op);
+}
+
+svint64_t test_svneg_s64_z(svbool_t pg, svint64_t op)
+{
+  // CHECK-LABEL: test_svneg_s64_z
+  // CHECK: %[[PG:.*]] = call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.neg.nxv2i64( zeroinitializer,  %[[PG]],  %op)
+  // CHECK: ret  %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svneg,_s64,_z,)(pg, op);
+}
+
+svint8_t test_svneg_s8_m(svint8_t inactive, svbool_t pg, svint8_t op)
+{
+  // CHECK-LABEL: test_svneg_s8_m
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.neg.nxv16i8( %inactive,  %pg,  %op)
+  // CHECK: ret  %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svneg,_s8,_m,)(inactive, pg, op);
+}
+
+svint16_t test_svneg_s16_m(svint16_t inactive, svbool_t pg, svint16_t op)
+{
+  // CHECK-LABEL: test_svneg_s16_m
+  // CHECK: %[[PG:.*]] = call  @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.neg.nxv8i16( %inactive,  %[[PG]],  %op)
+  // CHECK: ret  %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svneg,_s16,_m,)(inactive, pg, op);
+}
+
+svint32_t test_svneg_s32_m(svint32_t inactive, svbool_t pg, svint32_t op)
+{
+  // CHECK-LABEL: test_svneg_s32_m
+  // CHECK: %[[PG:.*]] = call  @llvm.aarch64.sve.convert.from.svbool.nxv4i1( %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.neg.nxv4i32( %inactive,  %[[PG]],  %op)
+  // CHECK: ret  %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svneg,_s32,_m,)(inactive, pg, op);
+}
+
+svint64_t test_svneg_s64_m(svint64_t inactive, svbool_t pg, svint64_t op)
+{
+  // CHECK-LABEL: test_svneg_s64_m
+  // CHECK: %[[PG:.*]] = call  @llvm.aarch64.sve.convert.from.svbool.nxv2i1( %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.neg.nxv2i64( %inactive,  %[[PG]],  %op)
+  // CHECK: ret  %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svneg,_s64,_m,)(inactive, pg, op);
+}
+
+svint8_t test_svneg_s8_x(svbool_t pg, svint8_t op)
+{
+  // CHECK-LABEL: test_svneg_s8_x
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.neg.nxv16i8( undef,  %pg,  %op)
+  // CHECK: ret  %[[INTRINSIC]]
+  return SVE_ACLE_FUNC(svneg,_s8,_x,)(pg, op);
+}
+
+svint16_t test_svneg_s16_x(svbool_t pg, svint16_t op)
+{
+  // CHECK-LABEL: test_svneg_s16_x
+  // CHECK: %[[PG:.*]] = call  @llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.neg.nxv8i16( undef,  %[[PG]],  %op)
+

[PATCH] D76680: [SveEmitter] Add immediate checks for lanes and complex imms

2020-04-06 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen marked 3 inline comments as done.
sdesmalen added inline comments.



Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:9208
+def err_rotation_argument_to_cmla
+: Error<"argument should be the value 0,90,180 or 270">;
 def warn_neon_vector_initializer_non_portable : Warning<

efriedma wrote:
> SjoerdMeijer wrote:
> > A proper nit, perhaps some spaces here: "0,90,180".
> Still not done?
Sorry, I forgot about that earlier. Should be fixed now.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76680/new/

https://reviews.llvm.org/D76680



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[PATCH] D76680: [SveEmitter] Add immediate checks for lanes and complex imms

2020-04-06 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen updated this revision to Diff 255500.
sdesmalen added a comment.

- Addressed comments - added spaces to `0, 90, 180 or 270`


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76680/new/

https://reviews.llvm.org/D76680

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/arm_sve.td
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmla.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dot.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mla.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_cadd.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_cmla.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_dot.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_mla.c
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -455,9 +455,19 @@
 Bitwidth = ElementBitwidth;
 NumVectors = 0;
 break;
+  case 'e':
+Signed = false;
+ElementBitwidth /= 2;
+break;
   case 'h':
 ElementBitwidth /= 2;
 break;
+  case 'q':
+ElementBitwidth /= 4;
+break;
+  case 'o':
+ElementBitwidth *= 4;
+break;
   case 'P':
 Signed = true;
 Float = false;
Index: clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_mla.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_mla.c
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+#include 
+
+svfloat16_t test_svmla_lane_f16(svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 7]}}
+  return SVE_ACLE_FUNC(svmla_lane,_f16,,)(op1, op2, op3, 8);
+}
+
+svfloat32_t test_svmla_lane_f32(svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svmla_lane,_f32,,)(op1, op2, op3, -1);
+}
+
+svfloat64_t test_svmla_lane_f64(svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 1]}}
+  return SVE_ACLE_FUNC(svmla_lane,_f64,,)(op1, op2, op3, 2);
+}
Index: clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_dot.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_dot.c
@@ -0,0 +1,47 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+#include 
+
+svint32_t test_svdot_lane_s32(svint32_t op1, svint8_t op2, svint8_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svdot_lane,_s32,,)(op1, op2, op3, -1);
+}
+
+svint32_t test_svdot_lane_s32_1(svint32_t op1, svint8_t op2, svint8_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svdot_lane,_s32,,)(op1, op2, op3, 4);
+}
+
+svint64_t test_svdot_lane_s64(svint64_t op1, svint16_t op2, svint16_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 1]}}
+  return SVE_ACLE_FUNC(svdot_lane,_s64,,)(op1, op2, op3, -1);
+}
+
+svint64_t test_svdot_lane_s64_1(svint64_t op1, svint16_t op2, svint16_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 1]}}
+  return SVE_ACLE_FUNC(svdot_lane,_s64,,)(op1, op2, op3, 2);
+}
+
+svuint32_t test_svdot_lane_u32(svuint32_t op1, svuint8_t op2, svuint8_t op3)
+{
+  // expected-error-re@+1 {{argument value {{[0-9]+}} is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svdot_lane,_u32,,)(op1, op2, op3, 4);
+}
+
+svuint64_t test_svdot_lane_

[PATCH] D77597: [SveEmitter] Add ExpandOp1SVALL and builtin for svptrue

2020-04-06 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: SjoerdMeijer, efriedma, rovka.
Herald added a subscriber: tschuett.
Herald added a reviewer: rengolin.
Herald added a project: clang.
sdesmalen added a parent revision: D77596: [SveEmitter] Add NoOverload flag and 
builtin for svpfalse.

Some ACLE builtins leave out the argument to specify the predicate
pattern, which is expected to be expanded to SV_ALL pattern.

This patch adds the flag ExpandOp1SVALL to expand the second operand
to an SVE_ALL value, or append a SV_ALL if the builtin only takes
a single operand.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77597

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptrue.c

Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptrue.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptrue.c
@@ -0,0 +1,201 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+svbool_t test_svptrue_b8()
+{
+  // CHECK-LABEL: test_svptrue_b8
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_b8();
+}
+
+svbool_t test_svptrue_b16()
+{
+  // CHECK-LABEL: test_svptrue_b16
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
+  // CHECK: %[[CAST:.*]] = call  @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %[[INTRINSIC]])
+  // CHECK: ret  %[[CAST]]
+  return svptrue_b16();
+}
+
+svbool_t test_svptrue_b32()
+{
+  // CHECK-LABEL: test_svptrue_b32
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
+  // CHECK: %[[CAST:.*]] = call  @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %[[INTRINSIC]])
+  // CHECK: ret  %[[CAST]]
+  return svptrue_b32();
+}
+
+svbool_t test_svptrue_b64()
+{
+  // CHECK-LABEL: test_svptrue_b64
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
+  // CHECK: %[[CAST:.*]] = call  @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %[[INTRINSIC]])
+  // CHECK: ret  %[[CAST]]
+  return svptrue_b64();
+}
+
+svbool_t test_svptrue_pat_b8()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_POW2);
+}
+
+svbool_t test_svptrue_pat_b8_1()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_1
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 1)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL1);
+}
+
+svbool_t test_svptrue_pat_b8_2()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_2
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 2)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL2);
+}
+
+svbool_t test_svptrue_pat_b8_3()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_3
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 3)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL3);
+}
+
+svbool_t test_svptrue_pat_b8_4()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_4
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 4)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL4);
+}
+
+svbool_t test_svptrue_pat_b8_5()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_5
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 5)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL5);
+}
+
+svbool_t test_svptrue_pat_b8_6()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_6
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 6)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL6);
+}
+
+svbool_t test_svptrue_pat_b8_7()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_7
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 7)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL7);
+}
+
+svbool_t test_svptrue_pat_b8_8()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_8
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 8)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL8);
+}
+
+svbool_t test_svptrue_pat_b8_9()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_9
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 9)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL16);
+}
+
+svbool_t test_svptrue_pat_b8_10()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_10
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL32);
+}
+
+svbool_t test_svptrue_pat_b8_11()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_11
+  // CHECK: %[[INTRINSIC:.*]] = call  @l

[PATCH] D77595: [SveEmitter] Add NoAuto flag and builtins for svwhile.

2020-04-06 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: SjoerdMeijer, efriedma, rovka.
Herald added a subscriber: tschuett.
Herald added a project: clang.
sdesmalen added a parent revision: D77594: [SveEmitter] Add support for _n form 
builtins.
sdesmalen added a child revision: D77596: [SveEmitter] Add NoOverload flag and 
builtin for svpfalse.

Add the NoAuto flag for intrinsics that can't easily be code-generated
using the default overloaded type and are better handled special-cased
in a switch statement.

This patch also adds all svwhile builtins.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77595

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_whilele.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_whilelt.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilege.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilegt.c
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -520,6 +520,13 @@
 Immediate = true;
 PredicatePattern = true;
 break;
+  case 'k':
+Predicate = false;
+Signed = true;
+Float = false;
+ElementBitwidth = Bitwidth = 32;
+NumVectors = 0;
+break;
   case 'l':
 Predicate = false;
 Signed = true;
@@ -527,6 +534,20 @@
 ElementBitwidth = Bitwidth = 64;
 NumVectors = 0;
 break;
+  case 'm':
+Predicate = false;
+Signed = false;
+Float = false;
+ElementBitwidth = Bitwidth = 32;
+NumVectors = 0;
+break;
+  case 'n':
+Predicate = false;
+Signed = false;
+Float = false;
+ElementBitwidth = Bitwidth = 64;
+NumVectors = 0;
+break;
   case 'S':
 Constant = true;
 Pointer = true;
Index: clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilegt.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilegt.c
@@ -0,0 +1,185 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svbool_t test_svwhilegt_b8_s32(int32_t op1, int32_t op2)
+{
+  // CHECK-LABEL: test_svwhilegt_b8_s32
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilegt.nxv16i1.i32(i32 %op1, i32 %op2)
+  // CHECK: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svwhilegt_b8'}}
+  // expected-warning@+1 {{implicit declaration of function 'svwhilegt_b8_s32'}}
+  return SVE_ACLE_FUNC(svwhilegt_b8,_s32,,)(op1, op2);
+}
+
+svbool_t test_svwhilegt_b16_s32(int32_t op1, int32_t op2)
+{
+  // CHECK-LABEL: test_svwhilegt_b16_s32
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilegt.nxv8i1.i32(i32 %op1, i32 %op2)
+  // CHECK: %[[CAST:.*]] = call  @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %[[INTRINSIC]])
+  // CHECK: ret  %[[CAST]]
+  // overload-warning@+2 {{implicit declaration of function 'svwhilegt_b16'}}
+  // expected-warning@+1 {{implicit declaration of function 'svwhilegt_b16_s32'}}
+  return SVE_ACLE_FUNC(svwhilegt_b16,_s32,,)(op1, op2);
+}
+
+svbool_t test_svwhilegt_b32_s32(int32_t op1, int32_t op2)
+{
+  // CHECK-LABEL: test_svwhilegt_b32_s32
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilegt.nxv4i1.i32(i32 %op1, i32 %op2)
+  // CHECK: %[[CAST:.*]] = call  @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %[[INTRINSIC]])
+  // CHECK: ret  %[[CAST]]
+  // overload-warning@+2 {{implicit declaration of function 'svwhilegt_b32'}}
+  // expected-warning@+1 {{implicit declaration of function 'svwhilegt_b32_s32'}}
+  return SVE_ACLE_FUNC(svwhilegt_b32,_s32,,)(op1, op2);
+}
+
+svbool_t test_svwhilegt_b64_s32(int32_t op1, int32_t op2)
+{
+  // CHECK-LABEL: test_svwhilegt_b64_s32
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64

[PATCH] D77596: [SveEmitter] Add NoOverload flag and builtin for svpfalse

2020-04-06 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: SjoerdMeijer, efriedma, rovka.
Herald added a subscriber: tschuett.
Herald added a project: clang.
sdesmalen added a parent revision: D77595: [SveEmitter] Add NoAuto flag and 
builtins for svwhile..
sdesmalen added a child revision: D77597: [SveEmitter] Add ExpandOp1SVALL and 
builtin for svptrue.

Add the NoOverload flag to tell CGBuiltin that it does not have
an overloaded type. This is used for e.g. svpfalse which does
not take any arguments and always returns a svbool_t.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77596

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfalse.c
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -261,6 +261,14 @@
 llvm_unreachable("Unsupported imm check");
   }
 
+  /// Returns the enum value for the flag type
+  uint64_t getEnumValueForFlag(StringRef C) const {
+auto Res = FlagTypes.find(C);
+if (Res != FlagTypes.end())
+  return Res->getValue();
+llvm_unreachable("Unsupported flag");
+  }
+
   // Returns the SVETypeFlags for a given value and mask.
   uint64_t encodeFlag(uint64_t V, StringRef MaskName) const {
 auto It = FlagTypes.find(MaskName);
@@ -844,6 +852,13 @@
   for (auto FlagRec : FlagsList)
 Flags |= FlagRec->getValueAsInt("Value");
 
+  // Create a dummy TypeSpec for non-overloaded builtins.
+  if (Types.empty()) {
+assert((Flags & getEnumValueForFlag("NoOverloadTy")) &&
+   "Expect TypeSpec for overloaded builtin!");
+Types = "i";
+  }
+
   // Extract type specs from string
   SmallVector TypeSpecs;
   TypeSpec Acc;
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfalse.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfalse.c
@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svbool_t test_svpfalse_b()
+{
+  // CHECK-LABEL: test_svpfalse_b
+  // CHECK: ret  zeroinitializer
+  return SVE_ACLE_FUNC(svpfalse,_b,,)();
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -7655,14 +7655,25 @@
   Ops[1] = Builder.CreateSelect(Ops[0], Ops[1], SplatZero);
 }
 
-Function *F = CGM.getIntrinsic(Builtin->LLVMIntrinsic, OverloadedTy);
+Function *F = TypeFlags.isNotOverloaded()
+  ? CGM.getIntrinsic(Builtin->LLVMIntrinsic)
+  : CGM.getIntrinsic(Builtin->LLVMIntrinsic, OverloadedTy);
 Value *Call = Builder.CreateCall(F, Ops);
-		return Call;
+
+// Predicate results must be converted to svbool_t.
+if (auto PredTy = dyn_cast(Call->getType()))
+  if (PredTy->getScalarType()->isIntegerTy(1))
+Call = EmitSVEPredicateCast(Call, cast(Ty));
+
+return Call;
   }
 
   switch (BuiltinID) {
   default:
 return nullptr;
+  case SVE::BI__builtin_sve_svpfalse_b:
+return ConstantInt::getFalse(Ty);
+
   case SVE::BI__builtin_sve_svwhilele_b8_s32:
   case SVE::BI__builtin_sve_svwhilele_b8_s64:
   case SVE::BI__builtin_sve_svwhilele_b8_u32:
Index: clang/include/clang/Basic/arm_sve.td
===
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -167,6 +167,7 @@
 def IsStructStore : FlagType<0x0004>;
 def IsZExtReturn  : FlagType<0x0008>; // Return value is sign-extend by default
 def NoAuto: FlagType<0x0010>;
+def NoOverloadTy  : FlagType<0x0020>;
 
 // These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h
 class ImmCheckType {
@@ -392,6 +393,7 @@
 def SVCMLA_LANE : SInst<"svcmla_lane[_{d}]", "ii", "hf",  MergeNone, "aarch64_sve_fcmla_lane", [], [ImmCheck<3, ImmCheckLaneIndexCompRotate, 2>,
 ImmCheck<4, ImmCheckComplexRotAll90>]>;
 
+
 def SVCADD_M : SInst<"svc

[PATCH] D76238: [SveEmitter] Implement builtins for contiguous loads/stores

2020-04-14 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/include/clang/Basic/arm_sve.td:186
+def SVLDFF1   : MInst<"svldff1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad], 
  MemEltTyDefault, "aarch64_sve_ldff1">;
+def SVLDFF1SB : MInst<"svldff1sb_{d}", "dPS", "silUsUiUl",   [IsLoad], 
  MemEltTyInt8,"aarch64_sve_ldff1">;
+def SVLDFF1UB : MInst<"svldff1ub_{d}", "dPW", "silUsUiUl",   [IsLoad, 
IsZExtReturn], MemEltTyInt8,"aarch64_sve_ldff1">;

Andrzej wrote:
> Tests for `ldff1sb` seem to be missing.
Good spot, I've added this test before committing the patch.


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[PATCH] D76617: [SveEmitter] Fix encoding/decoding of SVETypeFlags

2020-04-14 Thread Sander de Smalen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGf6ea026f179a: [SveEmitter] Fix encoding/decoding of 
SVETypeFlags (authored by sdesmalen).

Repository:
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Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -65,9 +65,6 @@
 applyModifier(CharMod);
   }
 
-  /// Return the value in SVETypeFlags for this type.
-  unsigned getTypeFlags() const;
-
   bool isPointer() const { return Pointer; }
   bool isVoidPointer() const { return Pointer && Void; }
   bool isSigned() const { return Signed; }
@@ -138,36 +135,22 @@
   /// The architectural #ifdef guard.
   std::string Guard;
 
+  // The merge suffix such as _m, _x or _z.
+  std::string MergeSuffix;
+
   /// The types of return value [0] and parameters [1..].
   std::vector Types;
 
   /// The "base type", which is VarType('d', BaseTypeSpec).
   SVEType BaseType;
 
-  unsigned Flags;
+  uint64_t Flags;
 
 public:
-  /// The type of predication.
-  enum MergeType {
-MergeNone,
-MergeAny,
-MergeOp1,
-MergeZero,
-MergeAnyExp,
-MergeZeroExp,
-MergeInvalid
-  } Merge;
-
-  Intrinsic(StringRef Name, StringRef Proto, int64_t MT, StringRef LLVMName,
-unsigned Flags, TypeSpec BT, ClassKind Class, SVEEmitter &Emitter,
-StringRef Guard)
-  : Name(Name.str()), LLVMName(LLVMName), Proto(Proto.str()),
-BaseTypeSpec(BT), Class(Class), Guard(Guard.str()), BaseType(BT, 'd'),
-Flags(Flags), Merge(MergeType(MT)) {
-// Types[0] is the return value.
-for (unsigned I = 0; I < Proto.size(); ++I)
-  Types.emplace_back(BaseTypeSpec, Proto[I]);
-  }
+  Intrinsic(StringRef Name, StringRef Proto, uint64_t MergeTy,
+StringRef MergeSuffix, uint64_t MemoryElementTy, StringRef LLVMName,
+uint64_t Flags, TypeSpec BT, ClassKind Class, SVEEmitter &Emitter,
+StringRef Guard);
 
   ~Intrinsic()=default;
 
@@ -179,14 +162,13 @@
 
   StringRef getGuard() const { return Guard; }
   ClassKind getClassKind() const { return Class; }
-  MergeType getMergeType() const { return Merge; }
 
   SVEType getReturnType() const { return Types[0]; }
   ArrayRef getTypes() const { return Types; }
   SVEType getParamType(unsigned I) const { return Types[I + 1]; }
   unsigned getNumParams() const { return Proto.size() - 1; }
 
-  unsigned getFlags() const { return Flags; }
+  uint64_t getFlags() const { return Flags; }
   bool isFlagSet(uint64_t Flag) const { return Flags & Flag;}
 
   /// Return the type string for a BUILTIN() macro in Builtins.def.
@@ -209,7 +191,7 @@
   void emitIntrinsic(raw_ostream &OS) const;
 
 private:
-  std::string getMergeSuffix() const;
+  std::string getMergeSuffix() const { return MergeSuffix; }
   std::string mangleName(ClassKind LocalCK) const;
   std::string replaceTemplatedArgs(std::string Name, TypeSpec TS,
std::string Proto) const;
@@ -221,8 +203,8 @@
   llvm::StringMap EltTypes;
   llvm::StringMap MemEltTypes;
   llvm::StringMap FlagTypes;
+  llvm::StringMap MergeTypes;
 
-  unsigned getTypeFlags(const SVEType &T);
 public:
   SVEEmitter(RecordKeeper &R) : Records(R) {
 for (auto *RV : Records.getAllDerivedDefinitions("EltType"))
@@ -231,8 +213,42 @@
   MemEltTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
 for (auto *RV : Records.getAllDerivedDefinitions("FlagType"))
   FlagTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+for (auto *RV : Records.getAllDerivedDefinitions("MergeType"))
+  MergeTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+  }
+
+  // Returns the SVETypeFlags for a given value and mask.
+  uint64_t encodeFlag(uint64_t V, StringRef MaskName) const {
+auto It = FlagTypes.find(MaskName);
+if (It != FlagTypes.end()) {
+  uint64_t Mask = It->getValue();
+  unsigned Shift = llvm::countTrailingZeros(Mask);
+  return (V << Shift) & Mask;
+}
+llvm_unreachable("Unsupported flag");
+  }
+
+  // Returns the SVETypeFlags for the given element type.
+  uint64_t encodeEltType(StringRef EltName) {
+auto It = EltTypes.find(EltName);
+if (It != EltTypes.end())
+  return encodeFlag(It->getValue(), "EltTypeMask");
+llvm_unreachable("Unsupported EltType");
+  }
+
+  // Returns the SVETypeFlags for the given memory element type.
+  uint64_t encodeMemoryElementType(uint64_t MT) {
+return encodeFlag(MT, "MemEltTypeMask");
   }
 
+  // Returns the SVETypeFlags for the given merge type.
+  uint64_t encodeMergeType(uint64_t MT) {
+return encodeFlag(MT, "MergeTypeMask");
+  }
+
+  //

[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

2020-04-14 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11621
+  if (VT.isFloatingPoint()) {
+SDValue LoadChain = SDValue(Load.getNode(), 1);
+Load = DAG.getMergeValues(

It seems like the LoadChain is lost if VT is of integer type.


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[PATCH] D76678: [SveEmitter] Add range checks for immediates and predicate patterns.

2020-04-14 Thread Sander de Smalen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGc8a5b30bac69: [SveEmitter] Add range checks for immediates 
and predicate patterns. (authored by sdesmalen).

Repository:
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Files:
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/include/clang/Sema/Sema.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdech.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_qdech.c
  clang/utils/TableGen/SveEmitter.cpp
  clang/utils/TableGen/TableGen.cpp
  clang/utils/TableGen/TableGenBackends.h

Index: clang/utils/TableGen/TableGenBackends.h
===
--- clang/utils/TableGen/TableGenBackends.h
+++ clang/utils/TableGen/TableGenBackends.h
@@ -95,6 +95,7 @@
 void EmitSveBuiltins(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitSveBuiltinCG(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitSveTypeFlags(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
+void EmitSveRangeChecks(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 
 void EmitMveHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
 void EmitMveBuiltinDef(llvm::RecordKeeper &Records, llvm::raw_ostream &OS);
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -74,6 +74,7 @@
   GenArmSveBuiltins,
   GenArmSveBuiltinCG,
   GenArmSveTypeFlags,
+  GenArmSveRangeChecks,
   GenArmCdeHeader,
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
@@ -197,6 +198,8 @@
"Generate arm_sve_builtin_cg_map.inc for clang"),
 clEnumValN(GenArmSveTypeFlags, "gen-arm-sve-typeflags",
"Generate arm_sve_typeflags.inc for clang"),
+clEnumValN(GenArmSveRangeChecks, "gen-arm-sve-sema-rangechecks",
+   "Generate arm_sve_sema_rangechecks.inc for clang"),
 clEnumValN(GenArmMveHeader, "gen-arm-mve-header",
"Generate arm_mve.h for clang"),
 clEnumValN(GenArmMveBuiltinDef, "gen-arm-mve-builtin-def",
@@ -390,6 +393,9 @@
   case GenArmSveTypeFlags:
 EmitSveTypeFlags(Records, OS);
 break;
+  case GenArmSveRangeChecks:
+EmitSveRangeChecks(Records, OS);
+break;
   case GenArmCdeHeader:
 EmitCdeHeader(Records, OS);
 break;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -46,6 +46,22 @@
 
 namespace {
 
+class ImmCheck {
+  unsigned Arg;
+  unsigned Kind;
+  unsigned ElementSizeInBits;
+
+public:
+  ImmCheck(unsigned Arg, unsigned Kind, unsigned ElementSizeInBits = 0)
+  : Arg(Arg), Kind(Kind), ElementSizeInBits(ElementSizeInBits) {}
+  ImmCheck(const ImmCheck &Other) = default;
+  ~ImmCheck() = default;
+
+  unsigned getArg() const { return Arg; }
+  unsigned getKind() const { return Kind; }
+  unsigned getElementSizeInBits() const { return ElementSizeInBits; }
+};
+
 class SVEType {
   TypeSpec TS;
   bool Float, Signed, Immediate, Void, Constant, Pointer;
@@ -146,11 +162,13 @@
 
   uint64_t Flags;
 
+  SmallVector ImmChecks;
+
 public:
   Intrinsic(StringRef Name, StringRef Proto, uint64_t MergeTy,
 StringRef MergeSuffix, uint64_t MemoryElementTy, StringRef LLVMName,
-uint64_t Flags, TypeSpec BT, ClassKind Class, SVEEmitter &Emitter,
-StringRef Guard);
+uint64_t Flags, ArrayRef ImmChecks, TypeSpec BT,
+ClassKind Class, SVEEmitter &Emitter, StringRef Guard);
 
   ~Intrinsic()=default;
 
@@ -171,6 +189,8 @@
   uint64_t getFlags() const { return Flags; }
   bool isFlagSet(uint64_t Flag) const { return Flags & Flag;}
 
+  ArrayRef getImmChecks() const { return ImmChecks; }
+
   /// Return the type string for a BUILTIN() macro in Builtins.def.
   std::string getBuiltinTypeStr();
 
@@ -204,6 +224,7 @@
   llvm::StringMap MemEltTypes;
   llvm::StringMap FlagTypes;
   llvm::StringMap MergeTypes;
+  llvm::StringMap ImmCheckTypes;
 
 public:
   SVEEmitter(RecordKeeper &R) : Records(R) {
@@ -215,6 +236,16 @@
   FlagTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
 for (auto *RV : Records.getAllDerivedDefinitions("MergeType"))
   MergeTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+for (auto *RV : Records.getAllDerivedDefinitions("ImmCheckType"))
+  ImmCheckTypes[RV->getNameInitAsString()] = RV->getValueAsInt("Value");
+  }
+
+  /// Returns the enum value for the immcheck type
+  unsigned getEnumValueForImmCheck(StringRef C) const {
+

[PATCH] D78131: [SVE] Fix unsigned is always >= 0

2020-04-14 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

LGTM, thanks for fixing @ctetreau!


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[PATCH] D77940: [AArch64] Add NVIDIA Carmel support

2020-04-14 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64.td:607
+   FeatureSVE
+   ]>;
+

Not sure how accurate the link you referenced is, but it doesn't mention SVE or 
Crypto extensions. Is that an omission in the blog post?



Comment at: llvm/unittests/Support/Host.cpp:271
+BogoMIPS: 62.50
+Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp 
asimdhp cpuid asimdrdm dcpop
+CPU implementer : 0x4e

nit: it probably doesn't matter much for the function `getHostCPUNameForARM`, 
but the feature list seems incomplete.



Comment at: llvm/unittests/Support/TargetParserTest.cpp:980
+  AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
+  AArch64::AEK_SIMD | AArch64::AEK_FP16 | AArch64::AEK_RAS |
+  AArch64::AEK_LSE | AArch64::AEK_SVE | AArch64::AEK_RDM,

nit: odd indentation here, have you used clang-format?


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[PATCH] D76929: [AArch64][SVE] Add SVE intrinsic for LD1RQ

2020-04-15 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11622
+  if (VT.isFloatingPoint())
+Load = DAG.getNode(ISD::BITCAST, DL, VT, Load);
+

I'd expect this to then use `Load.getValue(0)` ?


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[PATCH] D77595: [SveEmitter] Add builtins for svwhile

2020-04-15 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen updated this revision to Diff 257829.
sdesmalen retitled this revision from "[SveEmitter] Add NoAuto flag and 
builtins for svwhile." to "[SveEmitter] Add builtins for svwhile".
sdesmalen edited the summary of this revision.
sdesmalen added a comment.

- The function that returns a list of overloaded types for the intrinsics added 
in D77596  means we don't need to use custom 
codegen for the while intrinsics any more.


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Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_whilele.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_whilelt.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilege.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilegt.c

Index: clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilegt.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilegt.c
@@ -0,0 +1,185 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svbool_t test_svwhilegt_b8_s32(int32_t op1, int32_t op2)
+{
+  // CHECK-LABEL: test_svwhilegt_b8_s32
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilegt.nxv16i1.i32(i32 %op1, i32 %op2)
+  // CHECK: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svwhilegt_b8'}}
+  // expected-warning@+1 {{implicit declaration of function 'svwhilegt_b8_s32'}}
+  return SVE_ACLE_FUNC(svwhilegt_b8,_s32,,)(op1, op2);
+}
+
+svbool_t test_svwhilegt_b16_s32(int32_t op1, int32_t op2)
+{
+  // CHECK-LABEL: test_svwhilegt_b16_s32
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilegt.nxv8i1.i32(i32 %op1, i32 %op2)
+  // CHECK: %[[CAST:.*]] = call  @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %[[INTRINSIC]])
+  // CHECK: ret  %[[CAST]]
+  // overload-warning@+2 {{implicit declaration of function 'svwhilegt_b16'}}
+  // expected-warning@+1 {{implicit declaration of function 'svwhilegt_b16_s32'}}
+  return SVE_ACLE_FUNC(svwhilegt_b16,_s32,,)(op1, op2);
+}
+
+svbool_t test_svwhilegt_b32_s32(int32_t op1, int32_t op2)
+{
+  // CHECK-LABEL: test_svwhilegt_b32_s32
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilegt.nxv4i1.i32(i32 %op1, i32 %op2)
+  // CHECK: %[[CAST:.*]] = call  @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %[[INTRINSIC]])
+  // CHECK: ret  %[[CAST]]
+  // overload-warning@+2 {{implicit declaration of function 'svwhilegt_b32'}}
+  // expected-warning@+1 {{implicit declaration of function 'svwhilegt_b32_s32'}}
+  return SVE_ACLE_FUNC(svwhilegt_b32,_s32,,)(op1, op2);
+}
+
+svbool_t test_svwhilegt_b64_s32(int32_t op1, int32_t op2)
+{
+  // CHECK-LABEL: test_svwhilegt_b64_s32
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilegt.nxv2i1.i32(i32 %op1, i32 %op2)
+  // CHECK: %[[CAST:.*]] = call  @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %[[INTRINSIC]])
+  // CHECK: ret  %[[CAST]]
+  // overload-warning@+2 {{implicit declaration of function 'svwhilegt_b64'}}
+  // expected-warning@+1 {{implicit declaration of function 'svwhilegt_b64_s32'}}
+  return SVE_ACLE_FUNC(svwhilegt_b64,_s32,,)(op1, op2);
+}
+
+svbool_t test_svwhilegt_b8_u32(uint32_t op1, uint32_t op2)
+{
+  // CHECK-LABEL: test_svwhilegt_b8_u32
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilehi.nxv16i1.i32(i32 %op1, i32 %op2)
+  // CHECK: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svwhilegt_b8'}}
+  // expected-warning@+1 {{implicit declaration of function 'svwhilegt_b8_u32'}}
+  return SVE_ACLE_FUNC(svwhilegt_b8,_u32,,)(op1, op2);
+}
+
+svbool_t test_svwhilegt_b16_u32(uint32_t op1, uint32_t op2)
+{
+  // CHECK-LABEL: test_svwhilegt_b16_u32
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilehi.nxv8i1.i32(i32 %op1

[PATCH] D78239: [SveEmitter] Add builtins for FP conversions

2020-04-15 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: SjoerdMeijer, efriedma.
Herald added a subscriber: tschuett.
Herald added a project: clang.
sdesmalen added a parent revision: D78238: [SveEmitter] Add builtins for 
svwhilerw/svwhilewr.
sdesmalen added a child revision: D77597: [SveEmitter] Add ExpandOp1SVALL and 
builtin for svptrue.

This adds the flag IsOverloadCvt which tells CGBulitin to use
the result type and the type of the last operand as the
overloaded types for the LLVM IR intrinsic.

This also adds the flag IsFPConvert, which is needed to avoid
converting the predicate of the operation from svbool_t to
a predicate with fewer lanes, as the LLVM IR intrinsics use
the  as the predicate.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78239

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtlt.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtnt.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtx.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtxnt.c
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -556,6 +556,21 @@
 ElementBitwidth = Bitwidth = 64;
 NumVectors = 0;
 break;
+  case 'O':
+Predicate = false;
+Float = true;
+ElementBitwidth = 16;
+break;
+  case 'M':
+Predicate = false;
+Float = true;
+ElementBitwidth = 32;
+break;
+  case 'N':
+Predicate = false;
+Float = true;
+ElementBitwidth = 64;
+break;
   case 'S':
 Constant = true;
 Pointer = true;
@@ -1010,6 +1025,17 @@
   if (!InGuard.empty())
 OS << "#endif  //" << InGuard << "\n";
 
+  OS << "#if defined(__ARM_FEATURE_SVE2)\n";
+  OS << "#define svcvtnt_f16_x  svcvtnt_f16_m\n";
+  OS << "#define svcvtnt_f16_f32_x  svcvtnt_f16_f32_m\n";
+  OS << "#define svcvtnt_f32_x  svcvtnt_f32_m\n";
+  OS << "#define svcvtnt_f32_f64_x  svcvtnt_f32_f64_m\n\n";
+
+  OS << "#define svcvtxnt_f32_x svcvtxnt_f32_m\n";
+  OS << "#define svcvtxnt_f32_f64_x svcvtxnt_f32_f64_m\n\n";
+
+  OS << "#endif /*__ARM_FEATURE_SVE2 */\n\n";
+
   OS << "#ifdef __cplusplus\n";
   OS << "} // extern \"C\"\n";
   OS << "#endif\n\n";
Index: clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtxnt.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtxnt.c
@@ -0,0 +1,33 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svfloat32_t test_svcvtxnt_f32_f64_m(svfloat32_t inactive, svbool_t pg, svfloat64_t op)
+{
+  // CHECK-LABEL: test_svcvtxnt_f32_f64_m
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.fcvtxnt.f32f64( %inactive,  %pg,  %op)
+  // CHECK: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svcvtxnt_f32_m'}}
+  // expected-warning@+1 {{implicit declaration of function 'svcvtxnt_f32_f64_m'}}
+  return SVE_ACLE_FUNC(svcvtxnt_f32,_f64,_m,)(inactive, pg, op);
+}
+
+svfloat32_t test_svcvtxnt_f32_f64_x(svfloat32_t even, svbool_t pg, svfloat64_t op)
+{
+  // CHECK-LABEL: test_svcvtxnt_f32_f64_x
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.fcvtxnt.f32f64( %even,  %pg,  %op)
+  // CHECK: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svcvtxnt_f32_x'}}
+  // expected-warning@+1 {{implicit declaration of function 'svcvtxnt_f32_f64_x'}}
+  return SVE_ACLE_FUNC(svcvtxnt_f32,_f64,_x,)(even, pg, op);
+}
Index: clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtx.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve2-intr

[PATCH] D77596: [SveEmitter] Add IsOverloadNone flag and builtins for svpfalse and svcnt[bhwd]_pat

2020-04-15 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen updated this revision to Diff 257824.
sdesmalen retitled this revision from "[SveEmitter] Add NoOverload flag and 
builtin for svpfalse" to "[SveEmitter] Add IsOverloadNone flag and builtins for 
svpfalse and svcnt[bhwd]_pat".
sdesmalen edited the summary of this revision.
sdesmalen added a comment.

- Addressed suggestion to have separate function that returns a list of 
overloaded types.
- For IsOverloadNone as needed by this patch, this list will be empty.
- Also added builtins for svcntb_pat, svcnth_pat, svcntw_pat and svcntd_pat, 
because those don't require custom codegen.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77596/new/

https://reviews.llvm.org/D77596

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntb.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntd.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnth.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfalse.c
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -261,6 +261,14 @@
 llvm_unreachable("Unsupported imm check");
   }
 
+  /// Returns the enum value for the flag type
+  uint64_t getEnumValueForFlag(StringRef C) const {
+auto Res = FlagTypes.find(C);
+if (Res != FlagTypes.end())
+  return Res->getValue();
+llvm_unreachable("Unsupported flag");
+  }
+
   // Returns the SVETypeFlags for a given value and mask.
   uint64_t encodeFlag(uint64_t V, StringRef MaskName) const {
 auto It = FlagTypes.find(MaskName);
@@ -520,6 +528,13 @@
 Immediate = true;
 PredicatePattern = true;
 break;
+  case 'k':
+Predicate = false;
+Signed = true;
+Float = false;
+ElementBitwidth = Bitwidth = 32;
+NumVectors = 0;
+break;
   case 'l':
 Predicate = false;
 Signed = true;
@@ -527,6 +542,20 @@
 ElementBitwidth = Bitwidth = 64;
 NumVectors = 0;
 break;
+  case 'm':
+Predicate = false;
+Signed = false;
+Float = false;
+ElementBitwidth = Bitwidth = 32;
+NumVectors = 0;
+break;
+  case 'n':
+Predicate = false;
+Signed = false;
+Float = false;
+ElementBitwidth = Bitwidth = 64;
+NumVectors = 0;
+break;
   case 'S':
 Constant = true;
 Pointer = true;
@@ -823,6 +852,13 @@
   for (auto FlagRec : FlagsList)
 Flags |= FlagRec->getValueAsInt("Value");
 
+  // Create a dummy TypeSpec for non-overloaded builtins.
+  if (Types.empty()) {
+assert((Flags & getEnumValueForFlag("IsOverloadNone")) &&
+   "Expect TypeSpec for overloaded builtin!");
+Types = "i";
+  }
+
   // Extract type specs from string
   SmallVector TypeSpecs;
   TypeSpec Acc;
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfalse.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfalse.c
@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svbool_t test_svpfalse_b()
+{
+  // CHECK-LABEL: test_svpfalse_b
+  // CHECK: ret  zeroinitializer
+  return SVE_ACLE_FUNC(svpfalse,_b,,)();
+}
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c
@@ -0,0 +1,139 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+uint64_t test_svcntw_pat()
+{
+  // CHECK-LABEL: test_svcntw_pat
+  // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 0)
+  // CHECK: ret i64 %[[INTRINSIC]]
+  return svcntw_pat(SV_POW2);
+}
+
+uint64_t test_svcntw_pat_1()
+{
+  // CHECK-LABEL: test_svcntw_pat_1
+  // CHECK: %[[INTRINSIC:.*]] = call i64 @llvm.aarch64.sve.cntw(i32 1)
+  // CHECK: ret i64 %[[INTRINSIC]]
+  return svcntw_pat(SV_VL1);
+}
+
+uint64_t test_svcntw_pat_2()
+{
+  // CHECK-LABEL: test_svcntw_pat_2
+  // CHECK: %[[INTRINSIC:.*]] = call i64 @ll

[PATCH] D78238: [SveEmitter] Add builtins for svwhilerw/svwhilewr

2020-04-15 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: SjoerdMeijer, efriedma.
Herald added a subscriber: tschuett.
Herald added a project: clang.
sdesmalen added a parent revision: D77595: [SveEmitter] Add builtins for 
svwhile.
sdesmalen added a child revision: D78239: [SveEmitter] Add builtins for FP 
conversions.

This also adds the IsOverloadWhileRW flag which tells CGBuiltin to use
the result predicate type and the first pointer type as the
overloaded types for the LLVM IR intrinsic.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78238

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilerw.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr.c

Index: clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr.c
@@ -0,0 +1,131 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svbool_t test_svwhilewr_s8(const int8_t *op1, const int8_t *op2)
+{
+  // CHECK-LABEL: test_svwhilewr_s8
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilewr.b.nxv16i1.p0i8(i8* %op1, i8* %op2)
+  // CHECK: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svwhilewr'}}
+  // expected-warning@+1 {{implicit declaration of function 'svwhilewr_s8'}}
+  return SVE_ACLE_FUNC(svwhilewr,_s8,,)(op1, op2);
+}
+
+svbool_t test_svwhilewr_s16(const int16_t *op1, const int16_t *op2)
+{
+  // CHECK-LABEL: test_svwhilewr_s16
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilewr.h.nxv8i1.p0i16(i16* %op1, i16* %op2)
+  // CHECK: %[[INTRINSIC_REINT:.*]] = call  @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %[[INTRINSIC]])
+  // CHECK: ret  %[[INTRINSIC_REINT]]
+  // overload-warning@+2 {{implicit declaration of function 'svwhilewr'}}
+  // expected-warning@+1 {{implicit declaration of function 'svwhilewr_s16'}}
+  return SVE_ACLE_FUNC(svwhilewr,_s16,,)(op1, op2);
+}
+
+svbool_t test_svwhilewr_s32(const int32_t *op1, const int32_t *op2)
+{
+  // CHECK-LABEL: test_svwhilewr_s32
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilewr.s.nxv4i1.p0i32(i32* %op1, i32* %op2)
+  // CHECK: %[[INTRINSIC_REINT:.*]] = call  @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %[[INTRINSIC]])
+  // CHECK: ret  %[[INTRINSIC_REINT]]
+  // overload-warning@+2 {{implicit declaration of function 'svwhilewr'}}
+  // expected-warning@+1 {{implicit declaration of function 'svwhilewr_s32'}}
+  return SVE_ACLE_FUNC(svwhilewr,_s32,,)(op1, op2);
+}
+
+svbool_t test_svwhilewr_s64(const int64_t *op1, const int64_t *op2)
+{
+  // CHECK-LABEL: test_svwhilewr_s64
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilewr.d.nxv2i1.p0i64(i64* %op1, i64* %op2)
+  // CHECK: %[[INTRINSIC_REINT:.*]] = call  @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %[[INTRINSIC]])
+  // CHECK: ret  %[[INTRINSIC_REINT]]
+  // overload-warning@+2 {{implicit declaration of function 'svwhilewr'}}
+  // expected-warning@+1 {{implicit declaration of function 'svwhilewr_s64'}}
+  return SVE_ACLE_FUNC(svwhilewr,_s64,,)(op1, op2);
+}
+
+svbool_t test_svwhilewr_u8(const uint8_t *op1, const uint8_t *op2)
+{
+  // CHECK-LABEL: test_svwhilewr_u8
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilewr.b.nxv16i1.p0i8(i8* %op1, i8* %op2)
+  // CHECK: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svwhilewr'}}
+  // expected-warning@+1 {{implicit declaration of function 'svwhilewr_u8'}}
+  return SVE_ACLE_FUNC(svwhilewr,_u8,,)(op1, op2);
+}
+
+svbool_t test_svwhilewr_u16(const uint16_t *op1, const uint16_t *op2)
+{
+  // CHECK-LABEL: test_svwhilewr_u16
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.whilewr.h.nxv8i1.p0i16(i16* %op1, i16* %op2)

[PATCH] D77597: [SveEmitter] Add ExpandOp1SVALL and builtin for svptrue

2020-04-15 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen updated this revision to Diff 257834.
sdesmalen added a comment.

rebased patch.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77597/new/

https://reviews.llvm.org/D77597

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntb.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntd.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnth.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptrue.c

Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptrue.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptrue.c
@@ -0,0 +1,201 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+svbool_t test_svptrue_b8()
+{
+  // CHECK-LABEL: test_svptrue_b8
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_b8();
+}
+
+svbool_t test_svptrue_b16()
+{
+  // CHECK-LABEL: test_svptrue_b16
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
+  // CHECK: %[[CAST:.*]] = call  @llvm.aarch64.sve.convert.to.svbool.nxv8i1( %[[INTRINSIC]])
+  // CHECK: ret  %[[CAST]]
+  return svptrue_b16();
+}
+
+svbool_t test_svptrue_b32()
+{
+  // CHECK-LABEL: test_svptrue_b32
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
+  // CHECK: %[[CAST:.*]] = call  @llvm.aarch64.sve.convert.to.svbool.nxv4i1( %[[INTRINSIC]])
+  // CHECK: ret  %[[CAST]]
+  return svptrue_b32();
+}
+
+svbool_t test_svptrue_b64()
+{
+  // CHECK-LABEL: test_svptrue_b64
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
+  // CHECK: %[[CAST:.*]] = call  @llvm.aarch64.sve.convert.to.svbool.nxv2i1( %[[INTRINSIC]])
+  // CHECK: ret  %[[CAST]]
+  return svptrue_b64();
+}
+
+svbool_t test_svptrue_pat_b8()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_POW2);
+}
+
+svbool_t test_svptrue_pat_b8_1()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_1
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 1)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL1);
+}
+
+svbool_t test_svptrue_pat_b8_2()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_2
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 2)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL2);
+}
+
+svbool_t test_svptrue_pat_b8_3()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_3
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 3)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL3);
+}
+
+svbool_t test_svptrue_pat_b8_4()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_4
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 4)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL4);
+}
+
+svbool_t test_svptrue_pat_b8_5()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_5
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 5)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL5);
+}
+
+svbool_t test_svptrue_pat_b8_6()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_6
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 6)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL6);
+}
+
+svbool_t test_svptrue_pat_b8_7()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_7
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 7)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL7);
+}
+
+svbool_t test_svptrue_pat_b8_8()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_8
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 8)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL8);
+}
+
+svbool_t test_svptrue_pat_b8_9()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_9
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 9)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL16);
+}
+
+svbool_t test_svptrue_pat_b8_10()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_10
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL32);
+}
+
+svbool_t test_svptrue_pat_b8_11()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_11
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
+  // CHECK: ret  %[[INTRINSIC]]
+  return svptrue_pat_b8(SV_VL64);
+}
+
+svbool_t test_svptrue_pat_b8_12()
+{
+  // CHECK-LABEL: test_svptrue_pat_b8_12
+  // CHECK: %[[INTRINSIC:.*]]

[PATCH] D81252: [SVE ACLE] Remove redundant bool_t typedef.

2020-06-05 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D81252/new/

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[PATCH] D81304: [llvm][SveEmitter] Emit the bfloat version of `svld1ro`.

2020-06-08 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a comment.

Thanks @fpetrogalli, the changes look good to me. Just added some minor 
comments.




Comment at: clang/include/clang/Basic/AArch64SVEACLETypes.def:63
 
-SVE_VECTOR_TYPE("__SVFloat16_t", SveFloat16, SveFloat16Ty, 8, 16, true, true)
-SVE_VECTOR_TYPE("__SVFloat32_t", SveFloat32, SveFloat32Ty, 4, 32, true, true)
-SVE_VECTOR_TYPE("__SVFloat64_t", SveFloat64, SveFloat64Ty, 2, 64, true, true)
+SVE_VECTOR_TYPE("__SVBFloat16_t", SveBFloat16, SveBFloat16Ty, 8, 16, false, 
false, true)
+SVE_VECTOR_TYPE("__SVFloat16_t", SveFloat16, SveFloat16Ty, 8, 16, true, true, 
false)

nit: I'd move this below __SVFloat64_t separated by a newline.



Comment at: clang/utils/TableGen/SveEmitter.cpp:366
 S += "v";
-  else if (!Float)
+  else if (!isFloat() && !isBFloat())
 switch (ElementBitwidth) {

Maybe it's worth adding a
  bool isFloatingPoint() const { return Float || BFloat; }
to avoid having to write both `isFloat` and `isBFloat` everywhere.



Comment at: clang/utils/TableGen/SveEmitter.cpp:385
+switch (ElementBitwidth) {
+case 16: S += "y"; break;
+default: llvm_unreachable("Unhandled case!");

It's easier to just assert that ElementBitwidth == 16.



Comment at: clang/utils/TableGen/SveEmitter.cpp:942
+  if (T.isBFloat()) {
+switch (T.getElementSizeInBits()) {
+case 16:

It's easier to just assert that ElementBitwidth == 16


Repository:
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[PATCH] D81459: [SveEmitter] Add SVE tuple types and builtins for svundef.

2020-06-09 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: c-rhodes, david-arm, ctetreau, efriedma.
Herald added a subscriber: tschuett.
Herald added a reviewer: rengolin.
Herald added a project: clang.

This patch adds new SVE types to Clang that describe tuples of SVE
vectors. For example `svint32x2_t` which maps to the twice-as-wide
vector ``. Similarly, `svint32x3_t` will map to
``.

  

It also adds builtins to return an `undef` vector for a given
SVE type.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81459

Files:
  clang/include/clang/Basic/AArch64SVEACLETypes.def
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef3.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4.c
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -490,6 +490,15 @@
 
 void SVEType::applyModifier(char Mod) {
   switch (Mod) {
+  case '2':
+NumVectors = 2;
+break;
+  case '3':
+NumVectors = 3;
+break;
+  case '4':
+NumVectors = 4;
+break;
   case 'v':
 Void = true;
 break;
@@ -801,18 +810,7 @@
 }
 
 std::string Intrinsic::getBuiltinTypeStr() {
-  std::string S;
-
-  SVEType RetT = getReturnType();
-  // Since the return value must be one type, return a vector type of the
-  // appropriate width which we will bitcast.  An exception is made for
-  // returning structs of 2, 3, or 4 vectors which are returned in a sret-like
-  // fashion, storing them to a pointer arg.
-  if (RetT.getNumVectors() > 1) {
-S += "vv*"; // void result with void* first argument
-  } else
-S += RetT.builtin_str();
-
+  std::string S = getReturnType().builtin_str();
   for (unsigned I = 0; I < getNumParams(); ++I)
 S += getParamType(I).builtin_str();
 
@@ -1071,6 +1069,39 @@
   OS << "typedef __SVFloat16_t svfloat16_t;\n";
   OS << "typedef __SVFloat32_t svfloat32_t;\n";
   OS << "typedef __SVFloat64_t svfloat64_t;\n";
+  OS << "typedef __SVInt8x2_t svint8x2_t;\n";
+  OS << "typedef __SVInt16x2_t svint16x2_t;\n";
+  OS << "typedef __SVInt32x2_t svint32x2_t;\n";
+  OS << "typedef __SVInt64x2_t svint64x2_t;\n";
+  OS << "typedef __SVUint8x2_t svuint8x2_t;\n";
+  OS << "typedef __SVUint16x2_t svuint16x2_t;\n";
+  OS << "typedef __SVUint32x2_t svuint32x2_t;\n";
+  OS << "typedef __SVUint64x2_t svuint64x2_t;\n";
+  OS << "typedef __SVFloat16x2_t svfloat16x2_t;\n";
+  OS << "typedef __SVFloat32x2_t svfloat32x2_t;\n";
+  OS << "typedef __SVFloat64x2_t svfloat64x2_t;\n";
+  OS << "typedef __SVInt8x3_t svint8x3_t;\n";
+  OS << "typedef __SVInt16x3_t svint16x3_t;\n";
+  OS << "typedef __SVInt32x3_t svint32x3_t;\n";
+  OS << "typedef __SVInt64x3_t svint64x3_t;\n";
+  OS << "typedef __SVUint8x3_t svuint8x3_t;\n";
+  OS << "typedef __SVUint16x3_t svuint16x3_t;\n";
+  OS << "typedef __SVUint32x3_t svuint32x3_t;\n";
+  OS << "typedef __SVUint64x3_t svuint64x3_t;\n";
+  OS << "typedef __SVFloat16x3_t svfloat16x3_t;\n";
+  OS << "typedef __SVFloat32x3_t svfloat32x3_t;\n";
+  OS << "typedef __SVFloat64x3_t svfloat64x3_t;\n";
+  OS << "typedef __SVInt8x4_t svint8x4_t;\n";
+  OS << "typedef __SVInt16x4_t svint16x4_t;\n";
+  OS << "typedef __SVInt32x4_t svint32x4_t;\n";
+  OS << "typedef __SVInt64x4_t svint64x4_t;\n";
+  OS << "typedef __SVUint8x4_t svuint8x4_t;\n";
+  OS << "typedef __SVUint16x4_t svuint16x4_t;\n";
+  OS << "typedef __SVUint32x4_t svuint32x4_t;\n";
+  OS << "typedef __SVUint64x4_t svuint64x4_t;\n";
+  OS << "typedef __SVFloat16x4_t svfloat16x4_t;\n";
+  OS << "typedef __SVFloat32x4_t svfloat32x4_t;\n";
+  OS << "typedef __SVFloat64x4_t svfloat64x4_t;\n";
   OS << "typedef __SVBool_t  svbool_t;\n\n";
 
   OS << "typedef enum\n";
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4.c
@@ -0,0 +1,80 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O2 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+svint8x4_t test_svundef4_s8()
+{
+  // CHECK-LABEL: test_svundef4_s8
+  // CHECK: ret  undef
+  return svundef4_s8();
+}
+
+svint16x4_t test_svundef4_s16()
+{
+  // CHECK-LABEL: test_svundef4_s16
+  // CHECK: ret  undef
+  return svundef4_s16();
+}
+
+svint32x4_t test_svundef4_s32()
+{
+  // CHECK-LABEL: test_svundef4_s32
+  // CHECK: ret  undef
+  return svundef4_s32();
+}
+
+svint64x4_t test_svundef4_s64()
+{
+  // CHECK-LABEL: test_svundef4_s64
+  // CHECK: ret  undef
+  retu

[PATCH] D81462: [SveEmitter] Add builtins for svtbl2

2020-06-09 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: david-arm, efriedma, c-rhodes.
Herald added a subscriber: tschuett.
Herald added a project: clang.
sdesmalen added a parent revision: D81459: [SveEmitter] Add SVE tuple types and 
builtins for svundef..

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81462

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbl2.c

Index: clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbl2.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbl2.c
@@ -0,0 +1,145 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8_t test_svtbl2_s8(svint8x2_t data, svuint8_t indices)
+{
+  // CHECK-LABEL: test_svtbl2_s8
+  // CHECK-DAG: %[[V0:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv16i8.nxv32i8( %data, i32 0)
+  // CHECK-DAG: %[[V1:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv16i8.nxv32i8( %data, i32 1)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.tbl2.nxv16i8( %[[V0]],  %[[V1]],  %indices)
+  // CHECK-NEXT: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svtbl2'}}
+  // expected-warning@+1 {{implicit declaration of function 'svtbl2_s8'}}
+  return SVE_ACLE_FUNC(svtbl2,_s8,,)(data, indices);
+}
+
+svint16_t test_svtbl2_s16(svint16x2_t data, svuint16_t indices)
+{
+  // CHECK-LABEL: test_svtbl2_s16
+  // CHECK-DAG: %[[V0:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv8i16.nxv16i16( %data, i32 0)
+  // CHECK-DAG: %[[V1:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv8i16.nxv16i16( %data, i32 1)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.tbl2.nxv8i16( %[[V0]],  %[[V1]],  %indices)
+  // CHECK-NEXT: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svtbl2'}}
+  // expected-warning@+1 {{implicit declaration of function 'svtbl2_s16'}}
+  return SVE_ACLE_FUNC(svtbl2,_s16,,)(data, indices);
+}
+
+svint32_t test_svtbl2_s32(svint32x2_t data, svuint32_t indices)
+{
+  // CHECK-LABEL: test_svtbl2_s32
+  // CHECK-DAG: %[[V0:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv4i32.nxv8i32( %data, i32 0)
+  // CHECK-DAG: %[[V1:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv4i32.nxv8i32( %data, i32 1)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.tbl2.nxv4i32( %[[V0]],  %[[V1]],  %indices)
+  // CHECK-NEXT: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svtbl2'}}
+  // expected-warning@+1 {{implicit declaration of function 'svtbl2_s32'}}
+  return SVE_ACLE_FUNC(svtbl2,_s32,,)(data, indices);
+}
+
+svint64_t test_svtbl2_s64(svint64x2_t data, svuint64_t indices)
+{
+  // CHECK-LABEL: test_svtbl2_s64
+  // CHECK-DAG: %[[V0:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv2i64.nxv4i64( %data, i32 0)
+  // CHECK-DAG: %[[V1:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv2i64.nxv4i64( %data, i32 1)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.tbl2.nxv2i64( %[[V0]],  %[[V1]],  %indices)
+  // CHECK-NEXT: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svtbl2'}}
+  // expected-warning@+1 {{implicit declaration of function 'svtbl2_s64'}}
+  return SVE_ACLE_FUNC(svtbl2,_s64,,)(data, indices);
+}
+
+svuint8_t test_svtbl2_u8(svuint8x2_t data, svuint8_t indices)
+{
+  // CHECK-LABEL: test_svtbl2_u8
+  // CHECK-DAG: %[[V0:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv16i8.nxv32i8( %data, i32 0)
+  // CHECK-DAG: %[[V1:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv16i8.nxv32i8( %data, i32 1)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.tbl2.nxv16i8( %[[V0]],  %[[V1]],  %indices)
+  // CHECK-NEXT: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svtbl2'}}
+  // expected-warning@+1 {{implicit declaration of function 'svtbl2_u8'}}
+  return SVE_ACLE_FUNC(svtbl2,_u8,,)(data, indices);
+}
+
+svuint16_t test_svtbl

[PATCH] D81464: [SveEmitter] Add builtins to insert/extract subvectors from tuples (svget/svset)

2020-06-09 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
Herald added subscribers: cfe-commits, tschuett.
Herald added a project: clang.
sdesmalen added a parent revision: D81459: [SveEmitter] Add SVE tuple types and 
builtins for svundef..

For example:

  svint32_t svget4(svint32x4_t tuple, uint64_t imm_index)

returns the subvector at `index`, which must be in range `0..3`.

  svint32x3_t svset3(svint32x3_t tuple, uint64_t index, svint32_t vec)

returns a tuple vector with `vec` inserted into `tuple` at `index`, which must 
be in range `0..2`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81464

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_get2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_get3.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_get4.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_set2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_set3.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_set4.c

Index: clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_set4.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_set4.c
@@ -0,0 +1,143 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=note %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=note %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8x4_t test_svset4_s8(svint8x4_t tuple, svint8_t x)
+{
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_s8,,)(tuple, 4, x);
+}
+
+svint16x4_t test_svset4_s16(svint16x4_t tuple, svint16_t x)
+{
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_s16,,)(tuple, -1, x);
+}
+
+svint32x4_t test_svset4_s32(svint32x4_t tuple, svint32_t x)
+{
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_s32,,)(tuple, 4, x);
+}
+
+svint64x4_t test_svset4_s64(svint64x4_t tuple, svint64_t x)
+{
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_s64,,)(tuple, -1, x);
+}
+
+svuint8x4_t test_svset4_u8(svuint8x4_t tuple, svuint8_t x)
+{
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_u8,,)(tuple, 4, x);
+}
+
+svuint16x4_t test_svset4_u16(svuint16x4_t tuple, svuint16_t x)
+{
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_u16,,)(tuple, -1, x);
+}
+
+svuint32x4_t test_svset4_u32(svuint32x4_t tuple, svuint32_t x)
+{
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_u32,,)(tuple, 4, x);
+}
+
+svuint64x4_t test_svset4_u64(svuint64x4_t tuple, svuint64_t x)
+{
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_u64,,)(tuple, -1, x);
+}
+
+svfloat16x4_t test_svset4_f16(svfloat16x4_t tuple, svfloat16_t x)
+{
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_f16,,)(tuple, 4, x);
+}
+
+svfloat32x4_t test_svset4_f32(svfloat32x4_t tuple, svfloat32_t x)
+{
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_f32,,)(tuple, -1, x);
+}
+
+svfloat64x4_t test_svset4_f64(svfloat64x4_t tuple, svfloat64_t x)
+{
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_f64,,)(tuple, 4, x);
+}
+
+svint8x4_t test_svset4_s8_var(svint8x4_t tuple, uint64_t imm_index, svint8_t x)
+{
+  // expected-error-re@+1 {{argument to '{{.*}}' must be a constant integer}}
+  return SVE_ACLE_FUNC(svset4,_s8,,)(tuple, imm_index, x);
+}
+
+svint16x4_t test_svset

[PATCH] D81463: [SveEmitter] Add builtins for tuple creation (svcreate2/svcreate3/etc)

2020-06-09 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
Herald added a subscriber: tschuett.
Herald added a project: clang.
sdesmalen added a parent revision: D81459: [SveEmitter] Add SVE tuple types and 
builtins for svundef..

The svcreate builtins allow constructing a tuple from individual vectors, e.g.

  svint32x2_t svcreate2(svint32_t v2, svint32_t v2)`


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81463

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c

Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c
@@ -0,0 +1,99 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8x4_t test_svcreate4_s8(svint8_t x0, svint8_t x1, svint8_t x2, svint8_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_s8
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv64i8.nxv16i8( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_s8,,)(x0, x1, x2, x4);
+}
+
+svint16x4_t test_svcreate4_s16(svint16_t x0, svint16_t x1, svint16_t x2, svint16_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_s16
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv32i16.nxv8i16( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_s16,,)(x0, x1, x2, x4);
+}
+
+svint32x4_t test_svcreate4_s32(svint32_t x0, svint32_t x1, svint32_t x2, svint32_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_s32
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_s32,,)(x0, x1, x2, x4);
+}
+
+svint64x4_t test_svcreate4_s64(svint64_t x0, svint64_t x1, svint64_t x2, svint64_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_s64
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_s64,,)(x0, x1, x2, x4);
+}
+
+svuint8x4_t test_svcreate4_u8(svuint8_t x0, svuint8_t x1, svuint8_t x2, svuint8_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_u8
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv64i8.nxv16i8( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_u8,,)(x0, x1, x2, x4);
+}
+
+svuint16x4_t test_svcreate4_u16(svuint16_t x0, svuint16_t x1, svuint16_t x2, svuint16_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_u16
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv32i16.nxv8i16( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_u16,,)(x0, x1, x2, x4);
+}
+
+svuint32x4_t test_svcreate4_u32(svuint32_t x0, svuint32_t x1, svuint32_t x2, svuint32_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_u32
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_u32,,)(x0, x1, x2, x4);
+}
+
+svuint64x4_t test_svcreate4_u64(svuint64_t x0, svuint64_t x1, svuint64_t x2, svuint64_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_u64
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_u64,,)(x0, x1, x2, x4);
+}
+
+svfloat16x4_t test_svcreate4_f16(svfloat16_t x0, svfloat16_t x1, svfloat16_t x2, svfloat16_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_f16
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv32f16.nxv8f16( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_f16,,)(x0, x1, x2, x4);
+}
+
+svfloat32x4_t test_svcreate4_f32(svfloat32_t x0, svfloat32_t x1, svfloat32_t x2, svfloat32_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_f32
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv16f32.nxv4f32( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_f32,,)(

[PATCH] D80712: [SVE] Add checks for no warnings in SVE tests

2020-06-10 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c:6
 
+// ASM-NOT: warning
 #include 

Just thinking out loud here; we don't need to test for the specific warnings, 
because LLVM doesn't emit any other warnings and any Clang's warnings are 
otherwise caught by `-Werror`.



Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c:6
 
+// ASM-NOT: warning
 #include 

sdesmalen wrote:
> Just thinking out loud here; we don't need to test for the specific warnings, 
> because LLVM doesn't emit any other warnings and any Clang's warnings are 
> otherwise caught by `-Werror`.
Can you add a comment to these checks, so that if someone breaks it (because 
their code causes a new warning), they know where to look?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80712/new/

https://reviews.llvm.org/D80712



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[PATCH] D81721: [SVE] Ensure proper mangling of ACLE tuple types

2020-06-12 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: rsandifo-arm, c-rhodes, efriedma.
Herald added subscribers: cfe-commits, psnobl, rkruppe, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: clang.
sdesmalen added a parent revision: D81459: [SveEmitter] Add SVE tuple types and 
builtins for svundef..

The AAPCS specifies that the tuple types such as `svint32x2_t`
should use their `arm_sve.h` names when mangled instead of their
builtin names.

  

This patch also renames the internal types for the tuples to
be prefixed with `__clang_`, so they are not misinterpreted as
specified internal types like the non-tuple types which *are* defined
in the AAPCS. Using a builtin type for the tuples is a purely
a choice of the Clang implementation.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81721

Files:
  clang/include/clang/Basic/AArch64SVEACLETypes.def
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1069,39 +1069,39 @@
   OS << "typedef __SVFloat16_t svfloat16_t;\n";
   OS << "typedef __SVFloat32_t svfloat32_t;\n";
   OS << "typedef __SVFloat64_t svfloat64_t;\n";
-  OS << "typedef __SVInt8x2_t svint8x2_t;\n";
-  OS << "typedef __SVInt16x2_t svint16x2_t;\n";
-  OS << "typedef __SVInt32x2_t svint32x2_t;\n";
-  OS << "typedef __SVInt64x2_t svint64x2_t;\n";
-  OS << "typedef __SVUint8x2_t svuint8x2_t;\n";
-  OS << "typedef __SVUint16x2_t svuint16x2_t;\n";
-  OS << "typedef __SVUint32x2_t svuint32x2_t;\n";
-  OS << "typedef __SVUint64x2_t svuint64x2_t;\n";
-  OS << "typedef __SVFloat16x2_t svfloat16x2_t;\n";
-  OS << "typedef __SVFloat32x2_t svfloat32x2_t;\n";
-  OS << "typedef __SVFloat64x2_t svfloat64x2_t;\n";
-  OS << "typedef __SVInt8x3_t svint8x3_t;\n";
-  OS << "typedef __SVInt16x3_t svint16x3_t;\n";
-  OS << "typedef __SVInt32x3_t svint32x3_t;\n";
-  OS << "typedef __SVInt64x3_t svint64x3_t;\n";
-  OS << "typedef __SVUint8x3_t svuint8x3_t;\n";
-  OS << "typedef __SVUint16x3_t svuint16x3_t;\n";
-  OS << "typedef __SVUint32x3_t svuint32x3_t;\n";
-  OS << "typedef __SVUint64x3_t svuint64x3_t;\n";
-  OS << "typedef __SVFloat16x3_t svfloat16x3_t;\n";
-  OS << "typedef __SVFloat32x3_t svfloat32x3_t;\n";
-  OS << "typedef __SVFloat64x3_t svfloat64x3_t;\n";
-  OS << "typedef __SVInt8x4_t svint8x4_t;\n";
-  OS << "typedef __SVInt16x4_t svint16x4_t;\n";
-  OS << "typedef __SVInt32x4_t svint32x4_t;\n";
-  OS << "typedef __SVInt64x4_t svint64x4_t;\n";
-  OS << "typedef __SVUint8x4_t svuint8x4_t;\n";
-  OS << "typedef __SVUint16x4_t svuint16x4_t;\n";
-  OS << "typedef __SVUint32x4_t svuint32x4_t;\n";
-  OS << "typedef __SVUint64x4_t svuint64x4_t;\n";
-  OS << "typedef __SVFloat16x4_t svfloat16x4_t;\n";
-  OS << "typedef __SVFloat32x4_t svfloat32x4_t;\n";
-  OS << "typedef __SVFloat64x4_t svfloat64x4_t;\n";
+  OS << "typedef __clang_svint8x2_t svint8x2_t;\n";
+  OS << "typedef __clang_svint16x2_t svint16x2_t;\n";
+  OS << "typedef __clang_svint32x2_t svint32x2_t;\n";
+  OS << "typedef __clang_svint64x2_t svint64x2_t;\n";
+  OS << "typedef __clang_svuint8x2_t svuint8x2_t;\n";
+  OS << "typedef __clang_svuint16x2_t svuint16x2_t;\n";
+  OS << "typedef __clang_svuint32x2_t svuint32x2_t;\n";
+  OS << "typedef __clang_svuint64x2_t svuint64x2_t;\n";
+  OS << "typedef __clang_svfloat16x2_t svfloat16x2_t;\n";
+  OS << "typedef __clang_svfloat32x2_t svfloat32x2_t;\n";
+  OS << "typedef __clang_svfloat64x2_t svfloat64x2_t;\n";
+  OS << "typedef __clang_svint8x3_t svint8x3_t;\n";
+  OS << "typedef __clang_svint16x3_t svint16x3_t;\n";
+  OS << "typedef __clang_svint32x3_t svint32x3_t;\n";
+  OS << "typedef __clang_svint64x3_t svint64x3_t;\n";
+  OS << "typedef __clang_svuint8x3_t svuint8x3_t;\n";
+  OS << "typedef __clang_svuint16x3_t svuint16x3_t;\n";
+  OS << "typedef __clang_svuint32x3_t svuint32x3_t;\n";
+  OS << "typedef __clang_svuint64x3_t svuint64x3_t;\n";
+  OS << "typedef __clang_svfloat16x3_t svfloat16x3_t;\n";
+  OS << "typedef __clang_svfloat32x3_t svfloat32x3_t;\n";
+  OS << "typedef __clang_svfloat64x3_t svfloat64x3_t;\n";
+  OS << "typedef __clang_svint8x4_t svint8x4_t;\n";
+  OS << "typedef __clang_svint16x4_t svint16x4_t;\n";
+  OS << "typedef __clang_svint32x4_t svint32x4_t;\n";
+  OS << "typedef __clang_svint64x4_t svint64x4_t;\n";
+  OS << "typedef __clang_svuint8x4_t svuint8x4_t;\n";
+  OS << "typedef __clang_svuint16x4_t svuint16x4_t;\n";
+  OS << "typedef __clang_svuint32x4_t svuint32x4_t;\n";
+  OS << "typedef __clang_svuint64x4_t svuint64x4_t;\n";
+  OS << "typedef __clang_svfloat16x4_t svfloat16x4_t;\n";
+  OS << "typedef __clang_svfloat32x4_t svfloat32x4_t;\n";
+  OS << "typedef __clang_svfloat64x4_t svfloat64x4_t;\n";
   OS << "typedef __SVBoo

[PATCH] D81721: [SVE] Ensure proper mangling of ACLE tuple types

2020-06-12 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a comment.

See 
https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#appendix-c-mangling
 for details on the mangling rules.

I thought it would be easier to review if I kept these changes separate from 
D81459 .


Repository:
  rG LLVM Github Monorepo

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[PATCH] D81459: [SveEmitter] Add SVE tuple types and builtins for svundef.

2020-06-14 Thread Sander de Smalen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG91a4a592edb0: [SveEmitter] Add SVE tuple types and builtins 
for svundef. (authored by sdesmalen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81459/new/

https://reviews.llvm.org/D81459

Files:
  clang/include/clang/Basic/AArch64SVEACLETypes.def
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef3.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4.c
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -490,6 +490,15 @@
 
 void SVEType::applyModifier(char Mod) {
   switch (Mod) {
+  case '2':
+NumVectors = 2;
+break;
+  case '3':
+NumVectors = 3;
+break;
+  case '4':
+NumVectors = 4;
+break;
   case 'v':
 Void = true;
 break;
@@ -801,18 +810,7 @@
 }
 
 std::string Intrinsic::getBuiltinTypeStr() {
-  std::string S;
-
-  SVEType RetT = getReturnType();
-  // Since the return value must be one type, return a vector type of the
-  // appropriate width which we will bitcast.  An exception is made for
-  // returning structs of 2, 3, or 4 vectors which are returned in a sret-like
-  // fashion, storing them to a pointer arg.
-  if (RetT.getNumVectors() > 1) {
-S += "vv*"; // void result with void* first argument
-  } else
-S += RetT.builtin_str();
-
+  std::string S = getReturnType().builtin_str();
   for (unsigned I = 0; I < getNumParams(); ++I)
 S += getParamType(I).builtin_str();
 
@@ -1071,6 +1069,39 @@
   OS << "typedef __SVFloat16_t svfloat16_t;\n";
   OS << "typedef __SVFloat32_t svfloat32_t;\n";
   OS << "typedef __SVFloat64_t svfloat64_t;\n";
+  OS << "typedef __SVInt8x2_t svint8x2_t;\n";
+  OS << "typedef __SVInt16x2_t svint16x2_t;\n";
+  OS << "typedef __SVInt32x2_t svint32x2_t;\n";
+  OS << "typedef __SVInt64x2_t svint64x2_t;\n";
+  OS << "typedef __SVUint8x2_t svuint8x2_t;\n";
+  OS << "typedef __SVUint16x2_t svuint16x2_t;\n";
+  OS << "typedef __SVUint32x2_t svuint32x2_t;\n";
+  OS << "typedef __SVUint64x2_t svuint64x2_t;\n";
+  OS << "typedef __SVFloat16x2_t svfloat16x2_t;\n";
+  OS << "typedef __SVFloat32x2_t svfloat32x2_t;\n";
+  OS << "typedef __SVFloat64x2_t svfloat64x2_t;\n";
+  OS << "typedef __SVInt8x3_t svint8x3_t;\n";
+  OS << "typedef __SVInt16x3_t svint16x3_t;\n";
+  OS << "typedef __SVInt32x3_t svint32x3_t;\n";
+  OS << "typedef __SVInt64x3_t svint64x3_t;\n";
+  OS << "typedef __SVUint8x3_t svuint8x3_t;\n";
+  OS << "typedef __SVUint16x3_t svuint16x3_t;\n";
+  OS << "typedef __SVUint32x3_t svuint32x3_t;\n";
+  OS << "typedef __SVUint64x3_t svuint64x3_t;\n";
+  OS << "typedef __SVFloat16x3_t svfloat16x3_t;\n";
+  OS << "typedef __SVFloat32x3_t svfloat32x3_t;\n";
+  OS << "typedef __SVFloat64x3_t svfloat64x3_t;\n";
+  OS << "typedef __SVInt8x4_t svint8x4_t;\n";
+  OS << "typedef __SVInt16x4_t svint16x4_t;\n";
+  OS << "typedef __SVInt32x4_t svint32x4_t;\n";
+  OS << "typedef __SVInt64x4_t svint64x4_t;\n";
+  OS << "typedef __SVUint8x4_t svuint8x4_t;\n";
+  OS << "typedef __SVUint16x4_t svuint16x4_t;\n";
+  OS << "typedef __SVUint32x4_t svuint32x4_t;\n";
+  OS << "typedef __SVUint64x4_t svuint64x4_t;\n";
+  OS << "typedef __SVFloat16x4_t svfloat16x4_t;\n";
+  OS << "typedef __SVFloat32x4_t svfloat32x4_t;\n";
+  OS << "typedef __SVFloat64x4_t svfloat64x4_t;\n";
   OS << "typedef __SVBool_t  svbool_t;\n\n";
 
   OS << "typedef enum\n";
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4.c
@@ -0,0 +1,80 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O2 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+svint8x4_t test_svundef4_s8()
+{
+  // CHECK-LABEL: test_svundef4_s8
+  // CHECK: ret  undef
+  return svundef4_s8();
+}
+
+svint16x4_t test_svundef4_s16()
+{
+  // CHECK-LABEL: test_svundef4_s16
+  // CHECK: ret  undef
+  return svundef4_s16();
+}
+
+svint32x4_t test_svundef4_s32()
+{
+  // CHECK-LABEL: test_svundef4_s32
+  // CHECK: ret  undef
+  return svundef4_s32();
+}
+
+svint64x4_t test_svundef4_s64()
+{
+  // CHECK-LABEL: test_svundef4_s64
+  // CHECK: ret  undef
+  return svundef4_s64();
+}
+
+svuint8x4_t test_svundef4_u8()
+{
+  // CHECK-LABEL: test_svundef4_u8
+  // CHECK: ret  undef
+  return svundef4_u8();
+}
+
+svuint16x4_t test_svundef4_u16()
+{
+  // CHECK-LABEL: test_svund

[PATCH] D81721: [SVE] Ensure proper mangling of ACLE tuple types

2020-06-14 Thread Sander de Smalen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG98100353d784: [SVE] Ensure proper mangling of ACLE tuple 
types (authored by sdesmalen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81721/new/

https://reviews.llvm.org/D81721

Files:
  clang/include/clang/Basic/AArch64SVEACLETypes.def
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
  clang/utils/TableGen/SveEmitter.cpp

Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1069,39 +1069,39 @@
   OS << "typedef __SVFloat16_t svfloat16_t;\n";
   OS << "typedef __SVFloat32_t svfloat32_t;\n";
   OS << "typedef __SVFloat64_t svfloat64_t;\n";
-  OS << "typedef __SVInt8x2_t svint8x2_t;\n";
-  OS << "typedef __SVInt16x2_t svint16x2_t;\n";
-  OS << "typedef __SVInt32x2_t svint32x2_t;\n";
-  OS << "typedef __SVInt64x2_t svint64x2_t;\n";
-  OS << "typedef __SVUint8x2_t svuint8x2_t;\n";
-  OS << "typedef __SVUint16x2_t svuint16x2_t;\n";
-  OS << "typedef __SVUint32x2_t svuint32x2_t;\n";
-  OS << "typedef __SVUint64x2_t svuint64x2_t;\n";
-  OS << "typedef __SVFloat16x2_t svfloat16x2_t;\n";
-  OS << "typedef __SVFloat32x2_t svfloat32x2_t;\n";
-  OS << "typedef __SVFloat64x2_t svfloat64x2_t;\n";
-  OS << "typedef __SVInt8x3_t svint8x3_t;\n";
-  OS << "typedef __SVInt16x3_t svint16x3_t;\n";
-  OS << "typedef __SVInt32x3_t svint32x3_t;\n";
-  OS << "typedef __SVInt64x3_t svint64x3_t;\n";
-  OS << "typedef __SVUint8x3_t svuint8x3_t;\n";
-  OS << "typedef __SVUint16x3_t svuint16x3_t;\n";
-  OS << "typedef __SVUint32x3_t svuint32x3_t;\n";
-  OS << "typedef __SVUint64x3_t svuint64x3_t;\n";
-  OS << "typedef __SVFloat16x3_t svfloat16x3_t;\n";
-  OS << "typedef __SVFloat32x3_t svfloat32x3_t;\n";
-  OS << "typedef __SVFloat64x3_t svfloat64x3_t;\n";
-  OS << "typedef __SVInt8x4_t svint8x4_t;\n";
-  OS << "typedef __SVInt16x4_t svint16x4_t;\n";
-  OS << "typedef __SVInt32x4_t svint32x4_t;\n";
-  OS << "typedef __SVInt64x4_t svint64x4_t;\n";
-  OS << "typedef __SVUint8x4_t svuint8x4_t;\n";
-  OS << "typedef __SVUint16x4_t svuint16x4_t;\n";
-  OS << "typedef __SVUint32x4_t svuint32x4_t;\n";
-  OS << "typedef __SVUint64x4_t svuint64x4_t;\n";
-  OS << "typedef __SVFloat16x4_t svfloat16x4_t;\n";
-  OS << "typedef __SVFloat32x4_t svfloat32x4_t;\n";
-  OS << "typedef __SVFloat64x4_t svfloat64x4_t;\n";
+  OS << "typedef __clang_svint8x2_t svint8x2_t;\n";
+  OS << "typedef __clang_svint16x2_t svint16x2_t;\n";
+  OS << "typedef __clang_svint32x2_t svint32x2_t;\n";
+  OS << "typedef __clang_svint64x2_t svint64x2_t;\n";
+  OS << "typedef __clang_svuint8x2_t svuint8x2_t;\n";
+  OS << "typedef __clang_svuint16x2_t svuint16x2_t;\n";
+  OS << "typedef __clang_svuint32x2_t svuint32x2_t;\n";
+  OS << "typedef __clang_svuint64x2_t svuint64x2_t;\n";
+  OS << "typedef __clang_svfloat16x2_t svfloat16x2_t;\n";
+  OS << "typedef __clang_svfloat32x2_t svfloat32x2_t;\n";
+  OS << "typedef __clang_svfloat64x2_t svfloat64x2_t;\n";
+  OS << "typedef __clang_svint8x3_t svint8x3_t;\n";
+  OS << "typedef __clang_svint16x3_t svint16x3_t;\n";
+  OS << "typedef __clang_svint32x3_t svint32x3_t;\n";
+  OS << "typedef __clang_svint64x3_t svint64x3_t;\n";
+  OS << "typedef __clang_svuint8x3_t svuint8x3_t;\n";
+  OS << "typedef __clang_svuint16x3_t svuint16x3_t;\n";
+  OS << "typedef __clang_svuint32x3_t svuint32x3_t;\n";
+  OS << "typedef __clang_svuint64x3_t svuint64x3_t;\n";
+  OS << "typedef __clang_svfloat16x3_t svfloat16x3_t;\n";
+  OS << "typedef __clang_svfloat32x3_t svfloat32x3_t;\n";
+  OS << "typedef __clang_svfloat64x3_t svfloat64x3_t;\n";
+  OS << "typedef __clang_svint8x4_t svint8x4_t;\n";
+  OS << "typedef __clang_svint16x4_t svint16x4_t;\n";
+  OS << "typedef __clang_svint32x4_t svint32x4_t;\n";
+  OS << "typedef __clang_svint64x4_t svint64x4_t;\n";
+  OS << "typedef __clang_svuint8x4_t svuint8x4_t;\n";
+  OS << "typedef __clang_svuint16x4_t svuint16x4_t;\n";
+  OS << "typedef __clang_svuint32x4_t svuint32x4_t;\n";
+  OS << "typedef __clang_svuint64x4_t svuint64x4_t;\n";
+  OS << "typedef __clang_svfloat16x4_t svfloat16x4_t;\n";
+  OS << "typedef __clang_svfloat32x4_t svfloat32x4_t;\n";
+  OS << "typedef __clang_svfloat64x4_t svfloat64x4_t;\n";
   OS << "typedef __SVBool_t  svbool_t;\n\n";
 
   OS << "typedef enum\n";
Index: clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
===
--- clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
+++ clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
@@ -29,3 +29,72 @@
 void f11(S<__SVFloat64_t>) {}
 // CHECK: _Z3f121SIu10__SVBool_tE
 void f12(S<__SVBool_t>) {}
+
+// The tuple types don't use the internal name for mangling.
+
+// CHECK: _Z3f131SI10svint8x2_tE
+void f13(S<__clang_svint8x2_t>) {}
+//

[PATCH] D80851: [llvm][SveEmitter] SVE ACLE for quadword permute intrinsics.

2020-06-15 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

LGTM!


Repository:
  rG LLVM Github Monorepo

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[PATCH] D81304: [llvm][SveEmitter] Emit the bfloat version of `svld1ro`.

2020-06-16 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c:1
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE -triple 
aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s

stuij wrote:
> There should be no dependency on `-fallow-half-arguments-and-returns`. For 
> bfloat we should use `-mfloat-abi hard`. Does this work for `-mfloat-abi 
> softfp`?
`-fallow-half-arguments-and-returns` isn't strictly needed for this test, we 
just use the same RUN line for all the ACLE tests and we needed this for 
`__fp16` in some of the tests.

I don't believe that `-mfloat-abi softfp` is supported for AArch64.


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[PATCH] D81304: [llvm][SveEmitter] Emit the bfloat version of `svld1ro`.

2020-06-16 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

LGTM




Comment at: clang/include/clang/Basic/AArch64SVEACLETypes.def:44
 #define SVE_VECTOR_TYPE(Name, MangledName, Id, SingletonId, NumEls, ElBits,
\
-IsSigned, IsFP)
\
+IsSigned, IsFP, IsBF)\
   SVE_TYPE(Name, Id, SingletonId)

nit: odd formatting (of the last `\`), did you use clang-format?


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[PATCH] D81462: [SveEmitter] Add builtins for svtbl2

2020-06-17 Thread Sander de Smalen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGe51c1d06a992: [SveEmitter] Add builtins for svtbl2 (authored 
by sdesmalen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81462/new/

https://reviews.llvm.org/D81462

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbl2.c

Index: clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbl2.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbl2.c
@@ -0,0 +1,145 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8_t test_svtbl2_s8(svint8x2_t data, svuint8_t indices)
+{
+  // CHECK-LABEL: test_svtbl2_s8
+  // CHECK-DAG: %[[V0:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv16i8.nxv32i8( %data, i32 0)
+  // CHECK-DAG: %[[V1:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv16i8.nxv32i8( %data, i32 1)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.tbl2.nxv16i8( %[[V0]],  %[[V1]],  %indices)
+  // CHECK-NEXT: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svtbl2'}}
+  // expected-warning@+1 {{implicit declaration of function 'svtbl2_s8'}}
+  return SVE_ACLE_FUNC(svtbl2,_s8,,)(data, indices);
+}
+
+svint16_t test_svtbl2_s16(svint16x2_t data, svuint16_t indices)
+{
+  // CHECK-LABEL: test_svtbl2_s16
+  // CHECK-DAG: %[[V0:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv8i16.nxv16i16( %data, i32 0)
+  // CHECK-DAG: %[[V1:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv8i16.nxv16i16( %data, i32 1)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.tbl2.nxv8i16( %[[V0]],  %[[V1]],  %indices)
+  // CHECK-NEXT: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svtbl2'}}
+  // expected-warning@+1 {{implicit declaration of function 'svtbl2_s16'}}
+  return SVE_ACLE_FUNC(svtbl2,_s16,,)(data, indices);
+}
+
+svint32_t test_svtbl2_s32(svint32x2_t data, svuint32_t indices)
+{
+  // CHECK-LABEL: test_svtbl2_s32
+  // CHECK-DAG: %[[V0:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv4i32.nxv8i32( %data, i32 0)
+  // CHECK-DAG: %[[V1:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv4i32.nxv8i32( %data, i32 1)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.tbl2.nxv4i32( %[[V0]],  %[[V1]],  %indices)
+  // CHECK-NEXT: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svtbl2'}}
+  // expected-warning@+1 {{implicit declaration of function 'svtbl2_s32'}}
+  return SVE_ACLE_FUNC(svtbl2,_s32,,)(data, indices);
+}
+
+svint64_t test_svtbl2_s64(svint64x2_t data, svuint64_t indices)
+{
+  // CHECK-LABEL: test_svtbl2_s64
+  // CHECK-DAG: %[[V0:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv2i64.nxv4i64( %data, i32 0)
+  // CHECK-DAG: %[[V1:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv2i64.nxv4i64( %data, i32 1)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.tbl2.nxv2i64( %[[V0]],  %[[V1]],  %indices)
+  // CHECK-NEXT: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svtbl2'}}
+  // expected-warning@+1 {{implicit declaration of function 'svtbl2_s64'}}
+  return SVE_ACLE_FUNC(svtbl2,_s64,,)(data, indices);
+}
+
+svuint8_t test_svtbl2_u8(svuint8x2_t data, svuint8_t indices)
+{
+  // CHECK-LABEL: test_svtbl2_u8
+  // CHECK-DAG: %[[V0:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv16i8.nxv32i8( %data, i32 0)
+  // CHECK-DAG: %[[V1:.*]] = call  @llvm.aarch64.sve.tuple.get.nxv16i8.nxv32i8( %data, i32 1)
+  // CHECK: %[[INTRINSIC:.*]] = call  @llvm.aarch64.sve.tbl2.nxv16i8( %[[V0]],  %[[V1]],  %indices)
+  // CHECK-NEXT: ret  %[[INTRINSIC]]
+  // overload-warning@+2 {{implicit declaration of function 'svtbl2'}}
+  // expected-warning@+1 {{implicit declaration of function 'svtbl2_u8'}}
+  return SVE_ACLE_FUNC(svtbl2,_u8,,)(data, indices);
+}
+
+svuint16_t test_svtbl2_u16(svuint16x2_t data, sv

[PATCH] D81463: [SveEmitter] Add builtins for tuple creation (svcreate2/svcreate3/etc)

2020-06-18 Thread Sander de Smalen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1d7b4a7e5e4a: [SveEmitter] Add builtins for tuple creation 
(svcreate2/svcreate3/etc) (authored by sdesmalen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81463/new/

https://reviews.llvm.org/D81463

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c

Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c
@@ -0,0 +1,99 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8x4_t test_svcreate4_s8(svint8_t x0, svint8_t x1, svint8_t x2, svint8_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_s8
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv64i8.nxv16i8( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_s8,,)(x0, x1, x2, x4);
+}
+
+svint16x4_t test_svcreate4_s16(svint16_t x0, svint16_t x1, svint16_t x2, svint16_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_s16
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv32i16.nxv8i16( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_s16,,)(x0, x1, x2, x4);
+}
+
+svint32x4_t test_svcreate4_s32(svint32_t x0, svint32_t x1, svint32_t x2, svint32_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_s32
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_s32,,)(x0, x1, x2, x4);
+}
+
+svint64x4_t test_svcreate4_s64(svint64_t x0, svint64_t x1, svint64_t x2, svint64_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_s64
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_s64,,)(x0, x1, x2, x4);
+}
+
+svuint8x4_t test_svcreate4_u8(svuint8_t x0, svuint8_t x1, svuint8_t x2, svuint8_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_u8
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv64i8.nxv16i8( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_u8,,)(x0, x1, x2, x4);
+}
+
+svuint16x4_t test_svcreate4_u16(svuint16_t x0, svuint16_t x1, svuint16_t x2, svuint16_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_u16
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv32i16.nxv8i16( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_u16,,)(x0, x1, x2, x4);
+}
+
+svuint32x4_t test_svcreate4_u32(svuint32_t x0, svuint32_t x1, svuint32_t x2, svuint32_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_u32
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_u32,,)(x0, x1, x2, x4);
+}
+
+svuint64x4_t test_svcreate4_u64(svuint64_t x0, svuint64_t x1, svuint64_t x2, svuint64_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_u64
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv8i64.nxv2i64( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_u64,,)(x0, x1, x2, x4);
+}
+
+svfloat16x4_t test_svcreate4_f16(svfloat16_t x0, svfloat16_t x1, svfloat16_t x2, svfloat16_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_f16
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv32f16.nxv8f16( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_f16,,)(x0, x1, x2, x4);
+}
+
+svfloat32x4_t test_svcreate4_f32(svfloat32_t x0, svfloat32_t x1, svfloat32_t x2, svfloat32_t x4)
+{
+  // CHECK-LABEL: test_svcreate4_f32
+  // CHECK: %[[CREATE:.*]] = call  @llvm.aarch64.sve.tuple.create4.nxv16f32.nxv4f32( %x0,  %x1,  %x2,  %x4)
+  // CHECK-NEXT: ret  %[[CREATE]]
+  return SVE_ACLE_FUNC(svcreate4,_f32,,)(x0, x1, x2, x4);
+}
+
+svfloat64x4_t test_svcreate4_f64(svfloat64_t x0

[PATCH] D81464: [SveEmitter] Add builtins to insert/extract subvectors from tuples (svget/svset)

2020-06-18 Thread Sander de Smalen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG4ea8e27a642c: [SveEmitter] Add builtins to insert/extract 
subvectors from tuples (svget/svset) (authored by sdesmalen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81464/new/

https://reviews.llvm.org/D81464

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_get2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_get3.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_get4.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_set2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_set3.c
  clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_set4.c

Index: clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_set4.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/negative/acle_sve_set4.c
@@ -0,0 +1,143 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=note %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=note %s
+
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svint8x4_t test_svset4_s8(svint8x4_t tuple, svint8_t x)
+{
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_s8,,)(tuple, 4, x);
+}
+
+svint16x4_t test_svset4_s16(svint16x4_t tuple, svint16_t x)
+{
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_s16,,)(tuple, -1, x);
+}
+
+svint32x4_t test_svset4_s32(svint32x4_t tuple, svint32_t x)
+{
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_s32,,)(tuple, 4, x);
+}
+
+svint64x4_t test_svset4_s64(svint64x4_t tuple, svint64_t x)
+{
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_s64,,)(tuple, -1, x);
+}
+
+svuint8x4_t test_svset4_u8(svuint8x4_t tuple, svuint8_t x)
+{
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_u8,,)(tuple, 4, x);
+}
+
+svuint16x4_t test_svset4_u16(svuint16x4_t tuple, svuint16_t x)
+{
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_u16,,)(tuple, -1, x);
+}
+
+svuint32x4_t test_svset4_u32(svuint32x4_t tuple, svuint32_t x)
+{
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_u32,,)(tuple, 4, x);
+}
+
+svuint64x4_t test_svset4_u64(svuint64x4_t tuple, svuint64_t x)
+{
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_u64,,)(tuple, -1, x);
+}
+
+svfloat16x4_t test_svset4_f16(svfloat16x4_t tuple, svfloat16_t x)
+{
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_f16,,)(tuple, 4, x);
+}
+
+svfloat32x4_t test_svset4_f32(svfloat32x4_t tuple, svfloat32_t x)
+{
+  // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_f32,,)(tuple, -1, x);
+}
+
+svfloat64x4_t test_svset4_f64(svfloat64x4_t tuple, svfloat64_t x)
+{
+  // expected-error@+1 {{argument value 4 is outside the valid range [0, 3]}}
+  return SVE_ACLE_FUNC(svset4,_f64,,)(tuple, 4, x);
+}
+
+svint8x4_t test_svset4_s8_var(svint8x4_t tuple, uint64_t imm_index, svint8_t x)
+{
+  // expected-error-re@+1 {{argument to '{{.*}}' must be a constant integer}}
+  return SVE_ACLE_FUNC(svset4,_s8,,)(tuple, imm_index, x);
+}
+
+svint16x4_t test_svset4_s16_var(svint16x4_t tuple, uint64_t imm_index, svint16_t x)
+{
+  // expected-error-re@+1 {{argument to '{{.*}}' must be a constant integer}}
+  return SVE_ACLE_FUNC(svset4,_s16,,)(tuple, imm_index, x);
+}
+
+svint32x4_t test_svset4_s32_var(svint32

[PATCH] D81304: [llvm][SveEmitter] Emit the bfloat version of `svld1ro`.

2020-06-18 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c:1
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE -triple 
aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s

fpetrogalli wrote:
> sdesmalen wrote:
> > stuij wrote:
> > > There should be no dependency on `-fallow-half-arguments-and-returns`. 
> > > For bfloat we should use `-mfloat-abi hard`. Does this work for 
> > > `-mfloat-abi softfp`?
> > `-fallow-half-arguments-and-returns` isn't strictly needed for this test, 
> > we just use the same RUN line for all the ACLE tests and we needed this for 
> > `__fp16` in some of the tests.
> > 
> > I don't believe that `-mfloat-abi softfp` is supported for AArch64.
> @stuij - the following lines work, one with `softfp` and one with `hard`:
> 
> ```
> // RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
> -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
> -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
> -target\
> -feature +bf16 -mfloat-abi softfp -fallow-half-arguments-and-returns -S -O1 
> -Werror -Wall -emit-llvm -o - %s | FileCheck %s
> // RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
> -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
> -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
> -target\
> -feature +bf16 -mfloat-abi hard -fallow-half-arguments-and-returns -S -O1 
> -Werror -Wall -emit-llvm -o - %s | FileCheck %s
> ```
> 
> @sdesmalen I am not an experer here, but there is a test which targets 
> aarch64 that uses `softfp` (see 
> `clang/test/CodeGen/arm-bf16-params-returns.c`). The following line in that 
> test clearly targets `aarch64`:
> 
> ```
> // RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs 
> -mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 
> -o - %s | opt -S -mem2reg -sroa | FileCheck %s \
> --check-prefix=CHECK64-SOFTFP
> ```
> 
> @both - should I update the test with the two extra RUN lines mentioned up in 
> the message?
> @sdesmalen I am not an experer here, but there is a test which targets 
> aarch64 that uses softfp (see clang/test/CodeGen/arm-bf16-params-returns.c). 
> The following line in that test clearly targets aarch64:
`clang/test/CodeGen/arm-bf16-params-returns.c` also shows that setting `softfp` 
has no effect for AArch64.

> @both - should I update the test with the two extra RUN lines mentioned up in 
> the message?
No, I think the extra RUN lines aren't necessary.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81304/new/

https://reviews.llvm.org/D81304



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[PATCH] D82908: [SVE] ACLE: Fix builtins for svdup_lane_bf16 and svcvtnt_bf16_f32_x

2020-07-02 Thread Sander de Smalen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGf255656a97f7: [SVE] ACLE: Fix builtins for svdup_lane_bf16 
and svcvtnt_bf16_f32_x (authored by sdesmalen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82908/new/

https://reviews.llvm.org/D82908

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvtnt.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup-bfloat.c
  clang/utils/TableGen/SveEmitter.cpp


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1262,6 +1262,11 @@
   if (!InGuard.empty())
 OS << "#endif  //" << InGuard << "\n";
 
+  OS << "#if defined(__ARM_FEATURE_SVE_BF16)\n";
+  OS << "#define svcvtnt_bf16_x  svcvtnt_bf16_m\n";
+  OS << "#define svcvtnt_bf16_f32_x  svcvtnt_bf16_f32_m\n";
+  OS << "#endif /*__ARM_FEATURE_SVE_BF16 */\n\n";
+
   OS << "#if defined(__ARM_FEATURE_SVE2)\n";
   OS << "#define svcvtnt_f16_x  svcvtnt_f16_m\n";
   OS << "#define svcvtnt_f16_f32_x  svcvtnt_f16_f32_m\n";
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup-bfloat.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup-bfloat.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup-bfloat.c
@@ -51,3 +51,13 @@
   // expected-warning@+1 {{implicit declaration of function 'svdup_n_bf16_x'}}
   return SVE_ACLE_FUNC(svdup, _n, _bf16_x, )(pg, op);
 }
+
+svbfloat16_t test_svdup_lane_bf16(svbfloat16_t data, uint16_t index)
+{
+  // CHECK-LABEL: test_svdup_lane_bf16
+  // CHECK: %[[DUP:.*]] = call  
@llvm.aarch64.sve.dup.x.nxv8i16(i16 %index)
+  // CHECK: %[[INTRINSIC:.*]] = call  
@llvm.aarch64.sve.tbl.nxv8bf16( %data,  
%[[DUP]])
+  // CHECK: ret  %[[INTRINSIC]]
+  // expected-warning@+1 {{implicit declaration of function 'svdup_lane_bf16'}}
+  return SVE_ACLE_FUNC(svdup_lane,_bf16,,)(data, index);
+}
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvtnt.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvtnt.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvtnt.c
@@ -10,18 +10,18 @@
 #define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
 #endif
 
-svbfloat16_t test_svcvtnt_bf16_f32_x(svbool_t pg, svfloat32_t op) {
+svbfloat16_t test_svcvtnt_bf16_f32_x(svbfloat16_t even, svbool_t pg, 
svfloat32_t op) {
   // CHECK-LABEL: test_svcvtnt_bf16_f32_x
   // CHECK: %[[PG:.*]] = call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg)
-  // CHECK: %[[INTRINSIC:.*]] = call  
@llvm.aarch64.sve.fcvtnt.bf16f32( undef,  
%[[PG]],  %op)
+  // CHECK: %[[INTRINSIC:.*]] = call  
@llvm.aarch64.sve.fcvtnt.bf16f32( %even,  
%[[PG]],  %op)
   // CHECK: ret  %[[INTRINSIC]]
-  return SVE_ACLE_FUNC(svcvtnt_bf16, _f32, _x, )(pg, op);
+  return SVE_ACLE_FUNC(svcvtnt_bf16, _f32, _x, )(even, pg, op);
 }
 
-svbfloat16_t test_svcvtnt_bf16_f32_m(svbfloat16_t inactive, svbool_t pg, 
svfloat32_t op) {
+svbfloat16_t test_svcvtnt_bf16_f32_m(svbfloat16_t even, svbool_t pg, 
svfloat32_t op) {
   // CHECK-LABEL: test_svcvtnt_bf16_f32_m
   // CHECK: %[[PG:.*]] = call  
@llvm.aarch64.sve.convert.from.svbool.nxv8i1( %pg)
-  // CHECK: %[[INTRINSIC:.*]] = call  
@llvm.aarch64.sve.fcvtnt.bf16f32( %inactive,  %[[PG]],  %op)
+  // CHECK: %[[INTRINSIC:.*]] = call  
@llvm.aarch64.sve.fcvtnt.bf16f32( %even,  
%[[PG]],  %op)
   // CHECK: ret  %[[INTRINSIC]]
-  return SVE_ACLE_FUNC(svcvtnt_bf16, _f32, _m, )(inactive, pg, op);
+  return SVE_ACLE_FUNC(svcvtnt_bf16, _f32, _m, )(even, pg, op);
 }
Index: clang/include/clang/Basic/arm_sve.td
===
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -1110,7 +1110,7 @@
 
 let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
   defm SVCVT_BF16_F32   : SInstCvtMXZ<"svcvt_bf16[_f32]",  "ddPM", "dPM", "b", 
 "aarch64_sve_fcvt_bf16f32">;
-  defm SVCVTNT_BF16_F32 : SInstCvtMX<"svcvtnt_bf16[_f32]", "ddPM", "dPM", "b", 
 "aarch64_sve_fcvtnt_bf16f32">;
+  def SVCVTNT_BF16_F32 : SInst<"svcvtnt_bf16[_f32]", "ddPM", "b",  MergeOp1, 
"aarch64_sve_fcvtnt_bf16f32", [IsOverloadNone]>;
 }
 
 // svcvt_s##_f64
@@ -1204,6 +1204,11 @@
 // instruction such as DUP (indexed) if the lane index fits the range of the
 // instruction's immediate.
 def SVDUP_LANE   : SInst<"svdup_lane[_{d}]",  "ddL",  "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_tbl">;
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
+def SVDUP_LANE_BF16 :
+   SInst<"svdup_lane[_{d}]",  "ddL",  "b",   
MergeNone, "aarch64_sve_tbl">;
+}
+
 def SVDUPQ_LANE  : SInst<"svdupq_lane[_{d}]", "ddn",  "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_dupq_lane">;
 let ArchGuard = "defined(__ARM_FEATU

[PATCH] D83079: [clang] Default target features implied by `-march` on AArch64.

2020-07-02 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:118
+  case llvm::AArch64::ArchKind::ARMV8_6A:
+Features.push_back("+i8mm");
+Features.push_back("+bf16");

Looking at what Clang emits for e.g. `-march=armv8.5-a`, it just adds a 
target-feature `+v8.5a`. The definitions in 
`llvm/lib/Target/AArch64/AArch64.td`. suggests that LLVM is already able to 
infer all supported features from that. e.g.
```
def HasV8_4aOps : SubtargetFeature<
   :
   :

def HasV8_5aOps : SubtargetFeature<
  "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
  [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
   FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
   FeatureBranchTargetId]>;

def HasV8_6aOps : SubtargetFeature<
  "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",

  [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
   FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
```
So I don't think you necessarily have to decompose the architecture version 
into target-features in the Clang driver as well. For Clang it matters that the 
right set of feature macros are defined so that the ACLE header file exposes 
the correct set of functions for the given architecture version. At least for 
the SVE ACLE that is just a small handful of features.


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[PATCH] D83079: [clang][aarch64] Generate preprocessor macros for -march=armv8.6a+sve.

2020-07-07 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

LGTM




Comment at: clang/test/Preprocessor/aarch64-target-features.c:415
 // CHECK-BFLOAT: __ARM_FEATURE_BF16_VECTOR_ARITHMETIC 1
-

nit: unrelated change.


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[PATCH] D83079: [clang][aarch64] Generate preprocessor macros for -march=armv8.6a+sve.

2020-07-08 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:369
+  if (llvm::is_contained(Features, "+v8.6a")) {
+if (!llvm::is_contained(Features, "-i8mm") &&
+!llvm::is_contained(Features, "+noi8mm"))

Is this correct and/or necessary? I would expect LLVM to just handle features 
in the order they're passed, and the architecture version is always processed 
first, e.g. `-march=armv8.6-a+noi8mm` will always first process `armv8.6a` 
before processing features like `noi8mm`.


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[PATCH] D83079: [clang][aarch64] Generate preprocessor macros for -march=armv8.6a+sve.

2020-07-08 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:369
+  if (llvm::is_contained(Features, "+v8.6a")) {
+if (!llvm::is_contained(Features, "-i8mm") &&
+!llvm::is_contained(Features, "+noi8mm"))

fpetrogalli wrote:
> sdesmalen wrote:
> > Is this correct and/or necessary? I would expect LLVM to just handle 
> > features in the order they're passed, and the architecture version is 
> > always processed first, e.g. `-march=armv8.6-a+noi8mm` will always first 
> > process `armv8.6a` before processing features like `noi8mm`.
> I was expecting that too, but in in this place the `+i8mm` is added after 
> whatever the user have passed to -march, which means that without this extra 
> check the user input `-mattr=armv8.6a+sve+noimm8` becomes broken because we 
> are adding `-target-feature=+i8mm` after `-i8mm`.  This behavior is guarded 
> by a regression tests that starts failing if I don't use these extra checks. 
> This was not needed in the original place were I added the functionality 
> because the `+i8mm` was being added right after `+v8.6a` and before splitting 
> up the `+sve+noi8mm`, so that the user input was the one (un)setting the 
> feature.
As you said, we end up with a Feature list as follows:

  parsing(-march=armv8.6-a+noi8mm)
  => Features = [ v8.6a ]

  parsing(+noi8mm)
  => Features = [ v8.6a, -i8mm ]

  Then going through the feature list again:
  => Features = [ v8.6a, -i8mm, +i8mm ]
  ^  
\_/
   adds +i8mm

To fix that, you can insert these features into the list straight after 
"+v8.6a", instead of appending at the end of the Features list. Either that, or 
calling `llvm::AArch64::getDefaultExtensions() + 
llvm::AArch64::getExtensionFeatures()` in `getAArch64ArchFeaturesFromMarch` 
like is done in `DecodeAArch64Mcpu`, which should do all this for free. That 
seems like a more invasive change though that you shouldn't try to do in this 
patch.


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[PATCH] D83079: [clang][aarch64] Generate preprocessor macros for -march=armv8.6a+sve.

2020-07-13 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:370
+  if (V8_6Pos != std::end(Features)) {
+V8_6Pos = Features.insert(std::next(V8_6Pos), "+i8mm");
+V8_6Pos = Features.insert(V8_6Pos, "+bf16");

Both `+i8mm` and `+bf16` should be added at iterator `V8_6Pos`, because I 
believe that `std::next(V8_6Pos)` inserts it after the item that follows 
`v8.6a`, rather than after `v8.6a` directly.


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[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

2020-07-13 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a comment.

In D83553#2145227 , @efriedma wrote:

> What's the tradeoff of representing these in IR as vscale'ed vector types, as 
> opposed to fixed-wdith vector types?

If you mean alloca's for single vectors, then that's partly to do with better 
test coverage of the stackframe layout with scalable vectors until we can start 
testing that with auto-vectorized code. Also, currently LLVM only implements 
the VL-scaled addressing modes for the scalable IR type and would otherwise 
always use base addressing mode if the type is fixed-width (`basereg = sp/fp + 
byteoffset; ld1 dstreg, [basereg, #0 mul VL]`), so until we add those smarts, 
code quality will probably be better.

Comment at: clang/lib/CodeGen/CGRecordLayoutBuilder.cpp:135
   llvm::Type *getStorageType(const FieldDecl *FD) {
-llvm::Type *Type = Types.ConvertTypeForMem(FD->getType());
+llvm::Type *Type = Types.ConvertTypeForMem(FD->getType(), false, true);
 if (!FD->isBitField()) return Type;

Can you add comments for the `false` and `true` parameters, e.g. 
`/*ForBitField*/ false, /*EnforceFixedLengthSVEAttribute*/ true`

Comment at: clang/lib/CodeGen/CodeGenModule.cpp:3731
   if (!Ty)
-Ty = getTypes().ConvertTypeForMem(ASTTy);
+Ty = getTypes().ConvertTypeForMem(ASTTy, false, true);

same here.

Comment at: clang/lib/CodeGen/CodeGenTypes.cpp:81
+llvm::Optional
+CodeGenTypes::getFixedSVETypeForMemory(const Type *T) {
+  unsigned VectorSize;

nit: `s/getFixedSVETypeForMemory/getFixedLengthSVETypeForMemory/`

Comment at: clang/lib/CodeGen/CodeGenTypes.cpp:94
+  case BuiltinType::SveUint8:
+  case BuiltinType::SveBool:
+MemEltTy = llvm::Type::getInt8Ty(Context);

Can you add a comment explaining why `SveBool` gets an `i8` element type for 
it's memory type?

Comment at: clang/lib/CodeGen/CodeGenTypes.h:137
   /// memory representation is usually i8 or i32, depending on the target.
-  llvm::Type *ConvertTypeForMem(QualType T, bool ForBitField = false);
+  llvm::Type *ConvertTypeForMem(QualType T, bool ForBitField = false,
+bool EnforceFixedLengthSVEAttribute = false);

Can you add a comment here to explain what EnforceFixedLengthSVEAttribute does?

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[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

2020-07-13 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/include/clang/Basic/Attr.td:1541
 
+def ArmSveVectorBits128 : TypeAttr {
+  let Spellings = [];

nit: Can you add a comment saying why these are undocumented (and have no 
spellings)



Comment at: clang/lib/AST/ASTContext.cpp:1872
 
+bool getSveVectorWidth(const Type *T, unsigned &Width) {
+  if (T->hasAttr(attr::ArmSveVectorBits128))

Should this function just return `unsigned` and error when it doesn't have any 
of the ArmSveVectorBits attributes?
i.e. if `isVLST()` returns true, then it is an error if it doesn't have any of 
the attributes handled below.



Comment at: clang/lib/AST/ASTContext.cpp:1897
+
+bool ASTContext::getArmSveVectorBits(const Type *T, unsigned &Width) const {
+  if (!T->isVLST())

nit: I find this name a bit misleading, because I would expect the 
(ARM_SVE_VECTOR_) bits to be the same regardless of the type. Maybe rename this 
to `getBitwidthForAttributedSveType` ?



Comment at: clang/lib/Sema/SemaType.cpp:7754
 /// the ACLE, such as svint32_t and svbool_t.
-static void HandleArmSveVectorBitsTypeAttr(QualType &CurType,
-   const ParsedAttr &Attr, Sema &S) {
+static void HandleArmSveVectorBitsTypeAttr(TypeProcessingState &State,
+   QualType &CurType,

Unrelated changes?



Comment at: clang/lib/Sema/SemaType.cpp:7839
+  default:
+llvm_unreachable("unsupported vector size!");
+  case 128:

If we only support power-of-two for now, we should only have an 
`llvm_unreachable` if we prevent parsing any of the other widths (and give an 
appropriate diagnostic saying those widths are not yet supported).



Comment at: clang/test/Sema/attr-arm-sve-vector-bits.c:45
+
+fixed_int8_t global_int8;
+fixed_bfloat16_t global_bfloat16;

nit: For the tests that you've added below, can you add more elaborate comments 
explaining what you're trying to test?
e.g. here I assume that sizeless globals are otherwise not allowed, but they 
are when attributed with arm_sve_vector_bits. It would be good to have that 
explained a bit.



Comment at: clang/test/Sema/attr-arm-sve-vector-bits.c:80
+  void *sel __attribute__((unused));
+  sel = c ? ss8 : fs8; // expected-error {{incompatible operand types 
('svint8_t' (aka '__SVInt8_t') and 'fixed_int8_t' (aka '__SVInt8_t'))}}
+  sel = c ? fs8 : ss8; // expected-error {{incompatible operand types 
('fixed_int8_t' (aka '__SVInt8_t') and 'svint8_t' (aka '__SVInt8_t'))}}

Is this diagnostic produced because of any code-changes in this patch?



Comment at: clang/test/Sema/attr-arm-sve-vector-bits.c:136
+
+struct struct_int8 { fixed_int8_t x, y[5]; };
+struct struct_int16 { fixed_int16_t x, y[5]; };

nit: Is it necessary to test this for all the types?



Comment at: clang/test/Sema/attr-arm-sve-vector-bits.c:206
+// --//
+// Test call
+

nit: s/Test call/Test the scalable and fixed-width annotated types can be used 
interchangeably/


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[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

2020-07-13 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:2806
+def err_attribute_bad_sve_vector_size : Error<
+  "unsupported SVE vector size '%0'">;
+def err_attribute_arm_feature_sve_bits_macro_not_defined : Error<

Do you want to be more specific in the wording here by saying that it doesn't 
match the value set by -msve-vector-bits?



Comment at: clang/lib/Sema/SemaType.cpp:7784
+  // The __ARM_FEATURE_SVE_BITS macro must be defined when using this 
attribute.
+  auto &PP = S.getPreprocessor();
+  if (!PP.isMacroDefined("__ARM_FEATURE_SVE_BITS")) {

I think that the code that checks if the value of the attribute matches the 
value set by -msve-vector-bits should be part of Sema, not the parser. Also I'm 
tempted to suggest decoupling the value of the macro from the code that checks 
the attribute-value matches -msve-vector-bits.

If the arm_sve.h header file defines a constant value like this:
```#if defined(__ARM_SVE_FEATURE_BITS)
const unsigned __arm_sve_feature_bits = __ARM_SVE_FEATURE_BITS
#endif```
You can check for the availability and value of this constant in the AST during 
semantic analysis. That way, if for whatever reason the value of the macro is 
redefined, the compiler can issue a diagnostic. Ideally we would insert a 
`__arm_sve_feature_bits` constant into the compilation unit directly when 
-msve-vector-bits is passed, but I don't know Clang enough to suggest where or 
at which point to add that.



Comment at: clang/lib/Sema/SemaType.cpp:7795
+  if (!MI)
+llvm_unreachable("Bad macro!");
+

Should this just be an `assert` instead? `MI` should never be nullptr if 
`isMacrodefined(..)` returns `true`.



Comment at: clang/lib/Sema/SemaType.cpp:7809
+S.Diag(Attr.getLoc(),
+   diag::err_attribute_arm_feature_sve_bits_macro_argument_type);
+Attr.setInvalid();

__ARM_FEATURE_SVE_BITS is never supposed to be set by the user, so the parsing 
and diagnostic can be simplified, e.g.
```if(MI->getNumTokens() != 1 || 
MI->tokens().front().isNot(tok::numeric_constant)) {
  S.Diag(Attr.getLoc(), diag::err_arm_feature_sve_bits_macro_broken)
  Attr.setInvalid();
  return;
}```
but this is probably no longer relevant if you implement the suggestion above 
on line 7784.



Comment at: clang/lib/Sema/SemaType.cpp:7815
+  // The attribute vector size must equal __ARM_FEATURE_SVE_BITS.
+  ExprResult ExprRes = S.ActOnNumericConstant(ArmFeatureSveBitsTok);
+  const auto *ArmSveFeatureBits = dyn_cast(ExprRes.get());

nit: `ExprRes` is not very descriptive, how about 
`ArmFeatureSveBitsMacroExprRes` ?



Comment at: clang/lib/Sema/SemaType.cpp:7818
+  unsigned VecSize = static_cast(SveVectorSizeInBits.getZExtValue());
+  if (ArmSveFeatureBits->getValue() != VecSize) {
+S.Diag(Attr.getLoc(), diag::err_attribute_bad_sve_vector_size) << VecSize;

`ArmSveFeatureBits` can be `nullptr`. Or it shouldn't use `dyn_cast`.



Comment at: clang/test/Sema/arm-feature-sve-bits-macro.c:1
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -fsyntax-only -verify 
-D__ARM_FEATURE_SVE_BITS=512 -D__ARM_FEATURE_SVE 
-fallow-half-arguments-and-returns %s
+

nit: `-D__ARM_FEATURE_SVE` is no longer necessary.


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[PATCH] D83079: [clang][aarch64] Generate preprocessor macros for -march=armv8.6a+sve.

2020-07-13 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:370
+  if (V8_6Pos != std::end(Features)) {
+V8_6Pos = Features.insert(std::next(V8_6Pos), "+i8mm");
+V8_6Pos = Features.insert(V8_6Pos, "+bf16");

sdesmalen wrote:
> Both `+i8mm` and `+bf16` should be added at iterator `V8_6Pos`, because I 
> believe that `std::next(V8_6Pos)` inserts it after the item that follows 
> `v8.6a`, rather than after `v8.6a` directly.
Never mind the above comment, you pointed out offline that `std::next` is 
correct because `insert` inserts the value before V8_6Pos, my bad!

Looking at the documentation for `std::vector::insert`, it seems you can write:
```if (V8_6Pos != std::end(Features))
  Features.insert(std::next(V8_6Pos), {"+bf16", "+i8mm"});```
which avoids having to update V8_6Pos.


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[PATCH] D83079: [clang][aarch64] Generate preprocessor macros for -march=armv8.6a+sve.

2020-07-13 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.

LGTM again!




Comment at: clang/test/Preprocessor/aarch64-target-features.c:163
+
+// RUN: %clang -target aarch64-none-linux-gnu 
-march=armv8.6-a+sve+noi8mm+nobf16+nof32mm -x c -E -dM %s -o - | FileCheck 
--check-prefix=CHECK-SVE-8_6-NOI8MMNOBF16NOF32MM %s
+// CHECK-SVE-8_6-NOI8MMNOBF16NOF32MM-NOT: __ARM_FEATURE_SVE_BF16 1

nit: I don't think you really need to test all permutations, one positive test 
(for `-march=armv8.6-a+sve`) and this negative test should be sufficient?


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[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

2020-07-14 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/include/clang/Basic/Attr.td:1541
 
+def ArmSveVectorBits128 : TypeAttr {
+  let Spellings = [];

aaron.ballman wrote:
> sdesmalen wrote:
> > nit: Can you add a comment saying why these are undocumented (and have no 
> > spellings)
> Also, I think these are all missing `let SemaHandler = 0;` and `let ASTNode = 
> 0;`
> 
> Is there a reason why we need N different type attributes instead of having a 
> single type attribute which encodes the N as an argument? I think this may 
> simplify the patch somewhat as you no longer need to switch over N as much.
> Is there a reason why we need N different type attributes instead of having a 
> single type attribute which encodes the N as an argument?
AIUI this was a workaround for getting the value of N from an AttributedType, 
because this only has `getAttrKind` to return the attribute kind, but no way to 
get the corresponding argument/value. This seemed like a simple way to do that 
without having to create a new subclass for Type and having to support that in 
various places. Is the latter the approach you were thinking of? (or is there 
perhaps a simpler way?)


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[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

2020-07-14 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/lib/Sema/SemaType.cpp:7784
+  // The __ARM_FEATURE_SVE_BITS macro must be defined when using this 
attribute.
+  auto &PP = S.getPreprocessor();
+  if (!PP.isMacroDefined("__ARM_FEATURE_SVE_BITS")) {

efriedma wrote:
> c-rhodes wrote:
> > sdesmalen wrote:
> > > I think that the code that checks if the value of the attribute matches 
> > > the value set by -msve-vector-bits should be part of Sema, not the 
> > > parser. Also I'm tempted to suggest decoupling the value of the macro 
> > > from the code that checks the attribute-value matches -msve-vector-bits.
> > > 
> > > If the arm_sve.h header file defines a constant value like this:
> > > ```#if defined(__ARM_SVE_FEATURE_BITS)
> > > const unsigned __arm_sve_feature_bits = __ARM_SVE_FEATURE_BITS
> > > #endif```
> > > You can check for the availability and value of this constant in the AST 
> > > during semantic analysis. That way, if for whatever reason the value of 
> > > the macro is redefined, the compiler can issue a diagnostic. Ideally we 
> > > would insert a `__arm_sve_feature_bits` constant into the compilation 
> > > unit directly when -msve-vector-bits is passed, but I don't know Clang 
> > > enough to suggest where or at which point to add that.
> > > I think that the code that checks if the value of the attribute matches 
> > > the value set by -msve-vector-bits should be part of Sema, not the parser.
> > This code which is checking `N==__ARM_FEATURE_SVE_BITS` is in Sema, maybe 
> > there's a more suitable place I'm not aware of but I think it makes sense 
> > to check this when looking at the type attribute.
> > 
> > > That way, if for whatever reason the value of the macro is redefined, the 
> > > compiler can issue a diagnostic. 
> > I'm not convinced having a constant in the header fixes that, I suspect the 
> > user could redefine that constant as they could the macro, e.g.:
> > ```void f() {
> >   const unsigned __arm_sve_feature_bits = 512;
> > }```
> > 
> > Ideally we want to diagnose inconsistent vector-lengths since we don't 
> > support it,  but for the time being maybe we can be explicit about what we 
> > do support and encourage users to use the `-msve-vector-bits` flag.
> > 
> > 
> I don't think it makes sense to try to parse the value of the 
> __ARM_FEATURE_SVE_BITS out of the macro.  The macro should be defined by the 
> compiler itself, so we should have the value stored somewhere else.
> This code which is checking N==__ARM_FEATURE_SVE_BITS is in Sema, maybe 
> there's a more suitable place I'm not aware of but I think it makes sense to 
> check this when looking at the type attribute.
You're right, I mistook this Sema function for parsing function, my bad.

> I'm not convinced having a constant in the header fixes that, I suspect the 
> user could redefine that constant as they could the macro, e.g.:
> ```void f() {
>   const unsigned __arm_sve_feature_bits = 512;
> }```
You can probably search for the value of `__arm_sve_feature_bits` at a global 
scope rather than the current scope. It could also be an internal state 
variable in Clang. As long as we don't have to rely on the value of the macro 
while we're parsing the file. I'm personally not too bothered if you want to do 
this in a separate patch while you're still implementing the feature, or if you 
want to update this patch, but it needs to get fixed because parsing the macro 
is the wrong way around.

> Ideally we want to diagnose inconsistent vector-lengths since we don't 
> support it, but for the time being maybe we can be explicit about what we do 
> support and encourage users to use the -msve-vector-bits flag.
When this feature is implemented, the `-msve-vector-bits` driver flag is the 
only interface to set the vector-length, any other way would be invalid.



Comment at: clang/lib/Sema/SemaType.cpp:7818
+  unsigned VecSize = static_cast(SveVectorSizeInBits.getZExtValue());
+  if (ArmSveFeatureBits->getValue() != VecSize) {
+S.Diag(Attr.getLoc(), diag::err_attribute_bad_sve_vector_size) << VecSize;

c-rhodes wrote:
> sdesmalen wrote:
> > `ArmSveFeatureBits` can be `nullptr`. Or it shouldn't use `dyn_cast`.
> I've added a check + diagnostic if it's a nullptr
Thanks.


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[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

2020-07-14 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added a comment.

In D83553#2148429 , @efriedma wrote:

> > If you mean alloca's for single vectors
>
> I was really referring to the IR values themselves, not the memory 
> representation.  Since the width of the vectors is known, you could emit IR 
> without any mention of scalable types at all (assuming the backend was 
> extended to handle the intrinsics).

That's right, the reason is because codegen of the intrinsics currently only 
works on scalable types. By casting the pointer to a vscale-pointer, all IR 
values are always scalable so we don't need to worry about doing things like 
reinterpet_cast from a scalable to fixed-width vector, or vice versa.

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[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

2020-07-15 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

Thanks for the changes @c-rhodes, the use of a LANGOPT for this makes sense to 
me.
With my nits addressed, I'm happy with the patch if @aaron.ballman is.




Comment at: clang/include/clang/Basic/AttrDocs.td:4861
+  let Content = [{
+The ``arm_sve_vector_bits(N)`` attribute is defined by the Arm C Language
+Extensions (ACLE) for SVE. It is used to define fixed-length (VLST) variants of

nit: Can you add a line here to state this feature is still WIP ? (we can 
remove that in a later patch)
I know this is implied by your comment re __ARM_FEATURE_SVE_BITS being defined, 
but I guess it's better to be explicit to avoid confusion.



Comment at: clang/lib/Basic/Targets/AArch64.cpp:381
+  if (Opts.ArmSveVectorBits)
+Builder.defineMacro("__ARM_FEATURE_SVE_BITS__EXPERIMENTAL",
+Twine(Opts.ArmSveVectorBits));

nit: 
`s/__ARM_FEATURE_SVE_BITS__EXPERIMENTAL/__ARM_FEATURE_SVE_BITS_EXPERIMENTAL/` ?



Comment at: clang/lib/Driver/ToolChains/Clang.cpp:1723
+const Driver &D = getToolChain().getDriver();
+if (!Val.equals("128") && !Val.equals("256") && !Val.equals("512") &&
+!Val.equals("1024") && !Val.equals("2048")) {

[feel free to ignore] I don't think it necessarily needs to be restricted to 
this set, it should be able to support any multiple of 128bits. Although if you 
want to limit it for the first implementation that's fine.



Comment at: clang/lib/Sema/SemaType.cpp:7733
   }
+
   // The number of elements must be an ICE.

nit: unrelated change.



Comment at: clang/lib/Sema/SemaType.cpp:7789
+  llvm::APSInt SveVectorSizeInBits(32);
+  if (!validIntegerConstantExpr(S, Attr, SveVectorSizeInBits))
+return;

nit: can you rename this function to something like 
`verifyValidIntegerConstantExpr` to make it clear that that function gives a 
diagnostic if it fails?



Comment at: clang/test/Sema/attr-arm-sve-vector-bits.c:1
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=128 
-fallow-half-arguments-and-returns %s

nit: Given that this test uses `-fsyntax-only`, can you do the same as you did 
for `clang/test/Driver/aarch64-sve-vector-bits.c` and remove 
`aarch64-registered-target` and `#include ` and do the tests on the 
builtin types instead? e.g.

```typedef __SVInt32_t svint32_t;
typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));```


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[PATCH] D82141: [sve][acle] Add SVE BFloat16 extensions.

2020-06-19 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/include/clang/Basic/arm_sve.td:494
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
+  def SVBFDOT   : SInst<"svbfdot[_{0}]",   "dd$$", "f", MergeNone, 
"aarch64_sve_bfdot">;
+  def SVBFMLALB : SInst<"svbfmlalb[_{0}]", "dd$$", "f", MergeNone, 
"aarch64_sve_bfmlalb">;

The types for these intrinsics are always `svfloat32_t` and `svbfloat16_t`, 
which given their semantics is unlikely to ever be extended to other types, so 
it's easier to make the LLVM IR non-overloaded (i.e. hardcoding 
`llvm_nxv4f32_ty` and `llvm_nxv8bf16_ty`) and using the `IsOverloadNone` flag 
for these builtins. Then you can express this builtin as:
```def SVBFDOT: SInst<"svbfdot[_{0}]",  "MMdd", "b", MergeNone, 
"aarch64_sve_bfdot">;```
and drop the need for the `$` modifier.



Comment at: clang/include/clang/Basic/arm_sve.td:498
+  def SVBFMMLA  : SInst<"svbfmmla[_{0}]",  "dd$$", "f", MergeNone, 
"aarch64_sve_bfmmla">;
+  def SVBFDOT_N   : SInst<"svbfdot[_n_{0}]",   "dd$~", "f", MergeNone, 
"aarch64_sve_bfdot">;
+  def SVBFMLAL_N  : SInst<"svbfmlalb[_n_{0}]", "dd$~", "f", MergeNone, 
"aarch64_sve_bfmlalb">;

Similar to the suggestion above to use `"MMdd"` for SVBFDOT, this could use 
`"MMda"` and you don't need the `~` modifier.

nit: add whitespace above this line.
nit: the rest of this file tries to align the columns, that makes this file a 
bit easier to read.



Comment at: clang/include/clang/Basic/arm_sve.td:1032
+  defm SVCVT_BF16_F32 : SInstCvtMXZ<"svcvt_bf16[_f32]", "ddPM", "dPM", "b",  
"aarch64_sve_cvt_bf16f32">;
+  // svcvtnt_bf16_f32
+  defm SVCVTNT_BF16_F32 : SInstCvtMX<"svcvtnt_bf16[_f32]", "ddPM", "dPM", "b", 
 "aarch64_sve_cvtnt_bf16f32">;

nit: redundant comment (same for above)



Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfdot.c:27
+
+svfloat32_t test_bfdot_lane_1_f32(svfloat32_t x, svbfloat16_t y, svbfloat16_t 
z) {
+  // CHECK-LABEL: @test_bfdot_lane_1_f32(

Testing the edge cases 0 and 3 should be sufficient. (same for all other cases 
in this patch)



Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1343
 
+class SVE_bfloat
+: Intrinsic<[llvm_anyvector_ty],

nit: `SVE_bfloat` is not very descriptive, maybe use `SVE_4Vec_BF16` and 
`SVE_4Vec_BF16_Indexed`?



Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1811
 
+def int_aarch64_sve_cvt_bf16f32 : Builtin_SVCVT<"svcvt_bf16_f32_m",   
llvm_nxv8bf16_ty, llvm_nxv8i1_ty, llvm_nxv4f32_ty>;
+def int_aarch64_sve_cvtnt_bf16f32   : Builtin_SVCVT<"svcvtnt_bf16_f32_m", 
llvm_nxv8bf16_ty, llvm_nxv8i1_ty, llvm_nxv4f32_ty>;

nit:  use `fcvtbf` instead of `cvt` => `int_aarch64_sve_fcvtbf_bf16f32` ?


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[PATCH] D82178: [AArch64][SVE] Guard svbfloat16_t with feature macro in ACLE

2020-06-19 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/utils/TableGen/SveEmitter.cpp:1091
+  OS << "#if defined(__ARM_FEATURE_SVE_BF16)\n";
+  OS << "typedef __SVBFloat16_t svbfloat16_t;\n";
+  OS << "#endif\n\n";

Can you also add an error if `__ARM_FEATURE_SVE_BF16` is defined, but 
`__ARM_FEATURE_BF16_SCALAR_ARITHMETIC` isn't?
something like:
```#ifndef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC must be defined when 
__ARM_FEATURE_SVE_BF16 is defined"
#endif
```


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[PATCH] D82187: [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores.

2020-06-19 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: stuij, efriedma, c-rhodes, fpetrogalli.
Herald added subscribers: llvm-commits, lldb-commits, cfe-commits, danielkiss, 
psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added projects: clang, LLDB, LLVM.
sdesmalen added a parent revision: D82178: [AArch64][SVE] Guard svbfloat16_t 
with feature macro in ACLE.

This patch contains:

- Support in LLVM CodeGen for bfloat16 types for ld2/3/4 and st2/3/4.
- New bfloat16 ACLE builtins for svld(2|3|4)[_vnum] and svst(2|3|4)[_vnum]


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Files:
  clang/include/clang/Basic/AArch64SVEACLETypes.def
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4-bfloat.c
  clang/utils/TableGen/SveEmitter.cpp
  lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll

Index: llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s 2>%t | FileCheck %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; WARN-NOT: warning
@@ -44,6 +44,17 @@
   ret void
 }
 
+define void @st2h_bf16( %v0,  %v1,  %pred, bfloat* %addr) {
+; CHECK-LABEL: st2h_bf16:
+; CHECK: st2h { z0.h, z1.h }, p0, [x0]
+; CHECK-NEXT: ret
+  call void @llvm.aarch64.sve.st2.nxv8bf16( %v0,
+   %v1,
+   %pred,
+  bfloat* %addr)
+  ret void
+}
+
 ;
 ; ST2W
 ;
@@ -140,6 +151,18 @@
   ret void
 }
 
+define void @st3h_bf16( %v0,  %v1,  %v2,  %pred, bfloat* %addr) {
+; CHECK-LABEL: st3h_bf16:
+; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0]
+; CHECK-NEXT: ret
+  call void @llvm.aarch64.sve.st3.nxv8bf16( %v0,
+   %v1,
+   %v2,
+   %pred,
+  bfloat* %addr)
+  ret void
+}
+
 ;
 ; ST3W
 ;
@@ -243,6 +266,19 @@
   ret void
 }
 
+define void @st4h_bf16( %v0,  %v1,  %v2,  %v3,  %pred, bfloat* %addr) {
+; CHECK-LABEL: st4h_bf16:
+; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
+; CHECK-NEXT: ret
+  call void @llvm.aarch64.sve.st4.nxv8bf16( %v0,
+   %v1,
+   %v2,
+   %v3,
+   %pred,
+  bfloat* %addr)
+  ret void
+}
+
 ;
 ; ST4W
 ;
@@ -395,6 +431,7 @@
 declare void @llvm.aarch64.sve.st2.nxv4i32(, , , i32*)
 declare void @llvm.aarch64.sve.st2.nxv2i64(, , , i64*)
 declare void @llvm.aarch64.sve.st2.nxv8f16(, , , half*)
+declare void @llvm.aarch64.sve.st2.nxv8bf16(, , , bfloat*)
 declare void @llvm.aarch64.sve.st2.nxv4f32(, , , float*)
 declare void @llvm.aarch64.sve.st2.nxv2f64(, , , double*)
 
@@ -403,6 +440,7 @@
 declare void @llvm.aarch64.sve.st3.nxv4i32(, , , , i32*)
 declare void @llvm.aarch64.sve.st3.nxv2i64(, , , , i64*)
 declare void @llvm.aarch64.sve.st3.nxv8f16(, , , , half*)
+declare void @llvm.aarch64.sve.st3.nxv8bf16(, , , , bfloat*)
 declare void @llvm.aarch64.sve.st3.nxv4f32(, , , , float*)
 declare void @llvm.aarch64.sve.st3.nxv2f64(, , , , double*)
 
@@ -411,6 +449,7 @@
 declare void @llvm.aarch64.sve.st4.nxv4i32(, , , , , i32*)
 declare void @llvm.aarch64.sve.st4.nxv2i64(, , , , , i64*)
 declare void @llvm.aarch64.sve.st4.nxv8f16(, , , , , half*)
+declare void @llvm.aarch64.sve.st4.nxv8bf16(, , , , , bfloat*)
 declare void @llvm.aarch64.sve.st4.nxv4f32(, , , , , float*)
 declare void @llvm.aarch64.sve.st4.nxv2f64(, , , , , double*)
 
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 -asm-verbose=0 < %s | FileCheck %s
 
 ;
 ; LD1RQB
@@ -284,6 +284,14 @@
   ret  %res
 }
 
+define  @ld2h_bf16( %pred

[PATCH] D82187: [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores.

2020-06-19 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen marked 2 inline comments as done.
sdesmalen added inline comments.



Comment at: clang/include/clang/Basic/AArch64SVEACLETypes.def:69
 
-SVE_VECTOR_TYPE("__SVBFloat16_t", "__SVBFloat16_t", SveBFloat16, 
SveBFloat16Ty, 8, 16, false, false, true)
+SVE_VECTOR_TYPE("__SVBFloat16_t", "__SVBFloat16_t", SveBFloat16, 
SveBFloat16Ty, 8, 16, true, false, true)
 

fpetrogalli wrote:
> Why did you have to set `IsFP = true`? Seems like an unrelated change?
It's more for consistency with the other definitions (svfloat16/svfloat32/..) 
but is otherwise a non-functional change.



Comment at: clang/utils/TableGen/SveEmitter.cpp:541
 Float = false;
+BFloat = false;
 ElementBitwidth /= 4;

fpetrogalli wrote:
> Are these needed? I don't understand the rule for when to be specific on the 
> values of these variables.
For this patch, it's needed for `'l'` because otherwise it will incorrectly 
assume the type is bfloat if the type specifier is `b`.
It similarly applies to all the other modifiers that are defined as being of 
type `integer`.


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[PATCH] D82141: [sve][acle] Add SVE BFloat16 extensions.

2020-06-22 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1345
+: Intrinsic<[llvm_nxv4f32_ty],
+[llvm_nxv4f32_ty,
+ llvm_nxv8bf16_ty,

nit: keep this on one line.


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[PATCH] D82141: [sve][acle] Add SVE BFloat16 extensions.

2020-06-22 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

LGTM




Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1811
 
+def int_aarch64_sve_cvt_bf16f32 : Builtin_SVCVT<"svcvt_bf16_f32_m",   
llvm_nxv8bf16_ty, llvm_nxv8i1_ty, llvm_nxv4f32_ty>;
+def int_aarch64_sve_cvtnt_bf16f32   : Builtin_SVCVT<"svcvtnt_bf16_f32_m", 
llvm_nxv8bf16_ty, llvm_nxv8i1_ty, llvm_nxv4f32_ty>;

fpetrogalli wrote:
> sdesmalen wrote:
> > nit:  use `fcvtbf` instead of `cvt` => `int_aarch64_sve_fcvtbf_bf16f32` ?
> Renamed to `int_aarch64_sve_fcvt_bf16f32` and 
> `int_aarch64_sve_fcvtnt_bf16f32` respectively, because I think it wouldn't 
> make sense to add the `bf` suffix to the `cvtnt` version of the intrinsic.
I meant to write `int_aarch64_sve_bfcvt_bf16f32`. This seems consistent with 
all other intrinsics (`fcvt`, `fcvtzu`, `scvtf`, etc.) that use the name of the 
instruction directly in the name of the intrinsic.


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[PATCH] D82187: [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores.

2020-06-22 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen updated this revision to Diff 272342.
sdesmalen added a comment.

- Updated RUN line in tests to fix test failures.


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Files:
  clang/include/clang/Basic/AArch64SVEACLETypes.def
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4-bfloat.c
  clang/utils/TableGen/SveEmitter.cpp
  lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll

Index: llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s 2>%t | FileCheck %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; WARN-NOT: warning
@@ -44,6 +44,17 @@
   ret void
 }
 
+define void @st2h_bf16( %v0,  %v1,  %pred, bfloat* %addr) {
+; CHECK-LABEL: st2h_bf16:
+; CHECK: st2h { z0.h, z1.h }, p0, [x0]
+; CHECK-NEXT: ret
+  call void @llvm.aarch64.sve.st2.nxv8bf16( %v0,
+   %v1,
+   %pred,
+  bfloat* %addr)
+  ret void
+}
+
 ;
 ; ST2W
 ;
@@ -140,6 +151,18 @@
   ret void
 }
 
+define void @st3h_bf16( %v0,  %v1,  %v2,  %pred, bfloat* %addr) {
+; CHECK-LABEL: st3h_bf16:
+; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0]
+; CHECK-NEXT: ret
+  call void @llvm.aarch64.sve.st3.nxv8bf16( %v0,
+   %v1,
+   %v2,
+   %pred,
+  bfloat* %addr)
+  ret void
+}
+
 ;
 ; ST3W
 ;
@@ -243,6 +266,19 @@
   ret void
 }
 
+define void @st4h_bf16( %v0,  %v1,  %v2,  %v3,  %pred, bfloat* %addr) {
+; CHECK-LABEL: st4h_bf16:
+; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
+; CHECK-NEXT: ret
+  call void @llvm.aarch64.sve.st4.nxv8bf16( %v0,
+   %v1,
+   %v2,
+   %v3,
+   %pred,
+  bfloat* %addr)
+  ret void
+}
+
 ;
 ; ST4W
 ;
@@ -395,6 +431,7 @@
 declare void @llvm.aarch64.sve.st2.nxv4i32(, , , i32*)
 declare void @llvm.aarch64.sve.st2.nxv2i64(, , , i64*)
 declare void @llvm.aarch64.sve.st2.nxv8f16(, , , half*)
+declare void @llvm.aarch64.sve.st2.nxv8bf16(, , , bfloat*)
 declare void @llvm.aarch64.sve.st2.nxv4f32(, , , float*)
 declare void @llvm.aarch64.sve.st2.nxv2f64(, , , double*)
 
@@ -403,6 +440,7 @@
 declare void @llvm.aarch64.sve.st3.nxv4i32(, , , , i32*)
 declare void @llvm.aarch64.sve.st3.nxv2i64(, , , , i64*)
 declare void @llvm.aarch64.sve.st3.nxv8f16(, , , , half*)
+declare void @llvm.aarch64.sve.st3.nxv8bf16(, , , , bfloat*)
 declare void @llvm.aarch64.sve.st3.nxv4f32(, , , , float*)
 declare void @llvm.aarch64.sve.st3.nxv2f64(, , , , double*)
 
@@ -411,6 +449,7 @@
 declare void @llvm.aarch64.sve.st4.nxv4i32(, , , , , i32*)
 declare void @llvm.aarch64.sve.st4.nxv2i64(, , , , , i64*)
 declare void @llvm.aarch64.sve.st4.nxv8f16(, , , , , half*)
+declare void @llvm.aarch64.sve.st4.nxv8bf16(, , , , , bfloat*)
 declare void @llvm.aarch64.sve.st4.nxv4f32(, , , , , float*)
 declare void @llvm.aarch64.sve.st4.nxv2f64(, , , , , double*)
 
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 -asm-verbose=0 < %s | FileCheck %s
 
 ;
 ; LD1RQB
@@ -284,6 +284,14 @@
   ret  %res
 }
 
+define  @ld2h_bf16( %pred, bfloat* %addr) {
+; CHECK-LABEL: ld2h_bf16:
+; CHECK: ld2h { z0.h, z1.h }, p0/z, [x0]
+; CHECK-NEXT: ret
+  %res = call  @llvm.aarch64.sve.ld2.nxv16bf16.nxv8i1.p0bf16( %pred, bfloat* %addr)
+  ret  %res
+}
+
 ;
 ; LD2W
 ;
@@ -356,6 +364,14 @@
   ret  %res
 }
 
+define  @ld3h_bf16( %pred, bfloat* %addr) {
+; CHECK-LABEL: ld3h_bf16:
+; CHECK: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0]
+; CHECK-NEXT

[PATCH] D82298: [AArch64][SVE] Add bfloat16 support to load intrinsics

2020-06-23 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1.c:2-4
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-o - %s >/dev/null 2>%t

david-arm wrote:
> fpetrogalli wrote:
> > With @sdesmalen  we where thinking that maybe it is better to duplicate the 
> > run lines to have the BF16 intrinsics tested separately:
> > 
> > ```
> >  RUN: %clang_cc1 -D__ARM_FEATURE_SVE  ... -target-feature +sve ...
> >  RUN: %clang_cc1 _DENABLE_BF16_TEST -D__ARM_FEATURE_SVE 
> > -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 ... 
> > -target-feature +sve -target-feature +bf16 ... 
> > ```
> > 
> > and wrap the BF16 tests in `#ifdef ENABLE_BF16_TEST ... #endif`.
> > 
> > this will make sure that the non BF16 tests will be erroneously associated 
> > to the BF16 flags.
> > 
> > Please apply these to all the run lines involving BF16 modified in this 
> > patch.
> > 
> Is that definite? I mean there is a difference between "we were thinking" and 
> "this is how we are going to do things in future". :) Just to avoid 
> unnecessary code changes that's all. I presume existing tests already written 
> in the same way (committed in last week or so) would be changed too?
The other bfloat test are currently in a separate file (suffixed `-bfloat.c`). 
@fpetrogalli and I indeed discussed we could do this all in the same file using 
`#ifdef`s, but for now I'd actually prefer we stick with the approach we have 
gone down (specific test file for bfloat) until we've changed this for existing 
tests (in a separate patch).

So for now just move these tests to a separate file and please also add RUN 
lines like we've done for the SVE2 tests to check that we get diagnostics if 
`+sve` is passed (without `+bf16`).
(This actually hasn't been done yet for some of the newly introduced bfloat 
tests, so we'll need to fix that)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82298/new/

https://reviews.llvm.org/D82298



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[PATCH] D82182: [AArch64][SVE] Add bfloat16 support to perm and select intrinsics

2020-06-23 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen added inline comments.



Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c:2
 // REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu 
-target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple 
aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu 
-target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o 
- %s >/dev/null 2>%t
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s

Can you move the clang bfloat tests to separate files and add a RUN line 
similar to what we've done for the sve2 tests (to check that we get a 
diagnostic if +bf16 is not specified) ?


Repository:
  rG LLVM Github Monorepo

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[PATCH] D82187: [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores.

2020-06-23 Thread Sander de Smalen via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG121e585ec8aa: [AArch64][SVE] ACLE: Add bfloat16 to struct 
load/stores. (authored by sdesmalen).

Changed prior to commit:
  https://reviews.llvm.org/D82187?vs=272342&id=272678#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82187/new/

https://reviews.llvm.org/D82187

Files:
  clang/include/clang/Basic/AArch64SVEACLETypes.def
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4-bfloat.c
  clang/utils/TableGen/SveEmitter.cpp
  lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll

Index: llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s 2>%t | FileCheck %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; WARN-NOT: warning
@@ -44,6 +44,17 @@
   ret void
 }
 
+define void @st2h_bf16( %v0,  %v1,  %pred, bfloat* %addr) {
+; CHECK-LABEL: st2h_bf16:
+; CHECK: st2h { z0.h, z1.h }, p0, [x0]
+; CHECK-NEXT: ret
+  call void @llvm.aarch64.sve.st2.nxv8bf16( %v0,
+   %v1,
+   %pred,
+  bfloat* %addr)
+  ret void
+}
+
 ;
 ; ST2W
 ;
@@ -140,6 +151,18 @@
   ret void
 }
 
+define void @st3h_bf16( %v0,  %v1,  %v2,  %pred, bfloat* %addr) {
+; CHECK-LABEL: st3h_bf16:
+; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0]
+; CHECK-NEXT: ret
+  call void @llvm.aarch64.sve.st3.nxv8bf16( %v0,
+   %v1,
+   %v2,
+   %pred,
+  bfloat* %addr)
+  ret void
+}
+
 ;
 ; ST3W
 ;
@@ -243,6 +266,19 @@
   ret void
 }
 
+define void @st4h_bf16( %v0,  %v1,  %v2,  %v3,  %pred, bfloat* %addr) {
+; CHECK-LABEL: st4h_bf16:
+; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
+; CHECK-NEXT: ret
+  call void @llvm.aarch64.sve.st4.nxv8bf16( %v0,
+   %v1,
+   %v2,
+   %v3,
+   %pred,
+  bfloat* %addr)
+  ret void
+}
+
 ;
 ; ST4W
 ;
@@ -395,6 +431,7 @@
 declare void @llvm.aarch64.sve.st2.nxv4i32(, , , i32*)
 declare void @llvm.aarch64.sve.st2.nxv2i64(, , , i64*)
 declare void @llvm.aarch64.sve.st2.nxv8f16(, , , half*)
+declare void @llvm.aarch64.sve.st2.nxv8bf16(, , , bfloat*)
 declare void @llvm.aarch64.sve.st2.nxv4f32(, , , float*)
 declare void @llvm.aarch64.sve.st2.nxv2f64(, , , double*)
 
@@ -403,6 +440,7 @@
 declare void @llvm.aarch64.sve.st3.nxv4i32(, , , , i32*)
 declare void @llvm.aarch64.sve.st3.nxv2i64(, , , , i64*)
 declare void @llvm.aarch64.sve.st3.nxv8f16(, , , , half*)
+declare void @llvm.aarch64.sve.st3.nxv8bf16(, , , , bfloat*)
 declare void @llvm.aarch64.sve.st3.nxv4f32(, , , , float*)
 declare void @llvm.aarch64.sve.st3.nxv2f64(, , , , double*)
 
@@ -411,6 +449,7 @@
 declare void @llvm.aarch64.sve.st4.nxv4i32(, , , , , i32*)
 declare void @llvm.aarch64.sve.st4.nxv2i64(, , , , , i64*)
 declare void @llvm.aarch64.sve.st4.nxv8f16(, , , , , half*)
+declare void @llvm.aarch64.sve.st4.nxv8bf16(, , , , , bfloat*)
 declare void @llvm.aarch64.sve.st4.nxv4f32(, , , , , float*)
 declare void @llvm.aarch64.sve.st4.nxv2f64(, , , , , double*)
 
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 -asm-verbose=0 < %s | FileCheck %s
 
 ;
 ; LD1RQB
@@ -284,6 +284,14 @@
   ret  %res
 }
 
+define  @ld2h_bf16( %pred, bfloat* %addr) {
+; CHECK-LABEL: ld2h_bf16:
+; CHECK: ld2h { z0.h, z1.h }, p0/z, [x0]
+; CHECK-NEXT: ret
+  %res = call  @llvm.aarch64.sve.ld2.nxv16bf16.nxv8i1.p0bf16( %pred, bfloat* %addr)
+  ret  %res
+}
+

[PATCH] D82369: [SveEmitter] Add verify-checks to Clang bfloat16 tests

2020-06-23 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen created this revision.
sdesmalen added reviewers: c-rhodes, fpetrogalli, kmclaughlin.
Herald added a subscriber: tschuett.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82369

Files:
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfdot.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalb.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalt.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmmla.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvtnt.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4-bfloat.c

Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4-bfloat.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4-bfloat.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4-bfloat.c
@@ -1,5 +1,9 @@
 // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
 // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+
+// expected-error@arm_bf16.h:* {{__bf16 is not supported on this target}}
+// expected-error@arm_sve.h:*  {{__bf16 is not supported on this target}}
 
 #include 
 
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3-bfloat.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3-bfloat.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3-bfloat.c
@@ -1,5 +1,9 @@
 // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
 // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+
+// expected-error@arm_bf16.h:* {{__bf16 is not supported on this target}}
+// expected-error@arm_sve.h:*  {{__bf16 is not supported on this target}}
 
 #include 
 
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2-bfloat.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2-bfloat.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2-bfloat.c
@@ -1,5 +1,9 @@
 // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
 // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+
+// expected-error@arm_bf16.h:* {{__bf16 is not supported on this target}}
+// expected-error@arm_sve.h:*  {{__bf16 is not supported on this target}}
 
 #include 
 
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4-bfloat.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4-bfloat.c
+++ clan

[PATCH] D82298: [AArch64][SVE] Add bfloat16 support to load intrinsics

2020-06-24 Thread Sander de Smalen via Phabricator via cfe-commits

sdesmalen accepted this revision.
sdesmalen added a comment.

LGTM




Comment at: clang/include/clang/Basic/arm_sve.td:275
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
+  def SVLD1_BF  : MInst<"svld1[_{2}]",  "dPc",  "b", [IsLoad], 
MemEltTyDefault, "aarch64_sve_ld1">;
+  def SVLD1_VNUM_BF : MInst<"svld1_vnum[_{2}]", "dPcl", "b", [IsLoad], 
MemEltTyDefault, "aarch64_sve_ld1">;

micro nit: doesn't match column indentation of the code around it.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82298/new/

https://reviews.llvm.org/D82298



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