[PATCH] D82576: [PowerPC][Power10] Implement low-order Vector Modulus Builtins, and add Vector Multiply/Divide/Modulus Builtins Tests
bsaleil accepted this revision. bsaleil added a comment. This revision is now accepted and ready to land. Thanks for the explanation. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82576/new/ https://reviews.llvm.org/D82576 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D83722: [PowerPC] Add options to control paired vector memops support
bsaleil updated this revision to Diff 279341.
bsaleil added a comment.
Add PairedVectorMemops to the list of unsupported features in a comment
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D83722/new/
https://reviews.llvm.org/D83722
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-dependent-options.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/test/CodeGen/PowerPC/future-check-features.ll
Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,9 +1,9 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
-; RUN: -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \
-; RUN: %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
-; RUN: -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \
-; RUN: %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
define dso_local signext i32 @f() {
entry:
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -146,6 +146,7 @@
bool VectorsUseTwoUnits;
bool UsePPCPreRASchedStrategy;
bool UsePPCPostRASchedStrategy;
+ bool PairedVectorMemops;
bool PredictableSelectIsExpensive;
POPCNTDKind HasPOPCNTD;
@@ -266,6 +267,7 @@
bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
+ bool pairedVectorMemops() const { return PairedVectorMemops; }
bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; }
bool hasBPERMD() const { return HasBPERMD; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -122,6 +122,7 @@
VectorsUseTwoUnits = false;
UsePPCPreRASchedStrategy = false;
UsePPCPostRASchedStrategy = false;
+ PairedVectorMemops = false;
PredictableSelectIsExpensive = false;
HasPOPCNTD = POPCNTD_Unavailable;
Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td
===
--- llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -41,10 +41,10 @@
let CompleteModel = 1;
// Do not support QPX (Quad Processing eXtension), SPE (Signal Processing
- // Engine), prefixed instructions on Power 9, PC relative mem ops, or
- // instructions introduced in ISA 3.1.
- let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PCRelativeMemops,
- IsISA3_1];
+ // Engine), prefixed instructions on Power 9, paired vector mem ops,
+ // PC relative mem ops, or instructions introduced in ISA 3.1.
+ let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PairedVectorMemops,
+ PCRelativeMemops, IsISA3_1];
}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -454,6 +454,7 @@
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
+def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -237,6 +237,10 @@
SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
"Enable PC relative Memory Ops",
[FeatureISA3_0]>;
+def FeaturePairedVectorMemops:
+ SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
+ "32Byte load and store instructions",
+ [FeatureISA3_0]>;
def FeaturePredictableSe
[PATCH] D83722: [PowerPC] Add options to control paired vector memops support
bsaleil marked an inline comment as done. bsaleil added inline comments. Comment at: llvm/lib/Target/PowerPC/PPC.td:243 + "32Byte load and store instructions", + [FeatureISA3_0]>; amyk wrote: > Is this supposed to be `FeatureISA3_1`? We need to keep `FeatureISA3_0` to be able to enable MMA (that depends on this feature) with P9 codegen. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83722/new/ https://reviews.llvm.org/D83722 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D83722: [PowerPC] Add options to control paired vector memops support
bsaleil updated this revision to Diff 281341.
bsaleil added a comment.
Update diff so it can be applied to master
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D83722/new/
https://reviews.llvm.org/D83722
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-dependent-options.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/test/CodeGen/PowerPC/future-check-features.ll
Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,9 +1,9 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
-; RUN: -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \
-; RUN: %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
-; RUN: -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \
-; RUN: %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
define dso_local signext i32 @f() {
entry:
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -145,6 +145,7 @@
bool VectorsUseTwoUnits;
bool UsePPCPreRASchedStrategy;
bool UsePPCPostRASchedStrategy;
+ bool PairedVectorMemops;
bool PredictableSelectIsExpensive;
POPCNTDKind HasPOPCNTD;
@@ -259,6 +260,7 @@
bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
+ bool pairedVectorMemops() const { return PairedVectorMemops; }
bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; }
bool hasBPERMD() const { return HasBPERMD; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -116,6 +116,7 @@
VectorsUseTwoUnits = false;
UsePPCPreRASchedStrategy = false;
UsePPCPostRASchedStrategy = false;
+ PairedVectorMemops = false;
PredictableSelectIsExpensive = false;
HasPOPCNTD = POPCNTD_Unavailable;
Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td
===
--- llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -41,8 +41,10 @@
let CompleteModel = 1;
// Do not support SPE (Signal Processing Engine), prefixed instructions on
- // Power 9, PC relative mem ops, or instructions introduced in ISA 3.1.
- let UnsupportedFeatures = [HasSPE, PrefixInstrs, PCRelativeMemops, IsISA3_1];
+ // Power 9, paired vector mem ops, PC relative mem ops, or instructions
+ // introduced in ISA 3.1.
+ let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops,
+ PCRelativeMemops, IsISA3_1];
}
let SchedModel = P9Model in {
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -454,6 +454,7 @@
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
+def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -234,6 +234,10 @@
SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
"Enable PC relative Memory Ops",
[FeatureISA3_0]>;
+def FeaturePairedVectorMemops:
+ SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
+ "32Byte load and store instructions",
+ [FeatureISA3_0]>;
def FeaturePredictableSelectIsExpensive :
SubtargetFeature<"predictable-select-expensive",
@@ -339,7 +343,7 @@
// still exist with the exc
[PATCH] D81442: [PowerPC] Add clang options to control MMA support
bsaleil updated this revision to Diff 281381.
bsaleil added a comment.
Update diff so it can be applied to master.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81442/new/
https://reviews.llvm.org/D81442
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-dependent-options.cpp
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/test/CodeGen/PowerPC/future-check-features.ll
Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \
; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \
; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -107,6 +107,7 @@
bool HasP10Vector;
bool HasPrefixInstrs;
bool HasPCRelativeMemops;
+ bool HasMMA;
bool HasFCPSGN;
bool HasFSQRT;
bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
@@ -260,6 +261,7 @@
bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
+ bool hasMMA() const { return HasMMA; }
bool pairedVectorMemops() const { return PairedVectorMemops; }
bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -73,6 +73,7 @@
HasP8Crypto = false;
HasP9Vector = false;
HasP9Altivec = false;
+ HasMMA = false;
HasP10Vector = false;
HasPrefixInstrs = false;
HasPCRelativeMemops = false;
Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td
===
--- llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -41,9 +41,9 @@
let CompleteModel = 1;
// Do not support SPE (Signal Processing Engine), prefixed instructions on
- // Power 9, paired vector mem ops, PC relative mem ops, or instructions
+ // Power 9, paired vector mem ops, MMA, PC relative mem ops, or instructions
// introduced in ISA 3.1.
- let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops,
+ let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops, MMA,
PCRelativeMemops, IsISA3_1];
}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -455,6 +455,7 @@
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
+def MMA : Predicate<"PPCSubTarget->hasMMA()">;
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -238,6 +238,10 @@
SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
"32Byte load and store instructions",
[FeatureISA3_0]>;
+def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",
+ "Enable MMA instructions",
+ [FeatureP8Vector, FeatureP9Altivec,
+ FeaturePairedVectorMemops]>;
def FeaturePredictableSelectIsExpensive :
SubtargetFeature<"predictable-select-expensive",
@@ -343,7 +347,8 @@
// still exist with the exception of those we know are Power9 specific.
list P10AdditionalFeatures =
[DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
- FeaturePCRelativeMemops, FeatureP10Vector, FeaturePairedVecto
[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend
bsaleil added inline comments.
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:939
+ // The XFormMemOp flag for the following 8 insts is set on the instruction
format.
+ let mayLoad = 1, mayStore = 1 in {
+def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>;
Shouldn't `mayStore` be 0 instead of 1 here ?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D83364/new/
https://reviews.llvm.org/D83364
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[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins
bsaleil added a comment. Shouldn't we have test cases to test `vec_sl`, `vec_sr` and `vec_sra` ? Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:800 def int_ppc_altivec_vsrw : PowerPC_Vec_WWW_Intrinsic<"vsrw">; +def int_ppc_altivec_vsrq : PowerPC_Vec_QQQ_Intrinsic<"vsrq">; def int_ppc_altivec_vsrab : PowerPC_Vec_BBB_Intrinsic<"vsrab">; nit: indentation issue Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:919 + + def VSLQ : VX1_Int_Ty< 261, "vslq", int_ppc_altivec_vslq, v1i128>; + def VSRAQ : VX1_Int_Ty< 773, "vsraq", int_ppc_altivec_vsraq, v1i128>; nit: extra spaces before `:` here and in the next two lines Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83338/new/ https://reviews.llvm.org/D83338 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D81442: [PowerPC] Add clang options to control MMA support
bsaleil updated this revision to Diff 277466.
Herald added a subscriber: dang.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81442/new/
https://reviews.llvm.org/D81442
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-dependent-options.cpp
clang/test/Preprocessor/init-ppc64.c
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -643,6 +643,7 @@
// PPCPOWER10:#define _ARCH_PWR7 1
// PPCPOWER10:#define _ARCH_PWR8 1
// PPCPOWER10:#define _ARCH_PWR9 1
+// PPCPOWER10:#define __MMA__ 1
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s
//
@@ -660,6 +661,10 @@
// PPCFUTURE:#define _ARCH_PWR8 1
// PPCFUTURE:#define _ARCH_PWR9 1
// PPCFUTURE:#define _ARCH_PWR_FUTURE 1
+// PPCFUTURE:#define __MMA__ 1
+//
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s
+// PPC-MMA:#define __MMA__ 1
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
// PPC-FLOAT128:#define __FLOAT128__ 1
Index: clang/test/Driver/ppc-dependent-options.cpp
===
--- clang/test/Driver/ppc-dependent-options.cpp
+++ clang/test/Driver/ppc-dependent-options.cpp
@@ -63,6 +63,14 @@
// RUN: -check-prefix=CHECK-DEFAULT-P10
// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mmma %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MMA
+
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=future -std=c++11 -mno-vsx -mmma %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MMA
+
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mpower10-vector %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-P10V
@@ -98,5 +106,6 @@
// CHECK-NVSX-DMV: error: option '-mdirect-move' cannot be specified with '-mno-vsx'
// CHECK-NVSX-MULTI: error: option '-mfloat128' cannot be specified with '-mno-vsx'
// CHECK-NVSX-MULTI: error: option '-mpower9-vector' cannot be specified with '-mno-vsx'
+// CHECK-NVSX-MMA: error: option '-mmma' cannot be specified with '-mno-vsx'
// CHECK-NVSX: Neither enabled
// CHECK-VSX: VSX enabled
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -59,6 +59,7 @@
// Target cpu features.
bool HasAltivec = false;
+ bool HasMMA = false;
bool HasVSX = false;
bool HasP8Vector = false;
bool HasP8Crypto = false;
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -64,6 +64,8 @@
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
} else if (Feature == "-hard-float") {
FloatABI = SoftFloat;
+} else if (Feature == "+mma") {
+ HasMMA = true;
}
// TODO: Finish this list and add an assert that we've handled them
// all.
@@ -195,6 +197,8 @@
Builder.defineMacro("__FLOAT128__");
if (HasP9Vector)
Builder.defineMacro("__POWER9_VECTOR__");
+ if (HasMMA)
+Builder.defineMacro("__MMA__");
if (HasP10Vector)
Builder.defineMacro("__POWER10_VECTOR__");
@@ -231,6 +235,7 @@
// - direct-move
// - float128
// - power9-vector
+// - mma
// - power10-vector
// then go ahead and error since the customer has expressed an incompatible
// set of options.
@@ -253,6 +258,7 @@
Found |= FindVSXSubfeature("+direct-move", "-mdirect-move");
Found |= FindVSXSubfeature("+float128", "-mfloat128");
Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector");
+ Found |= FindVSXSubfeature("+mma", "-mmma");
Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector");
// Return false if any vsx subfeatures was found.
@@ -354,6 +360,7 @@
void PPCTargetInfo::addP10SpecificFeatures(
llvm::StringMap &Features) const {
Features["htm"] = false; // HTM was removed for P10.
+ Features["mma"] = true;
Features["power10-vector"] = true;
Features["pcrelative-memops"] = true;
return;
@@ -382,6 +389,7 @@
.Case("power10-vector", HasP10Vector)
.Case("pcrelative-memops", HasPCRelativeMemops)
.Case("spe", HasSPE)
+ .Case("mma", HasMMA)
.Default(false);
}
@@ -397,6 +405,7 @@
[PATCH] D83722: [PowerPC] Add options to control paired vector memops support
bsaleil created this revision.
bsaleil added reviewers: PowerPC, power-llvm-team, nemanjai, lei, saghir, amyk,
stefanp.
bsaleil added projects: LLVM, clang, PowerPC.
Herald added subscribers: llvm-commits, cfe-commits, dang, steven.zhang,
shchenz, hiraditya.
This patch adds frontend and backend options to enable and disable the PowerPC
paired vector memory operations added in ISA 3.1.
Instructions using these options will be added in subsequent patches.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D83722
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-dependent-options.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -146,6 +146,7 @@
bool VectorsUseTwoUnits;
bool UsePPCPreRASchedStrategy;
bool UsePPCPostRASchedStrategy;
+ bool PairedVectorMemops;
bool PredictableSelectIsExpensive;
POPCNTDKind HasPOPCNTD;
@@ -266,6 +267,7 @@
bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
+ bool pairedVectorMemops() const { return PairedVectorMemops; }
bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; }
bool hasBPERMD() const { return HasBPERMD; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -122,6 +122,7 @@
VectorsUseTwoUnits = false;
UsePPCPreRASchedStrategy = false;
UsePPCPostRASchedStrategy = false;
+ PairedVectorMemops = false;
PredictableSelectIsExpensive = false;
HasPOPCNTD = POPCNTD_Unavailable;
Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td
===
--- llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -43,8 +43,8 @@
// Do not support QPX (Quad Processing eXtension), SPE (Signal Processing
// Engine), prefixed instructions on Power 9, PC relative mem ops, or
// instructions introduced in ISA 3.1.
- let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PCRelativeMemops,
- IsISA3_1];
+ let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PairedVectorMemops,
+ PCRelativeMemops, IsISA3_1];
}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -427,6 +427,7 @@
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
+def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -237,6 +237,10 @@
SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
"Enable PC relative Memory Ops",
[FeatureISA3_0]>;
+def FeaturePairedVectorMemops:
+ SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
+ "32Byte load and store instructions",
+ [FeatureISA3_0]>;
def FeaturePredictableSelectIsExpensive :
SubtargetFeature<"predictable-select-expensive",
@@ -342,7 +346,7 @@
// still exist with the exception of those we know are Power9 specific.
list P10AdditionalFeatures =
[DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
- FeaturePCRelativeMemops, FeatureP10Vector];
+ FeaturePCRelativeMemops, FeatureP10Vector, FeaturePairedVectorMemops];
list P10SpecificFeatures = [];
list P10InheritableFeatures =
!listconcat(P9InheritableFeatures, P10AdditionalFeatures);
Index: clang/test/Driver/ppc-dependent-options.cpp
===
--- clang/test/Driver/ppc-dependent-options.cpp
+++ clang/test/Driver/ppc-dependent-options.cpp
@@ -55,6 +55,10 @@
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-FLT128
// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mpaired-vector-memops %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-PAIRED-VEC-MEMOPS
+
+// RUN: not %clang -target po
[PATCH] D81442: [PowerPC] Add clang options to control MMA support
bsaleil updated this revision to Diff 277580.
bsaleil added a comment.
Herald added subscribers: llvm-commits, hiraditya.
Also add target options with this patch
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81442/new/
https://reviews.llvm.org/D81442
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-dependent-options.cpp
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -108,6 +108,7 @@
bool HasP10Vector;
bool HasPrefixInstrs;
bool HasPCRelativeMemops;
+ bool HasMMA;
bool HasFCPSGN;
bool HasFSQRT;
bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
@@ -267,6 +268,7 @@
bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
+ bool hasMMA() const { return HasMMA; }
bool pairedVectorMemops() const { return PairedVectorMemops; }
bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -78,6 +78,7 @@
HasP8Crypto = false;
HasP9Vector = false;
HasP9Altivec = false;
+ HasMMA = false;
HasP10Vector = false;
HasPrefixInstrs = false;
HasPCRelativeMemops = false;
Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td
===
--- llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -43,8 +43,8 @@
// Do not support QPX (Quad Processing eXtension), SPE (Signal Processing
// Engine), prefixed instructions on Power 9, PC relative mem ops, or
// instructions introduced in ISA 3.1.
- let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PairedVectorMemops,
- PCRelativeMemops, IsISA3_1];
+ let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, MMA,
+ PairedVectorMemops, PCRelativeMemops, IsISA3_1];
}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -428,6 +428,7 @@
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
+def MMA : Predicate<"PPCSubTarget->hasMMA()">;
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -241,6 +241,10 @@
SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
"32Byte load and store instructions",
[FeatureISA3_0]>;
+def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",
+ "Enable MMA instructions",
+ [FeatureP8Vector, FeatureP9Altivec,
+ FeaturePairedVectorMemops]>;
def FeaturePredictableSelectIsExpensive :
SubtargetFeature<"predictable-select-expensive",
@@ -346,7 +350,8 @@
// still exist with the exception of those we know are Power9 specific.
list P10AdditionalFeatures =
[DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
- FeaturePCRelativeMemops, FeatureP10Vector, FeaturePairedVectorMemops];
+ FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
+ FeaturePairedVectorMemops];
list P10SpecificFeatures = [];
list P10InheritableFeatures =
!listconcat(P9InheritableFeatures, P10AdditionalFeatures);
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -643,6 +643,7 @@
// PPCPOWER10:#define _ARCH_PWR7 1
// PPCPOWER10:#define _ARCH_PWR8 1
// PPCPOWER10:#define _ARCH_PWR9 1
+// PPCPOWER10:#define __MMA__ 1
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s
//
@@ -660,6 +661,10 @@
// PPCFUTURE:#define _ARCH_PWR8 1
// PPCFUTURE:#defi
[PATCH] D83497: [PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.
bsaleil accepted this revision as: bsaleil. bsaleil added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83497/new/ https://reviews.llvm.org/D83497 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D83722: [PowerPC] Add options to control paired vector memops support
bsaleil updated this revision to Diff 277838.
bsaleil added a comment.
Re-upload with surrounding context
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D83722/new/
https://reviews.llvm.org/D83722
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-dependent-options.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -146,6 +146,7 @@
bool VectorsUseTwoUnits;
bool UsePPCPreRASchedStrategy;
bool UsePPCPostRASchedStrategy;
+ bool PairedVectorMemops;
bool PredictableSelectIsExpensive;
POPCNTDKind HasPOPCNTD;
@@ -266,6 +267,7 @@
bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
+ bool pairedVectorMemops() const { return PairedVectorMemops; }
bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; }
bool hasBPERMD() const { return HasBPERMD; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -122,6 +122,7 @@
VectorsUseTwoUnits = false;
UsePPCPreRASchedStrategy = false;
UsePPCPostRASchedStrategy = false;
+ PairedVectorMemops = false;
PredictableSelectIsExpensive = false;
HasPOPCNTD = POPCNTD_Unavailable;
Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td
===
--- llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -43,8 +43,8 @@
// Do not support QPX (Quad Processing eXtension), SPE (Signal Processing
// Engine), prefixed instructions on Power 9, PC relative mem ops, or
// instructions introduced in ISA 3.1.
- let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PCRelativeMemops,
- IsISA3_1];
+ let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PairedVectorMemops,
+ PCRelativeMemops, IsISA3_1];
}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -427,6 +427,7 @@
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
+def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -237,6 +237,10 @@
SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
"Enable PC relative Memory Ops",
[FeatureISA3_0]>;
+def FeaturePairedVectorMemops:
+ SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
+ "32Byte load and store instructions",
+ [FeatureISA3_0]>;
def FeaturePredictableSelectIsExpensive :
SubtargetFeature<"predictable-select-expensive",
@@ -342,7 +346,7 @@
// still exist with the exception of those we know are Power9 specific.
list P10AdditionalFeatures =
[DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
- FeaturePCRelativeMemops, FeatureP10Vector];
+ FeaturePCRelativeMemops, FeatureP10Vector, FeaturePairedVectorMemops];
list P10SpecificFeatures = [];
list P10InheritableFeatures =
!listconcat(P9InheritableFeatures, P10AdditionalFeatures);
Index: clang/test/Driver/ppc-dependent-options.cpp
===
--- clang/test/Driver/ppc-dependent-options.cpp
+++ clang/test/Driver/ppc-dependent-options.cpp
@@ -55,6 +55,10 @@
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-FLT128
// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mpaired-vector-memops %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-PAIRED-VEC-MEMOPS
+
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MULTI
@@ -96,6 +100,7 @@
// CHECK-NVSX-P10V: error: option '-mpower10-vector' cannot be specified with '-mno-vsx'
/
[PATCH] D83722: [PowerPC] Add options to control paired vector memops support
bsaleil updated this revision to Diff 277847.
bsaleil added a comment.
Add test to check `paired-vector-memops` is supported by the targets.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D83722/new/
https://reviews.llvm.org/D83722
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-dependent-options.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/test/CodeGen/PowerPC/future-check-features.ll
Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,9 +1,9 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
-; RUN: -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \
-; RUN: %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
-; RUN: -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \
-; RUN: %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
+; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
define dso_local signext i32 @f() {
entry:
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -146,6 +146,7 @@
bool VectorsUseTwoUnits;
bool UsePPCPreRASchedStrategy;
bool UsePPCPostRASchedStrategy;
+ bool PairedVectorMemops;
bool PredictableSelectIsExpensive;
POPCNTDKind HasPOPCNTD;
@@ -266,6 +267,7 @@
bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
+ bool pairedVectorMemops() const { return PairedVectorMemops; }
bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; }
bool hasBPERMD() const { return HasBPERMD; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -122,6 +122,7 @@
VectorsUseTwoUnits = false;
UsePPCPreRASchedStrategy = false;
UsePPCPostRASchedStrategy = false;
+ PairedVectorMemops = false;
PredictableSelectIsExpensive = false;
HasPOPCNTD = POPCNTD_Unavailable;
Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td
===
--- llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -43,8 +43,8 @@
// Do not support QPX (Quad Processing eXtension), SPE (Signal Processing
// Engine), prefixed instructions on Power 9, PC relative mem ops, or
// instructions introduced in ISA 3.1.
- let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PCRelativeMemops,
- IsISA3_1];
+ let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PairedVectorMemops,
+ PCRelativeMemops, IsISA3_1];
}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -427,6 +427,7 @@
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
+def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -237,6 +237,10 @@
SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
"Enable PC relative Memory Ops",
[FeatureISA3_0]>;
+def FeaturePairedVectorMemops:
+ SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
+ "32Byte load and store instructions",
+ [FeatureISA3_0]>;
def FeaturePredictableSelectIsExpensive :
SubtargetFeature<"predictable-select-expensive",
@@ -342,7 +346,7 @@
// still exist with the exception of those we know are Power9 specific.
li
[PATCH] D81442: [PowerPC] Add clang options to control MMA support
bsaleil updated this revision to Diff 277858.
bsaleil added a comment.
Add test to check that the `mma` option is supported by the targets.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81442/new/
https://reviews.llvm.org/D81442
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-dependent-options.cpp
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/test/CodeGen/PowerPC/future-check-features.ll
Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \
; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \
; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -108,6 +108,7 @@
bool HasP10Vector;
bool HasPrefixInstrs;
bool HasPCRelativeMemops;
+ bool HasMMA;
bool HasFCPSGN;
bool HasFSQRT;
bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
@@ -267,6 +268,7 @@
bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
+ bool hasMMA() const { return HasMMA; }
bool pairedVectorMemops() const { return PairedVectorMemops; }
bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -78,6 +78,7 @@
HasP8Crypto = false;
HasP9Vector = false;
HasP9Altivec = false;
+ HasMMA = false;
HasP10Vector = false;
HasPrefixInstrs = false;
HasPCRelativeMemops = false;
Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td
===
--- llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -43,8 +43,8 @@
// Do not support QPX (Quad Processing eXtension), SPE (Signal Processing
// Engine), prefixed instructions on Power 9, PC relative mem ops, or
// instructions introduced in ISA 3.1.
- let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PairedVectorMemops,
- PCRelativeMemops, IsISA3_1];
+ let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, MMA,
+ PairedVectorMemops, PCRelativeMemops, IsISA3_1];
}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -428,6 +428,7 @@
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
+def MMA : Predicate<"PPCSubTarget->hasMMA()">;
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -241,6 +241,10 @@
SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
"32Byte load and store instructions",
[FeatureISA3_0]>;
+def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",
+ "Enable MMA instructions",
+ [FeatureP8Vector, FeatureP9Altivec,
+ FeaturePairedVectorMemops]>;
def FeaturePredictableSelectIsExpensive :
SubtargetFeature<"predictable-select-expensive",
@@ -346,7 +350,8 @@
// still exist with the exception of those we know are Power9 specific.
list P10AdditionalFeatures =
[DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
- FeaturePCRelativeMemops, FeatureP10Vector, FeaturePairedV
[PATCH] D82576: [PowerPC][Power10] Implement low-order Vector Modulus Builtins, and add Vector Multiply/Divide/Modulus Builtins Tests
bsaleil added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:28 + return vec_mul(vulla, vullb); +} + Are the tests for `vec_mul` with `v4i32` missing ? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82576/new/ https://reviews.llvm.org/D82576 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D84968: [PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types
bsaleil created this revision.
bsaleil added reviewers: PowerPC, nemanjai, lei, hfinkel.
bsaleil added projects: PowerPC, LLVM.
Herald added subscribers: llvm-commits, cfe-commits, shchenz, kbarton,
hiraditya.
Herald added a project: clang.
bsaleil requested review of this revision.
Herald added a subscriber: wuzish.
This patch legalizes the `v256i1` and `v512i1` types that will be used for MMA.
It implements loads and stores of these types.
`v256i1` is a pair of VSX registers, so for this type, we load/store the two
underlying registers.
`v512i1` is used for MMA accumulators. So in addition to loading and storing
the 4 associated VSX registers, we generate instructions to prime (copy the VSX
registers to the accumulator) after loading and unprime (copy the accumulator
back to the VSX registers) before storing.
We also add the UACC register class. This class represents accumulator in their
unprimed form. This class is necessary to allow the distinction between primed
and unprimed accumulators to avoid invalid copies of the VSX registers
associated with primed accumulators.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D84968
Files:
clang/lib/Basic/Targets/PPC.h
clang/test/CodeGen/target-data.c
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
Index: llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
@@ -0,0 +1,143 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN: FileCheck %s --check-prefix=LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN: FileCheck %s --check-prefix=BE
+
+@f = common local_unnamed_addr global <512 x i1> zeroinitializer, align 16
+
+define void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
+; LE-LABEL: testLdSt:
+; LE: # %bb.0: # %entry
+; LE-NEXT:plxv vs1, f@PCREL+96(0), 1
+; LE-NEXT:plxv vs0, f@PCREL+112(0), 1
+; LE-NEXT:plxv vs3, f@PCREL+64(0), 1
+; LE-NEXT:plxv vs2, f@PCREL+80(0), 1
+; LE-NEXT:xxmtacc acc0
+; LE-NEXT:xxmfacc acc0
+; LE-NEXT:pstxv vs0, f@PCREL+176(0), 1
+; LE-NEXT:pstxv vs1, f@PCREL+160(0), 1
+; LE-NEXT:pstxv vs2, f@PCREL+144(0), 1
+; LE-NEXT:pstxv vs3, f@PCREL+128(0), 1
+; LE-NEXT:blr
+;
+; BE-LABEL: testLdSt:
+; BE: # %bb.0: # %entry
+; BE-NEXT:addis r3, r2, .LC0@toc@ha
+; BE-NEXT:ld r3, .LC0@toc@l(r3)
+; BE-NEXT:lxv vs1, 80(r3)
+; BE-NEXT:lxv vs0, 64(r3)
+; BE-NEXT:lxv vs3, 112(r3)
+; BE-NEXT:lxv vs2, 96(r3)
+; BE-NEXT:xxmtacc acc0
+; BE-NEXT:xxmfacc acc0
+; BE-NEXT:stxv vs1, 144(r3)
+; BE-NEXT:stxv vs0, 128(r3)
+; BE-NEXT:stxv vs3, 176(r3)
+; BE-NEXT:stxv vs2, 160(r3)
+; BE-NEXT:blr
+entry:
+ %arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 1
+ %0 = load <512 x i1>, <512 x i1>* %arrayidx, align 16
+ %arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 2
+ store <512 x i1> %0, <512 x i1>* %arrayidx1, align 16
+ ret void
+}
+
+define void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
+; LE-LABEL: testXLdSt:
+; LE: # %bb.0: # %entry
+; LE-NEXT:sldi r3, r3, 6
+; LE-NEXT:paddi r5, 0, f@PCREL, 1
+; LE-NEXT:add r6, r5, r3
+; LE-NEXT:lxv vs1, 32(r6)
+; LE-NEXT:lxv vs0, 48(r6)
+; LE-NEXT:lxvx vs3, r5, r3
+; LE-NEXT:lxv vs2, 16(r6)
+; LE-NEXT:sldi r3, r4, 6
+; LE-NEXT:xxmtacc acc0
+; LE-NEXT:add r4, r5, r3
+; LE-NEXT:xxmfacc acc0
+; LE-NEXT:stxvx vs3, r5, r3
+; LE-NEXT:stxv vs0, 48(r4)
+; LE-NEXT:stxv vs1, 32(r4)
+; LE-NEXT:stxv vs2, 16(r4)
+; LE-NEXT:blr
+;
+; BE-LABEL: testXLdSt:
+; BE: # %bb.0: # %entry
+; BE-NEXT:addis r5, r2, .LC0@toc@ha
+; BE-NEXT:ld r5, .LC0@toc@l(r5)
+; BE-NEXT:sldi r3, r3, 6
+; BE-NEXT:add r6, r5, r3
+; BE-NEXT:lxvx vs0, r5, r3
+; BE-NEXT:lxv vs1, 16(r6)
+; BE-NEXT:lxv vs3, 48(r6)
+; BE-NEXT:lxv vs2, 32(r6)
+; BE-NEXT:sldi r3, r4, 6
+; BE-NEXT:xxmtacc acc0
+; BE-NEXT:add r4, r5, r3
+; BE-NEXT:xxmfacc acc0
+; BE-NEXT:stxvx vs0, r5, r3
+; BE-NEXT:stxv vs1, 16(r4)
+; BE-NEXT:stxv vs3, 48(r4)
+; BE-NEXT:stxv vs2, 32(r4)
+; BE-NEXT:blr
+entry:
+ %arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %SrcIdx
+ %0 = load <512 x i1>, <512 x i1>* %arrayidx, align 16
+ %arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %DstIdx
+ store <512 x i1
[PATCH] D82675: [PowerPC] Implement Vector Extract Mask builtins in LLVM/Clang
bsaleil accepted this revision as: bsaleil. bsaleil added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82675/new/ https://reviews.llvm.org/D82675 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D84962: [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI
bsaleil added inline comments. Comment at: clang/test/CodeGen/builtins-ppc-vsx.c:1840 +// CHECK: %6 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %5, <4 x float> %4) + vec_cpsgn(a, b); +} Could you also add a call to `__builtin_vsx_xvcpsgnsp` and the same tests for vector double, so with calls to `__builtin_vsx_xvcpsgndp` and `vec_cpsgn` with `vector double` arguments ? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84962/new/ https://reviews.llvm.org/D84962 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D84968: [PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types
bsaleil updated this revision to Diff 294776.
bsaleil added a comment.
Use early exit in lowering functions and extend test case
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D84968/new/
https://reviews.llvm.org/D84968
Files:
clang/lib/Basic/Targets/PPC.h
clang/test/CodeGen/target-data.c
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
Index: llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
@@ -0,0 +1,238 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN: FileCheck %s --check-prefix=LE-PAIRED
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
+; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=BE-PAIRED
+
+@f = common local_unnamed_addr global <512 x i1> zeroinitializer, align 16
+@g = common local_unnamed_addr global <256 x i1> zeroinitializer, align 16
+
+define void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
+; LE-PAIRED-LABEL: testLdSt:
+; LE-PAIRED: # %bb.0: # %entry
+; LE-PAIRED-NEXT:plxv vs1, f@PCREL+96(0), 1
+; LE-PAIRED-NEXT:plxv vs0, f@PCREL+112(0), 1
+; LE-PAIRED-NEXT:plxv vs3, f@PCREL+64(0), 1
+; LE-PAIRED-NEXT:plxv vs2, f@PCREL+80(0), 1
+; LE-PAIRED-NEXT:xxmtacc acc0
+; LE-PAIRED-NEXT:xxmfacc acc0
+; LE-PAIRED-NEXT:pstxv vs0, f@PCREL+176(0), 1
+; LE-PAIRED-NEXT:pstxv vs1, f@PCREL+160(0), 1
+; LE-PAIRED-NEXT:pstxv vs2, f@PCREL+144(0), 1
+; LE-PAIRED-NEXT:pstxv vs3, f@PCREL+128(0), 1
+; LE-PAIRED-NEXT:blr
+;
+; BE-PAIRED-LABEL: testLdSt:
+; BE-PAIRED: # %bb.0: # %entry
+; BE-PAIRED-NEXT:addis r3, r2, .LC0@toc@ha
+; BE-PAIRED-NEXT:ld r3, .LC0@toc@l(r3)
+; BE-PAIRED-NEXT:lxv vs1, 80(r3)
+; BE-PAIRED-NEXT:lxv vs0, 64(r3)
+; BE-PAIRED-NEXT:lxv vs3, 112(r3)
+; BE-PAIRED-NEXT:lxv vs2, 96(r3)
+; BE-PAIRED-NEXT:xxmtacc acc0
+; BE-PAIRED-NEXT:xxmfacc acc0
+; BE-PAIRED-NEXT:stxv vs1, 144(r3)
+; BE-PAIRED-NEXT:stxv vs0, 128(r3)
+; BE-PAIRED-NEXT:stxv vs3, 176(r3)
+; BE-PAIRED-NEXT:stxv vs2, 160(r3)
+; BE-PAIRED-NEXT:blr
+entry:
+ %arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 1
+ %0 = load <512 x i1>, <512 x i1>* %arrayidx, align 64
+ %arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 2
+ store <512 x i1> %0, <512 x i1>* %arrayidx1, align 64
+ ret void
+}
+
+define void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
+; LE-PAIRED-LABEL: testXLdSt:
+; LE-PAIRED: # %bb.0: # %entry
+; LE-PAIRED-NEXT:sldi r3, r3, 6
+; LE-PAIRED-NEXT:paddi r5, 0, f@PCREL, 1
+; LE-PAIRED-NEXT:add r6, r5, r3
+; LE-PAIRED-NEXT:lxv vs1, 32(r6)
+; LE-PAIRED-NEXT:lxv vs0, 48(r6)
+; LE-PAIRED-NEXT:lxvx vs3, r5, r3
+; LE-PAIRED-NEXT:lxv vs2, 16(r6)
+; LE-PAIRED-NEXT:sldi r3, r4, 6
+; LE-PAIRED-NEXT:xxmtacc acc0
+; LE-PAIRED-NEXT:xxmfacc acc0
+; LE-PAIRED-NEXT:stxvx vs3, r5, r3
+; LE-PAIRED-NEXT:add r3, r5, r3
+; LE-PAIRED-NEXT:stxv vs0, 48(r3)
+; LE-PAIRED-NEXT:stxv vs1, 32(r3)
+; LE-PAIRED-NEXT:stxv vs2, 16(r3)
+; LE-PAIRED-NEXT:blr
+;
+; BE-PAIRED-LABEL: testXLdSt:
+; BE-PAIRED: # %bb.0: # %entry
+; BE-PAIRED-NEXT:addis r5, r2, .LC0@toc@ha
+; BE-PAIRED-NEXT:sldi r3, r3, 6
+; BE-PAIRED-NEXT:ld r5, .LC0@toc@l(r5)
+; BE-PAIRED-NEXT:add r6, r5, r3
+; BE-PAIRED-NEXT:lxvx vs0, r5, r3
+; BE-PAIRED-NEXT:sldi r3, r4, 6
+; BE-PAIRED-NEXT:lxv vs1, 16(r6)
+; BE-PAIRED-NEXT:lxv vs3, 48(r6)
+; BE-PAIRED-NEXT:lxv vs2, 32(r6)
+; BE-PAIRED-NEXT:xxmtacc acc0
+; BE-PAIRED-NEXT:xxmfacc acc0
+; BE-PAIRED-NEXT:stxvx vs0, r5, r3
+; BE-PAIRED-NEXT:add r3, r5, r3
+; BE-PAIRED-NEXT:stxv vs1, 16(r3)
+; BE-PAIRED-NEXT:stxv vs3, 48(r3)
+; BE-PAIRED-NEXT:stxv vs2, 32(r3)
+; BE-PAIRED-NEXT:blr
+entry:
+ %arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %SrcIdx
+ %0 = load <512 x i1>, <512 x i1>* %arrayidx, align 64
+ %arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %DstIdx
+ store <512 x i1> %0, <512 x i1>* %arrayidx1, align 64
+ ret void
+}
+
+define void @testUnalignedLdSt() {
+; LE-PAIRED-LABEL: testUnalignedLdSt:
+; LE-PAIRED: # %bb.0: # %entry
+; LE-PAIRED-NEXT:plxv vs1, f@PCREL+43(0), 1
+; LE-PAIRED-NEXT:plxv vs0, f@PCREL+59(0), 1
+; LE-PAIRED-NEXT:plxv vs3, f@PCREL+11(0), 1
+; LE-PAIRED-NEXT:plxv vs2, f@PCREL+27(0
[PATCH] D81442: [PowerPC] Add clang options to control MMA support
This revision was automatically updated to reflect the committed changes.
Closed by commit rG512e256c0d8c: [PowerPC] Add clang options to control MMA
support (authored by bsaleil).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81442/new/
https://reviews.llvm.org/D81442
Files:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-dependent-options.cpp
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/test/CodeGen/PowerPC/future-check-features.ll
Index: llvm/test/CodeGen/PowerPC/future-check-features.ll
===
--- llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \
; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \
; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
Index: llvm/lib/Target/PowerPC/PPCSubtarget.h
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -107,6 +107,7 @@
bool HasP10Vector;
bool HasPrefixInstrs;
bool HasPCRelativeMemops;
+ bool HasMMA;
bool HasFCPSGN;
bool HasFSQRT;
bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
@@ -260,6 +261,7 @@
bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
+ bool hasMMA() const { return HasMMA; }
bool pairedVectorMemops() const { return PairedVectorMemops; }
bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; }
Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp
===
--- llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -73,6 +73,7 @@
HasP8Crypto = false;
HasP9Vector = false;
HasP9Altivec = false;
+ HasMMA = false;
HasP10Vector = false;
HasPrefixInstrs = false;
HasPCRelativeMemops = false;
Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td
===
--- llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -41,9 +41,9 @@
let CompleteModel = 1;
// Do not support SPE (Signal Processing Engine), prefixed instructions on
- // Power 9, paired vector mem ops, PC relative mem ops, or instructions
+ // Power 9, paired vector mem ops, MMA, PC relative mem ops, or instructions
// introduced in ISA 3.1.
- let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops,
+ let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops, MMA,
PCRelativeMemops, IsISA3_1];
}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -504,6 +504,7 @@
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
+def MMA : Predicate<"PPCSubTarget->hasMMA()">;
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
Index: llvm/lib/Target/PowerPC/PPC.td
===
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -238,6 +238,10 @@
SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
"32Byte load and store instructions",
[FeatureISA3_0]>;
+def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",
+ "Enable MMA instructions",
+ [FeatureP8Vector, FeatureP9Altivec,
+ FeaturePairedVectorMemops]>;
def FeaturePredictableSelectIsExpensive :
SubtargetFeature<"predictable-select-expensive",
@@ -343,7 +347,8 @@
// still exist with the exception of those we know are Power9 specific.
list P10AdditionalFeatures =
[DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
-
[PATCH] D86795: [PowerPC] Implement builtins for xvcvspbf16 and xvcvbf16spn
bsaleil accepted this revision. bsaleil added a comment. This revision is now accepted and ready to land. LGTM, thanks for adding that. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D86795/new/ https://reviews.llvm.org/D86795 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D84962: [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI
bsaleil added inline comments.
Comment at: clang/lib/CodeGen/CGBuiltin.cpp:14298
llvm::Function *F = CGM.getIntrinsic(ID, ResultType);
-return Builder.CreateCall(F, {X, Y});
+return Builder.CreateCall(F, {Y, X});
}
Could you add a test case in `clang/test/CodeGen/builtins-ppc-vsx.c` showing
that calls to the builtins and calls to `vec_cpsgn` are generated as calls to
the `copysign` LLVM intrinsic with the arguments being inverted ?
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[PATCH] D84968: [PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types
bsaleil updated this revision to Diff 290804.
bsaleil added a comment.
Rebase so the patch can be applied on top of master. Also change the datalayout
string on all ppc64 platforms to improve compatibility between object files.
CHANGES SINCE LAST ACTION
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Files:
clang/lib/Basic/Targets/PPC.h
clang/test/CodeGen/target-data.c
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
Index: llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
@@ -0,0 +1,143 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN: FileCheck %s --check-prefix=LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN: FileCheck %s --check-prefix=BE
+
+@f = common local_unnamed_addr global <512 x i1> zeroinitializer, align 16
+
+define void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
+; LE-LABEL: testLdSt:
+; LE: # %bb.0: # %entry
+; LE-NEXT:plxv vs1, f@PCREL+96(0), 1
+; LE-NEXT:plxv vs0, f@PCREL+112(0), 1
+; LE-NEXT:plxv vs3, f@PCREL+64(0), 1
+; LE-NEXT:plxv vs2, f@PCREL+80(0), 1
+; LE-NEXT:xxmtacc acc0
+; LE-NEXT:xxmfacc acc0
+; LE-NEXT:pstxv vs0, f@PCREL+176(0), 1
+; LE-NEXT:pstxv vs1, f@PCREL+160(0), 1
+; LE-NEXT:pstxv vs2, f@PCREL+144(0), 1
+; LE-NEXT:pstxv vs3, f@PCREL+128(0), 1
+; LE-NEXT:blr
+;
+; BE-LABEL: testLdSt:
+; BE: # %bb.0: # %entry
+; BE-NEXT:addis r3, r2, .LC0@toc@ha
+; BE-NEXT:ld r3, .LC0@toc@l(r3)
+; BE-NEXT:lxv vs1, 80(r3)
+; BE-NEXT:lxv vs0, 64(r3)
+; BE-NEXT:lxv vs3, 112(r3)
+; BE-NEXT:lxv vs2, 96(r3)
+; BE-NEXT:xxmtacc acc0
+; BE-NEXT:xxmfacc acc0
+; BE-NEXT:stxv vs1, 144(r3)
+; BE-NEXT:stxv vs0, 128(r3)
+; BE-NEXT:stxv vs3, 176(r3)
+; BE-NEXT:stxv vs2, 160(r3)
+; BE-NEXT:blr
+entry:
+ %arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 1
+ %0 = load <512 x i1>, <512 x i1>* %arrayidx, align 16
+ %arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 2
+ store <512 x i1> %0, <512 x i1>* %arrayidx1, align 16
+ ret void
+}
+
+define void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
+; LE-LABEL: testXLdSt:
+; LE: # %bb.0: # %entry
+; LE-NEXT:sldi r3, r3, 6
+; LE-NEXT:paddi r5, 0, f@PCREL, 1
+; LE-NEXT:add r6, r5, r3
+; LE-NEXT:lxv vs1, 32(r6)
+; LE-NEXT:lxv vs0, 48(r6)
+; LE-NEXT:lxvx vs3, r5, r3
+; LE-NEXT:lxv vs2, 16(r6)
+; LE-NEXT:sldi r3, r4, 6
+; LE-NEXT:xxmtacc acc0
+; LE-NEXT:add r4, r5, r3
+; LE-NEXT:xxmfacc acc0
+; LE-NEXT:stxvx vs3, r5, r3
+; LE-NEXT:stxv vs0, 48(r4)
+; LE-NEXT:stxv vs1, 32(r4)
+; LE-NEXT:stxv vs2, 16(r4)
+; LE-NEXT:blr
+;
+; BE-LABEL: testXLdSt:
+; BE: # %bb.0: # %entry
+; BE-NEXT:addis r5, r2, .LC0@toc@ha
+; BE-NEXT:ld r5, .LC0@toc@l(r5)
+; BE-NEXT:sldi r3, r3, 6
+; BE-NEXT:add r6, r5, r3
+; BE-NEXT:lxvx vs0, r5, r3
+; BE-NEXT:lxv vs1, 16(r6)
+; BE-NEXT:lxv vs3, 48(r6)
+; BE-NEXT:lxv vs2, 32(r6)
+; BE-NEXT:sldi r3, r4, 6
+; BE-NEXT:xxmtacc acc0
+; BE-NEXT:add r4, r5, r3
+; BE-NEXT:xxmfacc acc0
+; BE-NEXT:stxvx vs0, r5, r3
+; BE-NEXT:stxv vs1, 16(r4)
+; BE-NEXT:stxv vs3, 48(r4)
+; BE-NEXT:stxv vs2, 32(r4)
+; BE-NEXT:blr
+entry:
+ %arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %SrcIdx
+ %0 = load <512 x i1>, <512 x i1>* %arrayidx, align 16
+ %arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %DstIdx
+ store <512 x i1> %0, <512 x i1>* %arrayidx1, align 16
+ ret void
+}
+
+define void @testUnalignedLdSt() {
+; LE-LABEL: testUnalignedLdSt:
+; LE: # %bb.0: # %entry
+; LE-NEXT:plxv vs1, f@PCREL+43(0), 1
+; LE-NEXT:plxv vs0, f@PCREL+59(0), 1
+; LE-NEXT:plxv vs3, f@PCREL+11(0), 1
+; LE-NEXT:plxv vs2, f@PCREL+27(0), 1
+; LE-NEXT:xxmtacc acc0
+; LE-NEXT:xxmfacc acc0
+; LE-NEXT:pstxv vs0, f@PCREL+67(0), 1
+; LE-NEXT:pstxv vs1, f@PCREL+51(0), 1
+; LE-NEXT:pstxv vs2, f@PCREL+35(0), 1
+; LE-NEXT:pstxv vs3, f@PCREL+19(0), 1
+; LE-NEXT:blr
+;
+; BE-LABEL: testUnalignedLdSt:
+; BE: # %bb.0: # %entry
+; BE-NEXT:addis r3, r2, .LC0@toc@ha
+; BE-NEXT:ld r3, .LC0@toc@l(r3)
+; BE-NEXT:li r4, 11
+; BE-NEXT:lxvx vs0, r3, r4
+; BE-NEXT:li r4, 27
+; BE-NEXT:lxvx vs1, r3, r4
+; BE-NEXT:l
[PATCH] D91819: [PowerPC] Enable paired vector type and intrinsics when MMA is disabled
bsaleil added inline comments.
Comment at: clang/lib/AST/ASTContext.cpp:1427
+ if (Target.getTriple().isPPC64() &&
+ Target.hasFeature("paired-vector-memops")) {
+if (Target.hasFeature("mma")) {
amyk wrote:
> Is it better to do `hasFeature()` over `PairedVectorMemops` and `HasMMA`?
`Target` is a `clang::TargetInfo` here so there is no `HasMMA` method
available. I'd need to add it, so I guess it's better to use directly
`hasFeature` instead of adding PPC specific code in that class.
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[PATCH] D91819: [PowerPC] Enable paired vector type and intrinsics when MMA is disabled
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
bsaleil marked an inline comment as done.
Closed by commit rG57d83c3a90c4: [PowerPC] Enable paired vector type and
intrinsics when MMA is disabled (authored by bsaleil).
Repository:
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https://reviews.llvm.org/D91819
Files:
clang/include/clang/AST/ASTContext.h
clang/include/clang/AST/Type.h
clang/include/clang/AST/TypeProperties.td
clang/include/clang/Basic/PPCTypes.def
clang/include/clang/Serialization/ASTBitCodes.h
clang/lib/AST/ASTContext.cpp
clang/lib/AST/ASTImporter.cpp
clang/lib/AST/ExprConstant.cpp
clang/lib/AST/ItaniumMangle.cpp
clang/lib/AST/MicrosoftMangle.cpp
clang/lib/AST/NSAPI.cpp
clang/lib/AST/PrintfFormatString.cpp
clang/lib/AST/Type.cpp
clang/lib/AST/TypeLoc.cpp
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/CodeGen/CodeGenTypes.cpp
clang/lib/CodeGen/ItaniumCXXABI.cpp
clang/lib/Index/USRGeneration.cpp
clang/lib/Sema/Sema.cpp
clang/lib/Sema/SemaChecking.cpp
clang/lib/Sema/SemaExpr.cpp
clang/lib/Serialization/ASTCommon.cpp
clang/lib/Serialization/ASTReader.cpp
clang/test/AST/ast-dump-ppc-mma-types.c
clang/test/AST/ast-dump-ppc-types.c
clang/tools/libclang/CIndex.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/paired-vector-intrinsics-without-mma.ll
Index: llvm/test/CodeGen/PowerPC/paired-vector-intrinsics-without-mma.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/paired-vector-intrinsics-without-mma.ll
@@ -0,0 +1,59 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mattr=-mma \
+; RUN: < %s | FileCheck %s
+
+; This test is to check that the paired vector intrinsics are available even
+; when MMA is disabled.
+
+define <16 x i8> @test1(<256 x i1>* %ptr) {
+; CHECK-LABEL: test1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxv v3, 0(r3)
+; CHECK-NEXT:lxv v2, 16(r3)
+; CHECK-NEXT:vaddubm v2, v3, v2
+; CHECK-NEXT:blr
+entry:
+ %0 = load <256 x i1>, <256 x i1>* %ptr, align 32
+ %1 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.pair(<256 x i1> %0)
+ %2 = extractvalue { <16 x i8>, <16 x i8> } %1, 0
+ %3 = extractvalue { <16 x i8>, <16 x i8> } %1, 1
+ %add = add <16 x i8> %2, %3
+ ret <16 x i8> %add
+}
+
+declare { <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.pair(<256 x i1>)
+
+define void @test2(<16 x i8> %v1, <16 x i8> %v2, <256 x i1>* %ptr) {
+; CHECK-LABEL: test2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vmr v4, v3
+; CHECK-NEXT:vmr v5, v2
+; CHECK-NEXT:stxv v4, 16(r7)
+; CHECK-NEXT:stxv v5, 0(r7)
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <256 x i1> @llvm.ppc.mma.assemble.pair(<16 x i8> %v2, <16 x i8> %v1)
+ store <256 x i1> %0, <256 x i1>* %ptr, align 32
+ ret void
+}
+
+declare <256 x i1> @llvm.ppc.mma.assemble.pair(<16 x i8>, <16 x i8>)
+
+define void @test3(<256 x i1>* %ptr) {
+; CHECK-LABEL: test3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvp vsp0, 0(r3)
+; CHECK-NEXT:stxvp vsp0, 32(r3)
+; CHECK-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %ptr to i8*
+ %1 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %0)
+ %add.ptr1 = getelementptr inbounds <256 x i1>, <256 x i1>* %ptr, i64 1
+ %2 = bitcast <256 x i1>* %add.ptr1 to i8*
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %1, i8* %2)
+ ret void
+}
+
+declare <256 x i1> @llvm.ppc.mma.lxvp(i8*)
+declare void @llvm.ppc.mma.stxvp(<256 x i1>, i8*)
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1600,13 +1600,9 @@
let Predicates = [MMA] in {
def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
(XXMTACC Concats.VecsToVecQuad)>;
- def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)),
-Concats.VecsToVecPair0>;
def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
v16i8:$vs3, v16i8:$vs2)),
(XXMTACC Concats.VecsToVecQuad)>;
- def : Pat<(v256i1 (int_ppc_mma_assemble_pair v16i8:$vs1, v16i8:$vs0)),
-Concats.VecsToVecPair0>;
def : Pat<(v512i1 (PPCxxmfacc v512i1:$AS)), (XXMFACC acc:$AS)>;
def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, (i64 0))),
Extracts.Vec0>;
@@ -1616,6 +1612,13 @@
Extracts.Vec2>;
def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, (i64 3))),
Extracts.Vec3>;
+}
+
+let Predicates = [PairedVectorMemops] in {
+ def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$
[PATCH] D91974: [PowerPC] Rename the vector pair intrinsics and builtins to replace the _mma_ prefix by _vsx_
bsaleil updated this revision to Diff 312238.
bsaleil added a comment.
Rebase and fix comment
Repository:
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https://reviews.llvm.org/D91974
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-mma.c
clang/test/CodeGen/builtins-ppc-pair-mma.c
clang/test/Sema/ppc-mma-types.c
clang/test/Sema/ppc-pair-mma-types.c
clang/test/SemaCXX/ppc-mma-types.cpp
clang/test/SemaCXX/ppc-pair-mma-types.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
llvm/test/CodeGen/PowerPC/mma-outer-product.ll
llvm/test/CodeGen/PowerPC/mma-phi-accs.ll
llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
llvm/test/CodeGen/PowerPC/paired-vector-intrinsics-without-mma.ll
llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
Index: llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
@@ -0,0 +1,357 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN: < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mattr=-mma \
+; RUN: < %s | FileCheck %s --check-prefix=CHECK-NOMMA
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O3 \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN: < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O3 \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mattr=-mma \
+; RUN: < %s | FileCheck %s --check-prefix=CHECK-BE-NOMMA
+
+; This test also checks that the paired vector intrinsics are available even
+; when MMA is disabled.
+
+; assemble_pair
+declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
+define void @ass_pair(<256 x i1>* %ptr, <16 x i8> %vc) {
+; CHECK-LABEL: ass_pair:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vmr v3, v2
+; CHECK-NEXT:stxv v2, 16(r3)
+; CHECK-NEXT:stxv v3, 0(r3)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: ass_pair:
+; CHECK-NOMMA: # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:vmr v3, v2
+; CHECK-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-NOMMA-NEXT:stxv v3, 0(r3)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: ass_pair:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:vmr v3, v2
+; CHECK-BE-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NEXT:blr
+;
+; CHECK-BE-NOMMA-LABEL: ass_pair:
+; CHECK-BE-NOMMA: # %bb.0: # %entry
+; CHECK-BE-NOMMA-NEXT:vmr v3, v2
+; CHECK-BE-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NOMMA-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NOMMA-NEXT:blr
+entry:
+ %0 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc, <16 x i8> %vc)
+ store <256 x i1> %0, <256 x i1>* %ptr, align 32
+ ret void
+}
+
+; disassemble_pair
+declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
+define void @disass_pair(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
+; CHECK-LABEL: disass_pair:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxv vs1, 0(r3)
+; CHECK-NEXT:lxv vs0, 16(r3)
+; CHECK-NEXT:stxv vs1, 0(r4)
+; CHECK-NEXT:stxv vs0, 0(r5)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: disass_pair:
+; CHECK-NOMMA: # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:lxv vs1, 0(r3)
+; CHECK-NOMMA-NEXT:lxv vs0, 16(r3)
+; CHECK-NOMMA-NEXT:stxv vs1, 0(r4)
+; CHECK-NOMMA-NEXT:stxv vs0, 0(r5)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: disass_pair:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxv vs1, 16(r3)
+; CHECK-BE-NEXT:lxv vs0, 0(r3)
+; CHECK-BE-NEXT:stxv vs0, 0(r4)
+; CHECK-BE-NEXT:stxv vs1, 0(r5)
+; CHECK-BE-NEXT:blr
+;
+; CHECK-BE-NOMMA-LABEL: disass_pair:
+; CHECK-BE-NOMMA: # %bb.0: # %entry
+; CHECK-BE-NOMMA-NEXT:lxv vs1, 16(r3)
+; CHECK-BE-NOMMA-NEXT:lxv vs0, 0(r3)
+; CHECK-BE-NOMMA-NEXT:stxv vs0, 0(r4)
+; CHECK-BE-NOMMA-NEXT:stxv vs1, 0(r5)
+; CHECK-BE-NOMMA-NEXT:blr
+entry:
+ %0 = load <256 x i1>, <256 x i1>* %ptr1, align 32
+ %1 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %0)
+ %2 = extractvalue { <16 x i8>, <16 x i8> } %1
[PATCH] D81748: [PowerPC] Add MMA builtin decoding and definitions
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGdaa127d77eab: [PowerPC] Add MMA builtin decoding and
definitions (authored by bsaleil).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81748/new/
https://reviews.llvm.org/D81748
Files:
clang/include/clang/AST/ASTContext.h
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Sema/Sema.h
clang/lib/AST/ASTContext.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-mma.c
Index: clang/test/CodeGen/builtins-ppc-mma.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-mma.c
@@ -0,0 +1,1038 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @test1(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], <16 x i8> [[VC]], <16 x i8> [[VC]])
+// CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
+// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
+// CHECK-NEXT:ret void
+//
+void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_quad vq = *((__vector_quad *)vqp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __vector_quad res;
+ __builtin_mma_assemble_acc(&res, vc, vc, vc, vc);
+ *((__vector_quad *)resp) = res;
+}
+
+// CHECK-LABEL: @test2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
+// CHECK-NEXT:[[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64
+// CHECK-NEXT:[[TMP2:%.*]] = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> [[TMP1]])
+// CHECK-NEXT:[[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <16 x i8>*
+// CHECK-NEXT:[[TMP4:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 0
+// CHECK-NEXT:store <16 x i8> [[TMP4]], <16 x i8>* [[TMP3]], align 16
+// CHECK-NEXT:[[TMP5:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 1
+// CHECK-NEXT:[[TMP6:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 16
+// CHECK-NEXT:[[TMP7:%.*]] = bitcast i8* [[TMP6]] to <16 x i8>*
+// CHECK-NEXT:store <16 x i8> [[TMP5]], <16 x i8>* [[TMP7]], align 16
+// CHECK-NEXT:[[TMP8:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 2
+// CHECK-NEXT:[[TMP9:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 32
+// CHECK-NEXT:[[TMP10:%.*]] = bitcast i8* [[TMP9]] to <16 x i8>*
+// CHECK-NEXT:store <16 x i8> [[TMP8]], <16 x i8>* [[TMP10]], align 16
+// CHECK-NEXT:[[TMP11:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 3
+// CHECK-NEXT:[[TMP12:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 48
+// CHECK-NEXT:[[TMP13:%.*]] = bitcast i8* [[TMP12]] to <16 x i8>*
+// CHECK-NEXT:store <16 x i8> [[TMP11]], <16 x i8>* [[TMP13]], align 16
+// CHECK-NEXT:ret void
+//
+void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __builtin_mma_disassemble_acc(resp, (__vector_quad*)vqp);
+}
+
+// CHECK-LABEL: @test3(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.mma.assemble.pair(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
+// CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
+// CHECK-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa !6
+// CHECK-NEXT:ret void
+//
+void test3(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_quad vq = *((__vector_quad *)vqp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __vector_pair res;
+ __builtin_mma_assemble_pair(&res, vc, vc);
+ *((__vector_pair *)resp) = res;
+}
+
+// CHECK-LABEL: @test4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>*
+// CHECK-NEXT:[[TMP1:%.*]] = load <256 x i1>, <256 x i1>* [[TMP0]], align 32
+// CHECK-NEXT:[[TMP2:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.pair(<256 x i1> [[TMP1]])
+// CHECK-NEXT:[[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <16 x i8>*
+// CHECK-NEXT:[[TMP4:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP2]], 0
+// CHECK-NEXT:store <16 x i8> [[TMP4]], <16 x i8>* [[TMP3]], align 16
+// CHECK-NEXT:[[TMP5:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP2]], 1
+// CHECK-NEXT:[[TMP6:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 16
+// CHECK-NEXT:[[TMP7:%.*]] = bitcast i8* [[TMP6]] to <16 x i8>*
+// CH
[PATCH] D82035: [PowerPC] Add Sema checks for MMA types
bsaleil updated this revision to Diff 302918.
bsaleil added a comment.
Change function name and improve comment
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82035/new/
https://reviews.llvm.org/D82035
Files:
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/include/clang/Sema/Sema.h
clang/lib/Sema/SemaChecking.cpp
clang/lib/Sema/SemaDecl.cpp
clang/lib/Sema/SemaExprCXX.cpp
clang/test/Sema/ppc-mma-types.c
clang/test/SemaCXX/ppc-mma-types.cpp
Index: clang/test/SemaCXX/ppc-mma-types.cpp
===
--- /dev/null
+++ clang/test/SemaCXX/ppc-mma-types.cpp
@@ -0,0 +1,384 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -fcxx-exceptions -target-cpu future %s -verify
+
+// vector quad
+
+// alias
+using vq_t = __vector_quad;
+void testVQAlias(int *inp, int *outp) {
+ vq_t *vqin = (vq_t *)inp;
+ vq_t *vqout = (vq_t *)outp;
+ *vqout = *vqin;
+}
+
+class TestClassVQ {
+ // method argument
+public:
+ void testVQArg1(__vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = vq;
+*vqp1 = vq;
+ }
+ void testVQArg2(const __vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = vq;
+*vqp2 = vq;
+ }
+ void testVQArg3(__vector_quad *vq, int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = *vq;
+vqp1 = vqp;
+ }
+ void testVQArg4(const __vector_quad *const vq, int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = *vq;
+vqp2 = vqp;
+ }
+ void testVQArg5(__vector_quad vqa[], int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = vqa[0];
+*vqp1 = vqa[1];
+ }
+ void testVQArg6(const vq_t vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = vq;
+*vqp2 = vq;
+ }
+ void testVQArg7(const vq_t *vq, int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = *vq;
+vqp1 = vqp;
+ }
+
+ // method return
+ __vector_quad testVQRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+vq1 = *vqp;
+return *vqp; // expected-error {{invalid use of PPC MMA type}}
+ }
+
+ __vector_quad *testVQRet2(int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+vq2 = *vqp;
+return vqp + 2;
+ }
+
+ const __vector_quad *testVQRet3(int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+vqp1 = vqp;
+return vqp + 2;
+ }
+
+ const vq_t testVQRet4(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+vqp2 = vqp;
+return *vqp; // expected-error {{invalid use of PPC MMA type}}
+ }
+
+ const vq_t *testVQRet5(int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+vq1 = *vqp;
+return vqp + 2;
+ }
+
+ // template argument
+ template
+ void testVQTemplate(T v, T *p) { // expected-note {{candidate template ignored: substitution failure [with T = __vector_quad]: invalid use of PPC MMA type}} \
+ expected-note {{candidate template ignored: substitution failure [with T = __vector_quad]: invalid use of PPC MMA type}}
+*(p + 1) = v;
+ }
+
+ // class field
+public:
+ __vector_quad vq1; // expected-error {{invalid use of PPC MMA type}}
+ __vector_quad *vqp1;
+
+private:
+ vq_t vq2; // expected-error {{invalid use of PPC MMA type}}
+ vq_t *vqp2;
+};
+
+// template
+template
+class ClassTemplateVQ1 {
+ T t; // expected-error {{invalid use of PPC MMA type}}
+};
+template
+class ClassTemplateVQ2 {
+ T *t;
+};
+template
+class ClassTemplateVQ3 {
+ int foo(T t) { return 10; }
+};
+template
+class ClassTemplateVQ4 {
+public:
+ T operator()(Ts...) const {} // expected-error {{invalid use of PPC MMA type}}
+};
+void testVQTemplate() {
+ ClassTemplateVQ1<__vector_quad> t1; // expected-note {{in instantiation of template class 'ClassTemplateVQ1<__vector_quad>' requested here}}
+ ClassTemplateVQ1<__vector_quad *> t2;
+ ClassTemplateVQ2<__vector_quad> t3;
+ ClassTemplateVQ2<__vector_quad *> t4;
+
+ ClassTemplateVQ3 t5;
+ // The following case is not prevented but it ok, this function type cannot be
+ // instantiated because we prevent any function from returning an MMA type.
+ ClassTemplateVQ3<__vector_quad(int, int, int)> t6;
+ ClassTemplateVQ3 t7; // expected-error {{invalid use of PPC MMA type}}
+
+ ClassTemplateVQ4 t8; // expected-note {{in instantiation of template class 'ClassTemplateVQ4' requested here}}
+ ClassTemplateVQ4 t9;
+
+ TestClassVQ tc;
+ __vector_quad vq;
+ __vector_quad *vqp = &vq;
+ tc.testVQTemplate(&vq, &vqp);
+ tc.testVQTemplate(&vq, &vqp);
+ tc.testVQTemplate(vq, vqp); // expected-error {{no matching
[PATCH] D90799: [PowerPC] Add paired vector load and store builtins and intrinsics
bsaleil created this revision.
bsaleil added reviewers: nemanjai, amyk, saghir, lei.
bsaleil added projects: LLVM, PowerPC.
Herald added subscribers: llvm-commits, cfe-commits, shchenz, kbarton,
hiraditya.
Herald added a project: clang.
bsaleil requested review of this revision.
This patch adds the Clang builtins and LLVM intrinsics to load and store vector
pairs.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D90799
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGen/CGBuiltin.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
Index: llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -698,3 +698,307 @@
declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>)
+
+; Function Attrs: nounwind
+define void @test_ldst_1(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvp vsp0, 0(r3)
+; CHECK-NEXT:stxvp vsp0, 0(r4)
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_1:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvp vsp0, 0(r3)
+; CHECK-BE-NEXT:stxvp vsp0, 0(r4)
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %0)
+ %2 = bitcast <256 x i1>* %vp2 to i8*
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %1, i8* %2)
+ ret void
+}
+
+; Function Attrs: argmemonly nounwind readonly
+declare <256 x i1> @llvm.ppc.mma.lxvp(i8*)
+
+; Function Attrs: argmemonly nounwind writeonly
+declare void @llvm.ppc.mma.stxvp(<256 x i1>, i8*)
+
+; Function Attrs: nounwind
+define void @test_ldst_2(<256 x i1>* %vpp, i64 %offset, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvpx vsp0, r3, r4
+; CHECK-NEXT:stxvpx vsp0, r5, r4
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_2:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r4
+; CHECK-BE-NEXT:stxvpx vsp0, r5, r4
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 %offset
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 %offset
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_3(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:plxvp vsp0, 18(r3), 0
+; CHECK-NEXT:pstxvp vsp0, 18(r4), 0
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_3:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:plxvp vsp0, 18(r3), 0
+; CHECK-BE-NEXT:pstxvp vsp0, 18(r4), 0
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 18
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 18
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_4(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:plxvp vsp0, 1(r3), 0
+; CHECK-NEXT:pstxvp vsp0, 1(r4), 0
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_4:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:plxvp vsp0, 1(r3), 0
+; CHECK-BE-NEXT:pstxvp vsp0, 1(r4), 0
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 1
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 1
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_5(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_5:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:plxvp vsp0, 42(r3), 0
+; CHECK-NEXT:pstxvp vsp0, 42(r4), 0
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_5:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:plxvp vsp0, 42(r3), 0
+; CHECK-BE-NEXT:pstxvp vsp0, 42(r4), 0
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 42
+ %2 = tail call <2
[PATCH] D82035: [PowerPC] Add Sema checks for MMA types
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf976ba613958: [PowerPC] Add Sema checks for MMA types
(authored by bsaleil).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82035/new/
https://reviews.llvm.org/D82035
Files:
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/include/clang/Sema/Sema.h
clang/lib/Sema/SemaChecking.cpp
clang/lib/Sema/SemaDecl.cpp
clang/lib/Sema/SemaExprCXX.cpp
clang/test/Sema/ppc-mma-types.c
clang/test/SemaCXX/ppc-mma-types.cpp
Index: clang/test/SemaCXX/ppc-mma-types.cpp
===
--- /dev/null
+++ clang/test/SemaCXX/ppc-mma-types.cpp
@@ -0,0 +1,384 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -fcxx-exceptions -target-cpu future %s -verify
+
+// vector quad
+
+// alias
+using vq_t = __vector_quad;
+void testVQAlias(int *inp, int *outp) {
+ vq_t *vqin = (vq_t *)inp;
+ vq_t *vqout = (vq_t *)outp;
+ *vqout = *vqin;
+}
+
+class TestClassVQ {
+ // method argument
+public:
+ void testVQArg1(__vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = vq;
+*vqp1 = vq;
+ }
+ void testVQArg2(const __vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = vq;
+*vqp2 = vq;
+ }
+ void testVQArg3(__vector_quad *vq, int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = *vq;
+vqp1 = vqp;
+ }
+ void testVQArg4(const __vector_quad *const vq, int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = *vq;
+vqp2 = vqp;
+ }
+ void testVQArg5(__vector_quad vqa[], int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = vqa[0];
+*vqp1 = vqa[1];
+ }
+ void testVQArg6(const vq_t vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = vq;
+*vqp2 = vq;
+ }
+ void testVQArg7(const vq_t *vq, int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = *vq;
+vqp1 = vqp;
+ }
+
+ // method return
+ __vector_quad testVQRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+vq1 = *vqp;
+return *vqp; // expected-error {{invalid use of PPC MMA type}}
+ }
+
+ __vector_quad *testVQRet2(int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+vq2 = *vqp;
+return vqp + 2;
+ }
+
+ const __vector_quad *testVQRet3(int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+vqp1 = vqp;
+return vqp + 2;
+ }
+
+ const vq_t testVQRet4(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+vqp2 = vqp;
+return *vqp; // expected-error {{invalid use of PPC MMA type}}
+ }
+
+ const vq_t *testVQRet5(int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+vq1 = *vqp;
+return vqp + 2;
+ }
+
+ // template argument
+ template
+ void testVQTemplate(T v, T *p) { // expected-note {{candidate template ignored: substitution failure [with T = __vector_quad]: invalid use of PPC MMA type}} \
+ expected-note {{candidate template ignored: substitution failure [with T = __vector_quad]: invalid use of PPC MMA type}}
+*(p + 1) = v;
+ }
+
+ // class field
+public:
+ __vector_quad vq1; // expected-error {{invalid use of PPC MMA type}}
+ __vector_quad *vqp1;
+
+private:
+ vq_t vq2; // expected-error {{invalid use of PPC MMA type}}
+ vq_t *vqp2;
+};
+
+// template
+template
+class ClassTemplateVQ1 {
+ T t; // expected-error {{invalid use of PPC MMA type}}
+};
+template
+class ClassTemplateVQ2 {
+ T *t;
+};
+template
+class ClassTemplateVQ3 {
+ int foo(T t) { return 10; }
+};
+template
+class ClassTemplateVQ4 {
+public:
+ T operator()(Ts...) const {} // expected-error {{invalid use of PPC MMA type}}
+};
+void testVQTemplate() {
+ ClassTemplateVQ1<__vector_quad> t1; // expected-note {{in instantiation of template class 'ClassTemplateVQ1<__vector_quad>' requested here}}
+ ClassTemplateVQ1<__vector_quad *> t2;
+ ClassTemplateVQ2<__vector_quad> t3;
+ ClassTemplateVQ2<__vector_quad *> t4;
+
+ ClassTemplateVQ3 t5;
+ // The following case is not prevented but it ok, this function type cannot be
+ // instantiated because we prevent any function from returning an MMA type.
+ ClassTemplateVQ3<__vector_quad(int, int, int)> t6;
+ ClassTemplateVQ3 t7; // expected-error {{invalid use of PPC MMA type}}
+
+ ClassTemplateVQ4 t8; // expected-note {{in instantiation of template class 'ClassTemplateVQ4' requested here}}
+ ClassTemplateVQ4 t9;
+
+ TestClassVQ tc;
+ __vector_quad vq;
+ __vector_quad *vqp = &vq;
+ tc.testVQTemplate(&
[PATCH] D90799: [PowerPC] Add paired vector load and store builtins and intrinsics
bsaleil updated this revision to Diff 302983.
bsaleil added a comment.
Add builtin tests
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D90799/new/
https://reviews.llvm.org/D90799
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-mma.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
Index: llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -698,3 +698,307 @@
declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>)
+
+; Function Attrs: nounwind
+define void @test_ldst_1(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvp vsp0, 0(r3)
+; CHECK-NEXT:stxvp vsp0, 0(r4)
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_1:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvp vsp0, 0(r3)
+; CHECK-BE-NEXT:stxvp vsp0, 0(r4)
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %0)
+ %2 = bitcast <256 x i1>* %vp2 to i8*
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %1, i8* %2)
+ ret void
+}
+
+; Function Attrs: argmemonly nounwind readonly
+declare <256 x i1> @llvm.ppc.mma.lxvp(i8*)
+
+; Function Attrs: argmemonly nounwind writeonly
+declare void @llvm.ppc.mma.stxvp(<256 x i1>, i8*)
+
+; Function Attrs: nounwind
+define void @test_ldst_2(<256 x i1>* %vpp, i64 %offset, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvpx vsp0, r3, r4
+; CHECK-NEXT:stxvpx vsp0, r5, r4
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_2:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r4
+; CHECK-BE-NEXT:stxvpx vsp0, r5, r4
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 %offset
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 %offset
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_3(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:plxvp vsp0, 18(r3), 0
+; CHECK-NEXT:pstxvp vsp0, 18(r4), 0
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_3:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:plxvp vsp0, 18(r3), 0
+; CHECK-BE-NEXT:pstxvp vsp0, 18(r4), 0
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 18
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 18
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_4(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:plxvp vsp0, 1(r3), 0
+; CHECK-NEXT:pstxvp vsp0, 1(r4), 0
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_4:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:plxvp vsp0, 1(r3), 0
+; CHECK-BE-NEXT:pstxvp vsp0, 1(r4), 0
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 1
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 1
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_5(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_5:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:plxvp vsp0, 42(r3), 0
+; CHECK-NEXT:pstxvp vsp0, 42(r4), 0
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_5:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:plxvp vsp0, 42(r3), 0
+; CHECK-BE-NEXT:pstxvp vsp0, 42(r4), 0
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 42
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 42
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8*
[PATCH] D82035: [PowerPC] Add Sema checks for MMA types
bsaleil added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:10339 + if (Context.getTargetInfo().getTriple().isPPC64()) +CheckPPCMMAType(RetValExp->getType(), ReturnLoc); } NeHuang wrote: > CheckPPCMMAType returns bool value. Do we need add it in the if condition > (similar as `CheckNonNullExpr` above) and execute a Diag()? or I may miss > something here. `CheckPPCMMAType` already emits the Diag if the type is invalid. That function also returns a bool in case the caller needs to do additional work when the type is invalid. It is not the case here, the Diag is enough so we do nothing with the result. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82035/new/ https://reviews.llvm.org/D82035 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D90799: [PowerPC] Add paired vector load and store builtins and intrinsics
bsaleil updated this revision to Diff 303132.
bsaleil added a comment.
Add support for the paired load/store intrinsics in `PPCLoopInstrFormPrep`
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D90799/new/
https://reviews.llvm.org/D90799
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-mma.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
Index: llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -698,3 +698,307 @@
declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>)
+
+; Function Attrs: nounwind
+define void @test_ldst_1(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvp vsp0, 0(r3)
+; CHECK-NEXT:stxvp vsp0, 0(r4)
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_1:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvp vsp0, 0(r3)
+; CHECK-BE-NEXT:stxvp vsp0, 0(r4)
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %0)
+ %2 = bitcast <256 x i1>* %vp2 to i8*
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %1, i8* %2)
+ ret void
+}
+
+; Function Attrs: argmemonly nounwind readonly
+declare <256 x i1> @llvm.ppc.mma.lxvp(i8*)
+
+; Function Attrs: argmemonly nounwind writeonly
+declare void @llvm.ppc.mma.stxvp(<256 x i1>, i8*)
+
+; Function Attrs: nounwind
+define void @test_ldst_2(<256 x i1>* %vpp, i64 %offset, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvpx vsp0, r3, r4
+; CHECK-NEXT:stxvpx vsp0, r5, r4
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_2:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r4
+; CHECK-BE-NEXT:stxvpx vsp0, r5, r4
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 %offset
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 %offset
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_3(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:plxvp vsp0, 18(r3), 0
+; CHECK-NEXT:pstxvp vsp0, 18(r4), 0
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_3:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:plxvp vsp0, 18(r3), 0
+; CHECK-BE-NEXT:pstxvp vsp0, 18(r4), 0
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 18
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 18
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_4(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:plxvp vsp0, 1(r3), 0
+; CHECK-NEXT:pstxvp vsp0, 1(r4), 0
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_4:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:plxvp vsp0, 1(r3), 0
+; CHECK-BE-NEXT:pstxvp vsp0, 1(r4), 0
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 1
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 1
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_5(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_5:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:plxvp vsp0, 42(r3), 0
+; CHECK-NEXT:pstxvp vsp0, 42(r4), 0
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_5:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:plxvp vsp0, 42(r3), 0
+; CHECK-BE-NEXT:pstxvp vsp0, 42(r4), 0
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 42
+ %2 = tail call <256 x i1> @llv
[PATCH] D90799: [PowerPC] Add paired vector load and store builtins and intrinsics
bsaleil updated this revision to Diff 303152.
bsaleil added a comment.
Rebase patch and add Sema check test case for the builtins
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D90799/new/
https://reviews.llvm.org/D90799
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-mma.c
clang/test/Sema/ppc-mma-types.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
Index: llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -698,3 +698,307 @@
declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>)
+
+; Function Attrs: nounwind
+define void @test_ldst_1(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvp vsp0, 0(r3)
+; CHECK-NEXT:stxvp vsp0, 0(r4)
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_1:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvp vsp0, 0(r3)
+; CHECK-BE-NEXT:stxvp vsp0, 0(r4)
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %0)
+ %2 = bitcast <256 x i1>* %vp2 to i8*
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %1, i8* %2)
+ ret void
+}
+
+; Function Attrs: argmemonly nounwind readonly
+declare <256 x i1> @llvm.ppc.mma.lxvp(i8*)
+
+; Function Attrs: argmemonly nounwind writeonly
+declare void @llvm.ppc.mma.stxvp(<256 x i1>, i8*)
+
+; Function Attrs: nounwind
+define void @test_ldst_2(<256 x i1>* %vpp, i64 %offset, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvpx vsp0, r3, r4
+; CHECK-NEXT:stxvpx vsp0, r5, r4
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_2:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r4
+; CHECK-BE-NEXT:stxvpx vsp0, r5, r4
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 %offset
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 %offset
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_3(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:plxvp vsp0, 18(r3), 0
+; CHECK-NEXT:pstxvp vsp0, 18(r4), 0
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_3:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:plxvp vsp0, 18(r3), 0
+; CHECK-BE-NEXT:pstxvp vsp0, 18(r4), 0
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 18
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 18
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_4(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:plxvp vsp0, 1(r3), 0
+; CHECK-NEXT:pstxvp vsp0, 1(r4), 0
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_4:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:plxvp vsp0, 1(r3), 0
+; CHECK-BE-NEXT:pstxvp vsp0, 1(r4), 0
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 1
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 1
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_5(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_5:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:plxvp vsp0, 42(r3), 0
+; CHECK-NEXT:pstxvp vsp0, 42(r4), 0
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_5:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:plxvp vsp0, 42(r3), 0
+; CHECK-BE-NEXT:pstxvp vsp0, 42(r4), 0
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 42
+ %2 = tail ca
[PATCH] D90799: [PowerPC] Add paired vector load and store builtins and intrinsics
bsaleil updated this revision to Diff 303540.
bsaleil added a comment.
Fix unaligned load/store select
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D90799/new/
https://reviews.llvm.org/D90799
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-mma.c
clang/test/Sema/ppc-mma-types.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
Index: llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -698,3 +698,315 @@
declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>)
+
+; Function Attrs: nounwind
+define void @test_ldst_1(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvp vsp0, 0(r3)
+; CHECK-NEXT:stxvp vsp0, 0(r4)
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_1:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvp vsp0, 0(r3)
+; CHECK-BE-NEXT:stxvp vsp0, 0(r4)
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %0)
+ %2 = bitcast <256 x i1>* %vp2 to i8*
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %1, i8* %2)
+ ret void
+}
+
+; Function Attrs: argmemonly nounwind readonly
+declare <256 x i1> @llvm.ppc.mma.lxvp(i8*)
+
+; Function Attrs: argmemonly nounwind writeonly
+declare void @llvm.ppc.mma.stxvp(<256 x i1>, i8*)
+
+; Function Attrs: nounwind
+define void @test_ldst_2(<256 x i1>* %vpp, i64 %offset, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvpx vsp0, r3, r4
+; CHECK-NEXT:stxvpx vsp0, r5, r4
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_2:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r4
+; CHECK-BE-NEXT:stxvpx vsp0, r5, r4
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 %offset
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 %offset
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_3(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:li r5, 18
+; CHECK-NEXT:lxvpx vsp0, r3, r5
+; CHECK-NEXT:stxvpx vsp0, r4, r5
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_3:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:li r5, 18
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r5
+; CHECK-BE-NEXT:stxvpx vsp0, r4, r5
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 18
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 18
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_4(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:li r5, 1
+; CHECK-NEXT:lxvpx vsp0, r3, r5
+; CHECK-NEXT:stxvpx vsp0, r4, r5
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_4:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:li r5, 1
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r5
+; CHECK-BE-NEXT:stxvpx vsp0, r4, r5
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 1
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 1
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_5(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_5:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:li r5, 42
+; CHECK-NEXT:lxvpx vsp0, r3, r5
+; CHECK-NEXT:stxvpx vsp0, r4, r5
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_5:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:li r5, 42
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r5
+; CHECK-BE-NEXT:stxvpx vsp0, r4, r5
+; CHECK-BE-N
[PATCH] D90799: [PowerPC] Add paired vector load and store builtins and intrinsics
bsaleil updated this revision to Diff 303973.
bsaleil added a comment.
Simplify control flow and improve test cases
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D90799/new/
https://reviews.llvm.org/D90799
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-mma.c
clang/test/Sema/ppc-mma-types.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
Index: llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -698,3 +698,315 @@
declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>)
+
+; Function Attrs: nounwind
+define void @test_ldst_1(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvp vsp0, 0(r3)
+; CHECK-NEXT:stxvp vsp0, 0(r4)
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_1:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvp vsp0, 0(r3)
+; CHECK-BE-NEXT:stxvp vsp0, 0(r4)
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %0)
+ %2 = bitcast <256 x i1>* %vp2 to i8*
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %1, i8* %2)
+ ret void
+}
+
+; Function Attrs: argmemonly nounwind readonly
+declare <256 x i1> @llvm.ppc.mma.lxvp(i8*)
+
+; Function Attrs: argmemonly nounwind writeonly
+declare void @llvm.ppc.mma.stxvp(<256 x i1>, i8*)
+
+; Function Attrs: nounwind
+define void @test_ldst_2(<256 x i1>* %vpp, i64 %offset, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvpx vsp0, r3, r4
+; CHECK-NEXT:stxvpx vsp0, r5, r4
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_2:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r4
+; CHECK-BE-NEXT:stxvpx vsp0, r5, r4
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 %offset
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 %offset
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_3(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:li r5, 18
+; CHECK-NEXT:lxvpx vsp0, r3, r5
+; CHECK-NEXT:stxvpx vsp0, r4, r5
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_3:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:li r5, 18
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r5
+; CHECK-BE-NEXT:stxvpx vsp0, r4, r5
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 18
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 18
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_4(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:li r5, 1
+; CHECK-NEXT:lxvpx vsp0, r3, r5
+; CHECK-NEXT:stxvpx vsp0, r4, r5
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_4:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:li r5, 1
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r5
+; CHECK-BE-NEXT:stxvpx vsp0, r4, r5
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 1
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 1
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_5(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_5:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:li r5, 42
+; CHECK-NEXT:lxvpx vsp0, r3, r5
+; CHECK-NEXT:stxvpx vsp0, r4, r5
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_5:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:li r5, 42
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r5
+; CHECK-BE-NEXT:stxvpx vsp0, r4, r5
[PATCH] D91200: [PowerPC] Prevent the use of MMA with P9 and earlier
bsaleil created this revision.
bsaleil added reviewers: nemanjai, saghir, lei, amyk, PowerPC.
bsaleil added projects: clang, PowerPC.
Herald added subscribers: cfe-commits, shchenz, kbarton.
bsaleil requested review of this revision.
We want to allow using MMA on `P10` CPU only. This patch prevents the use of
MMA with the `-mmma` option on `P9` CPUs and earlier.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D91200
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/test/Driver/ppc-mma-support-check.c
clang/test/Preprocessor/init-ppc64.c
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -648,7 +648,7 @@
// PPCFUTURE:#define _ARCH_PWR_FUTURE 1
// PPCFUTURE:#define __MMA__ 1
//
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none
-target-feature +mma -target-cpu power9 -fno-signed-char < /dev/null |
FileCheck -check-prefix PPC-MMA %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none
-target-feature +mma -target-cpu power10 -fno-signed-char < /dev/null |
FileCheck -check-prefix PPC-MMA %s
// PPC-MMA:#define __MMA__ 1
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none
-target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null |
FileCheck -check-prefix PPC-FLOAT128 %s
Index: clang/test/Driver/ppc-mma-support-check.c
===
--- /dev/null
+++ clang/test/Driver/ppc-mma-support-check.c
@@ -0,0 +1,22 @@
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr10 -mmma %s 2>&1 | FileCheck %s --check-prefix=HASMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=power10 -mmma %s 2>&1 | FileCheck %s --check-prefix=HASMMA
+
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr9 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr8 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr7 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+
+#ifdef __MMA__
+static_assert(false, "MMA enabled");
+#endif
+
+// HASMMA: MMA enabled
+// HASMMA-NOT: option '-mmma' cannot be specified with
+// NOMMA: option '-mmma' cannot be specified with
+
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -343,6 +343,12 @@
return false;
}
+ if (!(ArchDefs & ArchDefinePwr10) && llvm::find(FeaturesVec, "+mma") !=
FeaturesVec.end()) {
+// We have MMA on PPC but not power 10 and above.
+Diags.Report(diag::err_opt_not_valid_with_opt) << "-mmma" << CPU;
+return false;
+ }
+
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -648,7 +648,7 @@
// PPCFUTURE:#define _ARCH_PWR_FUTURE 1
// PPCFUTURE:#define __MMA__ 1
//
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s
// PPC-MMA:#define __MMA__ 1
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
Index: clang/test/Driver/ppc-mma-support-check.c
===
--- /dev/null
+++ clang/test/Driver/ppc-mma-support-check.c
@@ -0,0 +1,22 @@
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr10 -mmma %s 2>&1 | FileCheck %s --check-prefix=HASMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=power10 -mmma %s 2>&1 | FileCheck %s --check-prefix=HASMMA
+
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr9 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr8 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=
[PATCH] D91200: [PowerPC] Prevent the use of MMA with P9 and earlier
bsaleil updated this revision to Diff 304662.
bsaleil added a comment.
clang-format
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D91200/new/
https://reviews.llvm.org/D91200
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/test/Driver/ppc-mma-support-check.c
clang/test/Preprocessor/init-ppc64.c
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -648,7 +648,7 @@
// PPCFUTURE:#define _ARCH_PWR_FUTURE 1
// PPCFUTURE:#define __MMA__ 1
//
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none
-target-feature +mma -target-cpu power9 -fno-signed-char < /dev/null |
FileCheck -check-prefix PPC-MMA %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none
-target-feature +mma -target-cpu power10 -fno-signed-char < /dev/null |
FileCheck -check-prefix PPC-MMA %s
// PPC-MMA:#define __MMA__ 1
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none
-target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null |
FileCheck -check-prefix PPC-FLOAT128 %s
Index: clang/test/Driver/ppc-mma-support-check.c
===
--- /dev/null
+++ clang/test/Driver/ppc-mma-support-check.c
@@ -0,0 +1,22 @@
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr10 -mmma %s 2>&1 | FileCheck %s --check-prefix=HASMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=power10 -mmma %s 2>&1 | FileCheck %s --check-prefix=HASMMA
+
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr9 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr8 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr7 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+
+#ifdef __MMA__
+static_assert(false, "MMA enabled");
+#endif
+
+// HASMMA: MMA enabled
+// HASMMA-NOT: option '-mmma' cannot be specified with
+// NOMMA: option '-mmma' cannot be specified with
+
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -343,6 +343,13 @@
return false;
}
+ if (!(ArchDefs & ArchDefinePwr10) &&
+ llvm::find(FeaturesVec, "+mma") != FeaturesVec.end()) {
+// We have MMA on PPC but not power 10 and above.
+Diags.Report(diag::err_opt_not_valid_with_opt) << "-mmma" << CPU;
+return false;
+ }
+
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -648,7 +648,7 @@
// PPCFUTURE:#define _ARCH_PWR_FUTURE 1
// PPCFUTURE:#define __MMA__ 1
//
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s
// PPC-MMA:#define __MMA__ 1
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
Index: clang/test/Driver/ppc-mma-support-check.c
===
--- /dev/null
+++ clang/test/Driver/ppc-mma-support-check.c
@@ -0,0 +1,22 @@
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr10 -mmma %s 2>&1 | FileCheck %s --check-prefix=HASMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=power10 -mmma %s 2>&1 | FileCheck %s --check-prefix=HASMMA
+
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr9 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr8 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr7 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+
+#ifdef __MMA__
+s
[PATCH] D91200: [PowerPC] Prevent the use of MMA with P9 and earlier
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG170e45ae186b: [PowerPC] Prevent the use of MMA with P9 and
earlier (authored by bsaleil).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D91200/new/
https://reviews.llvm.org/D91200
Files:
clang/lib/Basic/Targets/PPC.cpp
clang/test/Driver/ppc-mma-support-check.c
clang/test/Preprocessor/init-ppc64.c
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -648,7 +648,7 @@
// PPCFUTURE:#define _ARCH_PWR_FUTURE 1
// PPCFUTURE:#define __MMA__ 1
//
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none
-target-feature +mma -target-cpu power9 -fno-signed-char < /dev/null |
FileCheck -check-prefix PPC-MMA %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none
-target-feature +mma -target-cpu power10 -fno-signed-char < /dev/null |
FileCheck -check-prefix PPC-MMA %s
// PPC-MMA:#define __MMA__ 1
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none
-target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null |
FileCheck -check-prefix PPC-FLOAT128 %s
Index: clang/test/Driver/ppc-mma-support-check.c
===
--- /dev/null
+++ clang/test/Driver/ppc-mma-support-check.c
@@ -0,0 +1,22 @@
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr10 -mmma %s 2>&1 | FileCheck %s --check-prefix=HASMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=power10 -mmma %s 2>&1 | FileCheck %s --check-prefix=HASMMA
+
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr9 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr8 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr7 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+
+#ifdef __MMA__
+static_assert(false, "MMA enabled");
+#endif
+
+// HASMMA: MMA enabled
+// HASMMA-NOT: option '-mmma' cannot be specified with
+// NOMMA: option '-mmma' cannot be specified with
+
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -347,6 +347,13 @@
return false;
}
+ if (!(ArchDefs & ArchDefinePwr10) &&
+ llvm::find(FeaturesVec, "+mma") != FeaturesVec.end()) {
+// We have MMA on PPC but not power 10 and above.
+Diags.Report(diag::err_opt_not_valid_with_opt) << "-mmma" << CPU;
+return false;
+ }
+
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}
Index: clang/test/Preprocessor/init-ppc64.c
===
--- clang/test/Preprocessor/init-ppc64.c
+++ clang/test/Preprocessor/init-ppc64.c
@@ -648,7 +648,7 @@
// PPCFUTURE:#define _ARCH_PWR_FUTURE 1
// PPCFUTURE:#define __MMA__ 1
//
-// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power10 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s
// PPC-MMA:#define __MMA__ 1
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
Index: clang/test/Driver/ppc-mma-support-check.c
===
--- /dev/null
+++ clang/test/Driver/ppc-mma-support-check.c
@@ -0,0 +1,22 @@
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr10 -mmma %s 2>&1 | FileCheck %s --check-prefix=HASMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=power10 -mmma %s 2>&1 | FileCheck %s --check-prefix=HASMMA
+
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr9 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr8 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu -fsyntax-only \
+// RUN: -mcpu=pwr7 -mmma %s 2>&1 | FileCheck %s --check-prefix=NOMMA
+
[PATCH] D90799: [PowerPC] Add paired vector load and store builtins and intrinsics
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3f78605a8cb1: [PowerPC] Add paired vector load and store
builtins and intrinsics (authored by bsaleil).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D90799/new/
https://reviews.llvm.org/D90799
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-mma.c
clang/test/Sema/ppc-mma-types.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
Index: llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
===
--- llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -698,3 +698,315 @@
declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)
declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>)
+
+; Function Attrs: nounwind
+define void @test_ldst_1(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvp vsp0, 0(r3)
+; CHECK-NEXT:stxvp vsp0, 0(r4)
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_1:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvp vsp0, 0(r3)
+; CHECK-BE-NEXT:stxvp vsp0, 0(r4)
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %0)
+ %2 = bitcast <256 x i1>* %vp2 to i8*
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %1, i8* %2)
+ ret void
+}
+
+; Function Attrs: argmemonly nounwind readonly
+declare <256 x i1> @llvm.ppc.mma.lxvp(i8*)
+
+; Function Attrs: argmemonly nounwind writeonly
+declare void @llvm.ppc.mma.stxvp(<256 x i1>, i8*)
+
+; Function Attrs: nounwind
+define void @test_ldst_2(<256 x i1>* %vpp, i64 %offset, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvpx vsp0, r3, r4
+; CHECK-NEXT:stxvpx vsp0, r5, r4
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_2:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r4
+; CHECK-BE-NEXT:stxvpx vsp0, r5, r4
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 %offset
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 %offset
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_3(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:li r5, 18
+; CHECK-NEXT:lxvpx vsp0, r3, r5
+; CHECK-NEXT:stxvpx vsp0, r4, r5
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_3:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:li r5, 18
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r5
+; CHECK-BE-NEXT:stxvpx vsp0, r4, r5
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 18
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 18
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_4(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:li r5, 1
+; CHECK-NEXT:lxvpx vsp0, r3, r5
+; CHECK-NEXT:stxvpx vsp0, r4, r5
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_4:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:li r5, 1
+; CHECK-BE-NEXT:lxvpx vsp0, r3, r5
+; CHECK-BE-NEXT:stxvpx vsp0, r4, r5
+; CHECK-BE-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %vpp to i8*
+ %1 = getelementptr i8, i8* %0, i64 1
+ %2 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %1)
+ %3 = bitcast <256 x i1>* %vp2 to i8*
+ %4 = getelementptr i8, i8* %3, i64 1
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %2, i8* %4)
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @test_ldst_5(<256 x i1>* %vpp, <256 x i1>* %vp2) {
+; CHECK-LABEL: test_ldst_5:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:li r5, 42
+; CHECK-NEXT:lxvpx vsp0, r3, r5
+; CHECK-NEXT:stxvpx vsp0, r4, r5
+; CHECK-NEXT:blr
+;
+; CHECK-BE-LABEL: test_ldst_5:
+; CHECK-BE:
[PATCH] D91819: [PowerPC] Enable paired vector type and intrinsics when MMA is disabled
bsaleil created this revision.
bsaleil added reviewers: nemanjai, saghir, amyk, lei.
bsaleil added projects: PowerPC, LLVM, clang.
Herald added subscribers: llvm-commits, cfe-commits, dexonsmith, shchenz,
arphaman, martong, kbarton, hiraditya.
Herald added a reviewer: shafik.
bsaleil requested review of this revision.
This patch enables the Clang type `__vector_pair` and its associated LLVM
intrinsics even when MMA is disabled. With this patch, the type is now
controller by the PPC `paired-vector-memops` option. The builtins and
intrinsics will be renamed to drop the `mma` prefix in another patch.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D91819
Files:
clang/include/clang/AST/ASTContext.h
clang/include/clang/AST/Type.h
clang/include/clang/AST/TypeProperties.td
clang/include/clang/Basic/PPCTypes.def
clang/include/clang/Serialization/ASTBitCodes.h
clang/lib/AST/ASTContext.cpp
clang/lib/AST/ASTImporter.cpp
clang/lib/AST/ExprConstant.cpp
clang/lib/AST/ItaniumMangle.cpp
clang/lib/AST/MicrosoftMangle.cpp
clang/lib/AST/NSAPI.cpp
clang/lib/AST/PrintfFormatString.cpp
clang/lib/AST/Type.cpp
clang/lib/AST/TypeLoc.cpp
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/CodeGen/CodeGenTypes.cpp
clang/lib/CodeGen/ItaniumCXXABI.cpp
clang/lib/Index/USRGeneration.cpp
clang/lib/Sema/Sema.cpp
clang/lib/Sema/SemaChecking.cpp
clang/lib/Sema/SemaExpr.cpp
clang/lib/Serialization/ASTCommon.cpp
clang/lib/Serialization/ASTReader.cpp
clang/test/AST/ast-dump-ppc-mma-types.c
clang/test/AST/ast-dump-ppc-types.c
clang/tools/libclang/CIndex.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/paired-vector-intrinsics-without-mma.ll
Index: llvm/test/CodeGen/PowerPC/paired-vector-intrinsics-without-mma.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/paired-vector-intrinsics-without-mma.ll
@@ -0,0 +1,59 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mattr=-mma \
+; RUN: < %s | FileCheck %s
+
+; This test is to check that the paired vector intrinsics are available even
+; when MMA is disabled.
+
+define <16 x i8> @test1(<256 x i1>* %ptr) {
+; CHECK-LABEL: test1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxv v3, 0(r3)
+; CHECK-NEXT:lxv v2, 16(r3)
+; CHECK-NEXT:vaddubm v2, v3, v2
+; CHECK-NEXT:blr
+entry:
+ %0 = load <256 x i1>, <256 x i1>* %ptr, align 32
+ %1 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.pair(<256 x i1> %0)
+ %2 = extractvalue { <16 x i8>, <16 x i8> } %1, 0
+ %3 = extractvalue { <16 x i8>, <16 x i8> } %1, 1
+ %add = add <16 x i8> %2, %3
+ ret <16 x i8> %add
+}
+
+declare { <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.pair(<256 x i1>)
+
+define void @test2(<16 x i8> %v1, <16 x i8> %v2, <256 x i1>* %ptr) {
+; CHECK-LABEL: test2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vmr v4, v3
+; CHECK-NEXT:vmr v5, v2
+; CHECK-NEXT:stxv v4, 16(r7)
+; CHECK-NEXT:stxv v5, 0(r7)
+; CHECK-NEXT:blr
+entry:
+ %0 = tail call <256 x i1> @llvm.ppc.mma.assemble.pair(<16 x i8> %v2, <16 x i8> %v1)
+ store <256 x i1> %0, <256 x i1>* %ptr, align 32
+ ret void
+}
+
+declare <256 x i1> @llvm.ppc.mma.assemble.pair(<16 x i8>, <16 x i8>)
+
+define void @test3(<256 x i1>* %ptr) {
+; CHECK-LABEL: test3:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxvp vsp0, 0(r3)
+; CHECK-NEXT:stxvp vsp0, 32(r3)
+; CHECK-NEXT:blr
+entry:
+ %0 = bitcast <256 x i1>* %ptr to i8*
+ %1 = tail call <256 x i1> @llvm.ppc.mma.lxvp(i8* %0)
+ %add.ptr1 = getelementptr inbounds <256 x i1>, <256 x i1>* %ptr, i64 1
+ %2 = bitcast <256 x i1>* %add.ptr1 to i8*
+ tail call void @llvm.ppc.mma.stxvp(<256 x i1> %1, i8* %2)
+ ret void
+}
+
+declare <256 x i1> @llvm.ppc.mma.lxvp(i8*)
+declare void @llvm.ppc.mma.stxvp(<256 x i1>, i8*)
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1600,13 +1600,9 @@
let Predicates = [MMA] in {
def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
(XXMTACC Concats.VecsToVecQuad)>;
- def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)),
-Concats.VecsToVecPair0>;
def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
v16i8:$vs3, v16i8:$vs2)),
(XXMTACC Concats.VecsToVecQuad)>;
- def : Pat<(v256i1 (int_ppc_mma_assemble_pair v16i8:$vs1, v16i8:$vs0)),
-Concats.VecsToVecPair0>;
def : Pat<(v512i1 (PPCxxmfacc v512i1:$AS)), (XXMFACC acc:$AS)>;
def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, (i64 0))),
Extracts.Vec0
[PATCH] D84968: [PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0156914275be: [PowerPC] Legalize v256i1 and v512i1 and
implement load and store of these types (authored by bsaleil).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D84968/new/
https://reviews.llvm.org/D84968
Files:
clang/lib/Basic/Targets/PPC.h
clang/test/CodeGen/target-data.c
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
Index: llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
@@ -0,0 +1,238 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN: FileCheck %s --check-prefix=LE-PAIRED
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
+; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=BE-PAIRED
+
+@f = common local_unnamed_addr global <512 x i1> zeroinitializer, align 16
+@g = common local_unnamed_addr global <256 x i1> zeroinitializer, align 16
+
+define void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
+; LE-PAIRED-LABEL: testLdSt:
+; LE-PAIRED: # %bb.0: # %entry
+; LE-PAIRED-NEXT:plxv vs1, f@PCREL+96(0), 1
+; LE-PAIRED-NEXT:plxv vs0, f@PCREL+112(0), 1
+; LE-PAIRED-NEXT:plxv vs3, f@PCREL+64(0), 1
+; LE-PAIRED-NEXT:plxv vs2, f@PCREL+80(0), 1
+; LE-PAIRED-NEXT:xxmtacc acc0
+; LE-PAIRED-NEXT:xxmfacc acc0
+; LE-PAIRED-NEXT:pstxv vs0, f@PCREL+176(0), 1
+; LE-PAIRED-NEXT:pstxv vs1, f@PCREL+160(0), 1
+; LE-PAIRED-NEXT:pstxv vs2, f@PCREL+144(0), 1
+; LE-PAIRED-NEXT:pstxv vs3, f@PCREL+128(0), 1
+; LE-PAIRED-NEXT:blr
+;
+; BE-PAIRED-LABEL: testLdSt:
+; BE-PAIRED: # %bb.0: # %entry
+; BE-PAIRED-NEXT:addis r3, r2, .LC0@toc@ha
+; BE-PAIRED-NEXT:ld r3, .LC0@toc@l(r3)
+; BE-PAIRED-NEXT:lxv vs1, 80(r3)
+; BE-PAIRED-NEXT:lxv vs0, 64(r3)
+; BE-PAIRED-NEXT:lxv vs3, 112(r3)
+; BE-PAIRED-NEXT:lxv vs2, 96(r3)
+; BE-PAIRED-NEXT:xxmtacc acc0
+; BE-PAIRED-NEXT:xxmfacc acc0
+; BE-PAIRED-NEXT:stxv vs1, 144(r3)
+; BE-PAIRED-NEXT:stxv vs0, 128(r3)
+; BE-PAIRED-NEXT:stxv vs3, 176(r3)
+; BE-PAIRED-NEXT:stxv vs2, 160(r3)
+; BE-PAIRED-NEXT:blr
+entry:
+ %arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 1
+ %0 = load <512 x i1>, <512 x i1>* %arrayidx, align 64
+ %arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 2
+ store <512 x i1> %0, <512 x i1>* %arrayidx1, align 64
+ ret void
+}
+
+define void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
+; LE-PAIRED-LABEL: testXLdSt:
+; LE-PAIRED: # %bb.0: # %entry
+; LE-PAIRED-NEXT:sldi r3, r3, 6
+; LE-PAIRED-NEXT:paddi r5, 0, f@PCREL, 1
+; LE-PAIRED-NEXT:add r6, r5, r3
+; LE-PAIRED-NEXT:lxv vs1, 32(r6)
+; LE-PAIRED-NEXT:lxv vs0, 48(r6)
+; LE-PAIRED-NEXT:lxvx vs3, r5, r3
+; LE-PAIRED-NEXT:lxv vs2, 16(r6)
+; LE-PAIRED-NEXT:sldi r3, r4, 6
+; LE-PAIRED-NEXT:xxmtacc acc0
+; LE-PAIRED-NEXT:xxmfacc acc0
+; LE-PAIRED-NEXT:stxvx vs3, r5, r3
+; LE-PAIRED-NEXT:add r3, r5, r3
+; LE-PAIRED-NEXT:stxv vs0, 48(r3)
+; LE-PAIRED-NEXT:stxv vs1, 32(r3)
+; LE-PAIRED-NEXT:stxv vs2, 16(r3)
+; LE-PAIRED-NEXT:blr
+;
+; BE-PAIRED-LABEL: testXLdSt:
+; BE-PAIRED: # %bb.0: # %entry
+; BE-PAIRED-NEXT:addis r5, r2, .LC0@toc@ha
+; BE-PAIRED-NEXT:sldi r3, r3, 6
+; BE-PAIRED-NEXT:ld r5, .LC0@toc@l(r5)
+; BE-PAIRED-NEXT:add r6, r5, r3
+; BE-PAIRED-NEXT:lxvx vs0, r5, r3
+; BE-PAIRED-NEXT:sldi r3, r4, 6
+; BE-PAIRED-NEXT:lxv vs1, 16(r6)
+; BE-PAIRED-NEXT:lxv vs3, 48(r6)
+; BE-PAIRED-NEXT:lxv vs2, 32(r6)
+; BE-PAIRED-NEXT:xxmtacc acc0
+; BE-PAIRED-NEXT:xxmfacc acc0
+; BE-PAIRED-NEXT:stxvx vs0, r5, r3
+; BE-PAIRED-NEXT:add r3, r5, r3
+; BE-PAIRED-NEXT:stxv vs1, 16(r3)
+; BE-PAIRED-NEXT:stxv vs3, 48(r3)
+; BE-PAIRED-NEXT:stxv vs2, 32(r3)
+; BE-PAIRED-NEXT:blr
+entry:
+ %arrayidx = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %SrcIdx
+ %0 = load <512 x i1>, <512 x i1>* %arrayidx, align 64
+ %arrayidx1 = getelementptr inbounds <512 x i1>, <512 x i1>* @f, i64 %DstIdx
+ store <512 x i1> %0, <512 x i1>* %arrayidx1, align 64
+ ret void
+}
+
+define void @testUnalignedLdSt() {
+; LE-PAIRED-LABEL: testUnalignedLdSt:
+; LE-PAIRED: # %bb.0: # %entry
+; LE-PAIRED-NEXT:plxv vs1, f@PCREL+43(0), 1
+; LE
[PATCH] D84962: [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI
bsaleil accepted this revision. bsaleil added a comment. LGTM, please fix the unrelated change when committing. Comment at: clang/test/CodeGen/builtins-ppc-vsx.c:1 -// REQUIRES: powerpc-registered-target +// requires: powerpc-registered-target // RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s Unrelated change ? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84962/new/ https://reviews.llvm.org/D84962 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D91974: [PowerPC] Rename the pair intrinsics and builtins to replace the _mma_ prefix by _vsx_
bsaleil created this revision.
bsaleil added reviewers: nemanjai, amyk, saghir, lei, PowerPC.
bsaleil added projects: PowerPC, LLVM.
Herald added subscribers: llvm-commits, cfe-commits, shchenz, kbarton,
hiraditya.
Herald added a project: clang.
bsaleil requested review of this revision.
On PPC, the vector pair instructions are independent from MMA.
This patch renames the vector pair LLVM intrinsics and Clang builtins to
replace the `_mma_` prefix by `_vsx_` in their names.
We also move the vector pair type/intrinsic/builtin tests to their own files.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D91974
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-mma.c
clang/test/CodeGen/builtins-ppc-pair-mma.c
clang/test/Sema/ppc-mma-types.c
clang/test/Sema/ppc-pair-mma-types.c
clang/test/SemaCXX/ppc-mma-types.cpp
clang/test/SemaCXX/ppc-pair-mma-types.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
llvm/test/CodeGen/PowerPC/mma-outer-product.ll
llvm/test/CodeGen/PowerPC/paired-vector-intrinsics-without-mma.ll
llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
Index: llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
@@ -0,0 +1,356 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN: < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O3 \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mattr=-mma \
+; RUN: < %s | FileCheck %s --check-prefix=CHECK-NOMMA
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O3 \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN: < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O3 \
+; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mattr=-mma \
+; RUN: < %s | FileCheck %s --check-prefix=CHECK-BE-NOMMA
+
+; This test is to check that the paired vector intrinsics are available even
+
+; assemble_pair
+declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)
+define void @ass_pair(<256 x i1>* %ptr, <16 x i8> %vc) {
+; CHECK-LABEL: ass_pair:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:vmr v3, v2
+; CHECK-NEXT:stxv v2, 16(r3)
+; CHECK-NEXT:stxv v3, 0(r3)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: ass_pair:
+; CHECK-NOMMA: # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:vmr v3, v2
+; CHECK-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-NOMMA-NEXT:stxv v3, 0(r3)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: ass_pair:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:vmr v3, v2
+; CHECK-BE-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NEXT:blr
+;
+; CHECK-BE-NOMMA-LABEL: ass_pair:
+; CHECK-BE-NOMMA: # %bb.0: # %entry
+; CHECK-BE-NOMMA-NEXT:vmr v3, v2
+; CHECK-BE-NOMMA-NEXT:stxv v2, 16(r3)
+; CHECK-BE-NOMMA-NEXT:stxv v2, 0(r3)
+; CHECK-BE-NOMMA-NEXT:blr
+entry:
+ %0 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc, <16 x i8> %vc)
+ store <256 x i1> %0, <256 x i1>* %ptr, align 32
+ ret void
+}
+
+; disassemble_pair
+declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)
+define void @disass_pair(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
+; CHECK-LABEL: disass_pair:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:lxv vs1, 0(r3)
+; CHECK-NEXT:lxv vs0, 16(r3)
+; CHECK-NEXT:stxv vs1, 0(r4)
+; CHECK-NEXT:stxv vs0, 0(r5)
+; CHECK-NEXT:blr
+;
+; CHECK-NOMMA-LABEL: disass_pair:
+; CHECK-NOMMA: # %bb.0: # %entry
+; CHECK-NOMMA-NEXT:lxv vs1, 0(r3)
+; CHECK-NOMMA-NEXT:lxv vs0, 16(r3)
+; CHECK-NOMMA-NEXT:stxv vs1, 0(r4)
+; CHECK-NOMMA-NEXT:stxv vs0, 0(r5)
+; CHECK-NOMMA-NEXT:blr
+;
+; CHECK-BE-LABEL: disass_pair:
+; CHECK-BE: # %bb.0: # %entry
+; CHECK-BE-NEXT:lxv vs1, 16(r3)
+; CHECK-BE-NEXT:lxv vs0, 0(r3)
+; CHECK-BE-NEXT:stxv vs0, 0(r4)
+; CHECK-BE-NEXT:stxv vs1, 0(r5)
+; CHECK-BE-NEXT:blr
+;
+; CHECK-BE-NOMMA-LABEL: disass_pair:
+; CHECK-BE-NOMMA: # %bb.0: # %entry
+; CHECK-BE-NOMMA-NEXT:lxv vs1, 16(r3)
+; CHECK-BE-NOMMA-NEXT:lxv vs0, 0(r3)
+; CHECK-BE-NOMMA-NEXT:stxv vs0,
[PATCH] D81508: [PowerPC] Add __vector_pair and __vector_quad types
bsaleil updated this revision to Diff 300408.
bsaleil added a comment.
Herald added a subscriber: dexonsmith.
Rebasing the patch
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81508/new/
https://reviews.llvm.org/D81508
Files:
clang/include/clang/AST/ASTContext.h
clang/include/clang/AST/Type.h
clang/include/clang/AST/TypeProperties.td
clang/include/clang/Basic/PPCTypes.def
clang/include/clang/Serialization/ASTBitCodes.h
clang/lib/AST/ASTContext.cpp
clang/lib/AST/ASTImporter.cpp
clang/lib/AST/ExprConstant.cpp
clang/lib/AST/ItaniumMangle.cpp
clang/lib/AST/MicrosoftMangle.cpp
clang/lib/AST/NSAPI.cpp
clang/lib/AST/PrintfFormatString.cpp
clang/lib/AST/Type.cpp
clang/lib/AST/TypeLoc.cpp
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/CodeGen/CodeGenTypes.cpp
clang/lib/CodeGen/ItaniumCXXABI.cpp
clang/lib/Index/USRGeneration.cpp
clang/lib/Sema/Sema.cpp
clang/lib/Sema/SemaExpr.cpp
clang/lib/Serialization/ASTCommon.cpp
clang/lib/Serialization/ASTReader.cpp
clang/test/AST/ast-dump-ppc-mma-types.c
clang/test/CodeGen/ppc-mma-types.c
clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
clang/tools/libclang/CIndex.cpp
Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1546,6 +1546,8 @@
case BuiltinType::OCLReserveID:
#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
#include "clang/Basic/AArch64SVEACLETypes.def"
+#define PPC_MMA_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
+#include "clang/Basic/PPCTypes.def"
#define BUILTIN_TYPE(Id, SingletonId)
#define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
#define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
Index: clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
===
--- /dev/null
+++ clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
@@ -0,0 +1,14 @@
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future %s \
+// RUN: -emit-llvm -o - | FileCheck %s
+
+// CHECK: _Z2f1Pu13__vector_quad
+void f1(__vector_quad *vq) {}
+
+// CHECK: _Z2f2Pu13__vector_pair
+void f2(__vector_pair *vp) {}
+
+// CHECK: _Z2f3Pu13__vector_quad
+void f3(__vector_quad *vq) {}
+
+// CHECK: _Z2f3Pu13__vector_pair
+void f3(__vector_pair *vp) {}
Index: clang/test/CodeGen/ppc-mma-types.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc-mma-types.c
@@ -0,0 +1,27 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future \
+// RUN: -emit-llvm -O3 -o - %s | FileCheck %s
+
+// CHECK-LABEL: @test1(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[ADD_PTR:%.*]] = getelementptr inbounds <512 x i1>, <512 x i1>* [[PTR1:%.*]], i64 2
+// CHECK-NEXT:[[TMP0:%.*]] = load <512 x i1>, <512 x i1>* [[ADD_PTR]], align 64, [[TBAA2:!tbaa !.*]]
+// CHECK-NEXT:[[ADD_PTR1:%.*]] = getelementptr inbounds <512 x i1>, <512 x i1>* [[PTR2:%.*]], i64 1
+// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[ADD_PTR1]], align 64, [[TBAA2]]
+// CHECK-NEXT:ret void
+//
+void test1(__vector_quad *ptr1, __vector_quad *ptr2) {
+ *(ptr2 + 1) = *(ptr1 + 2);
+}
+
+// CHECK-LABEL: @test2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[ADD_PTR:%.*]] = getelementptr inbounds <256 x i1>, <256 x i1>* [[PTR1:%.*]], i64 2
+// CHECK-NEXT:[[TMP0:%.*]] = load <256 x i1>, <256 x i1>* [[ADD_PTR]], align 32, [[TBAA6:!tbaa !.*]]
+// CHECK-NEXT:[[ADD_PTR1:%.*]] = getelementptr inbounds <256 x i1>, <256 x i1>* [[PTR2:%.*]], i64 1
+// CHECK-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[ADD_PTR1]], align 32, [[TBAA6]]
+// CHECK-NEXT:ret void
+//
+void test2(__vector_pair *ptr1, __vector_pair *ptr2) {
+ *(ptr2 + 1) = *(ptr1 + 2);
+}
Index: clang/test/AST/ast-dump-ppc-mma-types.c
===
--- /dev/null
+++ clang/test/AST/ast-dump-ppc-mma-types.c
@@ -0,0 +1,38 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu future \
+// RUN: -ast-dump -ast-dump-filter __vector %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu future \
+// RUN: -target-feature -mma -ast-dump %s | FileCheck %s \
+// RUN: --check-prefix=CHECK-NO-MMA
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr9 \
+// RUN: -ast-dump %s | FileCheck %s --check-prefix=CHECK-PWR9
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -ast-dump %s | FileCheck %s \
+// RUN: --check-prefix=CHECK-X86_64
+// RUN: %clang_cc1 -triple arm-unknown-unknown -ast-dump %s | FileCheck %s \
+// RUN: --check-prefix=CHECK-ARM
+// RUN: %clang_cc1 -triple riscv64-unknown-unknown -ast-dump %s | FileCheck %s \
+// RUN: --check-prefix=CHECK-RISCV64
+
+// This test case checks that t
[PATCH] D81748: [PowerPC] Add MMA builtin decoding and definitions
bsaleil updated this revision to Diff 300805.
bsaleil added a comment.
Herald added a subscriber: dexonsmith.
Rebase patch
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81748/new/
https://reviews.llvm.org/D81748
Files:
clang/include/clang/AST/ASTContext.h
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Sema/Sema.h
clang/lib/AST/ASTContext.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-mma.c
Index: clang/test/CodeGen/builtins-ppc-mma.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-mma.c
@@ -0,0 +1,1038 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @test1(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], <16 x i8> [[VC]], <16 x i8> [[VC]])
+// CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
+// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
+// CHECK-NEXT:ret void
+//
+void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_quad vq = *((__vector_quad *)vqp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __vector_quad res;
+ __builtin_mma_assemble_acc(&res, vc, vc, vc, vc);
+ *((__vector_quad *)resp) = res;
+}
+
+// CHECK-LABEL: @test2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
+// CHECK-NEXT:[[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64
+// CHECK-NEXT:[[TMP2:%.*]] = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> [[TMP1]])
+// CHECK-NEXT:[[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <16 x i8>*
+// CHECK-NEXT:[[TMP4:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 0
+// CHECK-NEXT:store <16 x i8> [[TMP4]], <16 x i8>* [[TMP3]], align 16
+// CHECK-NEXT:[[TMP5:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 1
+// CHECK-NEXT:[[TMP6:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 16
+// CHECK-NEXT:[[TMP7:%.*]] = bitcast i8* [[TMP6]] to <16 x i8>*
+// CHECK-NEXT:store <16 x i8> [[TMP5]], <16 x i8>* [[TMP7]], align 16
+// CHECK-NEXT:[[TMP8:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 2
+// CHECK-NEXT:[[TMP9:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 32
+// CHECK-NEXT:[[TMP10:%.*]] = bitcast i8* [[TMP9]] to <16 x i8>*
+// CHECK-NEXT:store <16 x i8> [[TMP8]], <16 x i8>* [[TMP10]], align 16
+// CHECK-NEXT:[[TMP11:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 3
+// CHECK-NEXT:[[TMP12:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 48
+// CHECK-NEXT:[[TMP13:%.*]] = bitcast i8* [[TMP12]] to <16 x i8>*
+// CHECK-NEXT:store <16 x i8> [[TMP11]], <16 x i8>* [[TMP13]], align 16
+// CHECK-NEXT:ret void
+//
+void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __builtin_mma_disassemble_acc(resp, (__vector_quad*)vqp);
+}
+
+// CHECK-LABEL: @test3(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.mma.assemble.pair(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
+// CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
+// CHECK-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa !6
+// CHECK-NEXT:ret void
+//
+void test3(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_quad vq = *((__vector_quad *)vqp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __vector_pair res;
+ __builtin_mma_assemble_pair(&res, vc, vc);
+ *((__vector_pair *)resp) = res;
+}
+
+// CHECK-LABEL: @test4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>*
+// CHECK-NEXT:[[TMP1:%.*]] = load <256 x i1>, <256 x i1>* [[TMP0]], align 32
+// CHECK-NEXT:[[TMP2:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.pair(<256 x i1> [[TMP1]])
+// CHECK-NEXT:[[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <16 x i8>*
+// CHECK-NEXT:[[TMP4:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP2]], 0
+// CHECK-NEXT:store <16 x i8> [[TMP4]], <16 x i8>* [[TMP3]], align 16
+// CHECK-NEXT:[[TMP5:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP2]], 1
+// CHECK-NEXT:[[TMP6:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 16
+// CHECK-NEXT:[[TMP7:%.*]] = bitcast i8* [[TMP6]] to <16 x i8>*
+// CHECK-NEXT:store <16 x i8> [[TMP5]], <16 x i8>* [[TMP7]], align 16
+// CHECK-NEXT:ret void
+//
+void test4(
[PATCH] D82035: [PowerPC] Add Sema checks for MMA types
bsaleil updated this revision to Diff 301010.
bsaleil added reviewers: nemanjai, saghir, lei, rsmith.
bsaleil added a comment.
Herald added a subscriber: dexonsmith.
Rebasing patch
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82035/new/
https://reviews.llvm.org/D82035
Files:
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/include/clang/Sema/Sema.h
clang/lib/Sema/SemaChecking.cpp
clang/lib/Sema/SemaDecl.cpp
clang/lib/Sema/SemaExprCXX.cpp
clang/test/Sema/ppc-mma-types.c
clang/test/SemaCXX/ppc-mma-types.cpp
Index: clang/test/SemaCXX/ppc-mma-types.cpp
===
--- /dev/null
+++ clang/test/SemaCXX/ppc-mma-types.cpp
@@ -0,0 +1,384 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -fcxx-exceptions -target-cpu future %s -verify
+
+// vector quad
+
+// alias
+using vq_t = __vector_quad;
+void testVQAlias(int *inp, int *outp) {
+ vq_t *vqin = (vq_t *)inp;
+ vq_t *vqout = (vq_t *)outp;
+ *vqout = *vqin;
+}
+
+class TestClassVQ {
+ // method argument
+public:
+ void testVQArg1(__vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = vq;
+*vqp1 = vq;
+ }
+ void testVQArg2(const __vector_quad vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = vq;
+*vqp2 = vq;
+ }
+ void testVQArg3(__vector_quad *vq, int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = *vq;
+vqp1 = vqp;
+ }
+ void testVQArg4(const __vector_quad *const vq, int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = *vq;
+vqp2 = vqp;
+ }
+ void testVQArg5(__vector_quad vqa[], int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = vqa[0];
+*vqp1 = vqa[1];
+ }
+ void testVQArg6(const vq_t vq, int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = vq;
+*vqp2 = vq;
+ }
+ void testVQArg7(const vq_t *vq, int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+*vqp = *vq;
+vqp1 = vqp;
+ }
+
+ // method return
+ __vector_quad testVQRet1(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+vq1 = *vqp;
+return *vqp; // expected-error {{invalid use of PPC MMA type}}
+ }
+
+ __vector_quad *testVQRet2(int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+vq2 = *vqp;
+return vqp + 2;
+ }
+
+ const __vector_quad *testVQRet3(int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+vqp1 = vqp;
+return vqp + 2;
+ }
+
+ const vq_t testVQRet4(int *ptr) { // expected-error {{invalid use of PPC MMA type}}
+__vector_quad *vqp = (__vector_quad *)ptr;
+vqp2 = vqp;
+return *vqp; // expected-error {{invalid use of PPC MMA type}}
+ }
+
+ const vq_t *testVQRet5(int *ptr) {
+__vector_quad *vqp = (__vector_quad *)ptr;
+vq1 = *vqp;
+return vqp + 2;
+ }
+
+ // template argument
+ template
+ void testVQTemplate(T v, T *p) { // expected-note {{candidate template ignored: substitution failure [with T = __vector_quad]: invalid use of PPC MMA type}} \
+ expected-note {{candidate template ignored: substitution failure [with T = __vector_quad]: invalid use of PPC MMA type}}
+*(p + 1) = v;
+ }
+
+ // class field
+public:
+ __vector_quad vq1; // expected-error {{invalid use of PPC MMA type}}
+ __vector_quad *vqp1;
+
+private:
+ vq_t vq2; // expected-error {{invalid use of PPC MMA type}}
+ vq_t *vqp2;
+};
+
+// template
+template
+class ClassTemplateVQ1 {
+ T t; // expected-error {{invalid use of PPC MMA type}}
+};
+template
+class ClassTemplateVQ2 {
+ T *t;
+};
+template
+class ClassTemplateVQ3 {
+ int foo(T t) { return 10; }
+};
+template
+class ClassTemplateVQ4 {
+public:
+ T operator()(Ts...) const {} // expected-error {{invalid use of PPC MMA type}}
+};
+void testVQTemplate() {
+ ClassTemplateVQ1<__vector_quad> t1; // expected-note {{in instantiation of template class 'ClassTemplateVQ1<__vector_quad>' requested here}}
+ ClassTemplateVQ1<__vector_quad *> t2;
+ ClassTemplateVQ2<__vector_quad> t3;
+ ClassTemplateVQ2<__vector_quad *> t4;
+
+ ClassTemplateVQ3 t5;
+ // The following case is not prevented but it ok, this function type cannot be
+ // instantiated because we prevent any function from returning an MMA type.
+ ClassTemplateVQ3<__vector_quad(int, int, int)> t6;
+ ClassTemplateVQ3 t7; // expected-error {{invalid use of PPC MMA type}}
+
+ ClassTemplateVQ4 t8; // expected-note {{in instantiation of template class 'ClassTemplateVQ4' requested here}}
+ ClassTemplateVQ4 t9;
+
+ TestClassVQ tc;
+ __vector_quad vq;
+ __vector_quad *vqp = &vq;
+ tc.testVQTemplate(&vq, &vqp);
+ tc.testVQTemplate(&vq, &vqp);
[PATCH] D81508: [PowerPC] Add __vector_pair and __vector_quad types
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG40dd4d5233d9: [Clang][PowerPC] Add __vector_pair and
__vector_quad types (authored by bsaleil).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81508/new/
https://reviews.llvm.org/D81508
Files:
clang/include/clang/AST/ASTContext.h
clang/include/clang/AST/Type.h
clang/include/clang/AST/TypeProperties.td
clang/include/clang/Basic/PPCTypes.def
clang/include/clang/Serialization/ASTBitCodes.h
clang/lib/AST/ASTContext.cpp
clang/lib/AST/ASTImporter.cpp
clang/lib/AST/ExprConstant.cpp
clang/lib/AST/ItaniumMangle.cpp
clang/lib/AST/MicrosoftMangle.cpp
clang/lib/AST/NSAPI.cpp
clang/lib/AST/PrintfFormatString.cpp
clang/lib/AST/Type.cpp
clang/lib/AST/TypeLoc.cpp
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/CodeGen/CodeGenTypes.cpp
clang/lib/CodeGen/ItaniumCXXABI.cpp
clang/lib/Index/USRGeneration.cpp
clang/lib/Sema/Sema.cpp
clang/lib/Sema/SemaExpr.cpp
clang/lib/Serialization/ASTCommon.cpp
clang/lib/Serialization/ASTReader.cpp
clang/test/AST/ast-dump-ppc-mma-types.c
clang/test/CodeGen/ppc-mma-types.c
clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
clang/tools/libclang/CIndex.cpp
Index: clang/tools/libclang/CIndex.cpp
===
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1546,6 +1546,8 @@
case BuiltinType::OCLReserveID:
#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
#include "clang/Basic/AArch64SVEACLETypes.def"
+#define PPC_MMA_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
+#include "clang/Basic/PPCTypes.def"
#define BUILTIN_TYPE(Id, SingletonId)
#define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
#define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
Index: clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
===
--- /dev/null
+++ clang/test/CodeGenCXX/ppc-mangle-mma-types.cpp
@@ -0,0 +1,14 @@
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future %s \
+// RUN: -emit-llvm -o - | FileCheck %s
+
+// CHECK: _Z2f1Pu13__vector_quad
+void f1(__vector_quad *vq) {}
+
+// CHECK: _Z2f2Pu13__vector_pair
+void f2(__vector_pair *vp) {}
+
+// CHECK: _Z2f3Pu13__vector_quad
+void f3(__vector_quad *vq) {}
+
+// CHECK: _Z2f3Pu13__vector_pair
+void f3(__vector_pair *vp) {}
Index: clang/test/CodeGen/ppc-mma-types.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc-mma-types.c
@@ -0,0 +1,27 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple powerpc64le-linux-unknown -target-cpu future \
+// RUN: -emit-llvm -O3 -o - %s | FileCheck %s
+
+// CHECK-LABEL: @test1(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[ADD_PTR:%.*]] = getelementptr inbounds <512 x i1>, <512 x i1>* [[PTR1:%.*]], i64 2
+// CHECK-NEXT:[[TMP0:%.*]] = load <512 x i1>, <512 x i1>* [[ADD_PTR]], align 64, [[TBAA2:!tbaa !.*]]
+// CHECK-NEXT:[[ADD_PTR1:%.*]] = getelementptr inbounds <512 x i1>, <512 x i1>* [[PTR2:%.*]], i64 1
+// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[ADD_PTR1]], align 64, [[TBAA2]]
+// CHECK-NEXT:ret void
+//
+void test1(__vector_quad *ptr1, __vector_quad *ptr2) {
+ *(ptr2 + 1) = *(ptr1 + 2);
+}
+
+// CHECK-LABEL: @test2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[ADD_PTR:%.*]] = getelementptr inbounds <256 x i1>, <256 x i1>* [[PTR1:%.*]], i64 2
+// CHECK-NEXT:[[TMP0:%.*]] = load <256 x i1>, <256 x i1>* [[ADD_PTR]], align 32, [[TBAA6:!tbaa !.*]]
+// CHECK-NEXT:[[ADD_PTR1:%.*]] = getelementptr inbounds <256 x i1>, <256 x i1>* [[PTR2:%.*]], i64 1
+// CHECK-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[ADD_PTR1]], align 32, [[TBAA6]]
+// CHECK-NEXT:ret void
+//
+void test2(__vector_pair *ptr1, __vector_pair *ptr2) {
+ *(ptr2 + 1) = *(ptr1 + 2);
+}
Index: clang/test/AST/ast-dump-ppc-mma-types.c
===
--- /dev/null
+++ clang/test/AST/ast-dump-ppc-mma-types.c
@@ -0,0 +1,38 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu future \
+// RUN: -ast-dump -ast-dump-filter __vector %s | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu future \
+// RUN: -target-feature -mma -ast-dump %s | FileCheck %s \
+// RUN: --check-prefix=CHECK-NO-MMA
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -target-cpu pwr9 \
+// RUN: -ast-dump %s | FileCheck %s --check-prefix=CHECK-PWR9
+// RUN: %clang_cc1 -triple x86_64-unknown-unknown -ast-dump %s | FileCheck %s \
+// RUN: --check-prefix=CHECK-X86_64
+// RUN: %clang_cc1 -triple arm-unknown-unknown -ast-dump %s | FileCheck %s \
+// RUN: --check-prefix=CHECK-ARM
+// RUN: %clang_cc1 -triple riscv64-unkno
[PATCH] D81748: [PowerPC] Add MMA builtin decoding and definitions
bsaleil updated this revision to Diff 301437.
bsaleil added a comment.
Fix typo and add comment to explain why we add the `ASTContext::DecodeTypeStr`
function.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81748/new/
https://reviews.llvm.org/D81748
Files:
clang/include/clang/AST/ASTContext.h
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Sema/Sema.h
clang/lib/AST/ASTContext.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-mma.c
Index: clang/test/CodeGen/builtins-ppc-mma.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-mma.c
@@ -0,0 +1,1038 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: @test1(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], <16 x i8> [[VC]], <16 x i8> [[VC]])
+// CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
+// CHECK-NEXT:store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
+// CHECK-NEXT:ret void
+//
+void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_quad vq = *((__vector_quad *)vqp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __vector_quad res;
+ __builtin_mma_assemble_acc(&res, vc, vc, vc, vc);
+ *((__vector_quad *)resp) = res;
+}
+
+// CHECK-LABEL: @test2(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
+// CHECK-NEXT:[[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64
+// CHECK-NEXT:[[TMP2:%.*]] = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> [[TMP1]])
+// CHECK-NEXT:[[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <16 x i8>*
+// CHECK-NEXT:[[TMP4:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 0
+// CHECK-NEXT:store <16 x i8> [[TMP4]], <16 x i8>* [[TMP3]], align 16
+// CHECK-NEXT:[[TMP5:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 1
+// CHECK-NEXT:[[TMP6:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 16
+// CHECK-NEXT:[[TMP7:%.*]] = bitcast i8* [[TMP6]] to <16 x i8>*
+// CHECK-NEXT:store <16 x i8> [[TMP5]], <16 x i8>* [[TMP7]], align 16
+// CHECK-NEXT:[[TMP8:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 2
+// CHECK-NEXT:[[TMP9:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 32
+// CHECK-NEXT:[[TMP10:%.*]] = bitcast i8* [[TMP9]] to <16 x i8>*
+// CHECK-NEXT:store <16 x i8> [[TMP8]], <16 x i8>* [[TMP10]], align 16
+// CHECK-NEXT:[[TMP11:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 3
+// CHECK-NEXT:[[TMP12:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 48
+// CHECK-NEXT:[[TMP13:%.*]] = bitcast i8* [[TMP12]] to <16 x i8>*
+// CHECK-NEXT:store <16 x i8> [[TMP11]], <16 x i8>* [[TMP13]], align 16
+// CHECK-NEXT:ret void
+//
+void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __builtin_mma_disassemble_acc(resp, (__vector_quad*)vqp);
+}
+
+// CHECK-LABEL: @test3(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.mma.assemble.pair(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
+// CHECK-NEXT:[[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
+// CHECK-NEXT:store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa !6
+// CHECK-NEXT:ret void
+//
+void test3(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
+ __vector_quad vq = *((__vector_quad *)vqp);
+ __vector_pair vp = *((__vector_pair *)vpp);
+ __vector_pair res;
+ __builtin_mma_assemble_pair(&res, vc, vc);
+ *((__vector_pair *)resp) = res;
+}
+
+// CHECK-LABEL: @test4(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>*
+// CHECK-NEXT:[[TMP1:%.*]] = load <256 x i1>, <256 x i1>* [[TMP0]], align 32
+// CHECK-NEXT:[[TMP2:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.pair(<256 x i1> [[TMP1]])
+// CHECK-NEXT:[[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <16 x i8>*
+// CHECK-NEXT:[[TMP4:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP2]], 0
+// CHECK-NEXT:store <16 x i8> [[TMP4]], <16 x i8>* [[TMP3]], align 16
+// CHECK-NEXT:[[TMP5:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP2]], 1
+// CHECK-NEXT:[[TMP6:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 16
+// CHECK-NEXT:[[TMP7:%.*]] = bitcast i8* [[TMP6]] to <16 x i8>*
+// CHECK-NEXT:store <16 x i8> [[TMP5]], <16 x i8>* [[TMP7]], align 16
+// CH
[PATCH] D74087: [Sema] Fix Sema checkArgCount function
bsaleil created this revision. bsaleil added a reviewer: rsmith. bsaleil added a project: clang. Herald added a subscriber: cfe-commits. This patch fixes the checkArgCount function in Sema that is used to check the number of arguments of a call when doing custom type-checking. The patch fixes that function in two ways: 1. It now displays the right range in case the number of actual arguments is greater than the number of expected arguments 2. It allows the function to properly handle the case in which the desired argument count is 0 and the number of actual arguments is 1 Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D74087 Files: clang/lib/Sema/SemaChecking.cpp Index: clang/lib/Sema/SemaChecking.cpp === --- clang/lib/Sema/SemaChecking.cpp +++ clang/lib/Sema/SemaChecking.cpp @@ -122,7 +122,7 @@ return S.Diag(range.getBegin(), diag::err_typecheck_call_too_many_args) << 0 /*function call*/ << desiredArgCount << argCount -<< call->getArg(1)->getSourceRange(); +<< range; } /// Check that the first argument to __builtin_annotation is an integer Index: clang/lib/Sema/SemaChecking.cpp === --- clang/lib/Sema/SemaChecking.cpp +++ clang/lib/Sema/SemaChecking.cpp @@ -122,7 +122,7 @@ return S.Diag(range.getBegin(), diag::err_typecheck_call_too_many_args) << 0 /*function call*/ << desiredArgCount << argCount -<< call->getArg(1)->getSourceRange(); +<< range; } /// Check that the first argument to __builtin_annotation is an integer ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D74087: [Sema] Fix Sema checkArgCount function
bsaleil updated this revision to Diff 242963.
bsaleil added a comment.
Adding test case
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D74087/new/
https://reviews.llvm.org/D74087
Files:
clang/lib/Sema/SemaChecking.cpp
clang/test/Sema/custom-checking.c
Index: clang/test/Sema/custom-checking.c
===
--- /dev/null
+++ clang/test/Sema/custom-checking.c
@@ -0,0 +1,29 @@
+// RUN: not %clang_cc1 -fsyntax-only %s 2>&1 | FileCheck %s -strict-whitespace
+
+int few_args() {
+ int r = 0;
+ __builtin_add_overflow(1, 2);
+ return r;
+}
+
+// CHECK: error: too few arguments to function call, expected 3, have 2
+// CHECK: __builtin_add_overflow(1, 2);
+// CHECK: ~~~^
+
+int many_args() {
+ int r = 0;
+ __builtin_add_overflow(1, 2, &r, 3, 4, 5, 6);
+ return r;
+}
+
+// CHECK: error: too many arguments to function call, expected 3, have 7
+// CHECK: __builtin_add_overflow(1, 2, &r, 3, 4, 5, 6);
+// CHECK:^~
+
+int equal_args() {
+ int r = 0;
+ __builtin_add_overflow(1, 2, &r);
+ return r;
+}
+
+// CHECK: 2 errors generated.
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -121,8 +121,7 @@
call->getArg(argCount - 1)->getEndLoc());
return S.Diag(range.getBegin(), diag::err_typecheck_call_too_many_args)
-<< 0 /*function call*/ << desiredArgCount << argCount
-<< call->getArg(1)->getSourceRange();
+<< 0 /*function call*/ << desiredArgCount << argCount << range;
}
/// Check that the first argument to __builtin_annotation is an integer
Index: clang/test/Sema/custom-checking.c
===
--- /dev/null
+++ clang/test/Sema/custom-checking.c
@@ -0,0 +1,29 @@
+// RUN: not %clang_cc1 -fsyntax-only %s 2>&1 | FileCheck %s -strict-whitespace
+
+int few_args() {
+ int r = 0;
+ __builtin_add_overflow(1, 2);
+ return r;
+}
+
+// CHECK: error: too few arguments to function call, expected 3, have 2
+// CHECK: __builtin_add_overflow(1, 2);
+// CHECK: ~~~^
+
+int many_args() {
+ int r = 0;
+ __builtin_add_overflow(1, 2, &r, 3, 4, 5, 6);
+ return r;
+}
+
+// CHECK: error: too many arguments to function call, expected 3, have 7
+// CHECK: __builtin_add_overflow(1, 2, &r, 3, 4, 5, 6);
+// CHECK:^~
+
+int equal_args() {
+ int r = 0;
+ __builtin_add_overflow(1, 2, &r);
+ return r;
+}
+
+// CHECK: 2 errors generated.
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -121,8 +121,7 @@
call->getArg(argCount - 1)->getEndLoc());
return S.Diag(range.getBegin(), diag::err_typecheck_call_too_many_args)
-<< 0 /*function call*/ << desiredArgCount << argCount
-<< call->getArg(1)->getSourceRange();
+<< 0 /*function call*/ << desiredArgCount << argCount << range;
}
/// Check that the first argument to __builtin_annotation is an integer
___
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